HI-8150PQI [HOLTIC]
CMOS HIGH VOLTAGE DISPLAY DRIVER; CMOS高电压显示驱动器
| 型号： | HI-8150PQI |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| 文件： | 总8页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8050/51, HI-8150/51
January 2001
CMOS HIGH VOLTAGE DISPLAY DRIVER
GENERAL DESCRIPTION
APPLICATIONS
! Dichroic Liquid Crystal Displays
! Standard Liquid Crystal Displays
! 5 Volt Serial Data to Parallel High Voltage
The HI-8050, HI-8051, HI-8150 and HI-8151 are CMOS
integrated circuits designed for high voltage LCD display
drive applications. The HI-8050 & HI-8051 have TTL logic
inputs whereas the HI-8150 & HI-8151 have CMOS logic
inputs. They drive up to 38 segments at voltages between
+5 and -30 volts. The optional negative converter on the
HI-8050 & HI-8150 can be used to generate the negative
display drive voltage. All products have test inputs to
facilitate opens and shorts testing as well as automatic
blanking of the display if the +5V power is lost.
PAD CONFIGURATION (Top View)
BPIN
BPOSC
VDD
N/C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
S27
S26
S25
S24
S23
S22
S21
S20
DOUT38
DOUT32
DOUT30
T2
T1
N/C
The HI-8050 and HI-8150 are designed to replace the
HI-8010 and HI-8020 devices in all 5 volt applications. They
offer significantly enhanced ESD protection along with a
considerably faster serial input data rate.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CONVOSC
CONVOUT
VEE
HI-8050PQI
HI-8150PQI
HI-8050PQT
&
S37
S38
S1
S2
S3
S4
S5
S6
The data is serially clocked into the device on the negative
edge of the clock and latched in parallel to the segment
outputs on the high to low transition of the load input. Serial
output data changes on the positive edge of the clock
allowing the cascading ofmultiple drivers for larger displays.
HI-8150PQT
BPOUT
N/C
S7
The device layout supports all previous pinouts of the
HI-8010/HI-8020 products. In addition, new technology and
features afford ne w packaging options. Consult your Holt
Sales Representative to explore the possibilities.
(See page 3-32A for HI-8051 & HI-8151 pin configurations)
FUNCTIONAL BLOCK DIAGRAM
FEATURES
DATA IN
DIN ⇒
DOUT38
DOUT32
DOUT30
! 4 MHz serial input data rate
! 38 segment outputs
38 Stage
Shift Register
CL ⇒
CS ⇒
CLK
CONTROL
LOGIC
! Cascadable
8020OPT ⇒
LD ⇒
LE
38 Bit Latch
! 5 Volt inputs translated to 35 Volts
! Test pins allow hardware all "ON", all "OFF" or
alternating
Oscillator
Divider
BPIN ⇒
Voltage
Translators
BPOSC ⇒
! Monitors 5 volt supply and forces all
segments to "OFF" condition if lost
Voltage
Translator
High Voltage
Drivers
! Negative voltage converter available on-chip
! CMOS low power
High Voltage
Buffer
! Military processing available
38 SEGMENTS
⇒ BPOUT
HOLT INTEGRATED CIRCUITS
1
(DS8050 Rev. C)
01/01
HI-8050/51, HI-8150/51
PIN DESCRIPTION TABLE
SIGNAL
VSS
FUNCTION
DESCRIPTION
POWER
0 Volts
8020OPT
LOGIC INPUT Open or high logic level selects the HI-8010/HI-8110 CL / CS logic. A low
selects the HI-8020/HI-8120 Logic (HI-8050 & HI-8150 only)
CS
CL
LOGIC INPUT Chip select - Active low
LOGIC INPUT Serial data input clock - Active low
LD
LOGIC INPUT Latches data in shift register to the segment outputs - Active high
LOGIC INPUT Serial input data to the shift register
DIN
BPIN
INPUT
Backplane frequency input. Either driven from an external source or connected
to BPOSC and an external resistor and capacitor.
BPOSC
VDD
OUTPUT
POWER
INPUT
Internal oscillator pin. Connected to BPIN and an external resisto r and capacitor
+5V ±5%, Positive voltage of the backplane and segments
CONVOSC
Used in conjunction with CONVOUT to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
CONVOUT
OUTPUT
Used in conjunction with CONVOSC to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
VEE
S1 to S38
BPOUT
T1
POWER
OUTPUT
OUTPUT
Negative voltage of the backplane and segments - between VSS and VDD- 35V
Segment outputs to LCD display
Backplane output to LCD display (See Figure 3 for cascading drivers)
LOGIC INPUT Used in conjunction with T2 to control display mod e. Normal mode is logic low.
LOGIC INPUT Used in conjunction with T1 to control display mode. Normal mode is logic low.
T2
DOUT30
OUTPUT
OUTPUT
OUTPUT
Logic output from the 30th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
DOUT32
DOUT38
Logic output from the 32nd bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
Logic output from the 38th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver.
HOLT INTEGRATED CIRCUITS
2
HI-8050/51, HI-8150/51
FUNCTIONAL DESCRIPTION
DOUT
INPUT LOGIC
The DOUT30, DOUT32, and DOUT38 pins are available for
cascading devices to drive more segments (See Figure 3) and
for verifying the integrity of the shift register data. The outputs
can drive 2 TTL loads. They change on the positive edge of
CL .
The data is clocked into a serial shift register from the DIN in-
put on the negative edge of CL while CS is held low. LD is
normally held low and pulsed high only when data from the
shift register is parallel latched to the segment outputs. CS
must be low when LD is pulsed. The latches are transparent
while LD is high. A logic "1" in the shift register causes the
corresponding segment output to be out of phase with the AUTOMATIC SEGMENTS OFF
BP output. All four logic inputs are TTL compatible on the
HI-8050/51and CMOS compatible on the HI-8150/51.
A threshold device detects when the 5V supply is below ap-
proximately 1V and forces all the segments and the backplane
to the same level. This feature is used to discharge the VEE
capacitor when the 5V power is switched off, to prolong the life
of the LCD display.
BPOSC and BPIN
The user has the option of creating the backplane frequency
internally or providing a signal from an external source. For
an internal oscillator, BPIN and BPOSC are connected to-
gether and the appropriate R & C combination is applied as
8020OPT
shown in Figure 1. The resulting backplane frequency is ap- The CL and CS inputs function the same as the HI-8010 and
proximately:
HI-8110 product (See Figure 5) if this pin is left open or held
high. If held low, the two pins function the same as the HI-8020
and HI-8120 product (See Figure 6). This input is available
only on the HI-8050 (TTL) and HI-8150 (CMOS) products.
fBP =
1
. (R = 220KW, C = 220pF, fBP ≈ 100HZ)
256 RC
The value of the resistor must be greater than 30KW.
TEST INPUTS
Alternatively, BPOSC is left open and an external backplane
signal of the desired frequency is applied to the BPIN input.
The test functions available are:
VEE & NEGATIVE VOLTAGE CONVERTER
T2
0
0
1
1
T1 Display M ode
0
1
0
1
Normal
All Off
All On
VEE can be connected to a negative power supply. Alterna-
tively, the HI-8050 & HI-8150 have the option of generating
the VEE voltage with a built-in -25 volt negative voltage con-
verter (See Figure 2). When not used, the open CONVOSC
pin is detected and all power consuming circuitry is dis-
abled. The converter will survive a short between two seg-
ments and stillmaintain a VEE voltage of -20V.
Alternating On/Off Segments
The test inputs must be tied to the appropriate logic level for
correct circuit operation. Both test inputs are TTL compatible
on the HI-8050/51 and CMOS compatible on the HI-8150/51.
VDD
68KW
R
C
OSC
CONVOSC
R SENSE
÷ 256
Control
VDD
VDD
Q
IN5818, IN5819
CONVOUT
330µH
R
BPIN
VSS
BPOSC
C
VEE
TO BACKPLANE
TRANSLATOR
AND DRIVER
10µF
VSS
VSS
Figure 2. OPTIONAL VOLTAGE CONVERTER
Figure 1. INTERNAL OSCILLATOR CIRCUIT
HOLT INTEGRATED CIRCUITS
3
HI-8050/51, HI-8150/51
LD
CL
CS
DIN
1M W
1mF
1M W
BPOUT
CS CL LD
DIN DO
CS CL LD
CS CL LD
1mF
DIN
DO
DIN
DO
R
C
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
1M W
1mF
1M W
360p
1mF
BACK
PLANE
SEGMENTS
SEGMENTS
SEGMENTS
Figure 4. OFFSET MEASUREMENT
Figure 3. RC OSCILLATOR AND CASCADED
DEVICES
DATA IN
DATA IN
DIN ⇒
DIN ⇒
DOUT
⇒
38 Stage
38 Stage
DOUT
⇒
Shift Register
Shift Register
CL ⇒
CS ⇒
CL ⇒
CS ⇒
CLK
CLK
Figure 5. HI-8010/HI-8110 CL & CS LOGIC
(8020OPT = OPEN or HIGH)
Figure 6. HI-8020/HI-8120 CL & CS LOGIC
(8020OPT = LOW)
CL
INPUT
tCL
tCW
DIN
INPUT
tDS
tDH
CS
INPUT
tCSS
tLCS
tCSL
tCSH
LD
INPUT
tLW
tLS
tCDO
DOUT
VALID
OUTPUT (8020OPT float or high)
tCDO
DOUT
OUTPUT (8020OPT low)
VALID
VALID
Figure 7. TIMING DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-8050/51, HI-8150/51
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V
Supply Voltage VDD ..........................0V to 7V Operating Temperature Range(Industrial) ....... -40°C to +85°C
VEE................VDD-35V to 0V (Hi-Temp/Mil) ..... -55°C to +125°C
Voltage at any input, except BPIN..-0.3V to VDD+0.3V Storage Temperature .................................... -65°C to +125°C
Voltage at BPIN input ..............VDD-35V to VDD+0.3V
DC current per input pin .....................................10 mA
Power Dissipation............................................500 mW
Solder Temperature (Leads) ..................... +280°C for 10 sec.
(Package) ........................................ +220°C
Junction Temperature, Tj .......................................... £ +175°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These a re stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational section s of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD = 5V ±5%, VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
VDD
IDD
CONDITION
MIN
TYP
MAX
7.0
UNITS
V
Operating Voltage
Supply Current:
3.0
(Converter Off, fBP = 0Hz)
Static, No Load
Static, No Load
Logic Inputs
Logic Inputs
Logic Inputs
Logic Inputs
200
µA
µA
V
IEE
120
0.8
Input Low Voltage, HI-8050/51 only (except BPIN)
Input High Voltage, HI-8050/51 only (except BPIN)
Input Low Voltage, HI-8150/51 only (except BPIN)
Input High Voltage, HI-8150/51 only (except BPIN)
Input Low Voltage, BPIN
VILTTL
VIHTTL
VILCMOS
VIHCMOS
VILX
VIHX
IIN1
0
2
VDD
0.3 VDD
VDD
0.6 VDD
VDD
100
V
0
V
V
V
0.7 VDD
VEE
0.8 VDD
Input High Voltage, BPIN
V
Input Current
Input Current
(except T1 & T2)
(T1 & T2)
VIN = 0V to 5V
VIN = 0V to 5V
nA
µA
pF
KΩ
Ω
mA
mA
V
IIN2
10
Input Capacitance
(Guaranteed, not tested)
CI
RSEG
RBP
10
15
600
-3.0
Segment Output Impedance
Backplane Output Impedance
Da ta Out Current:
IL = 10µA
IL = 10µA @ 25°C
VOH = 4.5
10
450
Source Current
Sink Current
@ No Load
IDOH
IDOL
VEEC
IDD
VEEC
VOS
VOL = 0.4
See Fig. 2
3.2
-22
Voltage Converter:
-21.5
-21
1.8
(VDD - VSS = 5V, TA = 25°C)
@ 0.1mA Load
@ 10KΩ Load
See Fig. 2
See Fig. 2
See Fig. 4
mA
V
mV
-20
Offset Voltage
(Guaranteed, not tested)
25
HOLT INTEGRATED CIRCUITS
5
HI-8050/51, HI-8150/51
AC ELECTRICAL CHARACTERISTICS (See Figure 7)
VDD = 5V ±5% , VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
VDD
MIN
TYP
MAX
UNITS
Clock Period
non-cascaded
cascaded
tCL
tCL
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
250
500
125
250
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Pulse Width
non-cascaded
cascaded
tCW
tCW
tDS
Data In - Setup
Data In - Hold
tDH
80
Chip Select - Setup to Clock
Chip Select - Hold to Clock
Load - Setup to Clock
Chip Select - Setup to Load
Load Pulse Width
tCSS
tCSH
tLS
100
120
120
0
tCSL
tLW
tLCS
tCDO
130
120
Chip Select - Hold to Load
Data Out Valid, from Clock
170
HI-8051 & HI-8151 PIN CONFIGURATIONS
(See page 3-27 for the HI-8050 & HI-8150 pin configurations)
1
LD
DIN
BPIN
BPOSC
39
38
37
36
35
34
33
32
31
30
29
28
27
S26
2
S25
S24
S23
S22
S21
S20
DOUT 38
N/C
T2
3
4
HI-8051PQI
HI-8151PQI
HI-8051PQT
5
VDD
S37
S38
S1
6
7
8
&
9
S2
S3
S4
S5
HI-8151PQT
10
11
T1
BPOUT
S19
12
13
S6
HOLT INTEGRATED CIRCUITS
6
HI-8050/51, HI-8150/51
ORDERING INFORMATION
HI - 805xPQx
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
LEAD
FINISH
FLOW
I
-40°C TO + 85°C
-55°C TO +125°C
I
NO
NO
SOLDER
SOLDER
T
T
PART
NUMBER
PACKAGE
DESCRIPTION
0
1
64 PIN PLASTIC THIN FLAT QUAD PACK (TQFP)
52 PIN PLASTIC QUAD FLAT PACK ( PQFP)
PART
NUMBER
LOGIC
INPUT LEVELS
#
SEGMENTS
HI-805
HI-815
TTL
38
38
CMOS
HOLT INTEGRATED CIRCUITS
7
HI-8050/51, HI-8150/51 PACKAGE DIMENSIONS
inches (millimeters)
52 PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type: 52PQS
.0256 BSC
(0.65 BSC)
.520 ± .010
(13.2 ± .25)
.394 ± .004
(10.00 ± .10)
SQ.
SQ.
.012 ± .002
(.30 ± .05)
.035 +.006/-.004
(.88 +.15/-.10)
.079 ± .002
(2.00 ± .05)
.012 R TYP .
(0.30 R TY P.)
See Detail A
.096 MAX.
(2.45 MAX. )
0° £ Q £ 7°
.008 R TYP.
(0.20 R TYP.)
.010 to .020
(0.25 to 0.50)
DETAIL A
64 PIN PLASTIC THIN QUAD FLAT PACK (TQFP)
Package Type: 64PTQS
.0157 BSC
(0.40 BSC)
.276 ± .004
(7.00 ± .10)
SQ.
.354 ± .008
(9.00 ± .20)
SQ.
.007 ± .004
(0.18 ± .05)
.024 +.006/-.004
(0.60 +.15/-.10)
.055 ± .002
(1.4 ± .05)
.008 R TYP.
(0.20 R TYP.)
See Detail A
.063 MAX.
(1.60 MAX.)
0° £ Q £ 7°
.008 R TYP.
.004 ± .002 (0.20 R TYP.)
(0.10 ± .05)
Detail A
HOLT INTEGRATED CIRCUITS
8
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