HI-8110QIF [HOLTIC]

CMOS HIGH VOLTAGE DISPLAY DRIVER; CMOS高电压显示驱动器
HI-8110QIF
型号: HI-8110QIF
厂家: HOLT INTEGRATED CIRCUITS    HOLT INTEGRATED CIRCUITS
描述:

CMOS HIGH VOLTAGE DISPLAY DRIVER
CMOS高电压显示驱动器

显示驱动器 高压
文件: 总9页 (文件大小:110K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HI-8010/HI-8110 Series  
CMOS HIGH VOLTAGE DISPLAY DRIVER  
August 2006  
PIN CONFIGURATION (Top View)  
GENERAL DESCRIPTION  
The HI-8010 & HI-8110 high voltage display drivers  
are constructed of MOS P Channel and N Channel  
enhancement mode devices in a single monolithic  
structure. They are designed to drive high voltage  
liquid crystal displays by converting low level input  
signals (TTL on the HI-8010 and CMOS on the  
HI-8110) to high voltage drive signals.  
51 50 49 48 47 46 45 44 43 42 41 40  
LD  
DIN  
LCDØ  
LCDØOPT  
VDD  
S26  
S25  
S24  
S23  
S22  
S21  
S20  
DOUT 38  
N/C  
N/C  
N/C  
BP  
S19  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
2
HI-8010PQI  
HI-8110PQI  
HI-8010PQT  
&
3
4
5
Both devices can drive up to 38 segments and  
require minimal display-to-data source interfacing.  
Serial data is loaded and held in internal latches until  
new display data is received.  
S37  
S38  
S1  
S2  
S3  
S4  
S5  
S6  
6
7
8
HI-8110PQT  
9
10  
11  
12  
52 - PIN  
PLASTIC QFP  
The HI-8010 & HI-8110 are available in a variety of  
ceramic and plastic packaging including leaded and  
leadless chip carriers; and J-lead and gull-wing quad  
flat packs.  
14 15 16 17 18 19 20 21 22 23 24 25 26  
FEATURES  
(See page 5 for additional package pin configurations)  
! 5 volt input translated to 30 volts or less  
! Pin-out adaptable to drive 30, 32 or 38  
LCD segments  
! RC oscillator or high voltage (BP) clock input  
! TTL compatible inputs (HI-8010 only)  
! CMOS compatible inputs (HI-8110 only)  
! Low power consumption  
FUNCTIONAL BLOCK DIAGRAM  
DATA IN  
DIN Þ  
DOUT 38  
DOUT 32  
DOUT 30  
Þ
Þ
Þ
38 Stage  
Shift Register  
CL Þ  
CS Þ  
LD Þ  
! Industrial (-40°C to +85°C) & Military (-55°C  
to +125°C) temperature ranges  
CLK  
LE  
! Pin for pin compatible with the Micrel  
MIC8010/8011 series and the AMI S4520  
series drivers  
38 Bit Latch  
LCDØ Þ  
Oscillator  
Divider  
! Cascadable  
Voltage  
Translators  
LCDØ OPT Þ  
! Military level processing available  
Voltage  
Translator  
High Voltage  
Drivers  
APPLICATIONS  
High Voltage  
Buffer  
! Dichroic Liquid Crystal Displays  
! Standard Liquid Crystal Displays  
! Vacuum Fluorescent Displays  
! MEMS Drivers  
SEGMENTS  
Þ BP  
HOLT INTEGRATED CIRCUITS  
www.holtic.com  
(DS8010, Rev. E)  
08/06  
HI-8010/HI-8110 Series  
PIN DESCRIPTIONS  
SYMBOL  
VSS  
FUNCTION  
POWER  
INPUT  
DESCRIPTION  
0 Volts  
CS  
Logic input  
Chip select  
CL  
INPUT  
Logic input  
Clocks shift register on negative edge and DOUT pins on positive edge  
LD  
INPUT  
Logic input  
Segment outputs equal shift register data if Load is high  
Shift register data input  
DIN  
INPUT  
Logic input  
LCD0  
LCD0OPT  
VDD  
INPUT  
Analog input  
Analog output  
5 Volts  
Display clock input and is always bonded out. Can swing from VEE to VDD  
Bonded out only if an RC oscillator is required  
OUTPUT  
POWER  
POWER  
OUTPUT  
OUTPUT  
OUTPUT  
VEE  
0 Volts to -30 Volts  
Logic output  
Display drive output  
Display drive output  
DOUT  
BP  
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38  
Low resistance drive for the backplane and swings from VDD to VEE  
High resistance drive for each segment and swings from VDD to VEE  
Segments  
FUNCTIONAL DESCRIPTION  
on the rising edge of the Clock (CL). Clock (CL), Load (LD)  
and Chip Select (CS) should be tied in common with each  
other, respectively, between all cascaded display drivers.  
Whenever a Logic "0" is applied to the Chip Select (CS)  
input, one bit of data is clocked into the shift register from the  
serial data input (DIN) with each negative transition of the  
Clock (CL) input. CS is internally tied to VSS on some  
versions. A Logic "1" present at the Load (LD) input will  
cause a parallel transfer of data from the shift register to the  
data latch. If the Load (LD) input is held high while data is  
clocked into the shift register, the latch will be transparent.  
All four logic inputs are TTL compatible on the HI-8010 and  
CMOS compatible on the HI-8110.  
INTERNAL OSCILLATOR CIRCUIT  
To display segments, a Logic "1" is stored in the appropriate  
shift register bit position, and the segment output is out-of-  
phase with the backplane.  
R
C
The backplane output functions in 1 of 2 modes; externally  
driven or self-oscillating. When the LCDØ input is externally  
driven with the LCDØOPT input open circuit (Figure 2), the  
backplane output will be in-phase with LCDØ. Utilizing the  
self-oscillating mode, inputs LCDØ and LCDØOPT are tied  
together and connected to an RC circuit (Figure 3).  
A 150KW resistor with a 470pF capacitor generates an  
approximate backplane frequency of 100Hz. The  
LCDØ/LCDØOPT oscillator frequency is divided by 256 to  
determine the backplane output frequency. The resistor  
value (R) must be at least 30KW for proper self-oscillator  
operation.  
÷ 256  
Q
LCDØ  
LCDØ  
OPT  
TO BACKPLANE  
TRANSLATOR  
AND DRIVER  
For displays having a number of segments greater than 38,  
two or more of the display drivers may be cascaded together  
by connecting the serial data output (DOUT) from the first  
driver, to the serial data input (DIN) of the following driver,  
etc. (See Figures 2 & 3). Data out (DOUT) will change state  
Figure 1  
HOLT INTEGRATED CIRCUITS  
2
HI-8010/HI-8110 Series  
CASCADING - EXT. OSCILLATOR  
CASCADING - RC OSCILLATOR  
LD  
CL  
CS  
LD  
CL  
CS  
LD  
LD  
LD  
LD  
CS CL  
DIN  
CS CL  
DIN  
CS CL  
DIN  
CS CL  
DIN  
CS CL LD  
DOUT  
CS CL LD  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
DIN  
DIN  
150KW  
HI-8110PQI  
HI-8110PQI  
HI-8110PQI  
HI-8010J-85  
HI-8010J-85  
HI-8010J-85  
LCDØ  
BP  
LCDØ  
BP  
LCDØ  
BP  
LCDØ  
BP  
LCDØ  
BP  
LCDØ  
BP  
LCDØ OPT  
LCDØ OPT  
LCDØ OPT  
470pf  
SEGMENTS  
1 - 32  
SEGMENTS BACK  
33 - 64  
SEGMENTS  
65 - 96  
SEGMENTS  
1 - 38  
SEGMENTS BACK  
39 - 76  
SEGMENTS  
77 - 114  
PLANE  
PLANE  
Figure 2  
Figure 3  
ABSOLUTE MAXIMUM RATINGS  
Voltages referenced to VSS = 0V  
Supply Voltage  
VDD........................ 0V to 7V  
VEE................VDD-35V to 0V  
Voltage at any input, except LCDØ..-0.3 to VDD+0.3V  
Power Dissipation......................................................300 mW  
Operating Temperature Range - Industrial........-40° to +85°C  
Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C  
Storage Temperature Range...........................-65° to +150°C  
Voltage at LCDØ input...............VDD-35 to VDD+0.3V  
DC Current any input pin...................................10 mA  
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.  
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).  
PARAMETER  
Operating Voltage  
SYMBOL  
VDD  
CONDITION  
MIN  
TYP  
MAX UNITS  
3.0  
7.0  
200  
150  
0.8  
V
µA  
µA  
V
Supply Current  
IDD  
Static, No Load  
IEE  
Static, No Load fBP=100Hz  
Input Low Voltage, HI-8010 (except LCDØ)  
Input High Voltage, HI-8010 (except LCDØ)  
Input Low Voltage, HI-8110 (except LCDØ)  
VILTTL  
VIHTTL  
VILCMOS  
0
2
VDD  
0.3 VDD  
VDD  
3
V
0
V
Input High Voltage, HI-8110 (except LCDØ) VIHCMOS  
0.7 VDD  
VEE  
3.5  
V
Input Low Voltage (LCDØ)  
Input High Voltage (LCDØ)  
Input Current  
VILX  
VIHX  
IIN  
V
VDD  
1
V
VIN = 0 to 5V  
µA  
pF  
KW  
W
Input Capacitance (not tested)  
Segment Output Impedance  
Backplane Output Impedance  
Data Out Current:  
CI  
5
RSEG  
RBP  
IDOH  
IDOL  
IL = 10µA  
10  
15  
IL = 10µA @ 25°C  
450  
600  
-0.6  
Source Current, VOH = 4.5V  
Sink Current, VOL = 0.5V  
mA  
mA  
0.6  
HOLT INTEGRATED CIRCUITS  
3
HI-8010/HI-8110 Series  
AC ELECTRICAL CHARACTERISTICS  
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).  
PARAMETER  
SYMBOL  
tCL  
VDD  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
MIN  
1200  
520  
50  
TYP  
MAX  
UNITS  
ns  
Clock Period  
Clock Pulse Width  
tCW  
ns  
Data In - Setup  
tDS  
ns  
Data In - Hold  
tDH  
400  
200  
450  
500  
300  
500  
300  
ns  
Chip Select - Setup to Clock  
Chip Select - Hold to Clock  
Load - Setup to Clock  
Chip Select - Setup to Load  
Load Pulse Width  
tCSS  
tCSH  
tLS  
ns  
ns  
ns  
tCSL  
tLW  
ns  
ns  
Chip Select - Hold to Load  
Data Out Valid, from Clock  
tLCS  
tCDO  
ns  
800  
ns  
TIMING DIAGRAM  
CL  
INPUT  
tCL  
DIN  
INPUT  
VALID  
VALID  
tDS  
tDH  
CS  
INPUT  
tCSS  
tLCS  
tCSL  
tCSH  
LD  
INPUT  
tLS  
tLW  
tCDO  
DOUT  
OUTPUT  
VALID  
VALID  
VALID  
HOLT INTEGRATED CIRCUITS  
4
HI-8010/HI-8110 Series  
ADDITIONAL HI-8010/HI-8110 PIN CONFIGURATIONS  
(See page 1 for the 52-Pin Plastic QFP)  
6
5
4
3
2
1 44 43 42 41 40  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
S27  
S28  
S29  
S30  
S31  
S32  
N/C  
VSS  
CS  
S17  
S16  
S15  
VEE  
S14  
S13  
S12  
S11  
S10  
S9  
8
9
HI-8010J-85  
&
HI-8110J-85  
10  
11  
12  
13  
14  
15  
16  
17  
44 - PIN  
PLASTIC  
PLCC  
CL  
LD  
S8  
18 19 20 21 22 23 24 25 26 27 28  
6
5
4
3
2
1
48 47 46 45 44 43  
42  
5
4
3
2
1
40 39 38 37 36  
7
LCDØ  
S28  
S27  
S26  
S25  
S24  
S23  
S22  
S21  
S20  
DOUT 38  
BP  
6
35  
34  
33  
32  
31  
30  
29  
28  
27  
LCDØOPT  
S25  
8
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
LCDØOPT  
VDD  
S37  
S38  
S1  
7
VDD  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
S24  
9
HI-8010SM-32  
&
HI-8110SM-32  
HI-8010SM-36  
&
HI-8110SM-36  
8
S23  
10  
11  
12  
13  
14  
15  
16  
17  
18  
9
S22  
10  
11  
12  
13  
14  
S21  
S2  
S20  
48 - PIN  
CERAMIC  
LCC  
40 - PIN  
CERAMIC  
LCC  
S3  
DOUT 30  
BP  
S4  
S5  
S19  
S6  
S8 15  
26 S18  
S7  
S19  
19 20 21 22 23 24 25 26 27 28 29 30  
16 17 18 19 20 21 22 23 24 25  
HOLT INTEGRATED CIRCUITS  
5
HI-8010/HI-8110 Series  
ORDERING INFORMATION  
HI - 8X10 J x - 85 (44-pin Plastic J Lead - PLCC)  
PART  
NUMBER  
LEAD  
FINISH  
Tin / Lead (Sn / Pb) Solder  
Blank  
F
100% Matte Tin (Pb-free, RoHS compliant)  
PART  
NUMBER  
INPUT  
LOGIC  
NUMBER OF MASTER/  
TEMPERATURE  
RANGE  
BURN  
IN  
FLOW  
SEGMENTS  
SLAVE  
BOTH  
BOTH  
8010  
8110  
TTL  
32  
32  
-40°C TO +85°C  
-40°C TO +85°C  
I
I
NO  
NO  
CMOS  
HI - 8X10PQ x x (52-pin Plastic Quad Flat Pack - PQFP)  
PART  
NUMBER  
LEAD  
FINISH  
Tin / Lead (Sn / Pb) Solder  
Blank  
F
100% Matte Tin (Pb-free, RoHS compliant)  
PART  
NUMBER  
NUMBER OF MASTER/  
SLAVE  
TEMPERATURE  
RANGE  
BURN  
IN  
FLOW  
SEGMENTS  
I
38  
38  
BOTH  
BOTH  
-40°C TO +85°C  
-55°C TO +125°C  
I
NO  
NO  
T
T
PART  
NUMBER  
INPUT  
LOGIC  
8010PQ  
8110PQ  
TTL  
CMOS  
HI - 8X10SM -xx (Ceramic Leadless Chip Carrier - LCC)  
NUMBER  
OF LEADS  
PART  
NUMBER  
MASTER/ NUMBER OF  
SEGMENTS  
BURN LEAD  
IN  
FLOW  
SLAVE  
FINISH  
38  
30  
48  
40  
Tin / Lead (Sn / Pb) Solder  
-32  
-36  
BOTH  
BOTH  
M
M
YES  
YES Tin / Lead (Sn / Pb) Solder  
INPUT  
LOGIC  
PART  
NUMBER  
TEMPERATURE  
RANGE  
TTL  
8010SM  
8110SM  
-55°C TO +125°C  
-55°C TO +125°C  
CMOS  
HOLT INTEGRATED CIRCUITS  
6
HI-8010/HI-8110 Series  
SEMI-CUSTOM PACKAGING  
The above part numbers represent the standard configurations of the HI-8010 & HI-8110 products. They can also be provided with a  
varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed  
below are currently available packages. Please contact the Holt Sales Department for your specific requirements.  
PACKAGE  
DESCRIPTION  
#
LEADS  
PLASTIC DUAL-IN-LINE (PDIP)  
40  
48  
52  
44  
40  
48  
40  
48  
44  
48  
40  
48  
PLASTIC QUAD FLAT PACK (PQFP)  
PLASTIC J-LEAD CHIP CARRIER (PLCC)  
CERAMIC DUAL-IN-LINE (CDIP)  
CERAMIC LEADLESS CHIP CARRIER (LCC)  
CERAMIC J-LEAD CHIP CARRIER  
CERAMIC LEADED CHIP CARRIER  
HOLT INTEGRATED CIRCUITS  
7
HI-8010/HI-8110 PACKAGE DIMENSIONS  
inches (millimeters)  
44-PIN PLASTIC PLCC  
Package Type:  
44J  
PIN NO. 1  
PIN NO. 1 IDENT  
.045 x 45°  
.045 x 45°  
.050 ±.005  
(1.27 ±.127)  
.690 ±.005  
(17.526 ±.127)  
SQ.  
.653 ±.004  
(16.586 ±.102)  
SQ.  
.031±.005  
(.787 ±.127)  
.017 ±.004  
(.432 ±.102)  
SEE DETAIL  
A
.009  
.011  
.015 .002  
(.381 ±.051)  
.172 ±.008  
(4.369 ±.203)  
.020 MIN  
(.508 MIN)  
DETAILA  
.025  
R
.045  
.610 ±.020  
(15.494±.508)  
52-PIN PLASTIC QUAD FLAT PACK  
Package Type: 52PQS  
.0256 BSC  
(0.65 BSC)  
.520 ±.010  
(13.2 ±.25)  
SQ.  
.394 ±.004  
(10.00 ±.10)  
SQ.  
.012 ±.003  
(.30 ±.08)  
.035 ±.006  
(.88 ±.15)  
±
.088 .032  
(1.6 ±.175)  
Typ.  
.008  
(0.20)  
Min.  
.009 ±.003R  
(.225 ±.075R)  
See Detail A  
.079 ±.002  
(2.00 ±.05)  
.092 ±.004  
(2.32 ±.12)  
0° £ Q £ 7°  
.009 R typ  
(0.23 R  
typ)  
DETAIL A  
HOLT INTEGRATED CIRCUITS  
8
HI-8010/HI-8110 PACKAGE DIMENSIONS  
inches (millimeters)  
40-PIN CERAMIC LEADLESS CHIP CARRIER  
PACKAGE TYPE: 40S  
.085 MAX.  
(2.159 MAX.)  
.044 ±.011  
(1.118 ±.280)  
PIN 1 IDENT.  
PIN 1 IDENT.  
.484 .009  
(12.294 ±.228)  
SQ.  
.020 ±.003  
(.508 ±.076)  
.040 ± .003  
(1.016 ±.076)  
48-PIN CERAMIC LEADLESS CHIP CARRIER  
Package Type: 48S  
.040 ±.007  
(1.016 ±.178)  
PIN 1 IDENT.  
.090 MAX.  
(2.286 MAX.)  
PIN 1 IDENT.  
.563 ±.009  
(14.300 ±.228)  
SQ.  
.020 TYP.  
(.508 TYP.)  
.040 TYP.  
(1.016 TYP.)  
HOLT INTEGRATED CIRCUITS  
9

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