HI-3582APCTF [HOLTIC]
ARINC 429 3.3V Terminal IC with High-Speed Interface; ARINC 429 3.3V终端芯片与高速接口
| 型号： | HI-3582APCTF |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | ARINC 429 3.3V Terminal IC with High-Speed Interface |
| 文件： | 总17页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-3582A, HI-3583A
ARINC 429
3.3V Terminal IC with High-Speed Interface
July 2013
GENERALDESCRIPTION
APPLICATIONS
The HI-3582A/HI-3583A from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582A/HI-3583A design offers a high-speed host CPU
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver.
Up to 16 labels may be programmed for each receiver.
The independent transmitter has a 32 X 32 FIFO and a
built-in line driver. The status of all three FIFOs can be
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit,
and the ability to unscramble the 32 bit word. Also,
versions are available with different values of input
resistance and output resistance to allow users to more
easily add external lightning protection circuitry.
•
•
•
Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
N/C
-
1
2
3
4
5
6
7
8
9
48 - CWSTR
47 - ENTX
46 - N/C
D/R1 -
FF1 -
HF1 -
D/R2 -
FF2 -
HF2 -
HI-3582APCI
HI-3582APCT
HI-3582APCM
&
HI-3583APCI
HI-3583APCT
HI-3583APCM
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41 - N/C
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
SEL -
EN1 -
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
36 - PL1
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are 3.3V CMOS compatible.
35 - BD00
34 - BD01
33 - N/C
The HI-3582A/HI-3583A apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FEATURES
·
·
·
·
ARINC specification 429 compatible
High-speed 3.3V logic interface
Dual receiver and transmitter interface
Analog line driver and receivers connect directly to
ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for transmitter and
each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
FF1 -
HF1 -
D/R2 -
FF2 -
HF2 -
SEL -
EN1 -
EN2 -
BD15 -
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
1
2
3
4
5
6
7
8
9
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
HI-3582APQI
HI-3582APQT
HI-3582APQM
&
HI-3583APQI
HI-3583APQT
HI-3583APQM
·
·
·
·
·
·
·
·
·
·
27 - BD00
Industrial & extended temperature ranges
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS3582A Rev. C)
07/13
HI-3582A, HI-3583A
PIN DESCRIPTIONS
SIGNAL
VDD
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
DESCRIPTION
+3.3V power supply pin
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
HF1
FIFO Half full, Receiver 1
D/R2
FF2
Receiver 2 data ready flag
FIFO full Receiver 2
HF2
FIFO Half full, Receiver 2
SEL
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
Data Bus control, enables receiver 1 data to outputs
EN2
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
POWER
I/O
0 V
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
INPUT
INPUT
OUTPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
PL2
TX/R
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
HFT
FFT
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT
POWER
INPUT
Transmitter FIFO Half Full
Transmitter FIFO Full
V-
-9.5V to -10.5V
TXAOUT
TXBOUT
V+
Line driver output - A side
Line driver output - B side
+9.5V to +10.5V
ENTX
CWSTR
RSR
Enable Transmission
INPUT
Clock for control word register
Read Status Register if SEL=0, read Control Register if SEL=1
Master Clock input
INPUT
CLK
INPUT
TX CLK
MR
OUTPUT
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
TEST
INPUT
Disable Transmitter output if high (pull-down)
HOLT INTEGRATED CIRCUITS
2
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
STATUS REGISTER
The HI-3582A/HI-3583A contain a 9-bit status register which can
be interrogated to determine the status of the ARINC receivers,
data FIFOs and transmitter. The contents of the status register are
output on BD00 - BD08 when the RSR pin is taken low and
SEL = 0. Unused bits are output as Zeros. The following table
defines the status register bits.
The HI-3582A/HI-3583A contain a 16-bit control register which is
used to configure the device. The control register bits CR0 - CR15
are loaded from BD00 - BD15 when CWSTR is pulsed low. The
control register contents are output on the databus when SEL = 1
and RSR is pulsed low. Each bit of the control register has the
following function:
SR
Bit
CR
Bit
FUNCTION
STATE
DESCRIPTION
FUNCTION
STATE
DESCRIPTION
CR0
Receiver 1
Data clock
Select
0
1
0
1
Data rate = CLK/10
Data rate = CLK/80
Normal operation
SR0
Data ready
(Receiver 1)
0
1
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
CR1
Label Memory
Read / Write
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
SR1
SR2
SR3
SR4
SR5
FIFO half full
(Receiver 1)
0
1
Receiver 1 FIFO holds less than 16
words
CR2
CR3
CR4
CR5
Enable Label
Recognition
(Receiver 1)
0
1
0
1
0
1
0
Disable label recognition
Enable label recognition
Disable Label Recognition
Enable Label recognition
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
Enable Label
Recognition
(Receiver 2)
FIFO full
(Receiver 1)
0
1
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
Enable
32nd bit
as parity
Self Test
The transmitter’s digital
outputs are internally connected
to the receiver logic inputs
Data ready
(Receiver 2)
0
1
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
1
0
1
Normal operation
CR6
Receiver 1
decoder
Receiver 1 decoder disabled
FIFO half full
(Receiver 2)
0
1
Receiver 2 FIFO holds less than 16
words
ARINC bits 9 and 10 must match
CR7 and CR8
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
CR7
CR8
CR9
-
-
-
-
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
FIFO full
(Receiver 2)
0
1
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
Receiver 2
Decoder
0
1
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
SR6 Transmitter FIFO
empty
0
1
0
1
Transmitter FIFO not empty
Transmitter FIFO empty.
Transmitter FIFO not full
CR10
CR11
CR12
-
-
-
-
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
SR7 Transmitter FIFO
full
Transmitter FIFO full. FFT pin is the
inverse of this bit.
Invert
Transmitter
parity
0
1
0
1
0
1
0
1
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Data rate=CLK/10, O/P slope=1.5us
Data rate=CLK/80, O/P slope=10us
Data rate=CLK/10
SR8 Transmitter FIFO
half full
0
1
Transmitter FIFO contains less than
16 words
CR13
CR14
CR15
Transmitter
data clock
select
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
Receiver 2
data clock
select
Data rate=CLK/80
Data
format
Scramble ARINC data
Unscramble ARINC data
HOLT INTEGRATED CIRCUITS
3
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
The HI-3582A/HI-3583Aguarantee recognition of these levels with a
common mode Voltage with respect to GND less than 4V for the
worst case condition (3.0V supply and 13V signal level).
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582A/
HI-3583A data bus during data read or write operations. The
following table describes this mapping:
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
ARINC
BIT
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
CR15=0
ARINC
BIT
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
CR15=1
HIGH SPEED
LOW SPEED
BIT RATE
PULSE RISE TIME 1.5 0.5 µsec
PULSE FALL TIME 1.5 0.5 µsec
100K BPS 1% 12K -14.5K BPS
BYTE 2
10 5 µsec
10 5 µsec
5 µsec 5% 34.5 to 41.7 µsec
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PULSE WIDTH
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
The HI-3582A/HI-3583A accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
operation achieves this is described below:
CR15=0
ARINC
BIT
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CR15=1
1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
THE RECEIVERS
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register. In this
manner the minimum pulse width is guaranteed.
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
DIFFERENTIALVOLTAGE
ONE
NULL
ZERO
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
vDD
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
HIGH SPEED LOW SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
10.4K BPS
15.6K BPS
RIN1A
OR
RIN2A
ONES
NULL
GND
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
vDD
ZEROES
RIN1B
OR
RIN2B
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
FIFO
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
matches
label
bits 9,10
match
CR7,8 (10,11)
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
0
1
1
0
0
1
1
1
1
X
No
Yes
X
0
0
0
1
1
1
1
1
1
X
X
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
Therefore, the 32nd bit retrieved from the receiver FIFO will
always be “0” when valid (odd parity) ARINC 429 words are
received.
X
No
Yes
No
Yes
No
Yes
X
RETRIEVING DATA
Yes
No
No
Yes
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
TO PINS
SEL
MUX
CONTROL
BITS
R/W
CONTROL
32 TO 16 DRIVER
CONTROL
EN
HF
FF
D/R
32 X 32
FIFO
LOAD
CONTROL
FIFO
LABEL /
DECODE
COMPARE
CONTROL
BIT
/
CLOCK
OPTION
CONTROLBITS
CR0, CR14
CLK
CLOCK
16 x 8
LABEL
MEMORY
BIT
COUNTER
AND
END OF
32ND
BIT
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
SEQUENCE
BIT CLOCK
EOS
WORD GAP
TIMER
WORD GAP
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
ZEROS
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until both
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating EN with SEL, the
byte selector, low to retrieve the first byte and then activating EN
with SEL high to retrieve the second byte. EN1 retrieves data
from receiver 1 and EN2 retrieves data from receiver 2.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (EN taken low) are labels. EN1 is
used to read labels for receiver 1, and EN2 to read labels for
receiver 2. Label data is presented on BD0-BD7.
When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full.
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO
contains 16 or more receivedARINC words. The HF1 (HF2) pin is
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the
HI-3582A/HI-3583Astatus register bits.
TRANSMITTER
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the FFT flag is asserted and the
FIFO ignores further attempts to load data.
LABELRECOGNITION
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00 - BD07 are
always compared to receivedARINC bits 1 - 8 respectively.
A transmitter FIFO half-full flag HFT is provided. When the
transmit FIFO contains less than 16 words, HFT is high,
indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
LOADING LABELS
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If Cr4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treated as data and are transmitted.
After a write that takes CR1 from 0 to 1, the next 16 writes of
data (PL pulsed low) load label data into each location of the
label memory from the BD00 - BD07 pins. The PL1 pin is used to
write label data for receiver 1 and PL2 for receiver 2. Note that
ARINC word reception is suspended during the label memory
write sequence.
CR4,12
DATA AND
TXAOUT
BIT CLOCK
PARITY
GENERATOR
LINE DRIVER
NULL TIMER
SEQUENCER
32 BIT PARALLEL
LOAD SHIFT REGISTER
TXBOUT
TEST
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
START
SEQUENCE
ADDRESS
32 x 32 FIFO
TX/R
HFT
WORD COUNTER
AND
FIFO CONTROL
FFT
LOAD
ENTX
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
CLK
DATA CLOCK
DIVIDER
TX CLK
CR13
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
6
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in
the data transmission shift register are presented sequentially to
the outputs in theARINC 429 format with the following timing:
The HI-3582A has 37.5 ohms in series with each line driver output.
The HI-3583A has 10 ohms in series. The HI-3583A is for
applications where external series resistance is needed, typically
for lightning protection devices.
REPEATER OPERATION
Repeater mode of operation allows a data word that has been
received by the HI-3582A/HI-3583A to be placed directly into the
transmitter FIFO. Repeater operation is similar to normal receiver
operation. In normal operation, either byte of a received data word
may be read from the receiver latches first by use of SEL input.
During repeater operation however, the lower byte of the data word
must be read first. This is necessary because, as the data is being
read, it is also being loaded into transmitter FIFO which is always
loaded with the lower byte of the data word first. Signal flow for
repeater operation is shown in the Timing Diagrams section.
HIGH SPEED LOW SPEED
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
10 Clocks
5 Clocks
5 Clocks
40 Clocks
80 Clocks
40 Clocks
40 Clocks
320 Clocks
WORD GAP TIME
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
HI-3582A-15 and HI-3583A-15
The parity generator counts the Ones in the 31-bit word. If
control register bit CR12 is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
Setting CR4 to a Zero bypasses the parity generator, and allows
32 bits of data to be transmitted.
The HI-3582A-15/HI-3583A-15 options are similar to the HI-3582A/
HI-3583A with the exception that they allow an external 15 Kohm
resistor to be added in series with each ARINC input without affect-
ing the ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
SELF TEST
Each side of the ARINC bus must be connected through a
15 Kohm series resistor in order for the chip to detect the correct
ARINC levels. The typical 10 volt differential signal is translated
and input to a window comparator and latch. The comparator lev-
els are set so that with the external 15 Kohm resistors, they are
just below the standard 6.5 volt minimum ARINC data threshold
and just above the standard 2.5 volt maximum ARINC null thresh-
old.
If control register bit CR5 is set low, the transmitter serial output
data are internally connected to each of the two receivers,
bypassing the analog interface circuitry. Data is passed
unmodified to receiver 1 and inverted to receiver 2. Taking TEST
high forces TXAOUT and TXBOUT into the null state regardless
of the state of CR5.
SYSTEM OPERATION
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
The two receivers are independent of the transmitter.
Therefore, control of data exchanges is strictly at the option of
the user. The only restrictions are:
HIGH SPEED OPERATION
1. The received data will be overwritten if the receiver FIFO
is full and at least one location is not retrieved before the next
complete ARINC word is received.
The HI-3582A and HI-3583A may be operated at clock frequencies
beyond that required for ARINC compliant operation. For operation
at Master Clock (CLK) frequencies up to 5MHz, please contact
Holt applications engineering.
2. The transmitter FIFO can store 32 words maximum and
ignores attempts to load additional data if full.
MASTER RESET (MR)
LINE DRIVER OPERATION
On a Master Reset data transmission and reception are immedi-
ately terminated, all three FIFOs are cleared as are the FIFO flags
at the device pins and in the Status Register. The Control
Register is not affected by a Master Reset.
The line driver in the HI-3582A/HI-3583A are designed to directly
drive the ARINC 429 bus. The two ARINC outputs (TXAOUT
and TXBOUT) provide a differential voltage to produce a +10 volt
One, a -10 volt Zero, and a 0 volt Null. Control register bit CR13
controls both the transmitter data rate, and the slope of the
differential output signal. No additional hardware is required to
control the slope. Programming CR13 to Zero causes a
100 kbits/s data rate and a slope of 1.5 µs on the ARINC outputs;
a One on CR13 causes a 12.5 kbit/s data rate and a slope of
10 µs. Timing is set by on-chip resistor and capacitor and tested
to be withinARINC requirements.
HOLT INTEGRATED CIRCUITS
7
HI-3582A, HI-3583A
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
DATA
NULL
DATA
DATA
NULL
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
RECEIVER OPERATION
BIT 31
BIT 32
ARINC DATA
D/R, HF, FF
tEND/R
tD/R
DON'T CARE
SEL
EN
tEN
tSELEN
tSELEN
tD/REN
tSELEN
tENSEL
tENSEL
tENEN
tREADEN
CLK
tCLKEN
tCLKEN
tDATAEN
tDATAEN
BYTE 1 VALID
BYTE 2 VALID
BYTE 1
DATA BUS
tENDATA
tENDATA
tENDATA
TRANSMITTER OPERATION
BYTE 2 VALID
DATA BUS
PL1
BYTE 1 VALID
tDWSET
tDWSET
tDWHLD
tDWHLD
tPL12
tPL
tPLCYC
PL2
tPL12
tPL
tTX/R
TX/R, FFT
HFT
tHFT
LOADING CONTROL WORD
VALID
DATA BUS
tCWSET
tCWHLD
CWSTR
tCWSTR
HOLT INTEGRATED CIRCUITS
8
HI-3582A, HI-3583A
TIMING DIAGRAMS (cont.)
STATUS REGISTER READ CYCLE
DON'T CARE
DON'T CARE
BYTE SELECT SEL
RSR
tSELEN
tENSEL
tDATAEN
DATA VALID
DATA BUS
tENDATA
CONTROL REGISTER READ CYCLE
BYTE SELECT SEL
RSR
DON'T CARE
DON'T CARE
tSELEN
tENSEL
tDATAEN
DATA VALID
DATA BUS
tENDATA
LABEL MEMORY LOAD SEQUENCE
tCWSTR
CWSTR
tCWHLD
tCWSET
DATA BUS
Set CR1=1
Label #1
Label #2
Label #16
Set CR1=0
tDWSET
tDWHLD
PL1 or PL2
tPL
tLABEL
LABEL MEMORY READ SEQUENCE
tCWSTR
CWSTR
tREADEN
EN1 or EN2
tCWHLD
tCWSET
tDATAEN
DATA BUS
Set CR1=1
Label #1
Label #2
Label #16
Set CR1=0
tENDATA
HOLT INTEGRATED CIRCUITS
9
HI-3582A, HI-3583A
TIMING DIAGRAMS (cont.)
TRANSMITTING DATA
PL2
tDTX/R
tPL2EN
TXR
tENTX/R
ENTX
ARINC BIT
DATA
BIT 1
ARINC BIT
DATA
BIT 2
ARINC BIT
tENDAT
DATA
BIT 32
+5V
+5V
TXAOUT
TXBOUT
-5V
+5V
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(TXAOUT) - TXBOUT)
tfx
trx
10%
10%
trx
90%
one level
zero level
null level
-10V
REPEATER OPERATION TIMING
BIT 32
RIN
D/R
EN
tEND/R
tD/R
tD/REN
tEN
tENEN
tEN
tSELEN
tENSEL
DON'T CARE
DON'T CARE
SEL
PL1
tSELEN
tENPL
tPLEN
tENSEL
tPLEN
tENPL
PL2
TXR
tTX/R
tTX/REN
tENTX/R
ENTX
tDTX/R
tENDAT
TXAOUT
TXBOUT
BIT 1
BIT 32
tNULL
HOLT INTEGRATED CIRCUITS
10
HI-3582A, HI-3583A
ABSOLUTE MAXIMUM RATINGS
Power Dissipation at 25°C
Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C
Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/°C
Supply Voltages VDD ......................................... -0.3V to +4.0V
V+ ......................................................... +11.0V
V- ......................................................... -11.0V
DC Current Drain per pin .............................................. 10mA
Storage Temperature Range ........................ -65°C to +150°C
Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B .. -120V to +120V
Voltage at any other pin ............................... -0.3V to VDD +0.3V
Solder temperature (Reflow) ............................................ 260°C
Operating Temperature Range (Industrial): .... -40°C to +85°C
(Extended): ....-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
11
HI-3582A, HI-3583A
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V , V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
TYP
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
MAX
ARINC INPUTS
-
Pins RIN1A, RIN1B, RIN2A, RIN2B
Differential Input Voltage:
(RIN1A to RIN1B, RIN2A to RIN2B)
ONE
ZERO
NULL
VIH
VIL
VNUL
Common mode voltages
less than 4V with
respect to GND
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
Input Resistance:
Input Current:
Differential
To GND
To VDD
RI
RG
RH
12
12
12
80
45
40
KW
KW
KW
Input Sink
Input Source
IIH
IIL
200
µA
µA
-450
Input Capacitance:
(Guaranteed but not tested)
Differential
To GND
To VDD
CI
CG
CH
(RIN1A to RIN1B, RIN2A to RIN2B)
20
20
20
pF
pF
pF
BI-DIRECTIONAL INPUTS - Pins BD00 - BD15
Input Voltage:
Input Current:
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
-1.5
V
V
30% VDD
1.5
Input Sink
Input Source
IIH
IIL
µA
µA
OTHER INPUTS
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
-1.5
V
V
30% VDD
1.5
Input Current:
Input Sink
Input Source
Pull-down Current (TEST Pin)
Pull-up Current (RSR Pin)
IIH
IIL
IPD
IPU
µA
µA
µA
µA
330
-330
ARINC OUTPUTS - Pins TXAOUT, TXBOUT
ARINC output voltage (Ref. To GND)
One or zero
Null
VDOUT
VNOUT
No load and magnitude at pin,
VDD = 3.3 V
4.50
-0.25
5.00
10.0
5.50
0.25
V
V
ARINC output voltage (Differential)
One or zero
Null
VDDIF
VNDIF
No load and magnitude at pin,
VDD = 3.3 V
9.0
-0.5
11.0
0.5
V
V
ARINC output current
IOUT
80
mA
OTHER OUTPUTS
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
VDD - 0.2V
1.6
V
V
10% VDD
-1.0
Output Current:
(All Outputs & Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
mA
mA
Output Capacitance:
CO
15
pF
Operating Voltage Range
VDD
V+
3.15
9.5
3.45
10.5
-10.5
V
V
V
V-
-9.5
Operating Supply Current
VDD
V+
IDD1
IDD2
IEE1
3.5
7.5
5.5
7
mA
mA
mA
10
10
V-
HOLT INTEGRATED CIRCUITS
12
HI-3582A, HI-3583A
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle
LIMITS
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
25
25
5
ns
ns
ns
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
Delay - D/R LOW to EN LOW
Delay - EN HIGH to D/R HIGH
tD/REN
tEND/R
0
ns
ns
25
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
tSELEN
tENSEL
0
10
ns
ns
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
50
20
ns
ns
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW (Same ARINC Word)
Spacing -EN HIGH to next EN LOW (Next ARINC Word)
CLK HIGH separation from second EN pulse HIGH (SEL is HIGH)
tEN
tENEN
tREADEN
tCLKEN
50
70
70
25
ns
ns
ns
ns
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - PL1 or PL2
tPL
30
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
30
10
ns
ns
Spacing - PL1 or PL2
Spacing - PL1 rising to PL2 rising
Spacing between Label Write pulses
tPL12
tPLCYC
tLABEL
40
40
ns
ns
ns
tCLK-10
Delay - PL2 HIGH to TX/R LOW
Delay - PL2 HIGH to HFT low
tTX/R
tHFT
30
25
ns
ns
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX LOW
tPL2EN
tDTX/R
0
0
ns
ns
ns
50
tENTX/R
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed
Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed
tENDAT
tENDAT
25
200
µs
µs
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0)
high to low
low to high
tfx
trx
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
(Low Speed, control register CR13 = Logic 1)
high to low
low to high
tfx
trx
5.0
5.0
10
10
15
15
µs
µs
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
Hold - PL HIGH to EN HIGH
tENPL
tPLEN
tTX/REN
tMR
0
0
ns
ns
ns
ns
Delay - TX/R LOW to ENTX HIGH
0
MASTER RESET PULSE WIDTH
175
ARINC DATA RATE AND BIT TIMING
1%
HOLT INTEGRATED CIRCUITS
13
HI-3582A, HI-3583A
ADDITIONAL HI-3582A / HI-3583A PIN CONFIGURATIONS
FF1 - 8
HF1 - 9
D/R2 - 10
FF2 - 11
HF2 - 12
SEL - 13
EN1 - 14
EN2 -15
BD15 - 16
BD14 - 17
BD13 - 18
BD12 - 19
BD11 - 20
46 - N/C
45 - CWSTR
44 - ENTX
43 - V+
42 - TXBOUT
41 - TXAOUT
40 - V-
39 - FFT
38 - HFT
37 - TX/R
36 - PL2
35 - PL1
HI-3582ACJI
HI-3582ACJT
HI-3582ACJM
&
HI-3583ACJI
HI-3583ACJT
HI-3583ACJM
34 - BD00
52 - Pin Cerquad J-Lead
(See page 1 for additional pin configuration)
ORDERING INFORMATION
HI - 358xA xx x x - xx
PART
INPUT SERIES RESISTANCE
NUMBER
BUILT-IN REQUIRED EXTERNALLY
No dash number 35K Ohm
-15 20K Ohm
0
15K Ohm
PART PACKAGE
NUMBER DESCRIPTION
Blank
F
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
PART TEMPERATURE
NUMBER RANGE
BURN
IN
FLOW
I
-40°C TO +85°C
I
No
No
T
M
-55°C TO +125°C
-55°C TO +125°C
T
M
Yes
PART PACKAGE
NUMBER DESCRIPTION
CJ
PC
PQ
52 PIN J-LEAD CERQUAD (52U) not available Pb-free
64 PIN PLASTIC CHIP-SCALE LPCC (64PCS)
52 PIN PLASTIC QUAD FLAT PACK PQFP (52PTQS)
PART
OUTPUT SERIES RESISTANCE
NUMBER
BUILT-IN
37.5 Ohms
10 Ohms
REQUIRED EXTERNALLY
3582A
3583A
0
27.5 Ohms
HOLT INTEGRATED CIRCUITS
14
HI-3582A, HI-3583A
REVISION HISTORY
P/N
Rev
Date
Description of Change
DS3582A NEW 02/12/09 New document
A
B
C
04/27/10 Added CLKEN to timing parameters
06/29/10 Added PLCYC to timing parameters
07/25/13 Updated Receiver Parity function, QFN and PQFP package drawings, timing parameter
tSELEN and solder temperature parameters. Remove note on heat sink connection for QFN
package. Update Voltage at ARINC input pins from +/-115V to +/-120V
HOLT INTEGRATED CIRCUITS
15
HI-3582A / HI-3583A PACKAGE DIMENSIONS
inches (millimeters)
52-PIN J-LEAD CERQUAD
Package Type: 52U
7
1 52
47
8
max
SQ.
.788
(20.0)
.720 ±.010
(18.29 ±.25)
.750 ±.007
(19.05 ±.18)
.190
(4.826)
max
.040 ± .005
(1.02 ± .013)
.019 ±.002
(.483 ±.051)
.050
(1.27)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BSC
52-PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 52PQS
.0256
BSC
(.65)
.520
(13.2)
.394
(10.0)
BSC SQ
BSC SQ
.012 .004
(.310 .09)
.035 .006
(.88 .15)
.063
(1.6)
typ
.008
min
(.20)
See Detail A
.005
R min
(.13)
.106
(2.7)
MAX.
.079 .008
(2.0 .20)
0° £ Q £ 7°
.005
(.13)
R min
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
D
ETAIL A
HOLT INTEGRATED CIRCUITS
16
HI-3582A / HI-3583A PACKAGE DIMENSIONS
inches (millimeters)
64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 64PCS
Electrically isolated heat
sink pad on bottom of
package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.354
(9.00)
BSC
.268 .039
(6.80 .05)
.0197
BSC
(0.50)
.354
(9.00)
.268 .039
(6.80 .05)
BSC
Top View
Bottom
View
.010
typ
(0.25)
.016 .002
(0.40 .05)
.008
(0.20)
typ
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.039
(1.00)
max
HOLT INTEGRATED CIRCUITS
17
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