HT16L21V110 [HOLTEK]
RAM Mapping 32×4 LCD Driver; 内存映射32 × 4 LCD驱动器
| 型号： | HT16L21V110 |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | RAM Mapping 32×4 LCD Driver |
| 文件： | 总32页 (文件大小：1392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT16L21
RAM Mapping 32×4 LCD Driver
Feature
Applications
•ꢀ Logicꢀoperatingꢀvoltage:ꢀ1.8V~5.5V
•ꢀ Leisureꢀproducts
•ꢀ LCDꢀoperatingꢀvoltageꢀ(VLCD):ꢀ2.4V~6.0V
•ꢀ ExternalꢀVLCDꢀpinꢀtoꢀsupplyꢀLCDꢀoperatingꢀvoltage
•ꢀ Internalꢀ32kHzꢀRCꢀoscillator
•ꢀ Games
•ꢀ Telephoneꢀdisplay
•ꢀ Audioꢀcomboꢀdisplay
•ꢀ Videoꢀplayerꢀdisplay
•ꢀ Kitchenꢀapplianceꢀdisplay
•ꢀ Measurementꢀequipmentꢀdisplay
•ꢀ Householdꢀappliance
•ꢀ Consumerꢀelectronics
•ꢀ Bias:ꢀ1/2ꢀorꢀ1/3;ꢀDuty:1/4
•ꢀ InternalꢀLCDꢀbiasꢀgenerationꢀwithꢀvoltage-followerꢀ
buffers
•ꢀ IntegratedꢀregulatorꢀtoꢀadjustꢀLCDꢀoperatingꢀvoltage:ꢀ
3.0V,ꢀ3.2V,ꢀ3.3V,ꢀ3.4V,ꢀ4.4V,ꢀ4.5V,ꢀ4.6V,ꢀ5.0V
•ꢀ IntegratedꢀLEDꢀdriver
•ꢀ SupportꢀI2CꢀorꢀSPIꢀ3-wireꢀserialꢀinterfaceꢀ
controlledꢀbyꢀIFSꢀpin
General Description
TheꢀHT16L21ꢀdeviceꢀisꢀaꢀmemoryꢀmappingꢀandꢀ
multi-functionꢀLCDꢀcontroller/driver.ꢀTheꢀdisplayꢀ
segmentsꢀofꢀtheꢀdeviceꢀareꢀ128ꢀpatternsꢀ(32ꢀsegmentsꢀ
andꢀ4ꢀcommons)ꢀdisplay.ꢀItꢀcanꢀalsoꢀsupportꢀLEDꢀ
driveꢀoutputsꢀonꢀcertainꢀSegmentꢀpins.ꢀTheꢀsoftwareꢀ
configurationꢀ featureꢀ ofꢀ theꢀ HT16L21ꢀ deviceꢀ
makesꢀitꢀsuitableꢀforꢀmultipleꢀLCDꢀapplicationsꢀ
includingꢀLCDꢀmodulesꢀandꢀdisplayꢀsubsystems.ꢀ
TheꢀHT16L21ꢀdeviceꢀcommunicatesꢀwithꢀmostꢀ
microprocessors/microcontrollersꢀviaꢀaꢀtwo-wireꢀ
bidirectionalꢀI2Cꢀorꢀaꢀthree-wireꢀSPIꢀinterface.
•ꢀ FourꢀselectableꢀLCDꢀframeꢀfrequencies:ꢀ
64Hzꢀorꢀ85.3Hzꢀorꢀ128Hzꢀorꢀ170.6Hz
•ꢀ 32×4ꢀbitsꢀRAMꢀforꢀdisplayꢀdataꢀstorage
•ꢀ Max.ꢀ32×4ꢀpixel:ꢀ32ꢀsegmentsꢀandꢀ4ꢀcommons
•ꢀ Supportꢀtwoꢀdriverꢀoutputꢀmodeꢀsegment/LEDꢀonꢀ
SEG24~SEG31/LED7~LED0
•ꢀ Versatileꢀblinkingꢀmodes:ꢀoff,ꢀ0.5Hz,ꢀ1Hz,ꢀ2Hz
•ꢀ R/Wꢀaddressꢀautoꢀincrement
•ꢀ Lowꢀpowerꢀconsumption
•ꢀ ManufacturedꢀinꢀsiliconꢀgateꢀCMOSꢀprocess
•ꢀ Packageꢀtypes:ꢀ44LQFP
Rev. 1.10
1
December 27, 2011
HT16L21
Block Diagram
VDD voltage supported range
RSTB
VDD
Power_on reset
VSS
SDA/DIO
SCL/CLK
CSB
Internal RC
Oscillator
Timing
generator
Column
/Segment
driver
I2C or 3-wire
Controller
COM0
COM3
8
output
Display RAM
IFS
VEꢀbit
VLCD
Regulator
SEG0
－
R
OP1
＋
SEG23
Segment
/LED driver
output
LCD
Voltage
Selector
SEG24/LED7
R
R
－
OP0
＋
SEG31/LED0
LCD bias generator
VLCD voltage supported range
Pin Assignment
44 43 42 41 40 39 38 37 36 35 34
33
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
1
CSB
CLK/SCL
DIO/SDA
RSTB
VDD
VLCD
COM0
32
31
30
29
28
27
26
25
24
23
2
3
4
5
6
7
8
9
10
11
HT16L21
44 LQFP
COM1
COM2
COM3
SEG0
12 13 14 15 16 17 18 19 20 21 22
Rev. 1.10
2
December 27, 2011
HT16L21
Pin Description
Pin Name
Type
Description
Serial data input/output pin
● Serial data (SDA) input/output for 2-wire I2C interface is an NMOS
open drain structure.
SDA/DIO
I/O
● Serial data (DIO) input/output for 3-wire SPI interface is a CMOS
input/output structure.
Serial clock input pin
● Serial data (SCL) is clock input for 2-wire I2C interface.
● Serial data (CLK) is clock input for 3-wire SPI interface
SCL/CLK
CSB
I
I
Chip select pin
This pin is available for 3-wire SPI interface and not used for I2C interface.
Communication interface select pin
This pin is used to select the communication interface. When this pin is
connected to VDD, the device communicates with MCU or microprocessors
via a 2-wire I2C interface. When this pin is connected to VSS, the device
communicates with MCU or microprocessors using a 3-wire SPI interface.
IFS
I
COM0~COM3
O
O
O
LCD common outputs
SEG0~SEG23
LCD segment outputs
SEG24/LED7~SEG31/LED0
LCD segment/LED multiplexed driver outputs
Reset input pin
1. This pin is used to initialize all the internal registers and the commands pin.
2. If use internal power on reset circuit only, the RSTB pin must be connected
RSTB
I
to VDD
.
VDD
VSS
—
—
—
Positive power supply
Negative power supply, ground.
LCD power supply pin
VLCD
Approximate Internal Connections
SCL, SDA (for schmit Trigger type)
COM0~COM4; SEG0~SEG31
DIO (for Schmitt trigger type)
VDD
Vselect-on
Vselect-off
LED0~7
VSS
VSS
IFS,
RSTB
CSB, CLK (for schmit Trigger type)
VDD
VDD
VSS
VSS
VSS
Rev. 1.10
3
December 27, 2011
HT16L21
ꢀ
Storageꢀtemperatureꢀꢀ......................... -55°Cꢀtoꢀ+150°Cꢀ
Operatingꢀtemperatureꢀꢀ....................... -40°Cꢀtoꢀ+85°Cꢀ
Absolute Maximum Ratings
Supplyꢀvoltageꢀꢀ........................ VSS−0.3VꢀtoꢀVSS+6.6Vꢀ
Inputꢀvoltageꢀꢀ.......................... VSS−0.3VꢀtoꢀVDD+0.3Vꢀ
LEDꢀdriverꢀoutputꢀcurrentꢀ(total)........................88mA
Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ"AbsoluteꢀMaximumꢀRatings"ꢀ
mayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheꢀdevice.ꢀFunctionalꢀoperationꢀofꢀthisꢀdeviceꢀatꢀotherꢀconditionsꢀbeyondꢀ
thoseꢀlistedꢀinꢀtheꢀspecificationꢀisꢀnotꢀimpliedꢀandꢀprolongedꢀexposureꢀtoꢀextremeꢀconditionsꢀmayꢀaffectꢀdeviceꢀ
reliability.
Timing Diagrams
I2C Timing
SDA
t
BUF
tSU:DAT
t
f
tHD:STA
tSP
t
LOW
tr
SCL
tHD:STA
tSU:STO
t
HD:DAT
t
HIGH
t
SU:STA
S
P
S
Sr
tAA
SDA
OUT
SPI Timing
tCSW
90%
VDD
90%
CSB
10%
10%
VSS
tCSL
tSYS
tCSH
90%
VDD
90%
90%
90%
CLK
tCW
tCW
10%
tDS
10%
10%
10%
VSS
VDD
tHS
90% 90%
10% 10%
DIO
(INPUT )
VSS
VDD
tPD
tPD
90%
90%
10%
DIO
(OUTPUT )
10%
VSS
Rev. 1.10
4
December 27, 2011
HT16L21
Reset Timing
80%
tSR
0.9V
0.9V
VDD
tRSON
tPOF
tRW
50%
50%
50%
50%
RSTB
tRSOFF
tRSOFF
tRSOFF
Data
transfer
50%
50%
50%
Note:ꢀ1.ꢀIfꢀtheꢀconditionsꢀofꢀresetꢀtimingꢀareꢀnotꢀsatisfiedꢀinꢀpowerꢀON/OFFꢀsequence,ꢀtheꢀinternalꢀpowerꢀonꢀresetꢀ
(POR)ꢀcircuitꢀwillꢀnotꢀoperateꢀnormally.
2.ꢀIfꢀtheꢀVDDꢀdropsꢀlowerꢀthanꢀtheꢀminimumꢀoperatingꢀvoltageꢀduringꢀoperating,ꢀtheꢀconditionsꢀofꢀpowerꢀonꢀ
resetꢀtimingꢀmustꢀalsoꢀbeꢀsatisfied.ꢀThatꢀisꢀtheꢀVDDꢀdropꢀtoꢀ0.9Vꢀandꢀkeepꢀatꢀ0.9Vꢀforꢀ10msꢀ(min.)ꢀbeforeꢀ
risingꢀtoꢀtheꢀnormalꢀoperatingꢀvoltage.ꢀ
3.ꢀDataꢀtransfersꢀonꢀtheꢀI2CꢀinterfaceꢀorꢀSPIꢀ3-wireꢀserialꢀinterfaceꢀshouldꢀatꢀleastꢀbeꢀdelayedꢀforꢀ1msꢀafterꢀ
theꢀpower-onꢀsequenceꢀtoꢀensureꢀthatꢀtheꢀresetꢀoperationꢀisꢀcomplete.
D.C. Characteristics
VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Test Condition
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
—
Condition
—
VDD
VLCD
VIH
VIL
Operating Voltage
1.8
2.4
0.7VDD
0
—
—
—
—
—
—
—
—
—
—
—
1
5.5
6.0
VDD
0.3VDD
1
V
LCD Operating Voltage
Input High Voltage
Input Low Voltage
—
—
V
—
CSB, CLK, DIO, RSTB
CSB, CLK, DIO, RSTB
VIN=VSS or VDD
V
—
V
IIL
Input Leakage Current
—
-1
μA
mA
mA
mA
mA
mA
mA
μA
μA
2.0V
-2
—
High Level Output
Current
IOH
3.3V VOH=0.9VDD for DIO pin
-6
—
5.0V
-12
3
—
2.0V
—
Low Level Output
Current
IOL
3.3V VOL=0.4V for SDA/DIO pin
5.0V
6
—
9
—
2.0V No load, fLCD=64Hz, 1/3bias, LCD
—
2.5
5
display on, Internal system oscillator on,
VLCD pin input voltage=5V,
disable integrated regulator
3.3V
—
2
IDD
Operating Current
Operating Current
Operating Current
5.0V
2.0V
—
—
4
10
μA
No load, fLCD=64Hz, 1/3bias, LCD
display on, Internal system oscillator on,
VLCD pin input voltage=5V,
ILCD1
25
40
μA
disable integrated regulator
No load, fLCD=64Hz, 1/3bias, LCD
display on, Internal system oscillator on,
VLCD pin input voltage=5.5V,
ILCD2
2.0V
—
30
52
μA
regulator output is set to 5V
No load, 1/3bias, LCD display off,
internal system oscillator off
3.3V
5.0V
—
—
—
—
1
2
μA
μA
ISTB1
Standby Current for VDD
VLCD pin input voltage =5V,
disable integrated regulator
Rev. 1.10
5
December 27, 2011
HT16L21
Test Condition
Condition
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
No load, 1/3bias, LCD display off,
internal system oscillator off
3.3V
—
—
—
1
2
μA
μA
V
Standby Current for
VLCD
ISTB2
VLCD pin input voltage =5V,
disable integrated regulator
5.0V
—
—
VLCD pin input voltage=5.5V, regulator
output is set to 4.5V, Ta=-40°C~85°C
4.35
4.42
250
500
-140
-300
250
500
-140
-300
10
4.5
4.65
4.58
—
Vreg
IOL1
IOH1
IOL2
IOH2
IOL3
Regulator Output
VLCD pin input voltage=5.5V, regulator
output is set to 4.5V, Ta=25°C
4.5
V
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
400
800
-230
-500
400
800
-230
-500
—
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
LCD Common Sink
Current
—
—
—
—
—
VLCD=5V, VOL=0.5V,
disable integrated regulator
—
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
—
LCD Common Source
Current
VLCD=5V, VOH=4.5V,
disable integrated regulator
—
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
—
LCD Segment Sink
Current
VLCD=5V, VOL=0.5V,
disable integrated regulator
—
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
—
LCD Segment Source
Current
VLCD=5V, VOH=4.5V,
disable integrated regulator
—
VLCD=3.3V, VOL=1V,
when SP1 bit is set to “1”
—
LED Sink Current
VLCD=5.0V, VOL=2V,
when SP1 bit is set to “1”
20
—
—
Note:ꢀ1.ꢀPleaseꢀuseꢀtheꢀintegratedꢀregulatorꢀwhenꢀtheꢀregulatorꢀoutputꢀvoltageꢀisꢀlessꢀthanꢀ(VLCD−0.5V).ꢀ
2.ꢀIfꢀ8ꢀLEDsꢀꢀturnꢀonꢀatꢀtheꢀsameꢀtime,ꢀtotalꢀcurrentꢀofꢀLEDꢀdriversꢀcanꢀnotꢀbeꢀallowedꢀꢀmoreꢀthanꢀ80mA.
Rev. 1.10
6
December 27, 2011
HT16L21
A.C. Characteristics
Unless otherwise specified, VDD =1.8 to 5.5V; VSS = 0 V; Ta =-40~85°C
Test Condition
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Condition
Frame frequency is set
to 64Hz
57.6
76
64
70.4
94.0
Frame frequency is set
to 85.3Hz
85.3
128
Ta=25°C,
DD=3.3V
fLCD1
—
Hz
V
Frame frequency is set
to 128Hz
115.2
152
140.8
Frame frequency is set
to170.6Hz
170.6 188.0
Frame frequency is set
to 64Hz
51.2
68
64
85.3
128
170.6
—
83.0
111
Frame frequency is set
to 85.3Hz
Ta=-40~85°C,
DD=2.5~5.5V
fLCD2
LCD Frame Frequency
—
Hz
V
Frame frequency is set
to 128Hz
102.4
136
166
222
64
Frame frequency is set
to170.6Hz
Frame frequency is set
to 64Hz
45.0
59.0
90.0
118.0
Frame frequency is set
to 85.3Hz
—
85.3
128
170.6
Ta=-40~85°C
DD=1.8~2.5V
fLCD3
—
Hz
V
Frame frequency is set
to 128Hz
—
Frame frequency is set
to170.6Hz
—
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
tSR
VDD Slew Rate
VDD Off Times
—
0.05
10
—
—
—
—
—
—
—
—
V/ms
ms
ns
tPOF
VDD drop down to 0.9V
When RSTB signal is externally input
from a microcontroller etc.
250
—
—
tRSON
RSTB Input Time
RSTB Pulse Width
R=100kΩ and C=0.1μF
(see application circuit)
100
—
ms
ns
When RSTB signal is externally input
from a microcontroller etc.
tRW
400
1
Wait Time for Data
Transfers
tRSOFF
2-wire I2C or 3-wire SPI interface
—
ms
Note:ꢀfLCDꢀ=ꢀ1/tLCD
Rev. 1.10
7
December 27, 2011
HT16L21
A.C. Characteristics – I2C Interface
Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
V
DD=1.8V to 5.5V VDD=3.0V to 5.5V
Symbol
fSCL
Parameter
Condition
Unit
Min.
Max.
Min.
Max.
Clock Frequency
—
—
100
—
400
kHz
Time in which the bus
must be free before a new
transmission can start
tBUF
Bus Free Time
4.7
—
1.3
—
μs
After this period, the first
clock pulse is generated
tHD: STA
Start Condition Hold Time
4
—
0.6
—
μs
tLOW
tHIGH
SCL Low Time
SCL High Time
—
—
4.7
4
—
—
1.3
0.6
—
—
μs
μs
Start Condition Setup
Time
Only relevant for repeated
START condition
tSU: STA
4.7
—
0.6
—
μs
tHD: DAT
tSU: DAT
tR
Data Hold Time
Data Setup Time
—
—
0
250
—
—
—
1
0
100
—
—
—
ns
ns
μs
μs
SDA and SCL Rise Time Note
0.3
0.3
tF
SDA and SCL Fall Time
Note
—
0.3
—
Stop Condition Set-Up
Time
tSU: STO
tAA
—
—
4
—
3.5
20
0.6
—
—
0.9
20
μs
μs
ns
Output Valid from Clock
—
—
Input Filter Time Constant
(SDA and SCL pins)
tSP
Noise suppression time
—
Note:ꢀTheseꢀparametersꢀareꢀperiodicallyꢀsampledꢀbutꢀnotꢀ100%ꢀtested.
A.C. Characteristics – SPI Interface
Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Test Condition
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Condition
For write data
250
1000
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
tSYS
Clock Cycle Time
—
For read data
For write data
For read data
For write data
For write data
—
—
—
—
—
tCW
Clock Pulse Width
400
50
tDS
Data Setup Time
Data Hold Time
tDH
50
tCSW
“H” CSB Pulse Width
—
—
50
For write data
For read data
50
CSB Setup Time
(CSB↓―CLK↑)
tCSL
tCSH
tPD
—
—
—
400
2
CS Hold Time (CLK↑―CSB↑)
tPD=10% to 90%
PD=90% to 10%
DATA Output Delay Time
(CLK―DIO)
CO=15pF
—
—
350
ns
t
Rev. 1.10
8
December 27, 2011
HT16L21
Characteristics Curves – fLCD vs. VDD vs. Temperature
LCD Frame Frequency fLCD is Set to 64Hz
LCD Frame Frequency fLCD is Set to 85.3Hz
100
90
80
70
80
60
-40℃
-40℃
70
-20℃
0℃
50
40
30
20
10
0
-20℃
60
0℃
50
25℃
65℃
85℃
25℃
40
65℃
30
85℃
20
10
0
1.2 1.5 1.8 2.1 2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
DD (V)
1.2 1.5 1.8 2.1 2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
DD (V)
V
V
LCD Frame Frequency fLCD is Set to 128Hz
LCD Frame Frequency fLCD is Set to 170.6Hz
160
140
200
180
160
120
-40℃
-40℃
-20℃
0℃
140
120
100
80
100
80
60
40
20
0
-20℃
0℃
25℃
65℃
85℃
25℃
65℃
85℃
60
40
20
0
1.2 1.5 1.8 2.1 2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
DD (V)
1.2 1.5 1.8 2.1 2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
DD (V)
V
V
Reset Function
Functional Description
WhenꢀtheꢀRSTBꢀpinꢀisꢀpulledꢀtoꢀaꢀlowꢀlevel,ꢀaꢀ
resetꢀoperationꢀisꢀexecutedꢀandꢀitꢀwillꢀinitializeꢀallꢀ
functions.ꢀTheꢀstatusꢀofꢀtheꢀinternalꢀcircuitsꢀafterꢀ
initializationꢀisꢀasꢀfollows:
Power-On Reset
Whenꢀtheꢀpowerꢀisꢀapplied,ꢀtheꢀdeviceꢀisꢀinitializedꢀ
byꢀanꢀinternalꢀpower-onꢀresetꢀcircuit.ꢀTheꢀstatusꢀofꢀtheꢀ
internalꢀcircuitsꢀafterꢀinitializationꢀisꢀasꢀfollows:
•ꢀ AllꢀcommonꢀoutputsꢀareꢀsetꢀtoꢀVLCD.
•ꢀ AllꢀcommonꢀoutputsꢀareꢀsetꢀtoꢀVLCD.
•ꢀ AllꢀsegmentꢀoutputsꢀareꢀsetꢀtoꢀVLCD
.
•ꢀ AllꢀsegmentꢀoutputsꢀareꢀsetꢀtoꢀVLCD
.
•ꢀ Theꢀ1/3ꢀbiasꢀdriveꢀmodeꢀisꢀselected.
•ꢀ Theꢀ1/3ꢀbiasꢀdriveꢀmodeꢀisꢀselected.
•ꢀ TheꢀsystemꢀoscillatorꢀandꢀtheꢀLCDꢀbiasꢀgeneratorꢀ
areꢀoffꢀstate.
•ꢀ TheꢀsystemꢀoscillatorꢀandꢀtheꢀLCDꢀbiasꢀgeneratorꢀ
areꢀoffꢀstate.
•ꢀ LCDꢀdisplayꢀisꢀoffꢀstate.
•ꢀ LCDꢀdisplayꢀisꢀoffꢀstate.
•ꢀ Integratedꢀregulatorꢀisꢀdisabled.
•ꢀ Integratedꢀregulatorꢀisꢀdisabled.
•ꢀ Internalꢀvoltageꢀadjustmentꢀfunctionꢀisꢀenabled.
•ꢀ Theꢀsegment/LEDꢀsharedꢀpinꢀisꢀsetꢀasꢀtheꢀsegmentꢀ
pin.
•ꢀ Frameꢀfrequencyꢀisꢀsetꢀtoꢀ64Hz.
•ꢀ Blinkingꢀfunctionꢀisꢀswitchedꢀoff.
•ꢀ Theꢀsegment/LEDꢀsharedꢀpinsꢀareꢀsetꢀasꢀtheꢀ
segmentꢀpins.
•ꢀ Frameꢀfrequencyꢀisꢀsetꢀtoꢀ64Hz.
•ꢀ Blinkingꢀfunctionꢀisꢀswitchedꢀoff.
Rev. 1.10
9
December 27, 2011
HT16L21
respectively.ꢀTheꢀfollowingꢀdiagramꢀisꢀaꢀdataꢀtransferꢀ
formatꢀforꢀI2CꢀorꢀSPIꢀinterface.
Display Memory – RAM Structure
TheꢀdisplayꢀRAMꢀisꢀstaticꢀ32×4-bitsꢀRAMꢀwhichꢀ
storesꢀtheꢀLCDꢀdata.ꢀLogicꢀ“1”ꢀinꢀtheꢀRAMꢀbit-mapꢀ
indicatesꢀtheꢀ“on”ꢀstateꢀofꢀtheꢀcorrespondingꢀLCDꢀ
segment;ꢀsimilarly,ꢀlogicꢀ0ꢀindicatesꢀtheꢀ“off”ꢀstate.
MSB
LSB
D0
LCD D7
D6
D5
D4
D3
D2
D1
TheꢀcontentsꢀofꢀtheꢀRAMꢀdataꢀareꢀdirectlyꢀmappedꢀ
toꢀtheꢀLCDꢀdata.ꢀTheꢀfirstꢀRAMꢀcolumnꢀcorrespondsꢀ
toꢀtheꢀsegmentsꢀoperatedꢀwithꢀrespectꢀtoꢀCOM0.ꢀInꢀ
multiplexedꢀLCDꢀapplicationsꢀtheꢀsegmentꢀdataꢀofꢀtheꢀ
second,ꢀthirdꢀandꢀfourthꢀcolumnꢀofꢀtheꢀdisplayꢀRAMꢀ
areꢀtime-multiplexedꢀwithꢀCOM1,ꢀCOM2ꢀandꢀCOM3ꢀ
LED LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0
LCD Display or LED output data transfer format for
I2C or SPI interface
32×4 Display Mode
WhenꢀtheꢀSP1ꢀbitꢀisꢀsetꢀtoꢀ“0”ꢀandꢀtheꢀSP0ꢀbitꢀisꢀsetꢀtoꢀ“0”ꢀorꢀ“1”,ꢀtheꢀdriveꢀmodeꢀisꢀselectedꢀasꢀ32ꢀsegmentsꢀbyꢀ
4ꢀcommons.ꢀThisꢀdriveꢀmodeꢀisꢀalsoꢀtheꢀdefaultꢀsettingꢀafterꢀaꢀreset.
Output
SEG1
SEG3
SEG5
↓
COM3
—
COM2
—
COM1
—
COM0
—
Output
SEG0
SEG2
SEG4
↓
COM3
—
COM2
—
COM1
—
COM0 Address
—
—
—
↓
00H
01H
02H
↓
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↓
↓
↓
↓
↓
↓
↓
SEG31
—
—
—
—
—
SEG30
—
—
—
—
—
D0
0FH
Data
D7
D6
D5
D4
D3
D2
D1
RAM mapping of 32×4 display mode
28×4 Display Mode
WhenꢀtheꢀSP1ꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀandꢀtheꢀSP0ꢀbitꢀisꢀsetꢀtoꢀ“0”,ꢀtheꢀdriveꢀmodeꢀisꢀselectedꢀasꢀ28ꢀsegmentsꢀbyꢀ
4ꢀcommonsꢀtogetherꢀwithꢀ4ꢀLEDꢀdrivingꢀoutputs.
Output
SEG1
SEG3
SEG5
↓
COM3
—
COM2
—
COM1
—
COM0
—
Output
SEG0
SEG2
SEG4
↓
COM3
—
COM2
—
COM1
—
COM0 Address
—
—
—
↓
00H
01H
02H
↓
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↓
↓
↓
↓
↓
↓
↓
SEG27
—
—
—
—
—
SEG26
—
—
—
—
—
D0
0DH
Data
D7
D6
D5
D4
D3
D2
D1
RAM mapping of 28×4 display mode
24×4 Display Mode
WhenꢀtheꢀSP1ꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀandꢀtheꢀSP0ꢀbitꢀisꢀsetꢀtoꢀ“1”,ꢀtheꢀdriveꢀmodeꢀisꢀselectedꢀasꢀ24ꢀsegmentsꢀbyꢀ
4ꢀcommonsꢀtogetherꢀwithꢀ8ꢀLEDꢀdrivingꢀoutputs.
Output
SEG1
SEG3
SEG5
COM3
—
COM2
—
COM1
—
COM0
—
Output
SEG0
SEG2
SEG4
COM3
—
COM2
—
COM1
—
COM0 Address
—
—
—
00H
01H
02H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
SEG23
—
—
—
—
—
SEG22
—
—
—
—
—
0BH
Data
D7
D6
D5
D4
D3
D2
D1
D0
RAM mapping of 24×4 display mode
Rev. 1.10
10
December 27, 2011
HT16L21
externalꢀVLCDꢀpinꢀandꢀalsoꢀintegratesꢀanꢀinternalꢀ
regulator.ꢀTheꢀLCDꢀvoltageꢀmayꢀbeꢀtemperatureꢀ
compensatedꢀexternallyꢀthroughꢀtheꢀVoltageꢀsupplyꢀtoꢀ
theꢀVLCDꢀpin.ꢀTheꢀinternalꢀregulatorꢀcanꢀalsoꢀprovideꢀ
theꢀLCDꢀoperatingꢀvoltage.ꢀTherefore,ꢀtheꢀfull-scaleꢀ
LCDꢀvoltageꢀ(VOP)ꢀisꢀobtainedꢀfromꢀ(VLCD–VSS)ꢀorꢀ
System Oscillator
TheꢀtimingꢀforꢀtheꢀinternalꢀlogicꢀandꢀtheꢀLCDꢀdriveꢀ
signalsꢀareꢀgeneratedꢀbyꢀanꢀinternalꢀoscillator.ꢀTheꢀ
SystemꢀClockꢀfrequencyꢀ(fSYS)ꢀdeterminesꢀtheꢀLCDꢀ
frameꢀfrequency.ꢀDuringꢀinitialꢀsystemꢀpowerꢀonꢀtheꢀ
SystemꢀOscillatorꢀwillꢀbeꢀinꢀtheꢀstopꢀstate.
(V –VSS).ꢀ
reg
FractionalꢀLCDꢀbiasingꢀvoltages,ꢀknownꢀasꢀ1/2ꢀorꢀ1/3ꢀ
biasꢀvoltage,ꢀareꢀobtainedꢀfromꢀanꢀinternalꢀvoltageꢀ
LCD Bias Generator
TheꢀLCDꢀsupplyꢀpowerꢀcanꢀcomeꢀfromꢀtheꢀexternalꢀ
VLCDꢀpinꢀorꢀtheꢀinternalꢀregulatorꢀoutputꢀvoltageꢀ
determinedꢀusingꢀtheꢀInternalꢀVoltageꢀAdjustmentꢀ
(IVA)ꢀsettingꢀcommand.ꢀTheꢀdeviceꢀprovidesꢀanꢀ
dividerꢀofꢀfourꢀseriesꢀresistorsꢀconnectedꢀbetweenꢀVLCD
andꢀVSS.ꢀTheꢀcentreꢀresistorꢀcanꢀbeꢀswitchedꢀoutꢀofꢀcir-
cuitsꢀtoꢀprovideꢀaꢀ1/2ꢀbiasꢀvoltageꢀlevelꢀconfiguration.
ꢀ
LCD Drive Mode Waveforms
•ꢀ WhenꢀtheꢀLCDꢀdriveꢀmodeꢀisꢀselectedꢀasꢀ1/4ꢀdutyꢀandꢀ1/2ꢀbias,ꢀtheꢀwaveformꢀandꢀLCDꢀdisplayꢀisꢀshownꢀasꢀ
follows:
tLCD
LCD segment
LCD segment
V
LCD
LCD
State1
V
State1
(on)
(on)
COM0
COM0
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
SS
V
V
LCD
LCD
State2
V
State2
(off)
(off)
COM1
COM1
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
SS
V
V
LCD
LCD
V
COM2
COM2
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
V
SS
V
LCD
LCD
V
COM3
COM3
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
SS
V
V
LCD
LCD
V
SEG n
SEG n
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
SS
V
V
LCD
VLCD
SEG n+1
SEG n+1
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
SS
V
V
LCD
LCD
V
SEG n+2
SEG n+2
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
V
SS
V
LCD
LCD
V
SEG n+3
SEG n+3
(V +V )/2
(LVCLDCD+SVSSS)/2
V
SS
V
SS
Waveforms for 1/4 duty drive mode with1/2 bias (VOP=VLCD−VSS
)
Note:ꢀtLCDꢀ=ꢀ1/fLCD
Rev. 1.10
11
December 27, 2011
HT16L21
•ꢀ WhenꢀtheꢀLCDꢀdriveꢀmodeꢀisꢀselectedꢀasꢀ1/4ꢀdutyꢀandꢀ1/3ꢀbias,ꢀtheꢀwaveformꢀandꢀLCDꢀdisplayꢀisꢀshownꢀasꢀ
follows:
tLCD
LCD segment
LCD segment
VLCD
State1
VLCD
VLCD- Vop/3
State1
(on)
(on)
VLCD- Vop/3
COM0
COM0
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
COM1
COM1
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM2
COM2
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM3
COM3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VLCD−VSS
)
Note:ꢀtLCDꢀ=ꢀ1/fLCD
Rev. 1.10
12
December 27, 2011
HT16L21
Segment Driver Outputs
Frame Frequency
TheꢀLCDꢀdriveꢀsectionꢀincludesꢀ32ꢀsegmentꢀoutputsꢀ
SEG0~SEG31ꢀorꢀ24ꢀsegmentꢀoutputsꢀSEG0~SEG23ꢀ
whichꢀshouldꢀbeꢀconnectedꢀdirectlyꢀtoꢀtheꢀLCDꢀ
panel.ꢀTheꢀsegmentꢀoutputꢀsignalsꢀareꢀgeneratedꢀinꢀ
accordanceꢀwithꢀtheꢀmultiplexedꢀLEDꢀsignalsꢀandꢀ
withꢀtheꢀdataꢀresidentꢀinꢀtheꢀdisplayꢀlatch.ꢀTheꢀunusedꢀ
segmentꢀoutputsꢀshouldꢀbeꢀleftꢀopen-circuitꢀwhenꢀlessꢀ
thanꢀ32ꢀorꢀ24ꢀsegmentꢀoutputsꢀareꢀrequired.
Theꢀdeviceꢀprovidesꢀfourꢀframeꢀfrequenciesꢀselectedꢀ
withꢀFrameꢀFrequencyꢀcommandꢀknownꢀasꢀ64Hz,ꢀ
85.3Hz,ꢀ128Hzꢀandꢀ170.6Hzꢀrespectively.
LED Function
TheꢀLEDꢀpinsꢀareꢀNMOS-structuredꢀoutputꢀpins.ꢀ
TheꢀDataꢀforꢀtheꢀLEDꢀoutputꢀisꢀcontainedꢀinꢀtheꢀ
LEDꢀoutputꢀsettingꢀcommand,ꢀstartingꢀfromꢀtheꢀmostꢀ
significantꢀbit.ꢀWhenꢀaꢀwrittenꢀdataꢀbitꢀforꢀaꢀLEDꢀpinꢀ
isꢀsetꢀtoꢀ1,ꢀtheꢀcorrespondingꢀdrivingꢀLEDꢀlightsꢀupꢀ
whileꢀtheꢀLEDꢀisꢀswitchedꢀoffꢀwhenꢀtheꢀwrittenꢀdataꢀ
bitꢀisꢀ0.ꢀTheꢀLEDꢀpinsꢀareꢀpin-sharedꢀwithꢀtheꢀLCDꢀ
segmentꢀpinsꢀandꢀcanꢀbeꢀselectedꢀusingꢀtheꢀSP1ꢀandꢀ
SP0ꢀbitsꢀinꢀtheꢀDriveꢀModeꢀcommand.
Column Driver Outputs
TheꢀLCDꢀdriveꢀsectionꢀincludesꢀ4ꢀcolumnꢀoutputsꢀ
COM0~COM3ꢀwhichꢀshouldꢀbeꢀconnectedꢀdirectlyꢀ
toꢀtheꢀLCDꢀpanel.ꢀTheꢀcolumnꢀoutputꢀsignalsꢀareꢀ
generatedꢀinꢀaccordanceꢀwithꢀtheꢀselectedꢀLCDꢀ
driveꢀmode.ꢀTheꢀunusedꢀcolumnꢀoutputsꢀshouldꢀbeꢀ
leftꢀopen-circuitꢀifꢀlessꢀthanꢀ4ꢀcolumnꢀoutputsꢀareꢀ
required.
I2C Serial Interface
I2C Operation
Address Pointer
TheꢀdeviceꢀsupportsꢀI2Cꢀserialꢀinterface.ꢀTheꢀI2Cꢀbusꢀ
isꢀforꢀbidirectional,ꢀtwo-lineꢀcommunicationꢀbetweenꢀ
differentꢀICsꢀorꢀmodules.ꢀTheꢀtwoꢀlinesꢀareꢀaꢀserialꢀ
dataꢀline,ꢀSDA,ꢀandꢀaꢀserialꢀclockꢀline,ꢀSCL.ꢀBothꢀ
linesꢀareꢀconnectedꢀtoꢀtheꢀpositiveꢀsupplyꢀviaꢀpull-upꢀ
resistorsꢀwithꢀaꢀtypicalꢀvalueꢀofꢀ4.7KΩ.ꢀWhenꢀtheꢀbusꢀ
isꢀfree,ꢀbothꢀlinesꢀareꢀhigh.ꢀDevicesꢀconnectedꢀtoꢀtheꢀ
busꢀmustꢀhaveꢀopen-drainꢀorꢀopen-collectorꢀoutputsꢀ
toꢀimplementꢀaꢀwired-orꢀfunction.ꢀDataꢀtransferꢀisꢀ
initiatedꢀonlyꢀwhenꢀtheꢀbusꢀisꢀnotꢀbusy.
TheꢀaddressingꢀmechanismꢀforꢀtheꢀdisplayꢀRAMꢀisꢀ
implementedꢀusingꢀtheꢀaddressꢀpointer.ꢀThisꢀallowsꢀ
theꢀloadingꢀofꢀanꢀindividualꢀdisplayꢀdataꢀbyte,ꢀorꢀaꢀ
seriesꢀofꢀdisplayꢀdataꢀbytes,ꢀintoꢀanyꢀlocationꢀofꢀtheꢀ
displayꢀRAM.ꢀTheꢀsequenceꢀcommencesꢀwithꢀtheꢀ
initializationꢀofꢀtheꢀaddressꢀpointerꢀbyꢀtheꢀDisplayꢀ
DataꢀInputꢀcommand.
Blinking Function
Theꢀdeviceꢀcontainsꢀversatileꢀblinkingꢀcapabilities.ꢀ
Theꢀwholeꢀdisplayꢀcanꢀbeꢀblinkedꢀatꢀfrequenciesꢀ
selectedꢀbyꢀtheꢀBlinkingꢀFrequencyꢀcommand.ꢀTheꢀ
blinkingꢀfrequencyꢀisꢀaꢀsubdividedꢀratioꢀofꢀtheꢀsystemꢀ
frequency.ꢀTheꢀratioꢀbetweenꢀtheꢀsystemꢀoscillatorꢀ
andꢀblinkingꢀfrequenciesꢀdependsꢀonꢀtheꢀblinkingꢀ
modeꢀinꢀwhichꢀtheꢀdeviceꢀisꢀoperating,ꢀasꢀshownꢀinꢀ
theꢀfollowingꢀtable:
Data Validity
TheꢀdataꢀonꢀtheꢀSDAꢀlineꢀmustꢀbeꢀstableꢀduringꢀtheꢀ
highꢀperiodꢀofꢀtheꢀserialꢀclock.ꢀTheꢀhighꢀorꢀlowꢀstateꢀ
ofꢀtheꢀdataꢀlineꢀcanꢀonlyꢀchangeꢀwhenꢀtheꢀclockꢀsignalꢀ
onꢀtheꢀSCLꢀlineꢀisꢀLowꢀasꢀshownꢀinꢀtheꢀdiagram.
SDA
Blinking Mode
Blinking Frequency (Hz)
SCL
0
1
2
3
Blink off
2
1
Dataꢀlineꢀstable;
Dataꢀvalid
Changeꢀofꢀdataꢀ
allowed
0.5
Rev. 1.10
13
December 27, 2011
HT16L21
START and STOP Conditions
•ꢀ AꢀhighꢀtoꢀlowꢀtransitionꢀonꢀtheꢀSDAꢀlineꢀwhileꢀSCLꢀisꢀhighꢀdefinesꢀaꢀSTARTꢀcondition.
•ꢀ AꢀlowꢀtoꢀhighꢀtransitionꢀonꢀtheꢀSDAꢀlineꢀwhileꢀSCLꢀisꢀhighꢀdefinesꢀaꢀSTOPꢀcondition.
•ꢀ STARTꢀandꢀSTOPꢀconditionsꢀareꢀalwaysꢀgeneratedꢀbyꢀtheꢀmaster.ꢀTheꢀbusꢀisꢀconsideredꢀtoꢀbeꢀbusyꢀafterꢀtheꢀ
STARTꢀcondition.ꢀTheꢀbusꢀisꢀconsideredꢀtoꢀbeꢀfreeꢀagainꢀaꢀcertainꢀtimeꢀafterꢀtheꢀSTOPꢀcondition.
•ꢀ TheꢀbusꢀstaysꢀbusyꢀifꢀaꢀrepeatedꢀSTARTꢀ(Sr)ꢀisꢀgeneratedꢀinsteadꢀofꢀaꢀSTOPꢀcondition.ꢀInꢀsomeꢀrespects,ꢀtheꢀ
START(S)ꢀandꢀrepeatedꢀSTARTꢀ(Sr)ꢀconditionsꢀareꢀfunctionallyꢀidentical.
SDA
SDA
SCL
SCL
S
P
STARTꢀcondition
STOPꢀcondition
Byte Format
EveryꢀbyteꢀputꢀonꢀtheꢀSDAꢀlineꢀmustꢀbeꢀ8-bitꢀlong.ꢀTheꢀnumberꢀofꢀbytesꢀthatꢀcanꢀbeꢀtransmittedꢀperꢀtransferꢀisꢀ
unrestricted.ꢀEachꢀbyteꢀhasꢀtoꢀbeꢀfollowedꢀbyꢀanꢀacknowledgeꢀbit.ꢀDataꢀisꢀtransferredꢀwithꢀtheꢀmostꢀsignificantꢀbit,ꢀ
MSB,ꢀfirst.
P
SDA
Sr
SCL
S
P
1
2
7
8
9
1
2
3-8
9
or
Sr
or
Sr
ACK
ACK
Acknowledge
•ꢀ Eachꢀbytesꢀofꢀeightꢀbitsꢀisꢀfollowedꢀbyꢀoneꢀacknowledgeꢀbit.ꢀThisꢀAcknowledgeꢀbitꢀisꢀaꢀlowꢀlevelꢀplacedꢀonꢀtheꢀ
busꢀbyꢀtheꢀreceiver.ꢀTheꢀmasterꢀgeneratesꢀanꢀextraꢀacknowledgeꢀrelatedꢀclockꢀpulse.
•ꢀ AꢀslaveꢀreceiverꢀwhichꢀisꢀaddressedꢀmustꢀgenerateꢀanꢀAcknowledge,ꢀACK,ꢀafterꢀtheꢀreceptionꢀofꢀeachꢀbyte.
•ꢀ TheꢀdeviceꢀthatꢀacknowledgesꢀmustꢀpullꢀdownꢀtheꢀSDAꢀlineꢀduringꢀtheꢀacknowledgeꢀclockꢀpulseꢀsoꢀthatꢀitꢀ
remainsꢀstableꢀlowꢀduringꢀtheꢀhighꢀperiodꢀofꢀthisꢀclockꢀpulse.
•ꢀ Aꢀmasterꢀreceiverꢀmustꢀsignalꢀanꢀendꢀofꢀdataꢀtoꢀtheꢀslaveꢀbyꢀgeneratingꢀaꢀnot-acknowledge,ꢀNACK,ꢀbitꢀonꢀtheꢀ
lastꢀbyteꢀthatꢀhasꢀbeenꢀclockedꢀoutꢀofꢀtheꢀslave.ꢀInꢀthisꢀcase,ꢀtheꢀmasterꢀreceiverꢀmustꢀleaveꢀtheꢀdataꢀlineꢀhighꢀ
duringꢀtheꢀ9thꢀpulseꢀtoꢀnotꢀacknowledge.ꢀTheꢀmasterꢀwillꢀgenerateꢀaꢀSTOPꢀorꢀrepeatedꢀSTARTꢀcondition.
DataꢀOutput
byꢀTransmitter
notꢀacknowledge
DataꢀOutptu
byꢀReceiver
acknowledge
SCLꢀFrom
Master
1
2
7
8
9
S
START
condition
clockꢀpulseꢀfor
acknowledgement
Rev. 1.10
14
December 27, 2011
HT16L21
Slave Addressing
•ꢀ TheꢀslaveꢀaddressꢀbyteꢀisꢀtheꢀfirstꢀbyteꢀreceivedꢀfollowingꢀtheꢀSTARTꢀconditionꢀformꢀtheꢀmasterꢀdevice.ꢀTheꢀ
firstꢀsevenꢀbitsꢀofꢀtheꢀfirstꢀbyteꢀmakeꢀupꢀtheꢀslaveꢀaddress.ꢀTheꢀeighthꢀbitꢀdefinesꢀaꢀreadꢀorꢀwriteꢀoperationꢀtoꢀbeꢀ
performed.ꢀWhenꢀtheꢀR/Wꢀbitꢀisꢀ“1”,ꢀthenꢀaꢀreadꢀoperationꢀisꢀselected.ꢀAꢀ“0”ꢀselectsꢀaꢀwriteꢀoperation.ꢀ
•ꢀ TheꢀHT16L21ꢀdeviceꢀaddressꢀbitsꢀareꢀ“0111000”.ꢀWhenꢀanꢀaddressꢀbyteꢀisꢀsent,ꢀtheꢀdeviceꢀcomparesꢀtheꢀfirstꢀ
sevenꢀbitsꢀafterꢀtheꢀSTARTꢀcondition.ꢀIfꢀtheyꢀmatch,ꢀtheꢀdeviceꢀoutputsꢀanꢀAcknowledgeꢀonꢀtheꢀSDAꢀline.
Slave Address
MSB
0
LSB
R/W
1
1
1
0
0
0
I2C Interface Write Operation
Byte Write Operation
•ꢀ Single Command Type
AꢀSingleꢀCommandꢀwriteꢀoperationꢀrequiresꢀaꢀSTARTꢀcondition,ꢀaꢀslaveꢀaddressꢀwithꢀanꢀR/Wꢀbit,ꢀaꢀcommandꢀ
byteꢀandꢀaꢀSTOPꢀconditionꢀforꢀaꢀsingleꢀcommandꢀwriteꢀoperation.
Slave Address
Command byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
S
0
1
1
1
0
0
0
0
P
ACK
ACK
Write
1st
I2C Single Command Type Write Operation
•ꢀ Compound Command Type
AꢀCompoundꢀCommandꢀwriteꢀoperationꢀrequiresꢀaꢀSTARTꢀcondition,ꢀaꢀslaveꢀaddressꢀwithꢀanꢀR/Wꢀbit,ꢀaꢀ
commandꢀbyte,ꢀaꢀcommandꢀsettingꢀbyteꢀandꢀaꢀSTOPꢀconditionꢀforꢀaꢀcompoundꢀcommandꢀwriteꢀoperation.
Slave Address
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
S
0
1
1
1
0
0
0
0
P
ACK
ACK
ACK
Write
1st
2nd
I2C Compound Command Type Write Operation
•ꢀ Display RAM Single Data Byte
AꢀdisplayꢀRAMꢀdataꢀbyteꢀwriteꢀoperationꢀrequiresꢀaꢀSTARTꢀcondition,ꢀaꢀslaveꢀaddressꢀwithꢀanꢀR/Wꢀbit,ꢀaꢀ
displayꢀdataꢀinputꢀcommandꢀbyte,ꢀaꢀvalidꢀRegisterꢀAddressꢀbyte,ꢀaꢀDataꢀbyteꢀandꢀaꢀSTOPꢀcondition.
Slave Address
Command byte
Register Address byte
A3 A2
Data byte
D4 D3
1
0
0
0
0
0
0
0
X
X
X
X
A1
A0
D7
D6
D5
D2
D1
D0
S
0
1
1
1
0
0
0
0
P
ACK
ACK
ACK
ACK
Write
1st
2nd
I2C Display RAM Single Data Byte Write Operation
Rev. 1.10
15
December 27, 2011
HT16L21
Display RAM Page Write Operation
I2C Interface Display RAM Read Operation
AfterꢀaꢀSTARTꢀconditionꢀtheꢀslaveꢀaddressꢀwithꢀtheꢀ
R/Wꢀbitꢀisꢀplacedꢀonꢀtheꢀbusꢀfollowedꢀwithꢀaꢀdisplayꢀ
dataꢀinputꢀcommandꢀbyteꢀandꢀtheꢀspecifiedꢀdisplayꢀ
RAMꢀRegisterꢀAddressꢀofꢀwhichꢀtheꢀcontentsꢀareꢀ
writtenꢀtoꢀtheꢀinternalꢀaddressꢀpointer.ꢀTheꢀdataꢀtoꢀbeꢀ
writtenꢀtoꢀtheꢀmemoryꢀwillꢀbeꢀtransmittedꢀnextꢀandꢀ
thenꢀtheꢀinternalꢀaddressꢀpointerꢀwillꢀbeꢀincrementedꢀ
byꢀ1ꢀtoꢀindicateꢀtheꢀnextꢀmemoryꢀaddressꢀlocationꢀ
afterꢀtheꢀreceptionꢀofꢀanꢀacknowledgeꢀclockꢀpulse.ꢀ
Afterꢀtheꢀinternalꢀaddressꢀpointꢀreachesꢀtheꢀmaximumꢀ
memoryꢀaddress,ꢀtheꢀaddressꢀpointerꢀwillꢀbeꢀresetꢀtoꢀ
00H.
Inꢀthisꢀmode,ꢀtheꢀmasterꢀreadsꢀtheꢀHT16L21ꢀdataꢀ
afterꢀsettingꢀtheꢀslaveꢀaddress.ꢀFollowingꢀtheꢀR/Wꢀ
bitꢀ(="0")ꢀisꢀanꢀacknowledgeꢀbit,ꢀaꢀcommandꢀbyteꢀ
andꢀtheꢀregisterꢀaddressꢀbyteꢀwhichꢀisꢀwrittenꢀtoꢀtheꢀ
internalꢀaddressꢀpointer.ꢀAfterꢀtheꢀstartꢀaddressꢀofꢀtheꢀ
ReadꢀOperationꢀhasꢀbeenꢀconfigured,ꢀanotherꢀSTARTꢀ
conditionꢀandꢀtheꢀslaveꢀaddressꢀtransferredꢀonꢀtheꢀbusꢀ
followedꢀbyꢀtheꢀR/Wꢀbitꢀ(="1").ꢀThenꢀtheꢀMSBꢀofꢀtheꢀ
dataꢀwhichꢀwasꢀaddressedꢀisꢀtransmittedꢀfirstꢀonꢀtheꢀ
I2Cꢀbus.ꢀTheꢀaddressꢀpointerꢀisꢀonlyꢀincrementedꢀbyꢀ
1ꢀafterꢀtheꢀreceptionꢀofꢀanꢀacknowledgeꢀclock.ꢀThatꢀ
meansꢀthatꢀifꢀtheꢀdeviceꢀisꢀconfiguredꢀtoꢀtransmitꢀ
theꢀdataꢀatꢀtheꢀaddressꢀofꢀAN+1,ꢀtheꢀmasterꢀwillꢀreadꢀ
andꢀacknowledgeꢀtheꢀtransferredꢀnewꢀdataꢀbyteꢀandꢀ
theꢀaddressꢀpointerꢀisꢀincrementedꢀtoꢀAN+2.ꢀAfterꢀ
theꢀinternalꢀaddressꢀpointerꢀreachesꢀtheꢀmaximumꢀ
memoryꢀaddress,ꢀtheꢀaddressꢀpointerꢀwillꢀbeꢀresetꢀtoꢀ
00H.
Theꢀmaximumꢀmemoryꢀaddressꢀisꢀshowꢀasꢀbelow.
SP1
0
SP0
X
Maximum Memory Address
0FH
0DH
0BH
1
0
1
1
Thisꢀcycleꢀofꢀreadingꢀconsecutiveꢀaddressesꢀwillꢀ
continueꢀuntilꢀtheꢀmasterꢀsendsꢀaꢀSTOPꢀcondition.
Slave Address
Command byte
Register Address byte
1
0
0
0
0
0
0
0
X
X
X
X
A3
A2
A1
A0
S
0
1
1
1
0
0
0
0
1st
2nd
Write
ACK
ACK
ACK
Data byte
D4 D3
Data byte
D4 D3
Data byte
D4 D3
D7
D6
D5
D2
D1
D0
D7
D6
D5
D2
D1
D0
D7
D6
D5
D2
D1
D0
P
1st data
2nd data
Nth data
ACK
ACK
ACK
ACK
I2C Interface N Bytes Display RAM Data Write Operation
Slave Address
Command byte
Register Address byte
A3 A2
1
0
0
0
0
0
0
0
X
X
X
X
A1
A0
S
0
1
1
1
0
0
0
0
P
1st
2nd
Write
ACK
ACK
ACK
0
Slave Address
Data byte
D4 D3
Data byte
D4 D3
Data byte
D4 D3
D7
D6
D5
D2
D1
D0
D7
D6
D5
D2
D1
D0
D7
D6
D5
D2
D1
D0
S
0
1
1
1
0
0
0
1
P
NACK
1st data
2nd data
Nth data
Read
ACK
ACK
ACK
ACK
I2C Interface N Bytes Display RAM Data Read Operation
Rev. 1.10
16
December 27, 2011
HT16L21
SPI Interface Write Operation
SPI Serial Interface
Byte Write Operation
SPI Operation
•ꢀ Single Command Type
Theꢀdeviceꢀalsoꢀincludesꢀaꢀ3-wireꢀSPIꢀserialꢀinterface.ꢀ
TheꢀSPIꢀoperationsꢀareꢀdescribedꢀasꢀfollows:
AꢀSingleꢀCommandꢀwriteꢀoperationꢀisꢀactivatedꢀ
byꢀtheꢀCSBꢀsignalꢀgoingꢀlow.ꢀTheꢀ8-bitꢀcommandꢀ
byteꢀisꢀshiftedꢀfromꢀtheꢀMSBꢀintoꢀtheꢀshiftꢀregisterꢀ
atꢀeachꢀCLKꢀrisingꢀedge.
•ꢀ TheꢀCSBꢀpinꢀisꢀusedꢀtoꢀactivateꢀtheꢀdataꢀtransfer.ꢀ
WhenꢀtheꢀCSBꢀpinꢀisꢀatꢀaꢀhighꢀlevel,ꢀtheꢀSPIꢀ
operationꢀwillꢀbeꢀresetꢀandꢀstopped.ꢀIfꢀtheꢀCSBꢀpinꢀ
changesꢀstateꢀfromꢀhighꢀtoꢀlow,ꢀdataꢀtransmissionꢀ
willꢀstart.
•ꢀ Compound Command Type
Forꢀaꢀcompoundꢀcommand,ꢀanꢀ8-bitꢀcommandꢀ
byteꢀisꢀfirstꢀshiftedꢀintoꢀtheꢀshiftꢀregisterꢀfollowedꢀ
byꢀanꢀ8-bitꢀcommandꢀsetting.ꢀNoteꢀthatꢀtheꢀCLKꢀ
highꢀpulseꢀwidth,ꢀafterꢀtheꢀcommandꢀbyteꢀhasꢀbeenꢀ
shiftedꢀin,ꢀmustꢀremainꢀatꢀthisꢀlevelꢀforꢀatꢀleastꢀ
2μsꢀafterꢀwhichꢀtheꢀcommandꢀsettingꢀdataꢀcanꢀbeꢀ
consecutivelyꢀshiftedꢀin.
•ꢀ TheꢀdataꢀisꢀtransferredꢀfromꢀtheꢀMSBꢀofꢀeachꢀbyteꢀ
andꢀisꢀshiftedꢀintoꢀtheꢀshiftꢀregisterꢀonꢀeachꢀCLKꢀ
risingꢀedge.
•ꢀ Theꢀinputꢀdataꢀisꢀautomaticallyꢀlatchedꢀintoꢀtheꢀ
internalꢀregisterꢀforꢀeachꢀ8-bitꢀinputꢀdataꢀafterꢀtheꢀ
CSBꢀsignalꢀgoesꢀlow.
•ꢀ Display RAM Single Data Byte
TheꢀdisplayꢀRAMꢀsingleꢀdataꢀwriteꢀoperationꢀ
consistsꢀofꢀaꢀdisplayꢀdataꢀinputꢀ(write)ꢀcommand,ꢀaꢀ
registerꢀaddressꢀandꢀaꢀwriteꢀdataꢀbyte.
•ꢀ Forꢀreadꢀoperations,ꢀtheꢀMCUꢀshouldꢀassertꢀaꢀhighꢀ
pulseꢀonꢀtheꢀCSBꢀpinꢀtoꢀchangeꢀtheꢀdataꢀtransferꢀ
directionꢀfromꢀinputꢀmodeꢀtoꢀoutputꢀmodeꢀonꢀtheꢀ
DIOꢀpinꢀafterꢀsendingꢀtheꢀcommandꢀbyteꢀandꢀtheꢀ
settingꢀvalues.ꢀIfꢀtheꢀMCUꢀsetsꢀtheꢀCSBꢀsignalꢀtoꢀaꢀ
highꢀlevelꢀagainꢀafterꢀreceivingꢀtheꢀoutputꢀdata,ꢀtheꢀ
dataꢀdirectionꢀonꢀtheꢀDIOꢀpinꢀwillꢀbeꢀchangedꢀintoꢀ
inputꢀmodeꢀandꢀtheꢀreadꢀoperationꢀwillꢀend.
CSB
CLK
Command byte
•ꢀ Forꢀaꢀreadꢀoperation,ꢀtheꢀdataꢀisꢀoutputꢀonꢀtheꢀDIOꢀ
pinꢀatꢀtheꢀCLKꢀfallingꢀedge.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
DIO
•ꢀ ForꢀdisplayꢀRAMꢀdataꢀread/writeꢀoperationsꢀusingꢀ
theꢀSPIꢀinterface,ꢀtheꢀread/writeꢀcontrolꢀbitꢀisꢀ
containedꢀinꢀtheꢀDisplayꢀDataꢀInputꢀCommand.ꢀ
ReferꢀtoꢀtheꢀDisplayꢀDataꢀInputꢀCommandꢀ
descriptionꢀforꢀmoreꢀdetails.
SPI Single Command Type Write Operation
CSB
2
μs(min)
CLK
Command byte
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Command setting
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DIO
SPI Compound Command Type Write Operation
CSB
CLK
2
μs(min)
2μs(min)
Display Data Input command byte
Data byte
Register Address byte
A3 A2 A1 A0
1
0
0
0
0
0
0
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
0
DIO
SPI Display RAM Single Data Byte Write Operation
Rev. 1.10
17
December 27, 2011
HT16L21
Theꢀmaximumꢀmemoryꢀaddressꢀisꢀshowꢀasꢀbelow.
Display RAM Page Write Operation
TheꢀdisplayꢀRAMꢀPageꢀwriteꢀoperationꢀconsistsꢀofꢀ
aꢀdisplayꢀdataꢀwriteꢀcommand,ꢀaꢀregisterꢀaddressꢀofꢀ
whichꢀtheꢀcontentsꢀareꢀwrittenꢀtoꢀtheꢀinternalꢀaddressꢀ
pointerꢀfollowedꢀbyꢀNꢀbytesꢀofꢀwrittenꢀdata.ꢀTheꢀ
dataꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀmemoryꢀwillꢀbeꢀtransmittedꢀ
nextꢀandꢀthenꢀtheꢀinternalꢀaddressꢀpointerꢀwillꢀbeꢀ
automaticallyꢀincrementedꢀbyꢀ1ꢀtoꢀindicateꢀtheꢀnextꢀ
memoryꢀaddressꢀlocation.ꢀAfterꢀtheꢀinternalꢀaddressꢀ
pointꢀreachesꢀtheꢀmaximumꢀmemoryꢀaddress,ꢀtheꢀ
addressꢀpointerꢀwillꢀbeꢀresetꢀtoꢀ00H.
SP1
0
SP0
X
Maximum Memory Address
0FH
0DH
0BH
1
0
1
1
CSB
CLK
2
μs(min)
2
μs(min)
2μs(min)
2
μs(min)
Data
byte
Display Data Input Command byte
Data byte
Data byte
Register Address byte
1
0
0
0
0
0
0
X
X
X
X
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7
0
DIO
1
st data
2nd data
3rd data
CSB
CLK
2
μs(min)
Data byte
DIO
D0
D7 D6 D5 D4 D3 D2 D1 D0
(N-1)th
data
Nth data
SPI Interface N Bytes Display RAM Data Write Operation
Rev. 1.10
18
December 27, 2011
HT16L21
receptionꢀofꢀeachꢀdataꢀbyte.ꢀThatꢀmeansꢀthatꢀifꢀtheꢀ
deviceꢀisꢀconfiguredꢀtoꢀtransmitꢀtheꢀdataꢀatꢀtheꢀaddressꢀ
ofꢀAN+1,ꢀtheꢀmasterꢀwillꢀreadꢀtheꢀtransferredꢀdataꢀbyteꢀ
andꢀtheꢀaddressꢀpointerꢀisꢀincrementedꢀtoꢀAN+2.ꢀAfterꢀ
theꢀinternalꢀaddressꢀpointerꢀreachesꢀtheꢀmaximumꢀ
memoryꢀaddress,ꢀtheꢀaddressꢀpointerꢀwillꢀbeꢀresetꢀtoꢀ
00H.
SPI Interface Display RAM Read Operation
Inꢀthisꢀmode,ꢀtheꢀmasterꢀreadsꢀtheꢀdeviceꢀdataꢀafterꢀ
sendingꢀtheꢀDisplayꢀDataꢀInputꢀcommandꢀwhenꢀtheꢀ
CSBꢀpinꢀchangesꢀstateꢀfromꢀhighꢀtoꢀlow.ꢀFollowingꢀ
theꢀread/writeꢀcontrolꢀbit,ꢀwhichꢀisꢀcontainedꢀinꢀtheꢀ
DisplayꢀDataꢀInputꢀcommand,ꢀisꢀtheꢀregisterꢀaddressꢀ
byteꢀwhichꢀisꢀwrittenꢀtoꢀtheꢀinternalꢀaddressꢀpointer.ꢀ
AfterꢀtheꢀstartꢀaddressꢀofꢀtheꢀReadꢀOperationꢀhasꢀ
beenꢀconfigured,ꢀanotherꢀCSBꢀhighꢀpulseꢀisꢀplacedꢀ
onꢀtheꢀbusꢀandꢀthenꢀtheꢀMSBꢀofꢀtheꢀdataꢀwhichꢀwasꢀ
addressedꢀisꢀtransmittedꢀfirstꢀonꢀtheꢀSPIꢀbus.ꢀTheꢀ
addressꢀpointerꢀisꢀonlyꢀincrementedꢀbyꢀ1ꢀafterꢀtheꢀ
Thisꢀcycleꢀofꢀreadingꢀconsecutiveꢀaddressesꢀwillꢀ
continueꢀuntilꢀtheꢀmasterꢀpullsꢀtheꢀCSBꢀlineꢀtoꢀaꢀhighꢀ
levelꢀtoꢀterminateꢀtheꢀdataꢀtransfer.
CSB
CLK
2
μs(min)
2μs(min)
2μs(min)
Data
byte
Display data Input command byte
Data byte
Data byte
Register Address byte
DIO
1
0
0
0
0
0
0
X
X
X
X
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7
1
1st data
2nd data
3rd data
CSB
CLK
2
μs(min)
Data byte
D0
D7 D6 D5 D4 D3 D2 D1 D0
DIO
(N-1)th
data
Nth data
SPI Interface N Bytes Display RAM Data Read Operation
Rev. 1.10
19
December 27, 2011
HT16L21
Command Summary
Software Reset Command
ThisꢀcommandꢀisꢀusedꢀtoꢀinitializeꢀtheꢀHT16L21ꢀdevice.
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Note R/W
Def
Soft Reset Command
Note:
1st
1
0
1
0
1
0
1
0
—
W
—
● When this software reset command is executed, all the command registers are initialized to the
default values.
● After the reset command is executed, the device will experience an internal initialization for 1ms.
● Normal operation can be executed after the device initialization is complete.
● During the initialization period, no commands can be executed.
● If the programmed command is not defined, the function will not be affected.
The status of the internal circuits after initialization is as follows:
● All segment/common outputs are set to VLCD
● The 1/3 bias drive mode is selected.
.
● The system oscillator and the LCD bias generator are in an off state.
● The LCD display is in an off state and the integrated regulator is disabled.
● The segment/LED shared pin is setup as a segment pin.
● The frame frequency is set to 64Hz.
● The blinking function is switched off.
Drive Mode Command
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note R/W Def
Drive mode setting command
Duty, Bias and pin-shared setting 2nd
1st
1
0
0
0
0
0
1
0
—
—
W
W
—
X
X
SP1 SP0
X
X
X
Bias
00H
Note:
Bit0
0
Bias
1/3 bias
1/2 bias
1
Segment/LED shared pin selected
SP1
SP0
Segment 28~31/LED3~0
Set as segment pins
Set as LED pins
Segment 24~27/LED7~4
Set as segment pins
Set as segment pins
Set as LED pins
0
1
1
X
0
1
Set as LED pins
● Power on status: The1/3 bias drive mode is selected and also the segment output pins are selected.
● If the programmed command is not defined, the function will not be affected.
Rev. 1.10
20
December 27, 2011
HT16L21
Display Data Input Command
ThisꢀcommandꢀsendsꢀdataꢀfromꢀMCUꢀtoꢀtheꢀmemoryꢀMAPꢀofꢀtheꢀHT16L21ꢀdevice.
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note
R/W Def
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Write operation
W
R
—
—
Display Data
Input/output
Command
1st
Read operation for 3-wire
SPI interface used only.
1
1
Display data start address
of memory map
Address pointer 2nd
Note:
X
X
X
X
A3 A2 A1
A0
W
00H
SP1
SP0
Maximum Memory Address
0
1
1
X
0
1
0FH
0DH
0BH
● Power on status: The address is set to 00H.
● If the programmed command is not defined, the function will not be affected.
System Mode Command
Thisꢀcommandꢀcontrolsꢀtheꢀinternalꢀsystemꢀoscillatorꢀon/offꢀandꢀdisplayꢀon/off.
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
1st
Bit6 Bit5
Bit4
0
Bit3
0
Bit2
1
Bit1
0
Note R/W
Def
—
System mode setting
command
1
0
0
0
—
—
W
W
System oscillator and
Display on/off Setting
2nd
X
X
X
X
X
X
S
E
00H
Note:
Bit
Internal System Oscillator
LCD Display
S
E
0
1
1
X
0
1
off
on
on
off
off
on
● Power on status: Display off and disable the internal system oscillator.
● If the programmed command is not defined, the function will not be affected.
Rev. 1.10
21
December 27, 2011
HT16L21
Frame Frequency Command
Thisꢀcommandꢀselectsꢀtheꢀframeꢀfrequency.
(MSB)
(LSB)
Bit0
Function
Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note R/W Def
Bit7
Frame frequency command
Frame frequency setting
Note:
1st
2nd
1
0
0
0
0
1
1
0
—
—
W
W
—
X
X
X
X
X
X
F1
F0
02H
Bit [1:0]
Frame Frequency
F1, F0
00
01
10
11
85.3Hz
170.6Hz
64Hz
128Hz
● Power on status: Frame frequency is set to 64Hz.
● If the programmed command is not defined, the function will not be affected.
Blinking Frequency Command
Thisꢀcommandꢀdefinesꢀtheꢀblinkingꢀfrequencyꢀofꢀtheꢀdisplayꢀmodes.
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note R/W Def
Blinking frequency command
1st
2nd
1
0
0
0
1
0
0
0
—
—
W
W
—
Blinking frequency setting
X
X
X
X
X
X
BK1 BK0
00H
Note:
Bit
Blinking Frequency
BK1
BK0
0
0
1
1
0
1
0
1
Blinking off
2Hz
1Hz
0.5Hz
● Power on status: Blinking function is switched off.
● If the programmed command is not defined, the function will not be affected.
LED Output Command
Thisꢀcommandꢀdefinesꢀtheꢀblinkingꢀfrequencyꢀofꢀtheꢀdisplayꢀmodes.
(MSB)
Bit7
(LSB)
Bit0
Function Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note
R/W Def
LED output
1st
1
0
0
0
1
1
0
0
—
W
W
—
command
X
X
X
X
LED3 LED2 LED1 LED0 When [SP1:SP0]=10 used
LED output
2nd
00H
data
LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 When [SP1:SP0]=11 used
Note:
● The LED registers and latches are cleared after a new configuration is written into the SP1 and SP0
bits in the Drive Mode command.
● If the programmed command is not defined, the function will not be affected.
Rev. 1.10
22
December 27, 2011
HT16L21
Internal Voltage Adjustment (IVA) Setting Command
Theꢀinternalꢀvoltageꢀ(VLCD)ꢀadjustmentꢀcanꢀprovideꢀsixteenꢀkindsꢀofꢀregulatorꢀvoltageꢀadjustmentꢀoptionsꢀbyꢀsettingꢀ
theꢀLCDꢀoperatingꢀvoltageꢀadjustmentꢀcommand.
(MSB)
Bit7
(LSB)
Bit0
Function
Byte
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Note
R/W Def
Internal voltage
adjustment
(IVA) Setting
1st
1
0
0
0
1
0
1
0
—
W
W
—
● The “VE” bit is used
to enable or disable
the internal regulator
adjustment for the LCD
voltage.
Internal voltage
adjust control
2nd
X
X
X
VE
X
V2 V1
V0
00H
● The V3~V0 bits can be
used to adjust the VLCD
voltage.
Note:
VE
Regulator Adjustment
Off – bias voltage is supplied from VLCD pin
On – bias voltage is supplied from the internal regulator
0
1
V2
V1
V0
Regulator Output Voltage (V)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0V
3.2V
3.3V
3.4V
4.4V
4.5V
4.6V
5.0V
● Power on status: Disable the internal regulator.
● When the VLCD voltage is lower than 3.5V, it is recommended to disable the internal regulator so that
the VLCD voltage is directly connected to the internal bias voltage generator.
● Caution: Use the internal regulator when the “Regulator output voltage<VLCD−0.5V”
● If the programmed command is not defined, the function will not be affected.
Rev. 1.10
23
December 27, 2011
HT16L21
Operation Flow Chart
Access procedures are illustrated below using flowcharts.
Initialization
Power On
Set Internal LCD bias and
segment/LED share pin
Set Internal LCD frame frequency
Set LCD blinking frequency
Next processing
Display Data Read/Write (Address Setting)
Start
Address setting
Display RAM data write
Display on and enable internal system clock
Next processing
Rev. 1.10
24
December 27, 2011
HT16L21
Application Circuit
I2C Interface
[SP1:SP0]=0x
•ꢀ RSTB pin is connected to a MCU
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
4.7K 4.7K
SCL
SDA
IFS
MCU
HT16L21
VSS
VDD
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
4.7K 4.7K
SCL
SDA
IFS
MCU
HT16L21
VDD
RSTB
VDD
VSS
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
4.7K 4.7K
SCL
SDA
IFS
MCU
HT16L21
VDD
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
25
December 27, 2011
HT16L21
[SP1:SP0]=10
•ꢀ RSTB pin is connected to a MCU
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
SEG0~27
4.7K 4.7K
VLCD
LED*4
RLED*4
SCL
LED0
LED1
LED2
LED3
MCU
SDA
IFS
HT16L21
VSS
VDD
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
4.7K 4.7K
VLCD
LED*4
R
LED*4
SCL
SDA
IFS
SEG0~27
LED0
LED1
LED2
LED3
MCU
HT16L21
VSS
VDD
RSTB
VDD
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
SEG0~27
4.7K 4.7K
VLCD
LED*4
R
LED*4
SCL
SDA
IFS
LED0
LED1
LED2
LED3
MCU
HT16L21
VSS
VDD
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
26
December 27, 2011
HT16L21
[SP1:SP0]=11
•ꢀ RSTB pin is connected to a MCU
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~23
SEG0~23
4.7K 4.7K
VLCD
RLED*8
LED*8
SCL
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
SDA
IFS
MCU
HT16L21
VSS
VDD
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~23
SEG0~23
4.7K 4.7K
VLCD
R
LED*8
LED*8
SCL
SDA
IFS
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
MCU
HT16L21
VDD
RSTB
VDD
VSS
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~23
SEG0~23
4.7K 4.7K
VLCD
RLED*8
LED*8
SCL
SDA
IFS
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
MCU
HT16L21
VDD
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
27
December 27, 2011
HT16L21
SPI Interface
[SP1:SP0]=0x
•ꢀ RSTB pin is connected to a MCU
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
CSB
CLK
DIO
MCU
HT16L21
VSS
IFS
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
CSB
CLK
DIO
MCU
HT16L21
IFS
RSTB
VDD
VSS
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~31
SEG0~31
CSB
CLK
DIO
MCU
HT16L21
IFS
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
28
December 27, 2011
HT16L21
[SP1:SP0]=10
•ꢀ RSTB pin is connected to a MCU
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
SEG0~27
VLCD
SCL
CLK
LED*4
R
LED*4
LED0
LED1
LED2
LED3
HT16L21
VSS
MCU
DIO
IFS
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
VLCD
CSB
CLK
DIO
SEG0~27
LED*4
R
LED*4
LED0
LED1
LED2
LED3
MCU
HT16L21
IFS
RSTB
VDD
VSS
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
COM0~COM3
SEG0~27
SEG0~27
VLCD
CSB
CLK
DIO
LED*4
RLED*4
LED0
LED1
LED2
LED3
MCU
HT16L21
IFS
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
29
December 27, 2011
HT16L21
[SP1:SP0]=11
•ꢀ RSTB pin is connected to a MCU
LCD panel
COM0~COM3
COM0~COM3
SEG0~23
SEG0~23
VLCD
R
LED*8
LED*8
CSB
CLK
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
MCU
DIO
HT16L21
VSS
IFS
RSTB
VDD
VLCD
0.1uF
0.1uF
VDD
VLCD
•ꢀ RSTB pin is connected to external resistor and capacitor
LCD panel
COM0~COM3
SEG0~23
VLCD
RLED*8
LED*8
CSB
CLK
DIO
COM0~COM3
SEG0~23
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
MCU
HT16L21
VSS
IFS
RSTB
VDD
VLCD
0.1uF
100K
0.1uF
0.1uF
VDD
VLCD
•ꢀ Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
SEG0~23
SEG0~23
VLCD
RLED*8
LED*8
CSB
CLK
COM0~COM3
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
HT16L21
MCU
DIO
IFS
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
Rev. 1.10
30
December 27, 2011
HT16L21
Package Information
Noteꢀthatꢀtheꢀpackageꢀinformationꢀprovidedꢀhereꢀisꢀforꢀconsultationꢀpurposesꢀonly.ꢀAsꢀthisꢀinformationꢀmayꢀbeꢀ
updatedꢀatꢀregularꢀintervalsꢀusersꢀareꢀremindedꢀtoꢀconsultꢀtheꢀHoltekꢀwebsiteꢀ(http://www.holtek.com.tw/english/
literature/package.pdf)ꢀforꢀtheꢀlatestꢀversionꢀofꢀtheꢀpackageꢀinformation.
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
C
H
D
G
3
3
2
3
I
3
4
2
2
F
A
B
E
1
2
4
4
=
K
J
1
1
1
Dimensions in inch
Symbol
Min.
0.469
0.390
0.469
0.390
―
Nom.
―
Max.
0.476
0.398
0.476
0.398
―
A
B
C
D
E
F
G
H
I
―
―
―
0.031
0.012
―
―
―
0.053
―
0.057
0.063
―
―
―
0.004
―
J
0.018
0.004
0°
0.030
0.008
7°
K
α
―
―
Dimensions in mm
Symbol
Min.
11.90
9.90
11.90
9.90
―
Nom.
―
Max.
12.10
10.10
12.10
10.10
―
A
B
C
D
E
F
G
H
I
―
―
―
0.80
0.30
―
―
―
1.35
―
1.45
1.60
―
―
―
0.10
―
J
0.45
0.10
0°
0.75
0.20
7°
K
α
―
―
Rev. 1.10
31
December 27, 2011
HT16L21
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
HoltekꢀSemiconductorꢀInc.ꢀ(TaipeiꢀSalesꢀOffice)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
HoltekꢀSemiconductorꢀInc.ꢀ(ShenzhenꢀSalesꢀOffice)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
HoltekꢀSemiconductorꢀ(USA),ꢀInc.ꢀ(NorthꢀAmericaꢀSalesꢀOffice)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
32
December 27, 2011
相关型号：
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