BC66F850 [HOLTEK]
2.4GHz Flash RF TX/RX MCU;
| 型号： | BC66F850 |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | 2.4GHz Flash RF TX/RX MCU LTE |
| 文件： | 总242页 (文件大小：7029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.4GHz Flash RF TX/RX MCU
BC66F840/BC66F850/BC66F860
Revision: V1.40 Date: �aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Table of Contents
Features............................................................................................................ 7
CPU Features ......................................................................................................................... ꢃ
Peripheral Features................................................................................................................. ꢃ
RF Transceiver Features......................................................................................................... 8
General Description......................................................................................... 8
Selection Table................................................................................................. 9
Block Diagram.................................................................................................. 9
Pin Assignment.............................................................................................. 10
Pin Descriptions ............................................................................................ 13
Absolute Maximum Ratings.......................................................................... 19
D.C. Characteristics....................................................................................... 19
A.C. Characteristics....................................................................................... 21
LVD & LVR Electrical Characteristics .......................................................... 21
ADC Characteristics...................................................................................... 22
Comparator Electrical Characteristics ........................................................ 22
RF Transceiver Electrical Characteristics................................................... 23
Power on Reset Electrical Characteristics.................................................. 24
System Architecture...................................................................................... 25
Clocking and Pipelining......................................................................................................... ꢁ5
Program Counter................................................................................................................... ꢁ6
Stack ..................................................................................................................................... ꢁꢃ
Arithmetic and Logic Unit – ALU ........................................................................................... ꢁꢃ
Flash Program Memory................................................................................. 28
Structure................................................................................................................................ ꢁ8
Special Vectors ..................................................................................................................... ꢁ9
Look-up Table........................................................................................................................ ꢁ9
Table Program Example........................................................................................................ ꢁ9
In Circuit Programming ......................................................................................................... 30
On-Chip Debug Support – OCDS ......................................................................................... 31
RAM Data Memory......................................................................................... 32
Structure................................................................................................................................ 3ꢁ
General Purpose Data �emorꢀ ............................................................................................ 3ꢁ
Special Purpose Data �emorꢀ ............................................................................................. 33
Rev. 1.40
ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Special Function Register Description........................................................ 36
Indirect Addressing Registers – IAR0ꢂ IAR1 ......................................................................... 36
�emorꢀ Pointers – �P0ꢂ �P1 .............................................................................................. 36
Bank Pointer – BP................................................................................................................. 3ꢃ
Accumulator – ACC............................................................................................................... 38
Program Counter Low Register – PCL.................................................................................. 38
Look-up Table Registers – TBLPꢂ TBHPꢂ TBLH..................................................................... 38
Status Register – STATUS.................................................................................................... 39
EEPROM Data Memory.................................................................................. 41
EEPRO� Data �emorꢀ Structure ........................................................................................ 41
EEPRO� Registers .............................................................................................................. 41
Reading Data from the EEPRO� ......................................................................................... 44
Writing Data to the EEPRO�................................................................................................ 44
Write Protection..................................................................................................................... 44
EEPRO� Interrupt ................................................................................................................ 44
Programming Considerations................................................................................................ 45
Oscillator ........................................................................................................ 46
Oscillator Overview ............................................................................................................... 46
System Clock Configurations................................................................................................ 46
External Crꢀstal/Ceramic Oscillator – HXT ........................................................................... 4ꢃ
External 3ꢁ.ꢃ68kHz Crꢀstal Oscillator – LXT........................................................................ 48
Internal 3ꢁkHz Oscillator – LIRC........................................................................................... 49
Supplementarꢀ Oscillator...................................................................................................... 49
Operating Modes and System Clocks ......................................................... 50
Sꢀstem Clocks ...................................................................................................................... 50
Sꢀstem Operation �odes...................................................................................................... 51
Control Register .................................................................................................................... 5ꢁ
Fast Wake-up........................................................................................................................ 55
Operating �ode Switching.................................................................................................... 56
Standbꢀ Current Considerations........................................................................................... 60
Wake-up................................................................................................................................ 60
Programming Considerations................................................................................................ 61
Watchdog Timer............................................................................................. 61
Watchdog Timer Clock Source.............................................................................................. 61
Watchdog Timer Control Register......................................................................................... 61
Watchdog Timer Operation ................................................................................................... 63
Reset and Initialisation.................................................................................. 64
Reset Functions .................................................................................................................... 64
Reset Initial Conditions ......................................................................................................... 68
Rev. 1.40
3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Input/Output Ports......................................................................................... 72
I/O Resistor Lists................................................................................................................... ꢃꢁ
Pull-high Resistors ................................................................................................................ ꢃ4
Port A Wake-up ..................................................................................................................... ꢃ4
I/O Port Control Registers..................................................................................................... ꢃ4
I/O Pin Structures.................................................................................................................. ꢃ4
Programming Considerations................................................................................................ ꢃ6
Timer Modules – TM ...................................................................................... 77
Introduction ........................................................................................................................... ꢃꢃ
T� Operation ........................................................................................................................ ꢃꢃ
T� Clock Source................................................................................................................... ꢃ8
T� Interrupts......................................................................................................................... ꢃ8
T� External Pins................................................................................................................... ꢃ8
T� Input/Output Pin Control Registers ................................................................................. ꢃ9
Programming Considerations................................................................................................ 83
Compact Type TM – CTM .............................................................................. 84
Compact T� Operation......................................................................................................... 84
Compact Tꢀpe T� Register Description................................................................................ 85
Compact Tꢀpe T� Operation �odes .................................................................................... 89
Compare �atch Output �ode............................................................................................... 89
Timer/Counter �ode ............................................................................................................. 9ꢁ
PW� Output �ode................................................................................................................ 9ꢁ
Standard Type TM – STM .............................................................................. 95
Standard T� Operation......................................................................................................... 95
Standard Tꢀpe T� Register Description ............................................................................... 96
Standard Tꢀpe T� Operation �odes.................................................................................. 100
Compare �atch Output �ode............................................................................................. 100
Timer/Counter �ode ........................................................................................................... 103
PW� Output �ode.............................................................................................................. 103
Single Pulse �ode .............................................................................................................. 106
Capture Input �ode ............................................................................................................ 108
Enhanced Type TM – ETM........................................................................... 109
Enhanced T� Operation..................................................................................................... 109
Enhanced Tꢀpe T� Register Description.............................................................................110
Enhanced Tꢀpe T� Operation �odes..................................................................................11ꢃ
Compare �atch Output �ode..............................................................................................11ꢃ
Timer/Counter �ode ........................................................................................................... 1ꢁꢁ
PW� Output �ode.............................................................................................................. 1ꢁꢁ
Single Pulse Output �ode .................................................................................................. 1ꢁ8
Capture Input �ode ............................................................................................................ 130
Rev. 1.40
4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Analog to Digital Converter ........................................................................ 133
A/D Overview ...................................................................................................................... 133
A/D Converter Register Description.................................................................................... 134
A/D Converter Data Registers – ADRLꢂ ADRH ................................................................... 135
A/D Converter Control Registers – ADCR0ꢂ ADCR1ꢂ ACERLꢂ ACERH .............................. 135
A/D Operation ..................................................................................................................... 141
A/D Input Pins ..................................................................................................................... 14ꢁ
Summarꢀ of A/D Conversion Steps..................................................................................... 143
Programming Considerations.............................................................................................. 144
A/D Transfer Function ......................................................................................................... 144
A/D Programming Examples............................................................................................... 145
Comparators ................................................................................................ 147
Comparator Operation ........................................................................................................ 14ꢃ
Comparator Interrupt........................................................................................................... 14ꢃ
Programming Considerations.............................................................................................. 14ꢃ
Serial Interface Module – SIM..................................................................... 149
SPI Interface ....................................................................................................................... 149
SPI Interface Operation....................................................................................................... 150
SPI Registers ...................................................................................................................... 151
SPI Communication ............................................................................................................ 154
IꢁC Interface ........................................................................................................................ 156
IꢁC Interface Operation........................................................................................................ 156
IꢁC Registers ....................................................................................................................... 15ꢃ
IꢁC Bus Communication ...................................................................................................... 161
IꢁC Bus Start Signal............................................................................................................. 16ꢁ
Slave Address ..................................................................................................................... 16ꢁ
IꢁC Bus Read/Write Signal .................................................................................................. 16ꢁ
IꢁC Bus Slave Address Acknowledge Signal....................................................................... 16ꢁ
IꢁC Bus Data and Acknowledge Signal ............................................................................... 163
IꢁC Time-out Control............................................................................................................ 164
Peripheral Clock Output.............................................................................. 166
Peripheral Clock Operation................................................................................................. 166
Serial Interface – SPIA................................................................................. 167
SPIA Interface Operation .................................................................................................... 168
SPIA Registers.................................................................................................................... 169
SPIA Communication .......................................................................................................... 1ꢃꢁ
SPIA Bus Enable/Disable.................................................................................................... 1ꢃꢁ
SPIA Operation ................................................................................................................... 1ꢃ4
Error Detection.................................................................................................................... 1ꢃ6
Rev. 1.40
5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Interrupts...................................................................................................... 177
Interrupt Registers............................................................................................................... 1ꢃꢃ
Interrupt Operation.............................................................................................................. 185
External Interrupt................................................................................................................. 18ꢃ
Comparator Interrupt........................................................................................................... 18ꢃ
�ulti-function Interrupt ........................................................................................................ 18ꢃ
A/D Converter Interrupt....................................................................................................... 188
Time Base Interrupt............................................................................................................. 188
EEPRO� Interrupt .............................................................................................................. 190
LVD Interrupt....................................................................................................................... 190
Serial Interface �odule Interrupt......................................................................................... 190
SPIA Interface Interrupt....................................................................................................... 191
T� Interrupt......................................................................................................................... 191
Interrupt Wake-up Function................................................................................................. 191
Programming Considerations.............................................................................................. 19ꢁ
Low Voltage Detector – LVD ....................................................................... 193
LVD Register....................................................................................................................... 193
LVD Operation..................................................................................................................... 194
RF Transceiver............................................................................................. 195
RF Transceiver Abbreviations ............................................................................................. 196
RF Transceiver State Control.............................................................................................. 19ꢃ
RF Transceiver Packet Processing..................................................................................... ꢁ00
RF Transceiver Data and Control Interface......................................................................... ꢁ03
RF Transceiver Register �ap ............................................................................................. ꢁ0ꢃ
Configuration Options................................................................................. 223
Application Circuits..................................................................................... 224
Instruction Set.............................................................................................. 225
Introduction ......................................................................................................................... ꢁꢁ5
Instruction Timing................................................................................................................ ꢁꢁ5
�oving and Transferring Data............................................................................................. ꢁꢁ5
Arithmetic Operations.......................................................................................................... ꢁꢁ5
Logical and Rotate Operation ............................................................................................. ꢁꢁ6
Branches and Control Transfer ........................................................................................... ꢁꢁ6
Bit Operations ..................................................................................................................... ꢁꢁ6
Table Read Operations ....................................................................................................... ꢁꢁ6
Other Operations................................................................................................................. ꢁꢁ6
Instruction Set Summary ............................................................................ 227
Table Conventions............................................................................................................... ꢁꢁꢃ
Instruction Definition................................................................................... 229
Package Information ................................................................................... 238
SAW Tꢀpe 3ꢁ-pin (5mm×5mm) QFN Outline Dimensions.................................................. ꢁ39
SAW Tꢀpe 40-pin (6mm×6mm for 0.ꢃ5mm) QFN Outline Dimensions............................... ꢁ40
SAW Tꢀpe 46-pin (6.5mm×4.5mm) QFN Outline Dimensions............................................ ꢁ41
Rev. 1.40
6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Features
CPU Features
•ꢀ Operatingꢀvoltage:
ꢀ
♦
fSYS=16MHz:ꢀ3.3V~5.5V
•ꢀ 0.25μsꢀinstructionꢀcycleꢀwithꢀ16MHzꢀsystemꢀclockꢀatꢀVDD=5V
•ꢀ Powerꢀdownꢀandꢀwake-upꢀfunctionsꢀtoꢀreduceꢀpowerꢀconsumption
•ꢀ Oscillatorꢀtypes:
ꢀ
♦
ꢀ
♦
ꢀ
♦
Externalꢀ16MHzꢀCrystalꢀ--ꢀHXT
Externalꢀ32.768kHzꢀCrystalꢀ--ꢀLXT
Internalꢀ32kHzꢀRCꢀ--ꢀLIRC
•ꢀ Multi-modeꢀoperation:ꢀNORMAL,ꢀSLOW,ꢀIDLEꢀandꢀSLEEP
•ꢀ Allꢀinstructionsꢀexecutedꢀinꢀoneꢀorꢀtwoꢀinstructionꢀcycles
•ꢀ Tableꢀreadꢀinstructions
•ꢀ 63ꢀpowerfulꢀinstructions
•ꢀ Upꢀtoꢀ12-levelꢀsubroutineꢀnesting
•ꢀ Bitꢀmanipulationꢀinstruction
Peripheral Features
•ꢀ ProgramꢀMemory:ꢀUpꢀtoꢀ16K×16
•ꢀ RAMꢀDataꢀMemory:ꢀUpꢀtoꢀ512×8
•ꢀ TrueꢀEEPROMꢀMemory:ꢀUpꢀtoꢀ256×8
•ꢀ WatchdogꢀTimerꢀfunction
•ꢀ Upꢀtoꢀ35ꢀbidirectionalꢀI/Oꢀlines
•ꢀ Twoꢀpin-sharedꢀexternalꢀinterrupts
•ꢀ MultipleꢀTimerꢀModuleꢀforꢀtimeꢀmeasure,ꢀinputꢀcapture,ꢀcompareꢀmatchꢀoutput,ꢀPWMꢀoutputꢀorꢀ
singleꢀpulseꢀoutputꢀfunction
•ꢀ SerialꢀInterfaceꢀModuleꢀ–ꢀSIMꢀ(SPI/I2C)
•ꢀ IndividualꢀSPIꢀinterfaceꢀ–ꢀSPIA
•ꢀ Comparatorꢀfunction
•ꢀ DualꢀTime-Baseꢀfunctionsꢀforꢀgenerationꢀofꢀfixedꢀtimeꢀinterruptꢀsignals
•ꢀ Upꢀtoꢀ16ꢀchannelsꢀ12-bitꢀA/DꢀConverter
•ꢀ Lowꢀvoltageꢀresetꢀfunction
•ꢀ Lowꢀvoltageꢀdetectꢀfunction
•ꢀ Packageꢀtypes:ꢀ32/40/46ꢀpinꢀQFN
Rev. 1.40
ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Features
•ꢀ LowꢀPowerꢀHighꢀPerformanceꢀ2.4GHzꢀGFSKꢀTransceiver
•ꢀ 2400-2483.5MHzꢀISMꢀbandꢀoperation
•ꢀ Supportꢀ250Kbps,ꢀ1Mbpsꢀandꢀ2Mbpsꢀairꢀdataꢀrate
•ꢀ Programmableꢀoutputꢀpower
•ꢀ Variableꢀpayloadꢀlengthꢀfromꢀ1ꢀtoꢀ32ꢀbytes
•ꢀ Automaticꢀpacketꢀprocessing
•ꢀ 6ꢀdataꢀpipesꢀforꢀ1:6ꢀstarꢀnetworks
General Description
TheꢀdevicesꢀareꢀFlashꢀMemoryꢀtypeꢀ8-bitꢀhighꢀperformanceꢀRISCꢀarchitectureꢀmicrocontrollers.ꢀ
OfferingꢀusersꢀtheꢀconvenienceꢀofꢀFlashꢀMemoryꢀmulti-programmingꢀfeatures,ꢀtheseꢀdevicesꢀalsoꢀ
includeꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀandꢀfeatures.ꢀOtherꢀmemoryꢀincludesꢀanꢀareaꢀofꢀRAMꢀDataꢀ
MemoryꢀasꢀwellꢀasꢀanꢀareaꢀofꢀtrueꢀEEPROMꢀmemoryꢀforꢀstorageꢀofꢀnon-volatileꢀdataꢀsuchꢀasꢀserialꢀ
numbers,ꢀcalibrationꢀdataꢀetc.ꢀ
Analogꢀfeaturesꢀincludeꢀaꢀmulti-channelꢀ12-bitꢀA/Dꢀconverterꢀandꢀaꢀcomparatorꢀfunctions.ꢀMultipleꢀ
andꢀextremelyꢀflexibleꢀTimerꢀModulesꢀprovideꢀtiming,ꢀpulseꢀgenerationꢀandꢀPWMꢀgenerationꢀ
functions.ꢀProtectiveꢀfeaturesꢀsuchꢀasꢀanꢀinternalꢀWatchdogꢀTimer,ꢀLowꢀVoltageꢀResetꢀandꢀLowꢀ
VoltageꢀDetectorꢀcoupledꢀwithꢀexcellentꢀnoiseꢀimmunityꢀandꢀESDꢀprotectionꢀensureꢀthatꢀreliableꢀ
operationꢀisꢀmaintainedꢀinꢀhostileꢀelectricalꢀenvironments.
AꢀfullꢀchoiceꢀofꢀHXT,ꢀLXTꢀandꢀLIRCꢀoscillatorꢀfunctionsꢀareꢀprovidedꢀincludingꢀaꢀfullyꢀintegratedꢀ
systemꢀoscillatorꢀwhichꢀrequiresꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀimplementation.ꢀTheꢀabilityꢀtoꢀ
operateꢀandꢀswitchꢀdynamicallyꢀbetweenꢀaꢀrangeꢀofꢀoperatingꢀmodesꢀusingꢀdifferentꢀclockꢀsourcesꢀ
givesꢀusersꢀtheꢀabilityꢀtoꢀoptimiseꢀmicrocontrollerꢀoperationꢀandꢀminimizeꢀpowerꢀconsumption.
TheꢀinclusionꢀofꢀflexibleꢀI/Oꢀprogrammingꢀfeatures,ꢀTime-Baseꢀfunctionsꢀalongꢀwithꢀmanyꢀotherꢀ
featuresꢀensureꢀthatꢀtheꢀdevicesꢀwillꢀfindꢀexcellentꢀuseꢀinꢀapplicationsꢀsuchꢀasꢀelectronicꢀmetering,ꢀ
environmentalꢀmonitoring,ꢀhandheldꢀinstruments,ꢀhouseholdꢀappliances,ꢀelectronicallyꢀcontrolledꢀ
tools,ꢀmotorꢀdrivingꢀinꢀadditionꢀtoꢀmanyꢀothers.
Rev. 1.40
8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Selection Table
Mostꢀfeaturesꢀareꢀcommonꢀtoꢀallꢀdevices,ꢀtheꢀmainꢀfeatureꢀdistinguishingꢀthemꢀareꢀMemoryꢀcapacity,ꢀ
I/Oꢀcount,ꢀA/DꢀConverterꢀchannels,ꢀTMꢀfeatures,ꢀstackꢀcapacityꢀandꢀpackageꢀtypes.ꢀTheꢀfollowingꢀ
tableꢀsummarisesꢀtheꢀmainꢀfeaturesꢀofꢀeachꢀdevice.
Program
Memory
Data
Memory
EEPROM
Memory
External
Interrupt
Part No.
I/O
A/D Converter
BC66F840
BC66F850
BC66F860
4k×16
8k×16
ꢁ56×8
384×8
51ꢁ×8
1ꢁ8×8
ꢁ56×8
ꢁ56×8
ꢁ1
ꢁ9
35
ꢁ
ꢁ
ꢁ
1ꢁ-bit×8
1ꢁ-bit×16
1ꢁ-bit×16
16k×16
Part No.
Timer Module SIM SPIA Time Base Comparator
Stacks
Package
16-bit CT�×1
BC66F840
16-bit ST�×1
16-bit ET�×1
√
√
√
√
√
√
ꢁ
ꢁ
ꢁ
1
1
1
8
8
3ꢁQFN
16-bit CT�×ꢁ
16-bit ST�×1
16-bit ET�×1
BC66F850
BC66F860
40QFN
46QFN
16-bit CT�×ꢁ
16-bit ST�×1
16-bit ET�×1
1ꢁ
Block Diagram
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Rev. 1.40
9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pin Assignment
2
2
2
2
5
2
6
3
3
7
3
8
9
0
1
2
V
D
D
O
I
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3
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1
2
3
4
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6
7
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4
3
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9
8
7
P
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6
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6
6
8
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2
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9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
2
2
2
2
5
2
6
3
3
7
3
8
9
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2
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5
B
T
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3
P
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1
2
3
4
5
6
7
8
2
2
2
2
2
1
1
1
4
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2
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0
9
8
7
P
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3
B
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0
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2
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6
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3
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5
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0
P
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2
B
6
C
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6
4
8
0
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P
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2
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1
0
B
S
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B
D
R
/
S
E
O
/
C
D
S
/
C
C
I
C
P
K
P
4
C
T
/
K
C
/
2
C
T
3
K
T
/
0
P
3
2
Q
F
-
N
A
P
3
C
S
/
K
C
S
/
L
C
X
X
/
/
2
T
P
2
C
S
/
I
D
S
/
A
D
1
T
P
1
C
S
/
O
D
D
P
0
C
S
/
S
C
9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
Rev. 1.40
10
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
3
3
3
3
3
1
2
3
3
3
4
3
5
4
6
7
8
9
0
P
3
C
S
/
K
C
S
/
L
C
1
2
3
4
5
6
7
8
9
1
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
P
P
5
4
3
B
B
B
P
2
C
S
/
I
D
S
/
A
D
P
1
C
S
/
O
D
P
O
O
P
V
P
P
V
I
/
T
N
C
S
2
P
0
C
S
/
S
C
P
7
E
P
/
K
C
/
1
A
5
N
C
S
1
B
C
6
6
8
F
0
5
2
S
1
0
B
S
B
B
D
R
/
S
E
P
6
E
T
/
3
P
/
A
N
A
A
4
1
4
0
Q
F
-
N
A
P
5
E
T
/
3
P
/
B
N
3
1
P
4
E
T
/
K
C
/
0
C
T
1
K
T
/
2
P
A
/
1
N
2
X
X
/
/
2
1
T
T
P
3
E
T
/
1
P
A
/
1
N
1
0
P
2
E
T
/
K
C
/
2
C
T
3
K
T
/
0
P
A
/
1
N
0
D
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
3
3
3
3
3
1
2
3
3
3
3
4
3
5
4
6
7
8
9
0
P
3
C
S
/
K
C
S
/
L
C
1
2
3
4
5
6
7
8
9
1
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
P
P
5
B
4
3
B
B
O
I
/
/
D
C
C
S
/
A
C
I
P
D
A
P
2
C
S
/
I
D
S
/
A
D
P
1
C
S
/
O
D
P
O
O
P
V
P
P
V
T
N
0
C
S
2
P
0
C
S
/
S
C
P
7
E
P
/
K
C
/
1
A
5
N
C
S
1
B
C
6
6
8
V
0
5
P
6
E
T
/
3
P
/
A
N
A
A
4
1
2
S
1
0
B
S
B
B
D
R
/
S
E
O
/
C
D
S
/
C
C
I
P
K
C
K
4
0
Q
F
-
N
A
P
5
E
T
/
3
P
/
B
N
3
1
P
4
E
T
/
K
C
/
0
C
T
1
K
T
/
2
P
A
/
1
N
2
X
X
/
/
2
T
P
3
E
T
/
1
P
A
/
1
N
1
1
T
0
P
2
E
T
/
K
C
/
2
C
T
3
K
T
/
0
P
A
/
1
N
0
D
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
Rev. 1.40
11
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
46 45 44 43 4ꢁ 41 40 39 38 3ꢃ 36 35 34 33
1
ꢁ
3
4
5
6
ꢃ
8
9
3ꢁ
31
30
ꢁ9
ꢁ8
ꢁꢃ
ꢁ6
ꢁ5
ꢁ4
PB6
VDDPA
RFP1
PA4/AN4
PA5/AN5
PA6/AN6
PAꢃ/ANꢃ
PE0/AN8
PE1/AN9
PEꢁ/AN10
PE3/AN11
PE4/AN1ꢁ
RFN1
VSSRXꢁ
BC66F860
46 QFN-A
VDD3RXRF/VDD3IF
VDD3B
CDVDD
VDDIO/PF3
10 11 1ꢁ 13 14 15 16 1ꢃ 18 19 ꢁ0 ꢁ1 ꢁꢁ ꢁ3
46 45 44 43 4ꢁ 41 40 39 38 3ꢃ 36 35 34 33
1
3ꢁ
31
30
ꢁ9
ꢁ8
ꢁꢃ
ꢁ6
ꢁ5
ꢁ4
PB6
VDDPA
RFP1
PA4/AN4
PA5/AN5
PA6/AN6
PAꢃ/ANꢃ
PE0/AN8
PE1/AN9
PEꢁ/AN10
PE3/AN11
PE4/AN1ꢁ
ꢁ
3
4
5
6
ꢃ
8
9
RFN1
VSSRXꢁ
BC66V860
46 QFN-A
VDD3RXRF/VDD3IF
VDD3B
CDVDD
VDDIO/PF3
10 11 1ꢁ 13 14 15 16 1ꢃ 18 19 ꢁ0 ꢁ1 ꢁꢁ ꢁ3
Rev. 1.40
1ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pin Descriptions
Withꢀtheꢀexceptionꢀofꢀtheꢀpowerꢀpins,ꢀallꢀpinsꢀonꢀtheseꢀdevicesꢀcanꢀbeꢀreferencedꢀbyꢀtheirꢀPortꢀname,ꢀ
e.g.ꢀPA0,ꢀPA1,ꢀetc,ꢀwhichꢀreferꢀtoꢀtheꢀdigitalꢀI/Oꢀfunctionꢀofꢀtheꢀpins.ꢀHoweverꢀsomeꢀofꢀtheseꢀPortꢀ
pinsꢀareꢀalsoꢀsharedꢀwithꢀotherꢀfunctionꢀsuchꢀasꢀtheꢀAnalogꢀtoꢀDigitalꢀConverter,ꢀTimerꢀModuleꢀpinsꢀ
etc.ꢀTheꢀfunctionꢀofꢀeachꢀpinꢀisꢀlistedꢀinꢀtheꢀfollowingꢀtable,ꢀhoweverꢀtheꢀdetailsꢀbehindꢀhowꢀeachꢀ
pinꢀisꢀconfiguredꢀisꢀcontainedꢀinꢀotherꢀsectionsꢀofꢀtheꢀdatasheet.
TheꢀBC66V8x0ꢀdeviceꢀisꢀtheꢀcorrespondingꢀEVꢀchipꢀofꢀtheꢀBC66F8x0ꢀdevice.ꢀItꢀsupportsꢀtheꢀ“On-
ChipꢀDebug”ꢀfunctionꢀforꢀdebuggingꢀduringꢀdevelopmentꢀusingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀ
connectedꢀtoꢀtheꢀHoltekꢀHT-IDEꢀdevelopmentꢀtools.
BC66F840/BC66V840
Pin Name
Function
OP
I/T
O/T Pin-Shared Mapping
Microcontroller Pins
PAWU
PAPU
PA0~PAꢃ
Port A
ST C�OS
—
PB0~PB5
PC0~PC6
PD0~PD5
CLKO
Port B
Port C
PBPU
PCPU
PDPU
ST C�OS
ST C�OS
ST C�OS
—
—
—
—
Port Dꢂ internallꢀ connected to RF transceiver
Clock outputꢂ internallꢀ connected to RF transceiver CTRL1
—
C�OS
—
AN0~ANꢃ
VREF
A/D Converter input
A/D Converter reference input
Comparator input
ACERL AN
ADCR1 AN
PA0~PAꢃ
PA3
—
C+ꢂ C-
CPC
CPC
—
AN
—
—
PA0ꢂ PA1
CX
Comparator output
T�0 input
C�OS PAꢁ
TCK0
ST
ST
—
—
PC5
PC4
TCKꢁ~TCK3 T�ꢁꢂ T�3 input
TP0ꢂ TPꢁ T�0ꢂ T�ꢁ I/O
TP3Aꢂ TP3B T�3 I/O
—
T�PC
T�PC
ST C�OS PC4ꢂ PC5
ST C�OS PB5ꢂ PC6
INTEG
INTC0
INT0
INT1
External Interrupt 0
ST
ST
—
—
PB3
PDꢁ
External Interrupt 1
Internallꢀ connected to RF transceiver
INTEG
INTC0
PCK
SDI
Peripheral Clock output
SPI Data input
SPI Data output
SPI Slave Select
SPI Serial Clock
IꢁC Clock
—
—
—
ST
—
C�OS PAꢃ
PCꢁ
C�OS PC1
—
SDO
SCS
—
—
ST C�OS PC0
ST C�OS PC3
ST N�OS PC3
ST N�OS PCꢁ
SCK
SCL
—
—
SDA
OSC1
OSCꢁ
XT1
IꢁC Data
—
HXT pin
CO
CO
CO
CO
CO
—
HXT
—
—
HXT
—
—
—
HXT pin
LXT pin
LXT
—
PB0
XTꢁ
LXT pin
LXT PB1
RES
Reset pin
ST
—
—
—
PBꢁ
PB5
VDDIO
VDD
Power supplꢀ for interconnected pins
Positive Power supplꢀ
PWR
PWR
—
—
Rev. 1.40
13
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pin Name
VSS
Function
OP
—
—
—
—
—
I/T
PWR
—
O/T Pin-Shared Mapping
Negative power supplꢀꢂ ground
—
—
OCDSCK
OCDSDA
ICPCK
OCDS clock pinꢂ for EV chip used onlꢀ
OCDS data pinꢂ for EV chip used onlꢀ
ICP clock pinꢂ for EV chip used onlꢀ
ICP data pinꢂ for EV chip used onlꢀ
C�OS PBꢁ
ST N�OS PB4
C�OS PBꢁ
ST N�OS PB4
—
ICPDA
2.4GHz RF Transceiver Pins
RFP1
RF positive input/output port
—
—
—
—
—
—
—
—
—
—
—
—
RFN1
VDDPA
RF negative input/output port
1.8V Regulator output for Power Amplifier
VDD3RXRF/
VDD3IF
RF Transceiver positive power supplꢀ
—
PWR
—
—
VDD3B
CDVDD
VSSRXꢁ
RF Transceiver positive power supplꢀ
—
—
—
PWR
—
—
—
—
—
—
—
1.8V regulator output decoupling capacitor pin
RF Transceiver negative power supplꢀꢂ ground
PWR
Note:ꢀI/T:ꢀInputꢀtype;ꢀ
ꢀ
ꢀ
O/T:ꢀOutputꢀtype
OP:ꢀOptionalꢀbyꢀconfigurationꢀoptionꢀ(CO)ꢀorꢀregisterꢀoption
PWR:ꢀPower;ꢀ
ꢀ
ꢀ
ꢀ
CO:ꢀConfigurationꢀoption;ꢀ ST:ꢀSchmittꢀTriggerꢀinput
NMOS:ꢀNMOSꢀoutput
CMOS:ꢀCMOSꢀoutput;ꢀꢀ
SCOM:ꢀSoftwareꢀcontrolledꢀLCDꢀCOM;ꢀ AN:ꢀAnalogꢀinputꢀpin
HXT:ꢀHighꢀfrequencyꢀcrystalꢀoscillator
LXT:ꢀLowꢀfrequencyꢀcrystalꢀoscillator
BC66F850/BC66V850
Pin-Shared
Mapping
Pin Name
Microcontroller Pins
Function
OP
I/T
O/T
PAWU
PAPU
PA0~PAꢃ
Port A
ST C�OS
—
PB0~PB6
PC0~PC5
PD0~PD5
CLKO
Port B
Port C
PBPU
PCPU
PDPU
ST C�OS
ST C�OS
ST C�OS
—
—
Port Dꢂ internallꢀ connected to RF transceiver
—
Clock outputꢂ internallꢀ connected to RF transceiver CTRL1
—
C�OS
—
PE0~PEꢃ
AN0~AN15
VREF
Port E
PEPU
ST C�OS
—
PA0~PAꢃꢂ PE0~PEꢃ
PA3
A/D Converter input
A/D Converter reference input
Comparator input
Comparator output
ACERL AN
ADCR1 AN
—
—
—
C+ꢂ C-
CPC
CPC
—
AN
—
PA0ꢂ PA1
CX
C�OS PAꢁ
TCK0~TCK1 T�0ꢂ T�1 input
TCKꢁ~TCK3 T�ꢁꢂ T�3 input
ST
ST
—
—
PE4
PEꢁ
—
TP0~TPꢁ
T�0~T�ꢁ I/O
T�3 I/O
T�PC
T�PC
ST C�OS PEꢁ~PE4
ST C�OS PE6ꢂ PE5
TP3Aꢂ TP3B
Rev. 1.40
14
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pin-Shared
Mapping
Pin Name
INT0
Function
OP
I/T
ST
ST
O/T
—
INTEG
INTC0
External Interrupt 0
External Interrupt 1
PB3
PDꢁ
INTEG
INTC0
INT1
—
Internallꢀ connected to RF transceiver
Peripheral Clock output
SPI Data input
PCK
—
—
—
ST
—
C�OS PEꢃ
PCꢁ
C�OS PC1
SDI
—
SDO
SPI Data output
—
SCS
SPI Slave Select
—
ST C�OS PC0
ST C�OS PC3
ST N�OS PC3
ST N�OS PCꢁ
SCK
SPI Serial Clock
—
SCL
IꢁC Clock
—
SDA
IꢁC Data
—
OSC1
OSCꢁ
XT1
HXT pin
CO
CO
CO
CO
CO
—
HXT
—
—
HXT
—
—
—
HXT pin
LXT pin
LXT
—
PB0
XTꢁ
LXT pin
LXT PB1
RES
Reset pin
ST
—
—
—
—
PBꢁ
PC5
VDDIO
VDD
Power supplꢀ for interconnected pins
Positive Power supplꢀ
Negative power supplꢀꢂ ground
OCDS clock pinꢂ for EV chip used onlꢀ
OCDS data pinꢂ for EV chip used onlꢀ
ICP clock pinꢂ for EV chip used onlꢀ
ICP data pinꢂ for EV chip used onlꢀ
PWR
PWR
PWR
—
—
—
—
VSS
—
OCDSCK
OCDSDA
ICPCK
ICPDA
—
C�OS PBꢁ
—
ST N�OS PB4
C�OS PBꢁ
ST N�OS PB4
—
—
—
2.4GHz RF Transceiver Pins
RFP1
RF positive input/output port
—
—
—
—
—
—
—
—
—
—
—
—
RFN1
VDDPA
RF negative input/output port
1.8V Regulator output for Power Amplifier
VDD3RXRF/
VDD3IF
RF Transceiver positive power supplꢀ
—
PWR
—
—
VDD3B
CDVDD
VSSRXꢁ
RF Transceiver positive power supplꢀ
—
—
—
PWR
—
—
—
—
—
—
—
1.8V regulator output decoupling capacitor pin
RF Transceiver negative power supplꢀꢂ ground
PWR
Note:ꢀI/T:ꢀInputꢀtype;ꢀ
ꢀ
ꢀ
O/T:ꢀOutputꢀtype
OP:ꢀOptionalꢀbyꢀconfigurationꢀoptionꢀ(CO)ꢀorꢀregisterꢀoption
PWR:ꢀPower;ꢀ
ꢀ
ꢀ
ꢀ
CO:ꢀConfigurationꢀoption;ꢀ ST:ꢀSchmittꢀTriggerꢀinput
NMOS:ꢀNMOSꢀoutput
CMOS:ꢀCMOSꢀoutput;ꢀꢀ
SCOM:ꢀSoftwareꢀcontrolledꢀLCDꢀCOM;ꢀ AN:ꢀAnalogꢀinputꢀpin
HXT:ꢀHighꢀfrequencyꢀcrystalꢀoscillator
LXT:ꢀLowꢀfrequencyꢀcrystalꢀoscillator
Rev. 1.40
15
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
BC66F860/BC66V860
Pin Name
Microcontroller Pins
Function
OP
I/T
O/T Pin-Shared Mapping
PAWU
PAPU
PA0~PAꢃ
Port A
ST C�OS
—
PB0~PB6
PC0~PC5
PD0~PD5
CLKO
Port B
Port C
PBPU
PCPU
PDPU
ST C�OS
ST C�OS
ST C�OS
—
—
Port Dꢂ internallꢀ connected to RF transceiver
—
Clock outputꢂ internallꢀ connected to RF transceiver CTRL1
—
C�OS
—
PE0~PEꢃ
AN0~AN15
VREF
Port E
PEPU
ST C�OS
—
PA0~PAꢃꢂ PE0~PEꢃ
PA3
A/D Converter input
A/D Converter reference input
Comparator input
Comparator output
ACERL AN
ADCR1 AN
—
—
—
C+ꢂ C-
CPC
CPC
—
AN
—
PA0ꢂ PA1
CX
C�OS PAꢁ
TCK0~TCK1 T�0ꢂ T�1 input
TCKꢁ~TCK3 T�ꢁꢂ T�3 input
ST
ST
—
—
PC5
PC4
—
TP0~TPꢁ
T�0~T�ꢁ I/O
T�PC
T�PC
ST C�OS PC4ꢂ PF0ꢂ PC5
ST C�OS PC6ꢂ PCꢃ
TP3Aꢂ TP3B T�3 I/O
INTEG
INTC0
INT0
INT1
External Interrupt 0
ST
ST
—
—
PB3
PDꢁ
External Interrupt 1
Internallꢀ connected to RF transceiver
INTEG
INTC0
PCK
Peripheral Clock output
SPI Data input
—
—
—
ST
—
C�OS PEꢃ
PCꢁ
C�OS PC1
SDI
—
SDO
SPI Data output
—
SCS
SPI Slave Select
—
ST C�OS PC0
ST C�OS PC3
ST N�OS PC3
ST N�OS PCꢁ
SCK
SPI Serial Clock
—
SCL
IꢁC Clock
—
SDA
IꢁC Data
—
OSC1
OSCꢁ
XT1
HXT pin
CO
CO
CO
CO
CO
—
HXT
—
—
HXT
—
—
—
HXT pin
LXT pin
LXT
—
PB0
XTꢁ
LXT pin
LXT PB1
RES
Reset pin
ST
—
—
—
—
PBꢁ
PF3
VDDIO
VDD
Power supplꢀ for interconnected pins
Positive Power supplꢀ
Negative power supplꢀꢂ ground
OCDS clock pinꢂ for EV chip used onlꢀ
OCDS data pinꢂ for EV chip used onlꢀ
ICP clock pinꢂ for EV chip used onlꢀ
ICP data pinꢂ for EV chip used onlꢀ
PWR
PWR
PWR
—
—
—
—
VSS
—
OCDSCK
OCDSDA
ICPCK
ICPDA
—
C�OS PBꢁ
—
ST N�OS PB4
C�OS PBꢁ
ST N�OS PB4
—
—
—
Rev. 1.40
16
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pin Name
Function
OP
I/T
O/T Pin-Shared Mapping
2.4GHz RF Transceiver Pins
RFP1
RF positive input/output port
—
—
—
—
—
—
—
—
—
—
—
—
RFN1
VDDPA
RF negative input/output port
1.8V Regulator output for Power Amplifier
VDD3RXRF/
VDD3IF
RF Transceiver positive power supplꢀ
—
PWR
—
—
VDD3B
CDVDD
VSSRXꢁ
RF Transceiver positive power supplꢀ
—
—
—
PWR
—
—
—
—
—
—
—
1.8V regulator output decoupling capacitor pin
RF Transceiver negative power supplꢀꢂ ground
PWR
Note:ꢀI/T:ꢀInputꢀtype;ꢀ
ꢀ
ꢀ
O/T:ꢀOutputꢀtype
OP:ꢀOptionalꢀbyꢀconfigurationꢀoptionꢀ(CO)ꢀorꢀregisterꢀoption
PWR:ꢀPower;ꢀ
ꢀ
ꢀ
ꢀ
CO:ꢀConfigurationꢀoption;ꢀ ST:ꢀSchmittꢀTriggerꢀinput
NMOS:ꢀNMOSꢀoutput
CMOS:ꢀCMOSꢀoutput;ꢀꢀ
SCOM:ꢀSoftwareꢀcontrolledꢀLCDꢀCOM;ꢀ AN:ꢀAnalogꢀinputꢀpin
HXT:ꢀHighꢀfrequencyꢀcrystalꢀoscillator
LXT:ꢀLowꢀfrequencyꢀcrystalꢀoscillator
Rev. 1.40
1ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
2.4GHz RF Transceiver IP Internal Control Signals
Internal Control Signal
Signal Name Signal Type
2.4GHz RF Transceiver IP
Signal Name Signal Type
PD0
O
O
I
CE
CSN
I
I
PD1/SCSA
PDꢁ/INT1
PD3/SDIA
PD4/SDOA
PD5/SCKA
CLKO
IRQ
O
O
I
I
�ISO
�OSI
SCK
O
O
O
I
XTALN
I
VDD3RXRFIF
VDD
VDD
VDD3B
VDD3B
VDD3RXRF
VDD3IF
SCSA
SDOA
SDIA
CSN
VDDPA
CDVDD
MOSI
MISO
SCK
IRQ
Interface
Control
2.4G RF
Transceiver
Circuitry
SCKA
INT1
CLKO
PD0
RFP1
RFN1
XTALN
CE
GND
VSSRX2
VDD3RXRFIF
VDD
VDD
VDD3B
VDDIO
VDDIO
VDD3B
VDD3RXRF
VDD3IF
SCSA
SDOA
SDIA
CSN
VDDPA
CDVDD
MOSI
MISO
SCK
IRQ
Interface
Control
Circuitry
2.4G RF
Transceiver
SCKA
INT1
CLKO
PD0
RFP1
RFN1
XTALN
CE
GND
VSSRX2
2.4GHz RF Transceiver IP Control Diagram
Rev. 1.40
18
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Absolute Maximum Ratings
SupplyꢀVoltageꢀꢀ...............................................................................................ꢀVSS-0.3VꢀtoꢀVSS+6.0V
StorageꢀTemperatureꢀ..................................................................................................ꢀ-50˚Cꢀtoꢀ150˚C
InputꢀVoltageꢀ......................ꢀ...........................................................................ꢀVSS-0.3VꢀtoꢀVDD+0.3V
OperatingꢀTemperatureꢀ................................................................................................ꢀ-40˚Cꢀtoꢀ85˚C
IOLꢀTotalꢀ..............................ꢀ................................................................... ................................ꢀ100mA
IOHꢀTotalꢀ..............................ꢀ..................................................................................................ꢀ-100mA
TotalꢀPowerꢀDissipationꢀ..................ꢀ.................................................................. ...................ꢀ500mW
ESDꢀHBMꢀꢀ............................................................................................................................ꢀ±1.5KV
ESDꢀMMꢀꢀ................................................................................................................................ꢀ±100V
Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ“AbsoluteꢀMaximumꢀ
Ratings”ꢀmayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheꢀdevice.ꢀFunctionalꢀoperationꢀofꢀthisꢀdeviceꢀatꢀotherꢀ
conditionsꢀbeyondꢀthoseꢀlistedꢀinꢀtheꢀspecificationꢀisꢀnotꢀimpliedꢀandꢀprolongedꢀexposureꢀtoꢀextremeꢀ
conditionsꢀmayꢀaffectꢀdeviceꢀreliability.ꢀ
*DeviceꢀisꢀESDꢀsensitive.ꢀHBMꢀ(HumanꢀBodyꢀMode)ꢀisꢀbasedꢀonꢀMIL-STD-883HꢀMethodꢀ3015.8.ꢀ
MMꢀ(MachineꢀMode)ꢀisꢀbasedꢀonꢀJEDECꢀEIA/JESD22-A115.
D.C. Characteristics
Ta=25˚C
Min. Typ. Max. Unit
Test Conditions
Symbol
Parameter
VDD
Conditions
f
SYS=4�Hz
fSYS=8�Hz
fSYS=16�Hz
SYS=4�Hz
ꢁ.ꢁ
ꢁ.4
3.0
ꢁ.ꢁ
ꢁ.4
3.3
ꢁ.ꢁ
ꢁ.4
3.6
—
—
—
—
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
V
V
Operating Voltage (BC66F840)
(HXT=16�Hz)
VDD1
—
f
Operating Voltage (BC66F850)
(HXT=16�Hz)
VDDꢁ
—
fSYS=8�Hz
fSYS=16�Hz
f
SYS=4�Hz
Operating Voltage (BC66F860)
(HXT=16�Hz)
VDD3
—
—
fSYS=8�Hz
fSYS=16�Hz
Operating Voltage
(For Port D & CLKO Internal Signals)
VDDIO
IDD1
—
ꢁ.ꢁ
—
5.5
V
3V
5V
3V
5V
3V
5V
3V
5V
—
—
—
—
—
—
—
—
ꢁ.0
4.5
40
50
40
50
10
30
3.0
ꢃ.0
60
80
60
80
ꢁ0
50
mA
mA
μA
μA
μA
μA
μA
μA
Operating Currentꢂ Normal �odeꢂ
fSYS=fH=fHXT
No loadꢂ fH=16�Hzꢂ ADC offꢂ
WDT enable
No loadꢂ fSYS=fLXTꢂ ADC offꢂ
WDT enableꢂ LXTLP=0
Operating Currentꢂ Slow �odeꢂ
fSYS=fL=fSUB=fLXT
IDDꢁ
No loadꢂ fSYS=fLXTꢂ ADC offꢂ
WDT enableꢂ LXTLP=1
Operating Currentꢂ Slow �odeꢂ
fSYS=fL=fSUB=fLIRC
No loadꢂ fSYS=fLIRCꢂ ADC offꢂ
WDT enable
IDD3
Rev. 1.40
19
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Test Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
5V
—
Conditions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0.9
ꢁ.5
0.ꢃ
ꢁ.0
0.6
1.6
0.5
1.5
1.5
mA
No loadꢂ fSYS=fH/ꢁꢂ ADC offꢂ
WDT enable
3.ꢃ5 mA
1.0
3.0
0.9
ꢁ.4
mA
mA
mA
mA
No loadꢂ fSYS=fH/4ꢂ ADC offꢂ
WDT enable
No loadꢂ fSYS=fH/8ꢂ ADC offꢂ
WDT enable
Operating Currentꢂ Normal �odeꢂ
fH=fHXT=16�Hz
IDD4
0.ꢃ5 mA
ꢁ.ꢁ5 mA
No loadꢂ fSYS=fH/16ꢂ ADC offꢂ
WDT enable
0.49 0.ꢃ4 mA
1.45 ꢁ.18 mA
0.4ꢃ 0.ꢃ1 mA
No loadꢂ fSYS=fH/3ꢁꢂ ADC offꢂ
WDT enable
No loadꢂ fSYS=fH/64ꢂ ADC offꢂ
WDT enable
1.4
5
ꢁ.1
10
mA
μA
μA
μA
μA
μA
μA
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA
V
No loadꢂ ADC offꢂ WDT enableꢂ
LXTLP=0
16
5
3ꢁ
IDLE0 �ode Standbꢀ Current
(LXT on)
IIDLE1
10
No loadꢂ ADC offꢂ WDT enableꢂ
LXTLP=1
16
1.3
ꢁ.ꢁ
1.0
ꢁ.0
0.1
0.3
5
3ꢁ
3.0
5.0
ꢁ.0
4.0
1.0
ꢁ.0
10
IDLE0 �ode Standbꢀ Current
(LIRC on)
No loadꢂ ADC offꢂ WDT enableꢂ
LVR disable
IIDLEꢁ
IDLE1 �ode Standbꢀ Current
(HXT)
No loadꢂ ADC offꢂ WDT enableꢂ
fSYS=16�Hz on
IIDLE3
SLEEP0 �ode Standbꢀ Current
(LIRC off)
No loadꢂ ADC offꢂ WDT disableꢂ
LVR disable
ISLEEP1
ISLEEPꢁ
ISLEEP3
ISLEEP4
VIL1
SLEEP1 �ode Standbꢀ Current
(LXT on)
No loadꢂ ADC offꢂ WDT enableꢂ
LXTLP=0ꢂ LVR disable
16
5
3ꢁ
10
SLEEP1 �ode Standbꢀ Current
(LXT on)
No loadꢂ ADC offꢂ WDT enableꢂ
LXTLP=1ꢂ LVR disable
15
1.3
ꢁ.ꢁ
—
—
—
—
—
—
8
30
5.0
10
SLEEP1 �ode Standbꢀ Current
(LIRC on)
No loadꢂ ADC offꢂ WDT enableꢂ
LVR disable
—
—
—
—
—
—
1.5
0.ꢁVDD
5.0
VDD
0.4VDD
VDD
—
Input Low Voltage for I/O Ports or
Input Pins except RES pin
0
V
5V
—
3.5
0.8VDD
0
V
Input High Voltage for I/O Ports or
Input Pins except RES pin
VIH1
V
VILꢁ
VIHꢁ
Input Low Voltage for RES pin
Input High Voltage for RES pin
—
V
—
0.9VDD
4
V
3V VOL=0.1VDD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
kΩ
kΩ
I/O Port Sink Current
(Except Port D)
IOL1
IOH1
IOLꢁ
IOHꢁ
IOL3
IOH3
RPH
5V VOL=0.1VDD
10
-ꢁ
ꢁ0
-4
—
3V VOH=0.9VDD
—
I/O Port Source Current
(Except Port D)
5V VOH=0.9VDD
-5
-10
4
—
3V VOL=0.1VDD or 0.1VDDIO
5V VOL=0.1VDD or 0.1VDDIO
3V VOH=0.9VDD or 0.9VDDIO
5V VOH=0.9VDD or 0.9VDDIO
3V VOL_CLKO=0.1VDD or 0.1VDDIO
5V VOL_CLKO=0.1VDD or 0.1VDDIO
3V VOH_CLKO=0.9VDD or 0.9VDDIO
5V VOH_CLKO=0.9VDD or 0.9VDDIO
ꢁ
—
I/O Port Sink Current
(For Port D)
5
10
-ꢁ
—
-1
—
I/O Port Source Current
(For Port D)
-ꢁ.5
4.5
10.5
-3
-5
—
ꢃ
—
Sink Current for CLKO output
Source Current for CLKO output
Pull-high Resistance for I/O Ports
14
-4
—
—
-6
-8
—
3V
5V
—
—
ꢁ0
10
60
30
100
50
Rev. 1.40
ꢁ0
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A.C. Characteristics
Ta=25˚C
Test Conditions
VDD Conditions
Symbol
Parameter
Operating clock (HXT)
Min. Typ. Max. Unit
fSYS
fLXT
3.3V~5.5V
—
—
—
—
16
3ꢁꢃ68
3ꢁ
—
—
�Hz
kHz
3ꢁꢃ68Hz Crꢀstal Oscillator Clock
—
5V
Ta=25˚C
-10%
+10% kHz
+60% kHz
fLIRC
Low Speed Internal RC Oscillator Clock
ꢁ.ꢁV~5.5V Ta=-40˚C to 85˚C -30%
3ꢁ
tTCK
TCKn Input Pulse Width
External Reset Low Pulse Width
Interrupt Pulse Width
—
—
—
—
—
—
—
—
—
—
0.3
10
10
—
—
—
—
—
4
μs
μs
tRES
tINT
tEERD
tEEWR
—
—
μs
EEPRO� Read Time
ꢁ
tSYS
ms
EEPRO� Write Time
—
ꢁ
4
Sꢀstem Start-up Timer Period
(Wake-up from HALTꢂ fSYS on at HALT state)
—
—
ꢁ
—
—
tSYS
tSST
—
—
—
fSYS=HXT
1ꢁ8
ꢁ
—
—
50
—
—
tSYS
tSYS
Sꢀstem Start-up Timer Period
(Wake-up from HALTꢂ fSYS off at HALT state)
fSYS=LIRC
—
Sꢀstem Reset Delaꢀ Time (Power On Reset)
ꢁ5
100 ms
tRSTD
Sꢀstem Reset Delaꢀ Time
(Anꢀ Reset except Power On Reset)
—
—
8.3
16.ꢃ 33.3 ms
Note:ꢀtSYS=1/fSYS
LVD & LVR Electrical Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
Conditions
LVR Enableꢂ ꢁ.1V option
LVR Enableꢂ ꢁ.55V option
LVR Enableꢂ 3.15V option
LVR Enableꢂ 3.8V option
LVDEN=1ꢂ VLVD=ꢁ.0V
LVDEN=1ꢂ VLVD=ꢁ.ꢁV
LVDEN=1ꢂ VLVD=ꢁ.4V
LVDEN=1ꢂ VLVD=ꢁ.ꢃV
LVDEN=1ꢂ VLVD=3.0V
LVDEN=1ꢂ VLVD=3.3V
LVDEN=1ꢂ VLVD=3.6V
LVDEN=1ꢂ VLVD=4.0V
VLVR1
VLVRꢁ
VLVR3
VLVR4
VLVD1
VLVDꢁ
VLVD3
VLVD4
VLVD5
VLVD6
VLVDꢃ
VLVD8
ꢁ.1
ꢁ.55
3.15
3.8
ꢁ.0
ꢁ.ꢁ
ꢁ.4
ꢁ.ꢃ
3.0
3.3
3.6
4.0
30
V
V
-5%×
Tꢀp.
+5%×
Tꢀp.
Low Voltage Reset Voltage
—
V
V
V
V
V
V
-5%×
Tꢀp.
+5%×
Tꢀp.
Low Voltage Detector Voltage
—
V
V
V
V
3V
5V
3V
5V
—
—
—
—
—
—
—
45
90
μA
μA
μA
μA
μs
μs
μs
μs
μs
Additional Power Consumption if LVR
is used
ILVR
LVR disable→LVR enable
60
—
40
60
Additional Power Consumption if LVD
is used
LVD disable→LVD enable
(LVR disable)
ILVD
—
ꢃ5
115
480
90
tLVR
tLVD
Low Voltage Width to Reset
Low Voltage Width to Interrupt
—
1ꢁ0
ꢁ0
15
ꢁ40
45
—
For LVR enable, LVD off→on
—
—
tLVDS
LVDO stable time
For LVR disable, LVD off→on 15
45
—
—
tSRESET
Software Reset Width to Reset
—
90
1ꢁ0
Rev. 1.40
ꢁ1
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ADC Characteristics
Ta=25˚C
Test Conditions
Min. Typ. Max. Unit
Conditions
Symbol
Parameter
VDD
—
VADI
VREF
VBG
A/D Converter Input Voltage
—
—
0
ꢁ
—
—
VREF
VDD
V
V
V
A/D Converter Reference Voltage
Reference Voltage with Buffer Voltage
—
—
-3% 1.09 +3%
VREF=VDDꢂ tADCK=0.5μs
Ta=25˚C
DNL1
DNLꢁ
INL1
Differential Non-linearitꢀ
Differential Non-linearitꢀ
Integral Non-linearitꢀ
Integral Non-linearitꢀ
—
—
—
—
-3
-4
-4
-8
—
—
—
—
+3 LSB
+4 LSB
+4 LSB
+8 LSB
VREF=VDDꢂ tADCK=0.5μs
Ta=-40˚C~85˚C
VREF=VDDꢂ tADC=0.5μs
Ta=25˚C
VREF=VDDꢂ tADCK=0.5μs
Ta=-40˚C~85˚C
INLꢁ
3V No load (tADCK=0.5μs )
5V No load (tADCK=0.5μs )
—
—
0.9 1.35 mA
1.ꢁ 1.8 mA
Additional Power Consumption if A/D
Converter is Used
IADC
Additional Power Consumption if VBG
Reference with Buffer is used
IBG
—
—
—
—
—
—
0.5
—
ꢁ00 300 μA
tADCK
tADC
A/D Converter Clock Period
—
10
—
μs
A/D Conversion Time (Include Sample
and Hold Time)
1ꢁ-bit ADC
16
tADCK
tADS
A/D Converter Sampling Time
A/D Converter On-to-Start Time
VBG Turn on Stable Time
—
—
—
—
—
—
—
ꢁ
4
—
—
—
tADCK
μs
tONꢁST
tBGS
—
—
ꢁ00
μs
Comparator Electrical Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
—
Conditions
VC�P
IC�P
Comparator Operating Voltage
Comparator Operating Current
—
—
—
—
—
ꢁ.ꢁ
—
—
3ꢃ
5.5
56
V
3V
5V
—
µA
µA
mV
mV
—
130
—
ꢁ00
+10
60
VC�POS
VHYS
Comparator Input Offset Voltage
Hꢀsteresis Width
−10
ꢁ0
—
40
Comparator Common �ode
Voltage Range
VC�
—
—
—
VSS
—
VDD −1.4V
V
AOL
tPD
Comparator Open Loop Gain
Comparator Response Time
—
—
60
—
80
—
dB
ns
With 100mV overdrive (Note)
3ꢃ0
560
Note:ꢀMeasuredꢀwithꢀcomparatorꢀoneꢀinputꢀpinꢀatꢀVCM=(VDD−1.4)/2ꢀwhileꢀtheꢀotherꢀpinꢀinputꢀtransitionꢀfromꢀVSSꢀtoꢀ
(VCMꢀ+100mV)ꢀorꢀfromꢀVDDꢀtoꢀ(VCMꢀ−100mV).
Rev. 1.40
ꢁꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Electrical Characteristics
Ta=25˚C
Test Conditions
Conditions
Symbol
Parameter
RF operating voltage
Min.
Typ.
Max.
Unit
VDD
VDDRF
—
—
1.9
3.0
3.6
V
V
(VDD3RXRFꢂ VDD3IFꢂ VDD3B)
RF digital input high voltage
RF digital input low voltage
RF digital output high voltage
RF digital output low voltage
RF power down current
RF standbꢀ-I current
VIHRF
VILRF
VOHRF
VOLRF
ISTBRF1
ISTBRFꢁ
ISTBRF3
fOP
—
—
—
—
—
—
—
—
—
—
0.ꢃVDDRF
—
—
—
—
4
5.ꢁ5
—
0
0.3VDDRF
VDDRF
0.3
V
V
I=-0.ꢁ5mA
VDDRF-0.3V
I=0.ꢁ5mA
0
—
V
—
—
—
—
—
—
μA
μA
μA
�Hz
Kbps
—
90
330
—
—
—
RF standbꢀ-II current
—
—
RF Operating frequencꢀ
Air data rate
ꢁ400
ꢁ50
ꢁ5ꢁꢃ
ꢁ000
RFSK
Transmitter
PRF
Output power
—
—
—
—
—
—
—
—
—
—
—
—
-40
—
—
—
—
—
—
—
—
—
—
0
3
dBm
�Hz
�Hz
�Hz
mA
RFSK=ꢁ�bps
RFSK=1�bps
RFSK=ꢁ50Kbps
ꢁ.5
1.8
1.6
8
—
—
—
—
—
—
—
—
—
—
PBW
�odulation ꢁ0dB bandwidth
Transmitter operating current
P
RF=-35dBm
PRF=-ꢁ5dBm
PRF=-ꢁ0dBm
PRF=-10dBm
PRF=-6dBm
PRF=-1dBm
PRF=3dBm
9
mA
10
1ꢁ
13
18
ꢁ5
mA
IDDTX
mA
mA
mA
mA
Receiver
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R
FSK=ꢁ�bps
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18
18
18
ꢁ0
-8ꢃ
-90
-96
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
mA
mA
mA
dBm
dBm
dBm
dBm
dB
IDDRX
Receiver operating current
RFSK=1�bps
RFSK=ꢁ50Kbps
�axInput 1E-3 BER
—
RFSK=ꢁ�bps
RXSENS 1E-3 BER sensitivitꢀ
RFSK=1�bps
RFSK=ꢁ50Kbps
C/I CO
C/I+1ST ACS C/I ꢁ�Hz (ꢁ�bps)
C/I-1ST ACS C/I ꢁ�Hz (ꢁ�bps)
Co-channel C/I (ꢁ�bps)
—
—
—
—
—
—
—
ꢁ
dB
-6
dB
C/I+ꢁND ACS C/I 4�Hz (ꢁ�bps)
C/I-ꢁND ACS C/I 4�Hz (ꢁ�bps)
C/I+3RD ACS C/I 6�Hz (ꢁ�bps)
C/I-3RD ACS C/I 6�Hz (ꢁ�bps)
-ꢁ1
-1ꢁ
-ꢁ9
-18
dB
dB
dB
dB
Rev. 1.40
ꢁ3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Conditions
C/I CO
Co-channel C/I (1�bps)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
C/I+1ST ACS C/I 1�Hz (1�bps)
C/I-1ST ACS C/I 1�Hz (1�bps)
4
-6
C/I+ꢁND ACS C/I ꢁ�Hz (1�bps)
C/I-ꢁND ACS C/I ꢁ�Hz (1�bps)
C/I+3RD ACS C/I 3�Hz (1�bps)
C/I-3RD ACS C/I 3�Hz (1�bps)
-ꢁ4
-1ꢁ
-ꢁ8
-16
9
C/I CO
C/I+1ST ACS C/I 1�Hz (ꢁ50Kbps)
C/I-1ST ACS C/I 1�Hz (ꢁ50Kbps)
Co-channel C/I (ꢁ50Kbps)
-13
-16
-ꢁ5
-9
C/I+ꢁND ACS C/I ꢁ�Hz (ꢁ50Kbps)
C/I-ꢁND ACS C/I ꢁ�Hz (ꢁ50Kbps)
C/I+3RD ACS C/I 3�Hz (ꢁ50Kbps)
C/I-3RD ACS C/I 3�Hz (ꢁ50Kbps)
-33
-33
Power on Reset Electrical Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Condition
VPOR
VDD Start Voltage to ensure Power-on Reset
—
—
—
—
—
—
—
100
—
mV
RPOR AC VDD Raising Rate to Ensure Power-on Reset
0.035
V/ms
�inimum Time for VDD to remain at VPOR to
ensure Power-on Reset
tPOR
—
—
1
—
—
ms
V
D
D
t
P
R
O
R
V
R
D
D
V
P
R
O
T
m
i
Rev. 1.40
ꢁ4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
System Architecture
Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀHoltekꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀ
toꢀtheirꢀinternalꢀsystemꢀarchitecture.ꢀTheꢀrangeꢀofꢀdevicesꢀtakeꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀ
withinꢀRISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀenhancedꢀperformance.ꢀ
Theꢀpipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀ
executionꢀareꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀcycle,ꢀwithꢀtheꢀ
exceptionꢀofꢀbranchꢀorꢀcallꢀinstructions.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀinstructionꢀsetꢀ
operations,ꢀwhichꢀcarriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀdecrement,ꢀ
branchꢀdecisions,ꢀetc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀAccumulatorꢀ
andꢀtheꢀALU.ꢀCertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀdirectlyꢀ
orꢀindirectlyꢀaddressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀwithꢀadditionalꢀ
architecturalꢀfeaturesꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀprovideꢀaꢀ
functionalꢀI/OꢀandꢀA/Dꢀcontrolꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀflexibility.ꢀThisꢀmakesꢀtheꢀ
devicesꢀsuitableꢀforꢀlow-cost,ꢀhigh-volumeꢀproductionꢀforꢀcontrollerꢀapplications.
Clocking and Pipelining
Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀeitherꢀaꢀHXT,ꢀLXTꢀorꢀLIRCꢀoscillatorꢀisꢀsubdividedꢀintoꢀfourꢀ
internallyꢀgeneratedꢀnon-overlappingꢀclocks,ꢀT1~T4.ꢀTheꢀProgramꢀCounterꢀisꢀincrementedꢀatꢀtheꢀ
beginningꢀofꢀtheꢀT1ꢀclockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀremainingꢀT2~T4ꢀ
clocksꢀcarryꢀoutꢀtheꢀdecodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀclockꢀcycleꢀformsꢀ
oneꢀinstructionꢀcycle.ꢀAlthoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀplaceꢀinꢀconsecutiveꢀ
instructionꢀcycles,ꢀtheꢀpipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀinstructionsꢀareꢀ
effectivelyꢀexecutedꢀinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀhereꢀtheꢀcontentsꢀ
ofꢀtheꢀProgramꢀCounterꢀareꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀcaseꢀtheꢀinstructionꢀ
willꢀtakeꢀoneꢀmoreꢀinstructionꢀcycleꢀtoꢀexecute.
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System Clocking and Pipelining
Rev. 1.40
ꢁ5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀmachineꢀcyclesꢀareꢀ
requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ
cycleꢀtoꢀfirstꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ
branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ
sensitiveꢀapplications.ꢀ
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Instruction Fetching
Program Counter
Duringꢀprogramꢀexecution,ꢀtheꢀProgramꢀCounterꢀisꢀusedꢀtoꢀkeepꢀtrackꢀofꢀtheꢀaddressꢀofꢀtheꢀnextꢀ
instructionꢀtoꢀbeꢀexecuted.ꢀItꢀisꢀautomaticallyꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀanꢀinstructionꢀisꢀ
executedꢀexceptꢀforꢀinstructions,ꢀsuchꢀasꢀ″JMP″ꢀorꢀ″CALL″ꢀthatꢀdemandꢀaꢀjumpꢀtoꢀaꢀnon-consecutiveꢀ
ProgramꢀMemoryꢀaddress.ꢀOnlyꢀtheꢀlowerꢀ8ꢀbits,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀRegister,ꢀareꢀ
directlyꢀaddressableꢀbyꢀtheꢀapplicationꢀprogram.
Whenꢀexecutingꢀinstructionsꢀrequiringꢀjumpsꢀtoꢀnon-consecutiveꢀaddressesꢀsuchꢀasꢀaꢀjumpꢀ
instruction,ꢀaꢀsubroutineꢀcall,ꢀinterruptꢀorꢀreset,ꢀetc.,ꢀtheꢀꢀmanagesꢀprogramꢀcontrolꢀbyꢀloadingꢀtheꢀ
requiredꢀaddressꢀintoꢀtheꢀProgramꢀCounter.ꢀForꢀconditionalꢀskipꢀinstructions,ꢀonceꢀtheꢀconditionꢀ
hasꢀbeenꢀmet,ꢀtheꢀnextꢀinstruction,ꢀwhichꢀhasꢀalreadyꢀbeenꢀfetchedꢀduringꢀtheꢀpresentꢀinstructionꢀ
execution,ꢀisꢀdiscardedꢀandꢀaꢀdummyꢀcycleꢀtakesꢀitsꢀplaceꢀwhileꢀtheꢀcorrectꢀinstructionꢀisꢀobtained.
Program Counter
Device
High Byte
PC11~PC8
PC1ꢁ~PC8
PC13~PC8
Low Byte (PCL Register)
BC66F840
BC66F850
BC66F860
PCLꢃ~PCL0
PCLꢃ~PCL0
PCLꢃ~PCL0
Program Counter
TheꢀlowerꢀbyteꢀofꢀtheꢀProgramꢀCounter,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCL,ꢀisꢀ
availableꢀforꢀprogramꢀcontrolꢀandꢀisꢀaꢀreadableꢀandꢀwriteableꢀregister.ꢀByꢀtransferringꢀdataꢀdirectlyꢀ
intoꢀthisꢀregister,ꢀaꢀshortꢀprogramꢀjumpꢀcanꢀbeꢀexecutedꢀdirectly,ꢀhowever,ꢀasꢀonlyꢀthisꢀlowꢀbyteꢀ
isꢀavailableꢀforꢀmanipulation,ꢀtheꢀjumpsꢀareꢀlimitedꢀtoꢀtheꢀpresentꢀpageꢀofꢀmemory,ꢀthatꢀisꢀ256ꢀ
locations.ꢀWhenꢀsuchꢀprogramꢀjumpsꢀareꢀexecutedꢀitꢀshouldꢀalsoꢀbeꢀnotedꢀthatꢀaꢀdummyꢀcycleꢀ
willꢀbeꢀinserted.ꢀManipulatingꢀtheꢀPCLꢀregisterꢀmayꢀcauseꢀprogramꢀbranching,ꢀsoꢀanꢀextraꢀcycleꢀisꢀ
neededꢀtoꢀpre-fetch.
Rev. 1.40
ꢁ6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Stack
ThisꢀisꢀaꢀspecialꢀpartꢀofꢀtheꢀmemoryꢀwhichꢀisꢀusedꢀtoꢀsaveꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀonly.ꢀ
Theꢀstackꢀhasꢀmultipleꢀlevelsꢀdependingꢀuponꢀtheꢀdeviceꢀandꢀisꢀneitherꢀpartꢀofꢀtheꢀdataꢀnorꢀpartꢀofꢀ
theꢀprogramꢀspace,ꢀandꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀTheꢀactivatedꢀlevelꢀisꢀindexedꢀbyꢀtheꢀStackꢀ
Pointer,ꢀandꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀAtꢀaꢀsubroutineꢀcallꢀorꢀinterruptꢀacknowledgeꢀsignal,ꢀ
theꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀpushedꢀontoꢀtheꢀstack.ꢀAtꢀtheꢀendꢀofꢀaꢀsubroutineꢀorꢀanꢀ
interruptꢀroutine,ꢀsignaledꢀbyꢀaꢀreturnꢀinstruction,ꢀRETꢀorꢀRETI,ꢀtheꢀProgramꢀCounterꢀisꢀrestoredꢀtoꢀ
itsꢀpreviousꢀvalueꢀfromꢀtheꢀstack.ꢀAfterꢀaꢀdeviceꢀreset,ꢀtheꢀStackꢀPointerꢀwillꢀpointꢀtoꢀtheꢀtopꢀofꢀtheꢀ
stack.
Ifꢀtheꢀstackꢀisꢀfullꢀandꢀanꢀenabledꢀinterruptꢀtakesꢀplace,ꢀtheꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀrecordedꢀbutꢀ
theꢀacknowledgeꢀsignalꢀwillꢀbeꢀinhibited.ꢀWhenꢀtheꢀStackꢀPointerꢀisꢀdecremented,ꢀbyꢀRETꢀorꢀRETI,ꢀ
theꢀinterruptꢀwillꢀbeꢀserviced.ꢀThisꢀfeatureꢀpreventsꢀstackꢀoverflowꢀallowingꢀtheꢀprogrammerꢀtoꢀuseꢀ
theꢀstructureꢀmoreꢀeasily.ꢀHowever,ꢀwhenꢀtheꢀstackꢀisꢀfull,ꢀaꢀCALLꢀsubroutineꢀinstructionꢀcanꢀstillꢀ
beꢀexecutedꢀwhichꢀwillꢀresultꢀinꢀaꢀstackꢀoverflow.ꢀPrecautionsꢀshouldꢀbeꢀtakenꢀtoꢀavoidꢀsuchꢀcasesꢀ
whichꢀmightꢀcauseꢀunpredictableꢀprogramꢀbranching.
Ifꢀtheꢀstackꢀisꢀoverflow,ꢀtheꢀfirstꢀProgramꢀCounterꢀsaveꢀinꢀtheꢀstackꢀwillꢀbeꢀlost.
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N
Device
Stack Level N
BC66F840
BC66F850
BC66F860
8
8
1ꢁ
Arithmetic and Logic Unit – ALU
Theꢀarithmetic-logicꢀunitꢀorꢀALUꢀisꢀaꢀcriticalꢀareaꢀofꢀtheꢀꢀthatꢀcarriesꢀoutꢀarithmeticꢀandꢀlogicꢀ
operationsꢀofꢀtheꢀinstructionꢀset.ꢀConnectedꢀtoꢀtheꢀmainꢀꢀdataꢀbus,ꢀtheꢀALUꢀreceivesꢀrelatedꢀ
instructionꢀcodesꢀandꢀperformsꢀtheꢀrequiredꢀarithmeticꢀorꢀlogicalꢀoperationsꢀafterꢀwhichꢀtheꢀresultꢀ
willꢀbeꢀplacedꢀinꢀtheꢀspecifiedꢀregister.ꢀAsꢀtheseꢀALUꢀcalculationꢀorꢀoperationsꢀmayꢀresultꢀinꢀcarry,ꢀ
borrowꢀorꢀotherꢀstatusꢀchanges,ꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀcorrespondinglyꢀupdatedꢀtoꢀreflectꢀtheseꢀ
changes.ꢀTheꢀALUꢀsupportsꢀtheꢀfollowingꢀfunctions:
•ꢀ Arithmeticꢀoperations:ꢀADD,ꢀADDM,ꢀADC,ꢀADCM,SUB,ꢀSUBM,ꢀSBC,ꢀSBCM,ꢀDAA
•ꢀ Logicꢀoperations:ꢀAND,ꢀOR,ꢀXOR,ꢀANDM,ꢀORM,XORM,ꢀCPL,ꢀCPLA
•ꢀ RotationꢀRRA,ꢀRR,ꢀRRCA,ꢀRRC,ꢀRLA,ꢀRL,ꢀRLCA,ꢀRLC
•ꢀ IncrementꢀandꢀDecrementꢀINCA,ꢀINC,ꢀDECA,ꢀDEC
•ꢀ Branchꢀdecision,ꢀJMP,ꢀSZ,ꢀSZA,ꢀSNZ,ꢀSIZ,ꢀSDZ,SIZA,ꢀSDZA,ꢀCALL,ꢀRET,ꢀRETI
Rev. 1.40
ꢁꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Flash Program Memory
TheꢀProgramꢀMemoryꢀisꢀtheꢀlocationꢀwhereꢀtheꢀuserꢀcodeꢀorꢀprogramꢀisꢀstored.ꢀForꢀtheseꢀdevicesꢀ
serieꢀtheꢀProgramꢀMemoryꢀisꢀFlashꢀtype,ꢀwhichꢀmeansꢀitꢀcanꢀbeꢀprogrammedꢀandꢀre-programmedꢀaꢀ
largeꢀnumberꢀofꢀtimes,ꢀallowingꢀtheꢀuserꢀtheꢀconvenienceꢀofꢀcodeꢀmodificationꢀonꢀtheꢀsameꢀdevice.ꢀ
Byꢀusingꢀtheꢀappropriateꢀprogrammingꢀtools,ꢀtheseꢀFlashꢀdevicesꢀofferꢀusersꢀtheꢀflexibilityꢀtoꢀ
convenientlyꢀdebugꢀandꢀdevelopꢀtheirꢀapplicationsꢀwhileꢀalsoꢀofferingꢀaꢀmeansꢀofꢀfieldꢀprogrammingꢀ
andꢀupdating.
Structure
TheꢀProgramꢀMemoryꢀhasꢀaꢀcapacityꢀofꢀupꢀtoꢀ16Kx16ꢀbits.ꢀTheꢀProgramꢀMemoryꢀisꢀaddressedꢀbyꢀ
theꢀProgramꢀCounterꢀandꢀalsoꢀcontainsꢀdata,ꢀtableꢀinformationꢀandꢀinterruptꢀentries.ꢀTableꢀdata,ꢀ
whichꢀcanꢀbeꢀsetupꢀinꢀanyꢀlocationꢀwithinꢀtheꢀProgramꢀMemory,ꢀisꢀaddressedꢀbyꢀaꢀseparateꢀtableꢀ
pointerꢀregister.
Device
Capacity
4K×16
Program Memory Banks
BC66F840
BC66F850
BC66F860
0
0
8K×16
16K×16
0~1
BC66F840
BC66F850
BC66F860
0000H
0004H
Reset
Reset
Reset
Interrupt
Vector
Interrupt
Vector
Interrupt
Vector
002CH
0FFFH
16 bits
1FFFH
16 bits
1FFFH
2000H
16 bits
Bank 1
3FFFH
Program Memory Structure
Rev. 1.40
ꢁ8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Special Vectors
WithinꢀtheꢀProgramꢀMemory,ꢀcertainꢀlocationsꢀareꢀreservedꢀforꢀtheꢀresetꢀandꢀinterrupts.ꢀTheꢀlocationꢀ
0000Hꢀisꢀreservedꢀforꢀuseꢀbyꢀtheꢀdeviceꢀresetꢀforꢀprogramꢀinitialisation.ꢀAfterꢀaꢀdeviceꢀresetꢀisꢀ
initiated,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀthisꢀlocationꢀandꢀbeginꢀexecution.
Look-up Table
AnyꢀlocationꢀwithinꢀtheꢀProgramꢀMemoryꢀcanꢀbeꢀdefinedꢀasꢀaꢀlook-upꢀtableꢀwhereꢀprogrammersꢀcanꢀ
storeꢀfixedꢀdata.ꢀToꢀuseꢀtheꢀlook-upꢀtable,ꢀtheꢀtableꢀpointerꢀmustꢀfirstꢀbeꢀsetupꢀbyꢀplacingꢀtheꢀaddressꢀ
ofꢀtheꢀlookꢀupꢀdataꢀtoꢀbeꢀretrievedꢀinꢀtheꢀtableꢀpointerꢀregister,ꢀTBLPꢀandꢀTBHP.ꢀTheseꢀregistersꢀ
defineꢀtheꢀtotalꢀaddressꢀofꢀtheꢀlook-upꢀtable.
Afterꢀsettingꢀupꢀtheꢀtableꢀpointer,ꢀtheꢀtableꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀProgramꢀMemoryꢀusingꢀ
theꢀ″TABRD[m]″ꢀorꢀ″TABRDL[m]″ꢀinstructions,ꢀrespectively.ꢀWhenꢀtheꢀinstructionꢀisꢀexecuted,ꢀ
theꢀlowerꢀorderꢀtableꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀuserꢀdefinedꢀ
DataꢀMemoryꢀregisterꢀ[m]ꢀasꢀspecifiedꢀinꢀtheꢀinstruction.ꢀTheꢀhigherꢀorderꢀtableꢀdataꢀbyteꢀfromꢀ
theꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀspecialꢀregister.ꢀAnyꢀunusedꢀbitsꢀinꢀthisꢀ
transferredꢀhigherꢀorderꢀbyteꢀwillꢀbeꢀreadꢀasꢀ″0″.
Theꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀaddressingꢀdataꢀflowꢀofꢀtheꢀlook-upꢀtable.
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Table Program Example
Theꢀfollowingꢀexampleꢀshowsꢀhowꢀtheꢀtableꢀpointerꢀandꢀtableꢀdataꢀisꢀdefinedꢀandꢀretrievedꢀfromꢀtheꢀ
microcontroller.ꢀThisꢀexampleꢀusesꢀrawꢀtableꢀdataꢀlocatedꢀinꢀtheꢀProgramꢀMemoryꢀwhichꢀisꢀstoredꢀ
thereꢀusingꢀtheꢀORGꢀstatement.ꢀTheꢀvalueꢀatꢀthisꢀORGꢀstatementꢀisꢀ“0F00H”ꢀwhichꢀrefersꢀtoꢀtheꢀstartꢀ
addressꢀofꢀtheꢀlastꢀpageꢀwithinꢀtheꢀ4KꢀProgramꢀMemoryꢀofꢀtheꢀBC66F840ꢀdevice.ꢀTheꢀtableꢀpointerꢀ
isꢀsetupꢀhereꢀtoꢀhaveꢀanꢀinitialꢀvalueꢀofꢀ“06H”.ꢀThisꢀwillꢀensureꢀthatꢀtheꢀfirstꢀdataꢀreadꢀfromꢀtheꢀdataꢀ
tableꢀwillꢀbeꢀatꢀtheꢀProgramꢀMemoryꢀaddressꢀ“0F06H”ꢀorꢀ6ꢀlocationsꢀafterꢀtheꢀstartꢀofꢀtheꢀlastꢀpage.ꢀ
Noteꢀthatꢀtheꢀvalueꢀforꢀtheꢀtableꢀpointerꢀisꢀreferencedꢀtoꢀtheꢀfirstꢀaddressꢀofꢀtheꢀpresentꢀpageꢀifꢀtheꢀ
“TABRDꢀ[m]”ꢀinstructionꢀisꢀbeingꢀused.ꢀTheꢀhighꢀbyteꢀofꢀtheꢀtableꢀdataꢀwhichꢀinꢀthisꢀcaseꢀisꢀequalꢀ
toꢀzeroꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀregisterꢀautomaticallyꢀwhenꢀtheꢀ“TABRDꢀ[m]”ꢀinstructionꢀisꢀ
executed.
BecauseꢀtheꢀTBLHꢀregisterꢀisꢀaꢀread-onlyꢀregisterꢀandꢀcannotꢀbeꢀrestored,ꢀcareꢀshouldꢀbeꢀtakenꢀ
toꢀensureꢀitsꢀprotectionꢀifꢀbothꢀtheꢀmainꢀroutineꢀandꢀInterruptꢀServiceꢀRoutineꢀuseꢀtableꢀreadꢀ
instructions.ꢀIfꢀusingꢀtheꢀtableꢀreadꢀinstructions,ꢀtheꢀInterruptꢀServiceꢀRoutinesꢀmayꢀchangeꢀtheꢀ
valueꢀofꢀtheꢀTBLHꢀandꢀsubsequentlyꢀcauseꢀerrorsꢀifꢀusedꢀagainꢀbyꢀtheꢀmainꢀroutine.ꢀAsꢀaꢀruleꢀitꢀisꢀ
recommendedꢀthatꢀsimultaneousꢀuseꢀofꢀtheꢀtableꢀreadꢀinstructionsꢀshouldꢀbeꢀavoided.ꢀHowever,ꢀinꢀ
situationsꢀwhereꢀsimultaneousꢀuseꢀcannotꢀbeꢀavoided,ꢀtheꢀinterruptsꢀshouldꢀbeꢀdisabledꢀpriorꢀtoꢀtheꢀ
executionꢀofꢀanyꢀmainꢀroutineꢀtable-readꢀinstructions.ꢀNoteꢀthatꢀallꢀtableꢀrelatedꢀinstructionsꢀrequireꢀ
twoꢀinstructionꢀcyclesꢀtoꢀcompleteꢀtheirꢀoperation.
Rev. 1.40
ꢁ9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Table Read Program Example:
tempreg1 db ?
tempreg2 db ?
; temporary register #1
; temporary register #2
:
:
mov a,06h
mov tblp,a
mov a,0Fh
mov tbhp,a
:
; initialise low table pointer - note that this address is referenced
; initialise high table pointer
:
tabrd
tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address “0F06H” transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrd tempreg2
; transfers value in table referenced by table pointer data at program
; memory address “0F05H” transferred to tempreg2 and TBLH in this
; example the data “1AH” is transferred to tempreg1 and data “0FH” to
; register tempreg2
:
:
org 0F00h
; sets initial address of program memory
dc
:
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
In Circuit Programming
TheꢀprovisionꢀofꢀFlashꢀtypeꢀProgramꢀMemoryꢀprovidesꢀtheꢀuserꢀwithꢀaꢀmeansꢀofꢀconvenientꢀandꢀ
easyꢀupgradesꢀandꢀmodificationsꢀtoꢀtheirꢀprogramsꢀonꢀtheꢀsameꢀdevice.
Asꢀanꢀadditionalꢀconvenience,ꢀHoltekꢀhasꢀprovidedꢀaꢀmeansꢀofꢀprogrammingꢀtheꢀmicrocontrollerꢀ
in-circuitꢀusingꢀaꢀ4-pinꢀinterface.ꢀThisꢀprovidesꢀmanufacturersꢀwithꢀtheꢀpossibilityꢀofꢀmanufacturingꢀ
theirꢀcircuitꢀboardsꢀcompleteꢀwithꢀaꢀprogrammedꢀorꢀun-programmedꢀmicrocontroller,ꢀandꢀthenꢀ
programmingꢀorꢀupgradingꢀtheꢀprogramꢀatꢀaꢀlaterꢀstage.ꢀThisꢀenablesꢀproductꢀmanufacturersꢀtoꢀeasilyꢀ
keepꢀtheirꢀmanufacturedꢀproductsꢀsuppliedꢀwithꢀtheꢀlatestꢀprogramꢀreleasesꢀwithoutꢀremovalꢀandꢀ
re-insertionꢀofꢀtheꢀdevice.
Holtek Writer Pins
MCU Programming Pins
Function
Programming Serial Data
Programming Clock
Power Supplꢀ
ICPDA
ICPCK
VDD
PB4
PBꢁ
VDD
VSS
VSS
Ground
TheꢀProgramꢀMemoryꢀcanꢀbeꢀprogrammedꢀseriallyꢀin-circuitꢀusingꢀthisꢀ4-wireꢀinterface.ꢀDataꢀ
isꢀdownloadedꢀandꢀuploadedꢀseriallyꢀonꢀaꢀsingleꢀpinꢀwithꢀanꢀadditionalꢀlineꢀforꢀtheꢀclock.ꢀTwoꢀ
additionalꢀlinesꢀareꢀrequiredꢀforꢀtheꢀpowerꢀsupplyꢀandꢀoneꢀlineꢀforꢀtheꢀreset.ꢀTheꢀtechnicalꢀdetailsꢀ
regardingꢀtheꢀin-circuitꢀprogrammingꢀofꢀtheꢀdevicesꢀareꢀbeyondꢀtheꢀscopeꢀofꢀthisꢀdocumentꢀandꢀwillꢀ
beꢀsuppliedꢀinꢀsupplementaryꢀliterature.
Rev. 1.40
30
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Duringꢀtheꢀprogrammingꢀprocess,ꢀtheꢀuserꢀmustꢀtakeꢀcareꢀofꢀtheꢀICPDAꢀandꢀICPCKꢀpinsꢀforꢀdataꢀ
andꢀclockꢀprogrammingꢀpurposesꢀtoꢀensureꢀthatꢀnoꢀotherꢀoutputsꢀareꢀconnectedꢀtoꢀtheseꢀtwoꢀpins.
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Note:ꢀ*ꢀmayꢀbeꢀresistorꢀorꢀcapacitor.ꢀTheꢀresistanceꢀofꢀ*ꢀmustꢀbeꢀgreaterꢀthanꢀ1kΩꢀorꢀtheꢀcapacitanceꢀ
ofꢀ*ꢀmustꢀbeꢀlessꢀthanꢀ1nF.
On-Chip Debug Support – OCDS
ThereꢀisꢀanꢀEVꢀchipꢀnamedꢀBC66V8x0ꢀwhichꢀisꢀusedꢀtoꢀemulateꢀtheꢀBC66F8x0ꢀdeviceꢀrespectively.ꢀ
TheꢀBC66V8x0ꢀdeviceꢀalsoꢀprovidesꢀtheꢀ“On-ChipꢀDebug”ꢀfunctionꢀtoꢀdebugꢀtheꢀcorrespondingꢀ
BC66F8x0ꢀdeviceꢀduringꢀdevelopmentꢀprocess.ꢀTheꢀdevices,ꢀBC66F8x0ꢀandꢀBC66V8x0,ꢀareꢀ
almostꢀfunctionalꢀcompatibleꢀexceptꢀtheꢀ“On-ChipꢀDebug”ꢀfunction.ꢀUsersꢀcanꢀuseꢀtheꢀBC66V8x0ꢀ
deviceꢀtoꢀemulateꢀtheꢀBC66F8x0ꢀdeviceꢀbehaviorsꢀbyꢀconnectingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀ
pinsꢀtoꢀtheꢀHoltekꢀHT-IDEꢀdevelopmentꢀtools.ꢀTheꢀOCDSDAꢀpinꢀisꢀtheꢀOCDSꢀData/Addressꢀinput/
outputꢀpinꢀwhileꢀtheꢀOCDSCKꢀpinꢀisꢀtheꢀOCDSꢀclockꢀinputꢀpin.ꢀWhenꢀusersꢀuseꢀtheꢀBC66V8x0ꢀ
EVꢀchipꢀforꢀdebugging,ꢀtheꢀcorrespondingꢀpinꢀfunctionsꢀsharedꢀwithꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀ
pinsꢀinꢀtheꢀBC66F8x0ꢀdeviceꢀwillꢀhaveꢀnoꢀeffectꢀinꢀtheꢀBC66V8x0ꢀEVꢀchip.ꢀHowever,ꢀtheꢀtwoꢀ
OCDSꢀpinsꢀwhichꢀareꢀpin-sharedꢀwithꢀtheꢀICPꢀprogrammingꢀpinsꢀareꢀstillꢀusedꢀasꢀtheꢀFlashꢀMemoryꢀ
programmingꢀpinsꢀforꢀICP.ꢀForꢀmoreꢀdetailedꢀOCDSꢀinformation,ꢀreferꢀtoꢀtheꢀcorrespondingꢀ
documentꢀnamedꢀ“Holtekꢀe-Linkꢀforꢀ8-bitꢀMCUꢀOCDSꢀUser’sꢀGuide”.
Holtek e-Link Pins
OCDSDA
OCDSCK
VDD
EV Chip Pins
OCDSDA
OCDSCK
VDD
Pin Description
On-Chip Debug Support Data/Address input/output
On-Chip Debug Support Clock input
Power Supplꢀ
GND
VSS
Ground
Rev. 1.40
31
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RAM Data Memory
TheꢀDataꢀMemoryꢀisꢀaꢀvolatileꢀareaꢀofꢀ8-bitꢀwideꢀRAMꢀinternalꢀmemoryꢀandꢀisꢀtheꢀlocationꢀwhereꢀ
temporaryꢀinformationꢀisꢀstored.
Structure
Dividedꢀintoꢀtwoꢀsections,ꢀtheꢀfirstꢀofꢀtheseꢀisꢀanꢀareaꢀofꢀRAM,ꢀknownꢀasꢀtheꢀSpecialꢀFunctionꢀDataꢀ
Memory.ꢀHereꢀareꢀlocatedꢀregistersꢀwhichꢀareꢀnecessaryꢀforꢀcorrectꢀoperationꢀofꢀtheꢀdevice.ꢀManyꢀ
ofꢀtheseꢀregistersꢀcanꢀbeꢀreadꢀfromꢀandꢀwrittenꢀtoꢀdirectlyꢀunderꢀprogramꢀcontrol,ꢀhowever,ꢀsomeꢀ
remainꢀprotectedꢀfromꢀuserꢀmanipulation.
Bank 0
00H
Special Purpose
Data Memory
40H in bank 1: EEC
7FH
80H
General Purpose
Data Memory
FFH
Bank 0
Bank 1
Bank 2
Bank 3
For BS66F840, there are 2 Data memory banks.
For BS66F850, there are 3 Data memory banks.
For BS66F860, there are 4 Data memory banks.
Data Memory Structure
General Purpose Data Memory
Allꢀmicrocontrollerꢀprogramsꢀrequireꢀanꢀareaꢀofꢀread/writeꢀmemoryꢀwhereꢀtemporaryꢀdataꢀcanꢀbeꢀ
storedꢀandꢀretrievedꢀforꢀuseꢀlater.ꢀItꢀisꢀthisꢀareaꢀofꢀRAMꢀmemoryꢀthatꢀisꢀknownꢀasꢀGeneralꢀPurposeꢀ
DataꢀMemory.ꢀThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀfullyꢀaccessibleꢀbyꢀtheꢀuserꢀprogrammingꢀforꢀbothꢀ
readingꢀandꢀwritingꢀoperations.ꢀByꢀusingꢀtheꢀbitꢀoperationꢀinstructionsꢀindividualꢀbitsꢀcanꢀbeꢀsetꢀorꢀ
resetꢀunderꢀprogramꢀcontrolꢀgivingꢀtheꢀuserꢀaꢀlargeꢀrangeꢀofꢀflexibilityꢀforꢀbitꢀmanipulationꢀinꢀtheꢀ
DataꢀMemory.
Device
Capacity
Banks
0: 80H~FFH
1: 80H~FFH
BC66F840
ꢁ56×8
0: 80H~FFH
1: 80H~FFH
ꢁ: 80H~FFH
BC66F850
BC66F860
384×8
51ꢁ×8
0: 80H~FFH
1: 80H~FFH
ꢁ: 80H~FFH
3: 80H~FFH
General Purpose Data Memory Structure
Rev. 1.40
3ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Special Purpose Data Memory
ThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀwhereꢀregisters,ꢀnecessaryꢀforꢀtheꢀcorrectꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀareꢀstored.ꢀMostꢀofꢀtheꢀregistersꢀareꢀbothꢀreadableꢀandꢀwriteableꢀbutꢀsomeꢀareꢀ
protectedꢀandꢀareꢀreadableꢀonly,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀlocatedꢀunderꢀtheꢀrelevantꢀSpecialꢀFunctionꢀ
Registerꢀsection.ꢀNoteꢀthatꢀforꢀlocationsꢀthatꢀareꢀunused,ꢀanyꢀreadꢀinstructionꢀtoꢀtheseꢀaddressesꢀwillꢀ
returnꢀtheꢀvalueꢀ“00H”.
Bank 0~1
IAR0
�P0
IAR1
�P1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
S�OD
LVDC
INTEG
INTC0
INTC1
INTCꢁ
�FI0
Unused
�FIꢁ
�FI3
�FI4
PA
Bank 0
Bank 1
00H
01H
0ꢁH
03H
04H
05H
06H
0ꢃH
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢁH
13H
14H
15H
16H
1ꢃH
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢁ0H
ꢁ1H
ꢁꢁH
ꢁ3H
ꢁ4H
ꢁ5H
ꢁ6H
ꢁꢃH
ꢁ8H
ꢁ9H
ꢁAH
ꢁBH
ꢁCH
ꢁDH
ꢁEH
ꢁFH
36H
3ꢃH
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
T�ꢁC0
T�ꢁC1
T�ꢁDL
T�ꢁDH
T�ꢁAL
T�ꢁAH
T�ꢁRP
Unused
EEA
EED
40H Unused
Unused
T�3C0
EEC
41H
4ꢁH
43H
44H
45H
46H
4ꢃH
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
5ꢁH
53H
54H
55H
56H
T�3C1
T�3Cꢁ
T�3DL
T�3DH
T�3AL
T�3AH
T�3BL
T�3BH
T�3RP
Unused
PB
PBC
PBPU
PC
PCC
PCPU
PD
PAC
PAPU
PAWU
Unused
T�PC
WDTC
TBC
LVRC
CPC
PDC
PDPU
ADRL
ADRH
ADCR0
ADCR1
ACERL
Unused
CTRL0
CTRL1
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
T�0RP
Unused
5FH
60H
IꢁCTOC
SI�C0
SI�C1
61H
6ꢁH
63H
64H
65H
66H
6ꢃH
68H
SI�D
SI�A/SI�Cꢁ
SPIAC0
SPIAC1
SPIAD
Unused
ꢃFH
Unused
: Unusedꢂ read as 00H
35H
Special Purpose Data Memory Structure – BC66F840
Rev. 1.40
33
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bank 0~ꢁ
IAR0
�P0
IAR1
�P1
BP
ACC
PCL
TBLP
Bank 0ꢂ ꢁ Bank 1
T�ꢁC0
T�ꢁC1
T�ꢁDL
T�ꢁDH
T�ꢁAL
00H
01H
0ꢁH
03H
04H
05H
06H
0ꢃH
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢁH
13H
14H
15H
16H
1ꢃH
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢁ0H
ꢁ1H
ꢁꢁH
ꢁ3H
ꢁ4H
ꢁ5H
ꢁ6H
ꢁꢃH
ꢁ8H
ꢁ9H
ꢁAH
ꢁBH
ꢁCH
ꢁDH
ꢁEH
ꢁFH
30H
31H
3ꢁH
33H
34H
35H
36H
3ꢃH
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
T�ꢁAH
T�ꢁRP
Unused
EEA
TBLH
TBHP
STATUS
S�OD
LVDC
INTEG
INTC0
INTC1
INTCꢁ
�FI0
�FI1
�FIꢁ
�FI3
�FI4
EED
40H Unused
Unused
T�3C0
EEC
41H
4ꢁH
43H
44H
45H
46H
4ꢃH
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
5ꢁH
53H
54H
55H
56H
5ꢃH
58H
59H
T�3C1
T�3Cꢁ
T�3DL
T�3DH
T�3AL
T�3AH
T�3BL
T�3BH
T�3RP
Unused
PB
PBC
PBPU
PC
PCC
PCPU
PD
PA
PAC
PAPU
PAWU
Unused
T�PC
WDTC
TBC
LVRC
CPC
PDC
PDPU
PE
PEC
PEPU
ADRL
ADRH
ADCR0
ADCR1
ACERL
ACERH
CTRL0
CTRL1
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
T�0RP
T�1C0
T�1C1
T�1DL
T�1DH
T�1AL
T�1AH
T�1RP
Unused
5FH
60H
IꢁCTOC
SI�C0
SI�C1
61H
6ꢁH
63H
64H
65H
66H
6ꢃH
68H
SI�D
SI�A/SI�Cꢁ
SPIAC0
SPIAC1
SPIAD
Unused
ꢃFH
: Unusedꢂ read as 00H
Special Purpose Data Memory Structure – BC66F850
Rev. 1.40
34
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bank 0~3
IAR0
�P0
IAR1
�P1
BP
ACC
PCL
TBLP
Bank 0ꢂ ꢁ~3 Bank 1
T�ꢁC0
00H
01H
0ꢁH
03H
04H
05H
06H
0ꢃH
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢁH
13H
14H
15H
16H
1ꢃH
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢁ0H
ꢁ1H
ꢁꢁH
ꢁ3H
ꢁ4H
ꢁ5H
ꢁ6H
ꢁꢃH
ꢁ8H
ꢁ9H
ꢁAH
ꢁBH
ꢁCH
ꢁDH
ꢁEH
ꢁFH
30H
31H
3ꢁH
33H
34H
35H
36H
3ꢃH
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
T�ꢁC1
T�ꢁDL
T�ꢁDH
T�ꢁAL
T�ꢁAH
T�ꢁRP
Unused
EEA
TBLH
TBHP
STATUS
S�OD
LVDC
INTEG
INTC0
INTC1
INTCꢁ
�FI0
�FI1
�FIꢁ
�FI3
�FI4
EED
40H Unused
EEC
41H
4ꢁH
43H
44H
45H
46H
4ꢃH
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
5ꢁH
53H
54H
55H
56H
5ꢃH
58H
59H
5AH
5BH
5CH
Unused
T�3C0
T�3C1
T�3Cꢁ
T�3DL
T�3DH
T�3AL
T�3AH
T�3BL
T�3BH
T�3RP
Unused
PB
PBC
PBPU
PC
PCC
PCPU
PD
PA
PAC
PAPU
PAWU
Unused
T�PC
WDTC
TBC
LVRC
CPC
PDC
PDPU
PE
PEC
PEPU
PF
ADRL
ADRH
ADCR0
ADCR1
ACERL
ACERH
CTRL0
CTRL1
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
T�0RP
T�1C0
T�1C1
T�1DL
T�1DH
T�1AL
T�1AH
T�1RP
PFC
PFPU
Unused
5FH
60H
IꢁCTOC
SI�C0
SI�C1
61H
6ꢁH
63H
64H
65H
66H
6ꢃH
68H
SI�D
SI�A/SI�Cꢁ
SPIAC0
SPIAC1
SPIAD
Unused
ꢃFH
: Unusedꢂ read as 00H
Special Purpose Data Memory Structure – BC66F860
Rev. 1.40
35
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Special Function Register Description
MostꢀofꢀtheꢀSpecialꢀFunctionꢀRegisterꢀdetailsꢀwillꢀbeꢀdescribedꢀinꢀtheꢀrelevantꢀfunctionalꢀsection,ꢀ
howeverꢀseveralꢀregistersꢀrequireꢀaꢀseparateꢀdescriptionꢀinꢀthisꢀsection.
Indirect Addressing Registers – IAR0, IAR1
TheꢀIndirectꢀAddressingꢀRegisters,ꢀIAR0ꢀandꢀIAR1,ꢀalthoughꢀhavingꢀtheirꢀlocationsꢀinꢀnormalꢀRAMꢀ
registerꢀspace,ꢀdoꢀnotꢀactuallyꢀphysicallyꢀexistꢀasꢀnormalꢀregisters.ꢀTheꢀmethodꢀofꢀindirectꢀaddressingꢀ
forꢀRAMꢀdataꢀmanipulationꢀusesꢀtheseꢀIndirectꢀAddressingꢀRegistersꢀandꢀMemoryꢀPointers,ꢀinꢀ
contrastꢀtoꢀdirectꢀmemoryꢀaddressing,ꢀwhereꢀtheꢀactualꢀmemoryꢀaddressꢀisꢀspecified.ꢀActionsꢀonꢀtheꢀ
IAR0ꢀandꢀIAR1ꢀregistersꢀwillꢀresultꢀinꢀnoꢀactualꢀreadꢀorꢀwriteꢀoperationꢀtoꢀtheseꢀregistersꢀbutꢀratherꢀ
toꢀtheꢀmemoryꢀlocationꢀspecifiedꢀbyꢀtheirꢀcorrespondingꢀMemoryꢀPointers,ꢀMP0ꢀorꢀMP1.ꢀActingꢀasꢀaꢀ
pair,ꢀIAR0ꢀandꢀMP0ꢀcanꢀtogetherꢀaccessꢀdataꢀfromꢀBankꢀ0ꢀwhileꢀtheꢀIAR1ꢀandꢀMP1ꢀregisterꢀpairꢀcanꢀ
accessꢀdataꢀfromꢀanyꢀbank.ꢀAsꢀtheꢀIndirectꢀAddressingꢀRegistersꢀareꢀnotꢀphysicallyꢀimplemented,ꢀ
readingꢀtheꢀIndirectꢀAddressingꢀRegistersꢀindirectlyꢀwillꢀreturnꢀaꢀresultꢀofꢀ"00H"ꢀandꢀwritingꢀtoꢀtheꢀ
registersꢀindirectlyꢀwillꢀresultꢀinꢀnoꢀoperation.
Memory Pointers – MP0, MP1
TwoꢀMemoryꢀPointers,ꢀknownꢀasꢀMP0ꢀandꢀMP1ꢀareꢀprovided.ꢀTheseꢀMemoryꢀPointersꢀareꢀ
physicallyꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀmanipulatedꢀinꢀtheꢀsameꢀwayꢀasꢀnormalꢀ
registersꢀprovidingꢀaꢀconvenientꢀwayꢀwithꢀwhichꢀtoꢀaddressꢀandꢀtrackꢀdata.ꢀWhenꢀanyꢀoperationꢀtoꢀ
theꢀrelevantꢀIndirectꢀAddressingꢀRegistersꢀisꢀcarriedꢀout,ꢀtheꢀactualꢀaddressꢀthatꢀtheꢀmicrocontrollerꢀ
isꢀdirectedꢀto,ꢀisꢀtheꢀaddressꢀspecifiedꢀbyꢀtheꢀrelatedꢀMemoryꢀPointer.ꢀMP0,ꢀtogetherꢀwithꢀIndirectꢀ
AddressingꢀRegister,ꢀIAR0,ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀBankꢀ0,ꢀwhileꢀMP1ꢀandꢀIAR1ꢀareꢀusedꢀtoꢀ
accessꢀdataꢀfromꢀallꢀbanksꢀaccordingꢀtoꢀBPꢀregister.ꢀDirectꢀAddressingꢀcanꢀonlyꢀbeꢀusedꢀwithꢀBankꢀ
0,ꢀallꢀotherꢀBanksꢀmustꢀbeꢀaddressedꢀindirectlyꢀusingꢀMP1ꢀandꢀIAR1.ꢀNoteꢀthatꢀforꢀthisꢀseriesꢀofꢀ
devices,ꢀtheꢀMemoryꢀPointers,ꢀMP0ꢀandꢀMP1,ꢀareꢀbothꢀ8-bitꢀregistersꢀandꢀusedꢀtoꢀaccessꢀtheꢀDataꢀ
MemoryꢀtogetherꢀwithꢀtheirꢀcorrespondingꢀindirectꢀaddressingꢀregistersꢀIAR0ꢀandꢀIAR1.
TheꢀfollowingꢀexampleꢀshowsꢀhowꢀtoꢀclearꢀaꢀsectionꢀofꢀfourꢀDataꢀMemoryꢀlocationsꢀalreadyꢀdefinedꢀ
asꢀlocationsꢀadres1ꢀtoꢀadres4.
Indirect Addressing Program Example
data .section data
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov a,04h
mov block,a
mov a,offset adres1
mov mp0,a
loop:
; setup size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
clr IAR0
inc mp0
; clear the data at address defined by MP0
; increment memory pointer
sdz block
jmp loop
; check if last memory location has been cleared
continue:
Theꢀimportantꢀpointꢀtoꢀnoteꢀhereꢀisꢀthatꢀinꢀtheꢀexampleꢀshownꢀabove,ꢀnoꢀreferenceꢀisꢀmadeꢀtoꢀspecificꢀ
RAMꢀaddresses.
Rev. 1.40
36
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bank Pointer – BP
Forꢀthisꢀseriesꢀofꢀdevices,ꢀtheꢀDataꢀMemoryꢀisꢀdividedꢀintoꢀupꢀtoꢀfourꢀbanksꢀdependingꢀuponꢀwhichꢀ
deviceꢀisꢀselectedꢀwhileꢀtheꢀProgramꢀMemoryꢀisꢀdividedꢀintoꢀtwoꢀbanksꢀforꢀtheꢀBC66F860ꢀdevice.ꢀ
SelectingꢀtheꢀrequiredꢀDataꢀorꢀProgramꢀMemoryꢀareaꢀisꢀachievedꢀusingꢀtheꢀBankꢀPointer.ꢀBitꢀ1~0ꢀareꢀ
usedꢀtoꢀselectꢀDataꢀMemoryꢀBanksꢀwhileꢀtheꢀbitꢀ5ꢀisꢀusedꢀtoꢀselectꢀProgramꢀMemoryꢀBanks.
TheꢀDataꢀMemoryꢀisꢀinitialisedꢀtoꢀBankꢀ0ꢀafterꢀaꢀreset,ꢀexceptꢀforꢀaꢀWDTꢀtime-outꢀresetꢀinꢀtheꢀPowerꢀ
DownꢀMode,ꢀinꢀwhichꢀcase,ꢀtheꢀDataꢀMemoryꢀbankꢀremainsꢀunaffected.ꢀItꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀ
SpecialꢀFunctionꢀDataꢀMemoryꢀisꢀnotꢀaffectedꢀbyꢀtheꢀbankꢀselection,ꢀwhichꢀmeansꢀthatꢀtheꢀSpecialꢀ
FunctionꢀRegistersꢀcanꢀbeꢀaccessedꢀfromꢀwithinꢀanyꢀbank.ꢀDirectlyꢀaddressingꢀtheꢀDataꢀMemoryꢀ
willꢀalwaysꢀresultꢀinꢀBankꢀ0ꢀbeingꢀaccessedꢀirrespectiveꢀofꢀtheꢀvalueꢀofꢀtheꢀBankꢀPointer.ꢀAccessingꢀ
dataꢀfromꢀbanksꢀotherꢀthanꢀBankꢀ0ꢀmustꢀbeꢀimplementedꢀusingꢀindirectꢀaddressing.
Bit
Device
7
6
5
—
4
3
2
1
0
BC66F840
BC66F850
BC66F860
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D�BP0
—
D�BP1 D�BP0
D�BP1 D�BP0
P�BP0
BP Register List
BC66F840 BP Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
D�BP0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
DMBP0:ꢀDataꢀMemoryꢀBankꢀPointer
0:ꢀBankꢀ0
1:ꢀBankꢀ1
BC66F850 BP Register
Bit
Name
R/W
7
6
5
4
3
2
1
D�BP1
R/W
0
0
D�BP0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
DMBP0:ꢀDataꢀMemoryꢀBankꢀPointer
00:ꢀBankꢀ0
01:ꢀBankꢀ1
10:ꢀBankꢀ2
11:ꢀBankꢀ2
Rev. 1.40
3ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
BC66F860 BP Register
Bit
Name
R/W
7
6
5
P�BP0
R/W
0
4
3
2
1
D�BP1
R/W
0
0
D�BP0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
PMBP0:ꢀProgramꢀMemoryꢀBankꢀPointer
0:ꢀBankꢀ0,ꢀProgramꢀMemoryꢀAddressꢀisꢀfromꢀ0000H~1FFFH
1:ꢀBankꢀ1,ꢀProgramꢀMemoryꢀAddressꢀisꢀfromꢀ2000H~3FFFH
Bitꢀ4~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
DMBP0:ꢀDataꢀMemoryꢀBankꢀPointer
00:ꢀBankꢀ0
01:ꢀBankꢀ1
10:ꢀBankꢀ2
11:ꢀBankꢀ3
Accumulator – ACC
TheꢀAccumulatorꢀisꢀcentralꢀtoꢀtheꢀoperationꢀofꢀanyꢀmicrocontrollerꢀandꢀisꢀcloselyꢀrelatedꢀwithꢀ
operationsꢀcarriedꢀoutꢀbyꢀtheꢀALU.ꢀTheꢀAccumulatorꢀisꢀtheꢀplaceꢀwhereꢀallꢀintermediateꢀresultsꢀ
fromꢀtheꢀALUꢀareꢀstored.ꢀWithoutꢀtheꢀAccumulatorꢀitꢀwouldꢀbeꢀnecessaryꢀtoꢀwriteꢀtheꢀresultꢀofꢀ
eachꢀcalculationꢀorꢀlogicalꢀoperationꢀsuchꢀasꢀaddition,ꢀsubtraction,ꢀshift,ꢀetc.,ꢀtoꢀtheꢀDataꢀMemoryꢀ
resultingꢀinꢀhigherꢀprogrammingꢀandꢀtimingꢀoverheads.ꢀDataꢀtransferꢀoperationsꢀusuallyꢀinvolveꢀ
theꢀtemporaryꢀstorageꢀfunctionꢀofꢀtheꢀAccumulator;ꢀforꢀexample,ꢀwhenꢀtransferringꢀdataꢀbetweenꢀ
oneꢀuserꢀdefinedꢀregisterꢀandꢀanother,ꢀitꢀisꢀnecessaryꢀtoꢀdoꢀthisꢀbyꢀpassingꢀtheꢀdataꢀthroughꢀtheꢀ
Accumulatorꢀasꢀnoꢀdirectꢀtransferꢀbetweenꢀtwoꢀregistersꢀisꢀpermitted.
Program Counter Low Register – PCL
Toꢀprovideꢀadditionalꢀprogramꢀcontrolꢀfunctions,ꢀtheꢀlowꢀbyteꢀofꢀtheꢀProgramꢀCounterꢀisꢀmadeꢀ
accessibleꢀtoꢀprogrammersꢀbyꢀlocatingꢀitꢀwithinꢀtheꢀSpecialꢀPurposeꢀareaꢀofꢀtheꢀDataꢀMemory.ꢀByꢀ
manipulatingꢀthisꢀregister,ꢀdirectꢀjumpsꢀtoꢀotherꢀprogramꢀlocationsꢀareꢀeasilyꢀimplemented.ꢀLoadingꢀ
aꢀvalueꢀdirectlyꢀintoꢀthisꢀPCLꢀregisterꢀwillꢀcauseꢀaꢀjumpꢀtoꢀtheꢀspecifiedꢀProgramꢀMemoryꢀlocation,ꢀ
however,ꢀasꢀtheꢀregisterꢀisꢀonlyꢀ8-bitꢀwide,ꢀonlyꢀjumpsꢀwithinꢀtheꢀcurrentꢀProgramꢀMemoryꢀpageꢀareꢀ
permitted.ꢀWhenꢀsuchꢀoperationsꢀareꢀused,ꢀnoteꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.
Look-up Table Registers – TBLP, TBHP, TBLH
Theseꢀthreeꢀspecialꢀfunctionꢀregistersꢀareꢀusedꢀtoꢀcontrolꢀoperationꢀofꢀtheꢀlook-upꢀtableꢀwhichꢀisꢀ
storedꢀinꢀtheꢀProgramꢀMemory.ꢀTBLPꢀandꢀTBHPꢀareꢀtheꢀtableꢀpointerꢀandꢀindicatesꢀtheꢀlocationꢀ
whereꢀtheꢀtableꢀdataꢀisꢀlocated.ꢀTheirꢀvalueꢀmustꢀbeꢀsetupꢀbeforeꢀanyꢀtableꢀreadꢀcommandsꢀareꢀ
executed.ꢀTheirꢀvalueꢀcanꢀbeꢀchanged,ꢀforꢀexampleꢀusingꢀtheꢀ"INC"ꢀorꢀ"DEC"ꢀinstructions,ꢀallowingꢀ
forꢀeasyꢀtableꢀdataꢀpointingꢀandꢀreading.ꢀTBLHꢀisꢀtheꢀlocationꢀwhereꢀtheꢀhighꢀorderꢀbyteꢀofꢀtheꢀtableꢀ
dataꢀisꢀstoredꢀafterꢀaꢀtableꢀreadꢀdataꢀinstructionꢀhasꢀbeenꢀexecuted.ꢀNoteꢀthatꢀtheꢀlowerꢀorderꢀtableꢀ
dataꢀbyteꢀisꢀtransferredꢀtoꢀaꢀuserꢀdefinedꢀlocation.
Rev. 1.40
38
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Status Register – STATUS
Thisꢀ8-bitꢀregisterꢀcontainsꢀtheꢀzeroꢀflagꢀ(Z),ꢀcarryꢀflagꢀ(C),ꢀauxiliaryꢀcarryꢀflagꢀ(AC),ꢀoverflowꢀflagꢀ
(OV),ꢀpowerꢀdownꢀflagꢀ(PDF),ꢀandꢀwatchdogꢀtime-outꢀflagꢀ(TO).ꢀTheseꢀarithmetic/logicalꢀoperationꢀ
andꢀsystemꢀmanagementꢀflagsꢀareꢀusedꢀtoꢀrecordꢀtheꢀstatusꢀandꢀoperationꢀofꢀtheꢀmicrocontroller.
WithꢀtheꢀexceptionꢀofꢀtheꢀTOꢀandꢀPDFꢀflags,ꢀbitsꢀinꢀtheꢀstatusꢀregisterꢀcanꢀbeꢀalteredꢀbyꢀinstructionsꢀ
likeꢀmostꢀotherꢀregisters.ꢀAnyꢀdataꢀwrittenꢀintoꢀtheꢀstatusꢀregisterꢀwillꢀnotꢀchangeꢀtheꢀTOꢀorꢀPDFꢀflag.ꢀ
Inꢀaddition,ꢀoperationsꢀrelatedꢀtoꢀtheꢀstatusꢀregisterꢀmayꢀgiveꢀdifferentꢀresultsꢀdueꢀtoꢀtheꢀdifferentꢀ
instructionꢀoperations.ꢀTheꢀTOꢀflagꢀcanꢀbeꢀaffectedꢀonlyꢀbyꢀaꢀsystemꢀpower-up,ꢀaꢀWDTꢀtime-outꢀorꢀ
byꢀexecutingꢀtheꢀ″CLRꢀWDT″ꢀorꢀ″HALT″ꢀinstruction.ꢀTheꢀPDFꢀflagꢀisꢀaffectedꢀonlyꢀbyꢀexecutingꢀ
theꢀ″HALT″ꢀorꢀ″CLRꢀWDT″ꢀinstructionꢀorꢀduringꢀaꢀsystemꢀpower-up.
TheꢀZ,ꢀOV,ꢀACꢀandꢀCꢀflagsꢀgenerallyꢀreflectꢀtheꢀstatusꢀofꢀtheꢀlatestꢀoperations.
•ꢀ Cꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀtakeꢀ
placeꢀduringꢀaꢀsubtractionꢀoperation;ꢀotherwiseꢀCꢀisꢀcleared.ꢀCꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀ
carryꢀinstruction.
•ꢀ ACꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀfromꢀ
theꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction;ꢀotherwiseꢀACꢀisꢀcleared.
•ꢀ Zꢀisꢀsetꢀifꢀtheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero;ꢀotherwiseꢀZꢀisꢀcleared.
•ꢀ OVꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbit,ꢀorꢀviceꢀversa;ꢀotherwiseꢀOVꢀisꢀcleared.
•ꢀ PDFꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction.ꢀPDFꢀisꢀsetꢀbyꢀ
executingꢀtheꢀ“HALT”ꢀinstruction.
•ꢀ TOꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTOꢀisꢀ
setꢀbyꢀaꢀWDTꢀtime-out.
Inꢀaddition,ꢀonꢀenteringꢀanꢀinterruptꢀsequenceꢀorꢀexecutingꢀaꢀsubroutineꢀcall,ꢀtheꢀstatusꢀregisterꢀwillꢀ
notꢀbeꢀpushedꢀontoꢀtheꢀstackꢀautomatically.ꢀIfꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregistersꢀareꢀimportantꢀandꢀifꢀ
theꢀsubroutineꢀcanꢀcorruptꢀtheꢀstatusꢀregister,ꢀprecautionsꢀmustꢀbeꢀtakenꢀtoꢀcorrectlyꢀsaveꢀit.
Rev. 1.40
39
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
STATUS Register
Bit
Name
R/W
7
6
5
TO
R
4
PDF
R
3
OV
R/W
x
2
Z
1
AC
R/W
x
0
—
—
—
—
—
—
C
R/W
x
R/W
x
POR
0
0
"x" unknown
Bitꢀ7,ꢀ6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
TO:ꢀWatchdogꢀTime-Outꢀflag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction
1:ꢀAꢀwatchdogꢀtime-outꢀoccurred.
Bitꢀ4
Bitꢀ3
PDF:ꢀPowerꢀdownꢀflag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction
1:ꢀByꢀexecutingꢀtheꢀ“HALT”ꢀinstruction
OV:ꢀOverflowꢀflag
0:ꢀNoꢀoverflow
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbitꢀorꢀviceꢀversa.
Bitꢀ2
Bitꢀ1
Z:ꢀZeroꢀflag
0:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀnotꢀzero
1:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero
AC:ꢀAuxiliaryꢀflag
0:ꢀNoꢀauxiliaryꢀcarry
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀ
fromꢀtheꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction
Bitꢀ0
C:ꢀCarryꢀflag
0:ꢀNoꢀcarry-out
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀ
notꢀtakeꢀplaceꢀduringꢀaꢀsubtractionꢀoperation
Cꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀcarryꢀinstruction.
Rev. 1.40
40
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
EEPROM Data Memory
TheꢀdevicesꢀcontainꢀanꢀareaꢀofꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀEEPROM,ꢀwhichꢀstandsꢀforꢀ
ElectricallyꢀErasableꢀProgrammableꢀReadꢀOnlyꢀMemory,ꢀisꢀbyꢀitsꢀnatureꢀaꢀnon-volatileꢀformꢀ
ofꢀre-programmableꢀmemory,ꢀwithꢀdataꢀretentionꢀevenꢀwhenꢀitsꢀpowerꢀsupplyꢀisꢀremoved.ꢀByꢀ
incorporatingꢀthisꢀkindꢀofꢀdataꢀmemory,ꢀaꢀwholeꢀnewꢀhostꢀofꢀapplicationꢀpossibilitiesꢀareꢀmadeꢀ
availableꢀtoꢀtheꢀdesigner.ꢀTheꢀavailabilityꢀofꢀEEPROMꢀstorageꢀallowsꢀinformationꢀsuchꢀasꢀproductꢀ
identificationꢀnumbers,ꢀcalibrationꢀvalues,ꢀspecificꢀuserꢀdata,ꢀsystemꢀsetupꢀdataꢀorꢀotherꢀproductꢀ
informationꢀtoꢀbeꢀstoredꢀdirectlyꢀwithinꢀtheꢀproductꢀmicrocontroller.ꢀTheꢀprocessꢀofꢀreadingꢀandꢀ
writingꢀdataꢀtoꢀtheꢀEEPROMꢀmemoryꢀhasꢀbeenꢀreducedꢀtoꢀaꢀveryꢀtrivialꢀaffair.
EEPROM Data Memory Structure
TheꢀEEPROMꢀDataꢀMemoryꢀcapacityꢀisꢀupꢀtoꢀ256×8ꢀbitsꢀforꢀthisꢀseriesꢀofꢀdevices.ꢀUnlikeꢀtheꢀ
ProgramꢀMemoryꢀandꢀRAMꢀDataꢀMemory,ꢀtheꢀEEPROMꢀDataꢀMemoryꢀisꢀnotꢀdirectlyꢀmappedꢀ
intoꢀmemoryꢀspaceꢀandꢀisꢀthereforeꢀnotꢀdirectlyꢀaddressableꢀinꢀtheꢀsameꢀwayꢀasꢀtheꢀotherꢀtypesꢀofꢀ
memory.ꢀReadꢀandꢀWriteꢀoperationsꢀtoꢀtheꢀEEPROMꢀareꢀcarriedꢀoutꢀinꢀsingleꢀbyteꢀoperationsꢀusingꢀ
anꢀaddressꢀandꢀdataꢀregisterꢀinꢀBankꢀ0ꢀandꢀaꢀsingleꢀcontrolꢀregisterꢀinꢀBankꢀ1.
Device
Capacity
Address
BC66F840
1ꢁ8×8
00H~ꢃFH
BC66F850
BC66F860
ꢁ56×8
00H~FFH
EEPROM Data Memory Structure
EEPROM Registers
ThreeꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀTheseꢀareꢀtheꢀ
addressꢀregister,ꢀEEA,ꢀtheꢀdataꢀregister,ꢀEEDꢀandꢀaꢀsingleꢀcontrolꢀregister,ꢀEEC.ꢀAsꢀbothꢀtheꢀEEAꢀ
andꢀEEDꢀregistersꢀareꢀlocatedꢀinꢀBankꢀ0,ꢀtheyꢀcanꢀbeꢀdirectlyꢀaccessedꢀinꢀtheꢀsameꢀwasꢀasꢀanyꢀotherꢀ
SpecialꢀFunctionꢀRegister.ꢀTheꢀEECꢀregisterꢀhowever,ꢀbeingꢀlocatedꢀinꢀBank1,ꢀcannotꢀbeꢀaddressedꢀ
directlyꢀandꢀcanꢀonlyꢀbeꢀreadꢀfromꢀorꢀwrittenꢀtoꢀindirectlyꢀusingꢀtheꢀMP1ꢀMemoryꢀPointerꢀandꢀ
IndirectꢀAddressingꢀRegister,ꢀIAR1.ꢀBecauseꢀtheꢀEECꢀcontrolꢀregisterꢀisꢀlocatedꢀatꢀaddressꢀ40Hꢀinꢀ
Bankꢀ1,ꢀtheꢀMP1ꢀMemoryꢀPointerꢀmustꢀfirstꢀbeꢀsetꢀtoꢀtheꢀvalueꢀ40HꢀandꢀtheꢀBankꢀPointerꢀregister,ꢀ
BP,ꢀsetꢀtoꢀtheꢀvalue,ꢀ01H,ꢀbeforeꢀanyꢀoperationsꢀonꢀtheꢀEECꢀregisterꢀareꢀexecuted.
Bit
Name
7
6
5
4
3
2
1
0
BC66F840
—
A6
A5
A4
A3
Aꢁ
A1
A0
EEA
BC66F850
BC66F860
Aꢃ
A6
A5
A4
A3
Aꢁ
A1
A0
EED (All devices)
EEC (All devices)
Dꢃ
—
D6
—
D5
—
D4
—
D3
Dꢁ
D1
D0
WREN
WR
RDEN
RD
EEPROM Register List
Rev. 1.40
41
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
EEA Register – BC66F840
Bit
Name
R/W
7
6
A6
R/W
x
5
A5
R/W
x
4
A4
R/W
x
3
A3
R/W
x
2
Aꢁ
R/W
x
1
A1
R/W
x
0
—
—
—
A0
R/W
x
POR
“x”: unknown
Bitꢀ7ꢀ
Bitꢀ6~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
DataꢀEEPROMꢀMemoryꢀaddress
DataꢀEEPROMꢀMemoryꢀaddressꢀbitꢀ6~bitꢀ0
EEA Register – BC66F850/BC66F860
Bit
Name
R/W
7
Aꢃ
R/W
x
6
A6
R/W
x
5
A5
R/W
x
4
A4
R/W
x
3
A3
R/W
x
2
Aꢁ
R/W
x
1
A1
R/W
x
0
A0
R/W
x
POR
“x”: unknown
Bitꢀ7~0ꢀ
DataꢀEEPROMꢀMemoryꢀaddress
DataꢀEEPROMꢀMemoryꢀaddressꢀbitꢀ7~bitꢀ0
EED Register
Bit
Name
R/W
7
Dꢃ
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
Dꢁ
R/W
x
1
D1
R/W
x
0
D0
R/W
x
POR
“x”: unknown
Bitꢀ7~0ꢀ
EEPROMꢀDataꢀbits
Rev. 1.40
4ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
EEC Register
Bit
Name
R/W
7
6
5
4
3
WREN
R/W
0
2
WR
R/W
0
1
RDEN
R/W
0
0
RD
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
WREN:ꢀDataꢀEEPROMꢀWriteꢀEnable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ
EEPROMꢀwriteꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀDataꢀ
EEPROMꢀwriteꢀoperations.
Bitꢀ2
WR:ꢀEEPROMꢀWriteꢀControl
0:ꢀWriteꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀwriteꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀwriteꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀWRENꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Bitꢀ1
Bitꢀ0
RDEN:ꢀDataꢀEEPROMꢀReadꢀEnable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ
EEPROMꢀreadꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀDataꢀ
EEPROMꢀreadꢀoperations.
RD :ꢀEEPROMꢀReadꢀControl
0:ꢀReadꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀreadꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀreadꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀreadꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀRDENꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Note:ꢀTheꢀWREN,ꢀWR,ꢀRDENꢀandꢀRDꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“1”ꢀatꢀtheꢀsameꢀtimeꢀinꢀoneꢀinstruction.ꢀTheꢀ
WRꢀandꢀRDꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“1”ꢀatꢀtheꢀsameꢀtime.
Rev. 1.40
43
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Reading Data from the EEPROM
ToꢀreadꢀdataꢀfromꢀtheꢀEEPROM,ꢀtheꢀreadꢀenableꢀbit,ꢀRDEN,ꢀinꢀtheꢀEECꢀregisterꢀmustꢀfirstꢀbeꢀsetꢀ
highꢀtoꢀenableꢀtheꢀreadꢀfunction.ꢀTheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀreadꢀmustꢀthenꢀbeꢀplacedꢀ
inꢀtheꢀEEAꢀregister.ꢀIfꢀtheꢀRDꢀbitꢀinꢀtheꢀEECꢀregisterꢀisꢀnowꢀsetꢀhigh,ꢀaꢀreadꢀcycleꢀwillꢀbeꢀinitiated.ꢀ
SettingꢀtheꢀRDꢀbitꢀhighꢀwillꢀnotꢀinitiateꢀaꢀreadꢀoperationꢀifꢀtheꢀRDENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀWhenꢀ
theꢀreadꢀcycleꢀterminates,ꢀtheꢀRDꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀzero,ꢀafterꢀwhichꢀtheꢀdataꢀcanꢀ
beꢀreadꢀfromꢀtheꢀEEDꢀregister.ꢀTheꢀdataꢀwillꢀremainꢀinꢀtheꢀEEDꢀregisterꢀuntilꢀanotherꢀreadꢀorꢀwriteꢀ
operationꢀisꢀexecuted.ꢀTheꢀapplicationꢀprogramꢀcanꢀpollꢀtheꢀRDꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀdataꢀisꢀ
validꢀforꢀreading.
Writing Data to the EEPROM
TheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀmustꢀfirstꢀbeꢀplacedꢀinꢀtheꢀEEAꢀregisterꢀandꢀtheꢀdataꢀ
placedꢀinꢀtheꢀEEDꢀregister.ꢀToꢀwriteꢀdataꢀtoꢀtheꢀEEPROM,ꢀtheꢀwriteꢀenableꢀbit,ꢀWREN,ꢀinꢀtheꢀEECꢀ
registerꢀmustꢀfirstꢀbeꢀsetꢀhighꢀtoꢀenableꢀtheꢀwriteꢀfunction.ꢀAfterꢀthis,ꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀ
mustꢀbeꢀimmediatelyꢀsetꢀhighꢀtoꢀinitiateꢀaꢀwriteꢀcycle.ꢀTheseꢀtwoꢀinstructionsꢀmustꢀbeꢀexecutedꢀ
consecutively.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀfirstꢀbeꢀclearedꢀbeforeꢀimplementingꢀanyꢀ
writeꢀoperations,ꢀandꢀthenꢀsetꢀagainꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀstarted.ꢀNoteꢀthatꢀsettingꢀtheꢀWRꢀbitꢀ
highꢀwillꢀnotꢀinitiateꢀaꢀwriteꢀcycleꢀifꢀtheꢀWRENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀAsꢀtheꢀEEPROMꢀwriteꢀcycleꢀisꢀ
controlledꢀusingꢀanꢀinternalꢀtimerꢀwhoseꢀoperationꢀisꢀasynchronousꢀtoꢀmicrocontrollerꢀsystemꢀclock,ꢀ
aꢀcertainꢀtimeꢀwillꢀelapseꢀbeforeꢀtheꢀdataꢀwillꢀhaveꢀbeenꢀwrittenꢀintoꢀtheꢀEEPROM.ꢀDetectingꢀwhenꢀ
theꢀwriteꢀcycleꢀhasꢀfinishedꢀcanꢀbeꢀimplementedꢀeitherꢀbyꢀpollingꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀorꢀ
byꢀusingꢀtheꢀEEPROMꢀinterrupt.ꢀWhenꢀtheꢀwriteꢀcycleꢀterminates,ꢀtheꢀWRꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀzeroꢀbyꢀtheꢀmicrocontroller,ꢀinformingꢀtheꢀuserꢀthatꢀtheꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀ
EEPROM.ꢀTheꢀapplicationꢀprogramꢀcanꢀthereforeꢀpollꢀtheꢀWRꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀwriteꢀcycleꢀ
hasꢀended.
Write Protection
Protectionꢀagainstꢀinadvertentꢀwriteꢀoperationꢀisꢀprovidedꢀinꢀseveralꢀways.ꢀAfterꢀtheꢀdevicesꢀ
areꢀpowered-onꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀwillꢀbeꢀclearedꢀpreventingꢀanyꢀwriteꢀ
operations.ꢀAlsoꢀatꢀpower-onꢀtheꢀBankꢀPointer,ꢀBP,ꢀwillꢀbeꢀresetꢀtoꢀzero,ꢀwhichꢀmeansꢀthatꢀDataꢀ
MemoryꢀBankꢀ0ꢀwillꢀbeꢀselected.ꢀAsꢀtheꢀEEPROMꢀcontrolꢀregisterꢀisꢀlocatedꢀinꢀBankꢀ1,ꢀthisꢀaddsꢀaꢀ
furtherꢀmeasureꢀofꢀprotectionꢀagainstꢀspuriousꢀwriteꢀoperations.ꢀDuringꢀnormalꢀprogramꢀoperation,ꢀ
ensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀisꢀclearedꢀwillꢀsafeguardꢀagainstꢀincorrectꢀ
writeꢀoperations.
EEPROM Interrupt
TheꢀEEPROMꢀwriteꢀinterruptꢀisꢀgeneratedꢀwhenꢀanꢀEEPROMꢀwriteꢀcycleꢀhasꢀended.ꢀTheꢀEEPROMꢀ
interruptꢀmustꢀfirstꢀbeꢀenabledꢀbyꢀsettingꢀtheꢀDEEꢀbitꢀinꢀtheꢀrelevantꢀinterruptꢀregister.ꢀHoweverꢀ
asꢀtheꢀEEPROMꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀInterrupt,ꢀtheꢀassociatedꢀMulti-functionꢀ
Interruptꢀenableꢀbitꢀmustꢀalsoꢀbeꢀset.ꢀWhenꢀanꢀEEPROMꢀwriteꢀcycleꢀends,ꢀtheꢀDEFꢀrequestꢀflagꢀ
andꢀitsꢀassociatedꢀMulti-functionꢀInterruptꢀrequestꢀflagꢀwillꢀbothꢀbeꢀset.ꢀIfꢀtheꢀglobal,ꢀEEPROMꢀandꢀ
Multi-functionꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀaꢀjumpꢀtoꢀtheꢀassociatedꢀMulti-functionꢀ
Interruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀservicedꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀflagꢀ
willꢀbeꢀautomaticallyꢀreset,ꢀtheꢀEEPROMꢀinterruptꢀflagꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀ
program.ꢀMoreꢀdetailsꢀcanꢀbeꢀobtainedꢀinꢀtheꢀInterruptꢀsection.
Rev. 1.40
44
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Programming Considerations
CareꢀmustꢀbeꢀtakenꢀthatꢀdataꢀisꢀnotꢀinadvertentlyꢀwrittenꢀtoꢀtheꢀEEPROM.ꢀProtectionꢀcanꢀbeꢀ
enhancedꢀbyꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀisꢀnormallyꢀclearedꢀtoꢀzeroꢀwhenꢀnotꢀwriting.ꢀAlsoꢀ
theꢀBankꢀPointerꢀcouldꢀbeꢀnormallyꢀclearedꢀtoꢀzeroꢀasꢀthisꢀwouldꢀinhibitꢀaccessꢀtoꢀBankꢀ1ꢀwhereꢀ
theꢀEEPROMꢀcontrolꢀregisterꢀexist.ꢀAlthoughꢀcertainlyꢀnotꢀnecessary,ꢀconsiderationꢀmightꢀbeꢀgivenꢀ
inꢀtheꢀapplicationꢀprogramꢀtoꢀtheꢀcheckingꢀofꢀtheꢀvalidityꢀofꢀnewꢀwriteꢀdataꢀbyꢀaꢀsimpleꢀreadꢀbackꢀ
process.ꢀWhenꢀwritingꢀdataꢀtheꢀWRꢀbitꢀmustꢀbeꢀsetꢀhighꢀimmediatelyꢀafterꢀtheꢀWRENꢀbitꢀhasꢀbeenꢀ
setꢀhigh,ꢀtoꢀensureꢀtheꢀwriteꢀcycleꢀexecutesꢀcorrectly.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀbeꢀ
clearedꢀbeforeꢀaꢀwriteꢀcycleꢀisꢀexecutedꢀandꢀthenꢀre-enabledꢀafterꢀtheꢀwriteꢀcycleꢀstarts.
Programming Examples
Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
SET IAR1.1
SET IAR1.0
BACK:
; set RDEN bit, enable read operations
; start Read Cycle – set RD bit
SZ IAR1.0
JMP BACK
CLR IAR1
CLR BP
MOV A, EED
MOV READ_DATA, A
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing Data to the EEPROM – polling method
CLR EMI
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
; user defined address
; user defined data
MOV A, 040H
MOV MP1, A
MOV A, 01H
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
MOV BP, A
SET IAR1.3
SET IAR1.2
; set WREN bit, enable write operations
; Start Write Cycle – set WR bit – executed immediately
; after set WREN bit
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR BP
; check for write cycle end
; disable EEPROM read/write
Rev. 1.40
45
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Oscillator
Variousꢀoscillatorꢀoptionsꢀofferꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀaccordingꢀtoꢀtheirꢀvariousꢀ
applicationꢀrequirements.ꢀTheꢀflexibleꢀfeaturesꢀofꢀtheꢀoscillatorꢀfunctionsꢀensureꢀthatꢀtheꢀbestꢀ
optimisationꢀcanꢀbeꢀachievedꢀinꢀtermsꢀofꢀspeedꢀandꢀpowerꢀsaving.ꢀOscillatorꢀselectionsꢀandꢀoperationꢀ
areꢀselectedꢀthroughꢀaꢀcombinationꢀofꢀconfigurationꢀoptionsꢀandꢀregisters.
Oscillator Overview
Inꢀadditionꢀtoꢀbeingꢀtheꢀsourceꢀofꢀtheꢀmainꢀsystemꢀclockꢀtheꢀoscillatorsꢀalsoꢀprovideꢀclockꢀsourcesꢀ
forꢀtheWatchdogꢀTimerꢀandꢀTimeꢀBaseꢀInterrupts.ꢀExternalꢀoscillatorsꢀrequiringꢀsomeꢀexternalꢀ
componentsꢀasꢀwellꢀasꢀfullyꢀintegratedꢀinternalꢀoscillators,ꢀrequiringꢀnoꢀexternalꢀcomponents,ꢀ
areꢀprovidedꢀtoꢀformꢀaꢀwideꢀrangeꢀofꢀbothꢀfastꢀandꢀslowꢀsystemꢀoscillators.ꢀAllꢀoscillatorꢀoptionsꢀ
areꢀselectedꢀthroughꢀtheꢀconfigurationꢀoptions.ꢀTheꢀhigherꢀfrequencyꢀoscillatorsꢀprovideꢀhigherꢀ
performanceꢀbutꢀcarryꢀwithꢀitꢀtheꢀdisadvantageꢀofꢀhigherꢀpowerꢀrequirements,ꢀwhileꢀtheꢀoppositeꢀ
isꢀofꢀcourseꢀtrueꢀforꢀtheꢀlowerꢀfrequencyꢀoscillators.ꢀWithꢀtheꢀcapabilityꢀofꢀdynamicallyꢀswitchingꢀ
betweenꢀfastꢀandꢀslowꢀsystemꢀclock,ꢀtheꢀdevicesꢀhaveꢀtheꢀflexibilityꢀtoꢀoptimizeꢀtheꢀperformance/
powerꢀratio,ꢀaꢀfeatureꢀespeciallyꢀimportantꢀinꢀpowerꢀsensitiveꢀportableꢀapplications.
Type
External Crꢀstal
Name
HXT
Freq.
16�Hz
Pins
OSC1/OSCꢁ
XT1/XTꢁ
—
External Low Speed Crꢀstal
Internal Low Speed RC
LXT
3ꢁ.ꢃ68kHz
3ꢁkHz
LIRC
Oscillator Types
System Clock Configurations
Thereꢀareꢀthreeꢀsystemꢀoscillators,ꢀoneꢀhighꢀspeedꢀoscillatorꢀandꢀtwoꢀlowꢀspeedꢀoscillators.ꢀTheꢀhighꢀ
speedꢀoscillatorꢀisꢀtheꢀexternalꢀcrystal/ceramicꢀoscillatorꢀ–ꢀHXT.ꢀTheꢀlowꢀspeedꢀoscillatorsꢀareꢀtheꢀ
internalꢀ32kHzꢀoscillatorꢀ–ꢀLIRCꢀandꢀtheꢀexternalꢀ32.768kHzꢀcrystalꢀoscillator.ꢀSelectingꢀwhetherꢀ
theꢀlowꢀorꢀhighꢀspeedꢀoscillatorꢀisꢀusedꢀasꢀtheꢀsystemꢀoscillatorꢀisꢀimplementedꢀusingꢀtheꢀHLCLKꢀbitꢀ
andꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀandꢀasꢀtheꢀsystemꢀclockꢀcanꢀbeꢀdynamicallyꢀselected.
Theꢀactualꢀsourceꢀclockꢀusedꢀforꢀtheꢀlowꢀspeedꢀoscillatorꢀisꢀchosenꢀviaꢀaꢀconfigurationꢀoption.ꢀTheꢀ
frequencyꢀofꢀtheꢀslowꢀspeedꢀorꢀhighꢀspeedꢀsystemꢀclockꢀisꢀalsoꢀdeterminedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀ
CKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀNoteꢀthatꢀtwoꢀoscillatorꢀselectionsꢀmustꢀbeꢀmadeꢀnamelyꢀ
oneꢀhighꢀspeedꢀandꢀoneꢀlowꢀspeedꢀsystemꢀoscillators.ꢀItꢀisꢀnotꢀpossibleꢀtoꢀchooseꢀaꢀno-oscillatorꢀ
selectionꢀforꢀeitherꢀtheꢀhighꢀorꢀlowꢀspeedꢀoscillator.
High Speed
Oscillator
fH
HXT
6-stage Prescaler
fH/ꢁ
fH/4
fH/8
fH/16
fH/3ꢁ
fH/64
Low Speed
Oscillator
fSYS
LXT
fSUB
LIRC
HLCLKꢂ
CKSꢁ~CKS0 bits
fSUB
Configuration
Option
Fast Wake-up from SLEEP �ode or
IDLE �ode Control (for HXT onlꢀ)
System Clock Configurations
Rev. 1.40
46
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
External Crystal/Ceramic Oscillator – HXT
TheꢀExternalꢀCrystal/CeramicꢀSystemꢀOscillatorꢀisꢀtheꢀhighꢀfrequencyꢀoscillator.ꢀForꢀmostꢀcrystalꢀ
oscillatorꢀconfigurations,ꢀtheꢀsimpleꢀconnectionꢀofꢀaꢀcrystalꢀacrossꢀOSC1ꢀandꢀOSC2ꢀwillꢀcreateꢀtheꢀ
necessaryꢀphaseꢀshiftꢀandꢀfeedbackꢀforꢀoscillation,ꢀwithoutꢀrequiringꢀexternalꢀcapacitors.ꢀHowever,ꢀ
forꢀsomeꢀcrystalꢀtypesꢀandꢀfrequencies,ꢀtoꢀensureꢀoscillation,ꢀitꢀmayꢀbeꢀnecessaryꢀtoꢀaddꢀtwoꢀsmallꢀ
valueꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀUsingꢀaꢀceramicꢀresonatorꢀwillꢀusuallyꢀrequireꢀtwoꢀsmallꢀvalueꢀ
capacitors,ꢀC1ꢀandꢀC2,ꢀtoꢀbeꢀconnectedꢀasꢀshownꢀforꢀoscillationꢀtoꢀoccur.ꢀTheꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀ
shouldꢀbeꢀselectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀmanufacturersꢀspecification.
Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ
thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterꢀconnectingꢀlinesꢀareꢀallꢀ
locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.
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Crystal/Resonator Oscillator – HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
0pF
16�Hz
0pF
Note: C1 and Cꢁ values are for guidance onlꢀ.
Crystal Recommended Capacitor Values
Rev. 1.40
4ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
External 32.768kHz Crystal Oscillator – LXT
TheꢀExternalꢀ32.768kHzꢀCrystalꢀSystemꢀOscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀ
whichꢀisꢀselectedꢀviaꢀconfigurationꢀoption.ꢀThisꢀclockꢀsourceꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ32.768kHzꢀ
andꢀrequiresꢀaꢀ32.768kHzꢀcrystalꢀtoꢀbeꢀconnectedꢀbetweenꢀpinsꢀXT1ꢀandꢀXT2.ꢀTheꢀexternalꢀresistorꢀ
andꢀcapacitorꢀcomponentsꢀconnectedꢀtoꢀtheꢀ32.768kHzꢀcrystalꢀareꢀnecessaryꢀtoꢀprovideꢀoscillation.ꢀ
Forꢀapplicationsꢀwhereꢀpreciseꢀfrequenciesꢀareꢀessential,ꢀtheseꢀcomponentsꢀmayꢀbeꢀrequiredꢀtoꢀ
provideꢀfrequencyꢀcompensationꢀdueꢀtoꢀdifferentꢀcrystalꢀmanufacturingꢀtolerances.ꢀDuringꢀpower-upꢀ
thereꢀisꢀaꢀtimeꢀdelayꢀassociatedꢀwithꢀtheꢀLXTꢀoscillatorꢀwaitingꢀforꢀitꢀtoꢀstart-up.
WhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀsystemꢀclockꢀisꢀswitchedꢀoffꢀtoꢀstopꢀ
microcontrollerꢀactivityꢀandꢀtoꢀconserveꢀpower.ꢀHowever,ꢀinꢀmanyꢀmicrocontrollerꢀapplicationsꢀ
itꢀmayꢀbeꢀnecessaryꢀtoꢀkeepꢀtheꢀinternalꢀtimersꢀoperationalꢀevenꢀwhenꢀtheꢀmicrocontrollerꢀisꢀinꢀ
theꢀSLEEPꢀorꢀIDLEꢀMode.ꢀToꢀdoꢀthis,ꢀanotherꢀclock,ꢀindependentꢀofꢀtheꢀsystemꢀclock,ꢀmustꢀbeꢀ
provided.
However,ꢀforꢀsomeꢀcrystals,ꢀtoꢀensureꢀoscillationꢀandꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀ
toꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀ
selectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀmanufacturer’sꢀspecification.ꢀTheꢀexternalꢀ
parallelꢀfeedbackꢀresistor,ꢀRp,ꢀisꢀrequired.
AꢀconfigurationꢀoptionꢀdeterminesꢀifꢀtheꢀXT1/XT2ꢀpinsꢀareꢀusedꢀforꢀtheꢀLXTꢀoscillatorꢀorꢀasꢀI/Oꢀ
pins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀnotꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀXT1/XT2ꢀpinsꢀcanꢀbeꢀusedꢀasꢀnormalꢀ
I/Oꢀpins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀ32.768kHzꢀcrystalꢀshouldꢀbeꢀconnectedꢀtoꢀ
theꢀXT1/XT2ꢀpins.
Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ
thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterꢀconnectingꢀlinesꢀareꢀallꢀ
locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.
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External LXT Oscillator – LXT
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
10pF
3ꢁ.ꢃ68kHz
10pF
Note: 1. C1 and Cꢁ values are for guidance onlꢀ.
2. Rp=5M~10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
Rev. 1.40
48
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
LXT Oscillator Low Power Function
TheꢀLXTꢀoscillatorꢀcanꢀfunctionꢀinꢀoneꢀofꢀtwoꢀmodes,ꢀtheꢀQuickꢀStartꢀModeꢀandꢀtheꢀLowꢀPowerꢀ
Mode.ꢀTheꢀmodeꢀselectionꢀisꢀexecutedꢀusingꢀtheꢀLXTLPꢀbitꢀinꢀtheꢀTBCꢀregister.
LXTLP Bit
LXT Mode
Quick Start
Low Power
0
1
Afterꢀpowerꢀon,ꢀtheꢀLXTLPꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀzeroꢀensuringꢀthatꢀtheꢀLXTꢀoscillatorꢀ
isꢀinꢀtheꢀQuickꢀStartꢀoperatingꢀmode.ꢀInꢀtheꢀQuickꢀStartꢀModeꢀtheꢀLXTꢀoscillatorꢀwillꢀpowerꢀupꢀ
andꢀstabiliseꢀquickly.ꢀHowever,ꢀafterꢀtheꢀLXTꢀoscillatorꢀhasꢀfullyꢀpoweredꢀupꢀitꢀcanꢀbeꢀplacedꢀ
intoꢀtheꢀLow-powerꢀmodeꢀbyꢀsettingꢀtheꢀLXTLPꢀbitꢀhigh.ꢀTheꢀoscillatorꢀwillꢀcontinueꢀtoꢀrunꢀbutꢀ
withꢀreducedꢀcurrentꢀconsumption,ꢀasꢀtheꢀhigherꢀcurrentꢀconsumptionꢀisꢀonlyꢀrequiredꢀduringꢀtheꢀ
LXTꢀoscillatorꢀstart-up.ꢀInꢀpowerꢀsensitiveꢀapplications,ꢀsuchꢀasꢀbatteryꢀapplications,ꢀwhereꢀpowerꢀ
consumptionꢀmustꢀbeꢀkeptꢀtoꢀaꢀminimum,ꢀitꢀisꢀthereforeꢀrecommendedꢀthatꢀtheꢀapplicationꢀprogramꢀ
setsꢀtheꢀLXTLPꢀbitꢀhighꢀaboutꢀ2ꢀsecondsꢀafterꢀpower-on.
ItꢀshouldꢀbeꢀnotedꢀthatꢀnoꢀmatterꢀwhatꢀconditionꢀtheꢀLXTLPꢀbitꢀisꢀsetꢀto,ꢀtheꢀLXTꢀoscillatorꢀwillꢀ
alwaysꢀfunctionꢀnormally,ꢀtheꢀonlyꢀdifferenceꢀisꢀthatꢀitꢀwillꢀtakeꢀmoreꢀtimeꢀtoꢀstartꢀupꢀifꢀinꢀtheꢀ
Low-powerꢀmode.
Internal 32kHz Oscillator – LIRC
TheꢀInternalꢀ32kHzꢀSystemꢀOscillatorꢀisꢀtheꢀlowꢀfrequencyꢀoscillator.ꢀItꢀisꢀaꢀfullyꢀintegratedꢀ
RCꢀoscillatorꢀwithꢀaꢀtypicalꢀfrequencyꢀofꢀ32kHzꢀatꢀ5V,ꢀrequiringꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀ
implementation.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀ
frequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀ
temperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀoscillationꢀfrequencyꢀareꢀminimised.ꢀAsꢀaꢀresult,ꢀatꢀaꢀ
powerꢀsupplyꢀofꢀ5Vꢀandꢀatꢀaꢀtemperatureꢀofꢀ25˚Cꢀdegrees,ꢀtheꢀfixedꢀoscillationꢀfrequencyꢀofꢀ32kHzꢀ
willꢀhaveꢀaꢀtoleranceꢀwithinꢀ10%.
Supplementary Oscillator
Theꢀlowꢀspeedꢀoscillator,ꢀinꢀadditionꢀtoꢀprovidingꢀaꢀsystemꢀclockꢀsource,ꢀisꢀalsoꢀusedꢀtoꢀprovideꢀaꢀ
clockꢀsourceꢀtoꢀotherꢀdeviceꢀfunctionsꢀsuchꢀasꢀtheꢀWatchdogꢀTimerꢀandꢀtheꢀTimeꢀBaseꢀInterrupts.
Rev. 1.40
49
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Operating Modes and System Clocks
Presentꢀdayꢀapplicationsꢀrequireꢀthatꢀtheirꢀmicrocontrollersꢀhaveꢀhighꢀperformanceꢀbutꢀoftenꢀstillꢀ
demandꢀthatꢀtheyꢀconsumeꢀasꢀlittleꢀpowerꢀasꢀpossible,ꢀconflictingꢀrequirementsꢀthatꢀareꢀespeciallyꢀ
trueꢀinꢀbatteryꢀpoweredꢀportableꢀapplications.ꢀTheꢀfastꢀclocksꢀrequiredꢀforꢀhighꢀperformanceꢀwillꢀ
byꢀtheirꢀnatureꢀincreaseꢀcurrentꢀconsumptionꢀandꢀofꢀcourseꢀvice-versa,ꢀlowerꢀspeedꢀclocksꢀreduceꢀ
currentꢀconsumption.ꢀAsꢀHoltekꢀhasꢀprovidedꢀtheseꢀdevicesꢀwithꢀbothꢀhighꢀandꢀlowꢀspeedꢀclockꢀ
sourcesꢀandꢀtheꢀmeansꢀtoꢀswitchꢀbetweenꢀthemꢀdynamically,ꢀtheꢀuserꢀcanꢀoptimiseꢀtheꢀoperationꢀofꢀ
theirꢀmicrocontrollerꢀtoꢀachieveꢀtheꢀbestꢀperformance/powerꢀratio.
System Clocks
TheꢀdevicesꢀhaveꢀmanyꢀdifferentꢀclockꢀsourcesꢀforꢀbothꢀtheꢀCPUꢀandꢀperipheralꢀfunctionꢀoperation.ꢀ
Byꢀprovidingꢀtheꢀuserꢀwithꢀaꢀwideꢀrangeꢀofꢀclockꢀoptionsꢀusingꢀconfigurationꢀoptionsꢀandꢀregisterꢀ
programming,ꢀaꢀclockꢀsystemꢀcanꢀbeꢀconfiguredꢀtoꢀobtainꢀmaximumꢀapplicationꢀperformance.
TheꢀmainꢀsystemꢀclockꢀcanꢀcomeꢀfromꢀaꢀhighꢀfrequencyꢀfHꢀorꢀlowꢀfrequencyꢀfSUBꢀsourceꢀandꢀisꢀ
selectedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀTheꢀhighꢀspeedꢀsystemꢀ
clockꢀcanꢀbeꢀsourcedꢀfromꢀaꢀHXTꢀoscillator.ꢀTheꢀlowꢀspeedꢀsystemꢀclockꢀsourceꢀcanꢀbeꢀsourcedꢀ
fromꢀtheꢀclockꢀfSUB.ꢀIfꢀfSUBꢀisꢀselected,ꢀthenꢀitꢀcanꢀbeꢀsourcedꢀfromꢀeitherꢀtheꢀLIRCꢀorꢀLXTꢀoscillator.ꢀ
Theꢀotherꢀchoice,ꢀwhichꢀisꢀaꢀdividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀhasꢀaꢀrangeꢀofꢀ
fH/2~fH/64.ꢀNoteꢀthatꢀwhenꢀtheꢀsystemꢀclockꢀsourceꢀfSYSꢀisꢀswitchedꢀtoꢀfLꢀfromꢀfH,ꢀtheꢀhighꢀspeedꢀ
oscillationꢀwillꢀstopꢀtoꢀconserveꢀtheꢀpower.ꢀThusꢀthereꢀisꢀnoꢀfH~fH/64ꢀforꢀperipheralꢀcircuitꢀtoꢀuse.
TheꢀfSUBꢀclockꢀisꢀusedꢀtoꢀprovideꢀaꢀsubstituteꢀclockꢀforꢀtheꢀmicrocontrollerꢀjustꢀafterꢀaꢀwake-upꢀhasꢀ
occurredꢀtoꢀenableꢀfasterꢀwake-upꢀtimes.ꢀTogetherꢀwithꢀfSYS/4ꢀitꢀisꢀalsoꢀusedꢀasꢀoneꢀofꢀtheꢀclockꢀ
sourcesꢀforꢀtheꢀTimeꢀBaseꢀinterruptꢀfunction.ꢀTheꢀfSUBꢀclockꢀisꢀalsoꢀusedꢀasꢀaꢀclockꢀsourceꢀforꢀtheꢀ
WatchdogꢀTimer,ꢀTMsꢀorꢀSIMꢀfunctions.
CLKOEN SR[1:0]
Control circuitrꢀ
CLKO
(internallꢀ connected to the
RF Transceiver clock input)
High Speed
Oscillator
fH
HXT
6-stage Prescaler
fH/ꢁ
fH/4
fH/8
fH/16
fH/3ꢁ
fH/64
Low Speed
Oscillator
fSYS
LXT
fSUB
LIRC
HLCLKꢂ
CKSꢁ~CKS0 bits
fSUB
Configuration
Option
Fast Wake-up from SLEEP �ode or
IDLE �ode Control (for HXT onlꢀ)
fSUB
fSUB
WDT
TimeBase
fTB
fSYS/4
TBCK
Operating Mode Clock Configurations
Note:ꢀWhenꢀtheꢀsystemꢀclockꢀsourceꢀfSYSꢀisꢀswitchedꢀtoꢀfLꢀfromꢀfH,ꢀtheꢀhighꢀspeedꢀoscillationꢀwillꢀ
stopꢀtoꢀconserveꢀtheꢀpower.ꢀThusꢀthereꢀisꢀnoꢀfH~fH/64ꢀforꢀperipheralꢀcircuitꢀtoꢀuse.
Rev. 1.40
50
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
System Operation Modes
Thereꢀareꢀsixꢀdifferentꢀmodesꢀofꢀoperationꢀforꢀtheꢀmicrocontroller,ꢀeachꢀoneꢀwithꢀitsꢀownꢀ
specialꢀcharacteristicsꢀandꢀwhichꢀcanꢀbeꢀchosenꢀaccordingꢀtoꢀtheꢀspecificꢀperformanceꢀandꢀ
powerꢀrequirementsꢀofꢀtheꢀapplication.ꢀThereꢀareꢀtwoꢀmodesꢀallowingꢀnormalꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀMode.ꢀTheꢀremainingꢀfourꢀmodes,ꢀtheꢀSLEEP0,ꢀ
SLEEP1,ꢀIDLE0ꢀandꢀIDLE1ꢀModeꢀareꢀusedꢀwhenꢀtheꢀmicrocontrollerꢀCPUꢀisꢀswitchedꢀoffꢀtoꢀ
conserveꢀpower.
Description
Operating Mode
CPU
On
On
Off
Off
Off
Off
fSYS
fH~fH/64
fSUB
fSUB
On
On
On
On
Off
On
NOR�AL �ode
SLOW �ode
IDLE0 �ode
Off
IDLE1 �ode
On
SLEEP0 �ode
SLEEP1 �ode
Off
Off
NORMAL Mode
Asꢀtheꢀnameꢀsuggestsꢀthisꢀisꢀoneꢀofꢀtheꢀmainꢀoperatingꢀmodesꢀwhereꢀtheꢀmicrocontrollerꢀhasꢀallꢀofꢀ
itsꢀfunctionsꢀoperationalꢀandꢀwhereꢀtheꢀsystemꢀclockꢀisꢀprovidedꢀbyꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators.ꢀ
Thisꢀmodeꢀoperatesꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀoperateꢀnormallyꢀwithꢀaꢀclockꢀsourceꢀwillꢀcomeꢀ
fromꢀtheꢀHXTꢀhighꢀspeedꢀoscillator.ꢀTheꢀhighꢀspeedꢀoscillatorꢀwillꢀhoweverꢀfirstꢀbeꢀdividedꢀbyꢀaꢀ
ratioꢀrangingꢀfromꢀ1ꢀtoꢀ64,ꢀtheꢀactualꢀratioꢀbeingꢀselectedꢀbyꢀtheꢀCKS2~LCKS0ꢀandꢀHLCLKꢀbitsꢀ
inꢀtheꢀSMODꢀregister.ꢀAlthoughꢀaꢀhighꢀspeedꢀoscillatorꢀisꢀused,ꢀrunningꢀtheꢀmicrocontrollerꢀatꢀaꢀ
dividedꢀclockꢀratioꢀreducesꢀtheꢀoperatingꢀcurrent.
SLOW Mode
Thisꢀisꢀalsoꢀaꢀmodeꢀwhereꢀtheꢀmicrocontrollerꢀoperatesꢀnormallyꢀalthoughꢀnowꢀwithꢀaꢀslowerꢀspeedꢀ
clockꢀsource.ꢀTheꢀclockꢀsourceꢀusedꢀwillꢀbeꢀfromꢀtheꢀlowꢀspeedꢀoscillators,ꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀ
oscillators.ꢀRunningꢀtheꢀmicrocontrollerꢀinꢀthisꢀmodeꢀallowsꢀitꢀtoꢀrunꢀwithꢀmuchꢀlowerꢀoperatingꢀ
currents.ꢀInꢀtheꢀSLOWꢀMode,ꢀtheꢀfHꢀisꢀoff.
SLEEP0 Mode
TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀtheꢀIDLENꢀbitꢀinꢀtheꢀSMODꢀ
registerꢀisꢀlow.ꢀInꢀtheꢀSLEEP0ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped,ꢀandꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀstoppedꢀ
too,ꢀandꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀdisabled.ꢀInꢀthisꢀmode,ꢀtheꢀLVDENꢀisꢀmustꢀsetꢀtoꢀ0.ꢀIfꢀtheꢀ
LVDENꢀisꢀsetꢀtoꢀ1,ꢀitꢀwon’tꢀenterꢀtheꢀSLEEP0ꢀMode.
SLEEP1 Mode
TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀtheꢀIDLENꢀbitꢀinꢀtheꢀSMODꢀ
registerꢀisꢀlow.ꢀInꢀtheꢀSLEEP1ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped.ꢀHowever,ꢀtheꢀfSUBꢀclockꢀwillꢀcontinueꢀ
toꢀoperateꢀifꢀtheꢀLVDENꢀisꢀsetꢀtoꢀ1ꢀorꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀenabledꢀasꢀitsꢀclockꢀsourceꢀisꢀ
fromꢀtheꢀfSUB
.
IDLE0 Mode
TheꢀIDLE0ꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀisꢀlow.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀ
systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀsomeꢀperipheralꢀfunctionsꢀwillꢀremainꢀ
operationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimer,ꢀTMsꢀandꢀSIM.ꢀInꢀtheꢀIDLE0ꢀMode,ꢀtheꢀsystemꢀoscillatorꢀ
willꢀbeꢀstopped.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀWatchdogꢀTimerꢀclock,ꢀfSUB,ꢀwillꢀbeꢀonꢀifꢀtheꢀWatchdogꢀ
Timerꢀfunctionꢀisꢀenabled.
Rev. 1.40
51
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
IDLE1 Mode
TheꢀIDLE1ꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀ
systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀmayꢀcontinueꢀtoꢀprovideꢀaꢀclockꢀsourceꢀ
toꢀkeepꢀsomeꢀperipheralꢀfunctionsꢀoperationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimer,ꢀTMsꢀandꢀSIM.ꢀInꢀtheꢀ
IDLE1ꢀMode,ꢀtheꢀsystemꢀoscillatorꢀwillꢀcontinueꢀtoꢀrun,ꢀandꢀthisꢀsystemꢀoscillatorꢀmayꢀbeꢀhighꢀ
speedꢀorꢀlowꢀspeedꢀsystemꢀoscillator.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀWatchdogꢀTimerꢀclock,ꢀfSUB,ꢀwillꢀbeꢀonꢀ
ifꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀenabled.
Control Register
Aꢀregister,ꢀSMOD,ꢀtogetherꢀwithꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀareꢀusedꢀforꢀoverallꢀcontrolꢀ
ofꢀtheꢀinternalꢀclocksꢀwithinꢀtheꢀdevices.
SMOD Register
Bit
7
CKSꢁ
R/W
1
6
CKS1
R/W
1
5
CKS0
R/W
0
4
FSTEN
R/W
0
3
LTO
R
2
HTO
R
1
IDLEN
R/W
1
0
HLCLK
R/W
0
Name
R/W
POR
0
1
Bitꢀ7~5
CKS2~CKS0:ꢀTheꢀsystemꢀclockꢀselectionꢀwhenꢀHLCLKꢀisꢀ0
000:ꢀfSUBꢀ(fLIRCꢀorꢀfLXT
001:ꢀfSUBꢀ(fLIRCꢀorꢀfLXT
010:ꢀfH/64
)
)
011:ꢀfH/32
100:ꢀfH/16
101:ꢀfH/8
110:ꢀfH/4
111:ꢀfH/2
Theseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀwhichꢀclockꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀsource.ꢀ
Inꢀadditionꢀtoꢀtheꢀsystemꢀclockꢀsource,ꢀwhichꢀisꢀtheꢀLIRCꢀorꢀLXTꢀclock,ꢀaꢀdividedꢀ
versionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀcanꢀalsoꢀbeꢀchosenꢀasꢀtheꢀsystemꢀclockꢀ
source.
Bitꢀ4
Bitꢀ3
FSTEN:ꢀFastꢀWake-upꢀControlꢀ(onlyꢀforꢀHXT)
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀFastꢀWake-upꢀControlꢀbitꢀwhichꢀdeterminesꢀifꢀtheꢀfSUBꢀclockꢀsourceꢀisꢀ
initiallyꢀusedꢀafterꢀtheꢀdevicesꢀwakeꢀup.ꢀWhenꢀtheꢀbitꢀisꢀhigh,ꢀtheꢀfSUBꢀclockꢀsourceꢀcanꢀ
beꢀusedꢀasꢀaꢀtemporaryꢀsystemꢀclockꢀtoꢀprovideꢀaꢀfasterꢀwakeꢀupꢀtimeꢀasꢀtheꢀfSUBꢀclockꢀ
isꢀavailable.
LTO:ꢀLowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflag
0:ꢀNotꢀready
1:ꢀReady
Thisꢀisꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflagꢀwhichꢀindicatesꢀwhenꢀtheꢀlowꢀspeedꢀ
systemꢀoscillatorꢀisꢀstableꢀafterꢀpowerꢀonꢀresetꢀorꢀaꢀwake-upꢀhasꢀoccurred.ꢀTheꢀflagꢀ
willꢀbeꢀlowꢀwhenꢀinꢀtheꢀSLEEP0ꢀModeꢀbutꢀafterꢀaꢀwake-upꢀhasꢀoccurred,ꢀtheꢀflagꢀwillꢀ
changeꢀtoꢀaꢀhighꢀlevelꢀafterꢀ1~2ꢀclockꢀcyclesꢀifꢀtheꢀLIRCꢀoscillatorꢀisꢀusedꢀorꢀ1024ꢀ
clockꢀcyclesꢀifꢀtheꢀLXTꢀoscillatorꢀisꢀused.
Rev. 1.40
5ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ2
Bitꢀ1
Bitꢀ0
HTO:ꢀHighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflag
0:ꢀNotꢀready
1:ꢀReady
Thisꢀisꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflagꢀwhichꢀindicatesꢀwhenꢀtheꢀhighꢀspeedꢀ
systemꢀoscillatorꢀisꢀstable.ꢀThisꢀflagꢀisꢀclearedꢀtoꢀ0ꢀbyꢀhardwareꢀwhenꢀtheꢀdevicesꢀareꢀ
poweredꢀonꢀandꢀthenꢀchangesꢀtoꢀaꢀhighꢀlevelꢀafterꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀ
stable.ꢀThereforeꢀthisꢀflagꢀwillꢀalwaysꢀbeꢀreadꢀasꢀ1ꢀbyꢀtheꢀapplicationꢀprogramꢀafterꢀ
deviceꢀpower-on.ꢀTheꢀflagꢀwillꢀbeꢀlowꢀwhenꢀinꢀtheꢀSLEEPꢀorꢀIDLE0ꢀModeꢀbutꢀafterꢀaꢀ
wake-upꢀhasꢀoccurred,ꢀtheꢀflagꢀwillꢀchangeꢀtoꢀaꢀhighꢀlevelꢀafterꢀ1024ꢀclockꢀcyclesꢀasꢀ
theꢀHXTꢀoscillatorꢀisꢀused.
IDLEN:ꢀIDLEꢀModeꢀcontrol
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀIDLEꢀModeꢀControlꢀbitꢀandꢀdeterminesꢀwhatꢀhappensꢀwhenꢀtheꢀHALTꢀ
instructionꢀisꢀexecuted.ꢀIfꢀthisꢀbitꢀisꢀhigh,ꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀtheꢀ
devicesꢀwillꢀenterꢀtheꢀIDLEꢀMode.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀCPUꢀwillꢀstopꢀrunningꢀ
butꢀtheꢀsystemꢀclockꢀwillꢀcontinueꢀtoꢀkeepꢀtheꢀperipheralꢀfunctionsꢀoperationalꢀasꢀtheꢀ
FSYSONꢀbitꢀisꢀhigh.ꢀIfꢀFSYSONꢀbitꢀisꢀlow,ꢀtheꢀCPUꢀandꢀtheꢀsystemꢀclockꢀwillꢀallꢀstopꢀ
inꢀIDLE0ꢀmode.ꢀIfꢀtheꢀbitꢀisꢀlowꢀtheꢀdevicesꢀwillꢀenterꢀtheꢀSLEEPꢀModeꢀwhenꢀaꢀHALTꢀ
instructionꢀisꢀexecuted.
HLCLK:ꢀSystemꢀclockꢀselection
0:ꢀfH/2~fH/64ꢀorꢀfSUB
1:ꢀfH
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀifꢀtheꢀfHꢀclockꢀorꢀtheꢀfH/2~fH/64ꢀorꢀfSUBꢀclockꢀisꢀusedꢀasꢀ
theꢀsystemꢀclock.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀfHꢀclockꢀwillꢀbeꢀselectedꢀandꢀifꢀlowꢀtheꢀ
fH/2~fH/64ꢀorꢀfSUBꢀclockꢀwillꢀbeꢀselected.ꢀWhenꢀsystemꢀclockꢀswitchesꢀfromꢀtheꢀfHꢀ
clockꢀtoꢀtheꢀfSUBꢀclock,ꢀtheꢀfHꢀclockꢀwillꢀbeꢀautomaticallyꢀswitchedꢀoffꢀtoꢀconserveꢀ
power.
CTRL0 Register
Bit
7
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
Name
R/W
FSYSON
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
0
R/W
POR
0
"x": unknown
Bitꢀ7
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀFastꢀWake-upꢀControlꢀbitꢀwhichꢀdeterminesꢀifꢀtheꢀfSUBꢀclockꢀsourceꢀisꢀ
initiallyꢀusedꢀafterꢀtheꢀdevicesꢀwakeꢀup.
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀwhenꢀaꢀspecificꢀLowꢀVoltageꢀResetꢀsituationꢀoccurs.ꢀThisꢀbitꢀcanꢀ
onlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.40
53
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ1
Bitꢀ0
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnonꢀdefinedꢀLVRꢀvoltageꢀregisterꢀ
values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ
0ꢀbyꢀtheꢀapplicationꢀprogram.
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ
program.
TheꢀCLKOꢀclockꢀsignalꢀisꢀderivedꢀfromꢀtheꢀexternalꢀcrystalꢀoscillatorꢀandꢀinternallyꢀconnectedꢀtoꢀ
theꢀRFꢀTransceiverꢀclockꢀinput.ꢀItꢀisꢀrecommendedꢀtoꢀenableꢀtheꢀCLKOꢀclockꢀalwaysꢀwhenꢀtheꢀRFꢀ
transceiverꢀisꢀused.
CTRL1 Register
Bit
7
6
5
4
CLKOEN
R/W
3
2
1
0
Name
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR1
R/W
0
SR0
R/W
0
POR
0
Bitꢀ7~5ꢀ
Bitꢀ4
Unimplemented,ꢀreadꢀasꢀ“0”
CLKOEN:ꢀCLKOꢀOutputꢀEnableꢀControl
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀisꢀusedꢀtoꢀenableꢀorꢀdisableꢀtheꢀCLKOꢀoutputꢀsignalꢀwhichꢀisꢀinternallyꢀ
connectedꢀtoꢀtheꢀRFꢀtransceiverꢀclockꢀinput.ꢀItꢀisꢀrecommendedꢀtoꢀenableꢀtheꢀCLKOꢀ
outputꢀwhenꢀtheꢀRFꢀtransceiverꢀisꢀusedꢀevenꢀifꢀtheꢀdevicesꢀenterꢀtheꢀpowerꢀdownꢀ
mode.
Bitꢀ3~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
SR1~SR0:ꢀCLKOꢀOutputꢀSlewꢀRateꢀControl
SR[1:0]
00
VCLKO=3V VCLKO=5V
0.ꢁꢁV/ns
0.ꢁ0V/ns
0.15V/ns
0.10V/ns
0.5V/ns
0.4V/ns
0.3V/ns
0.ꢁV/ns
01
10
11
TheseꢀbitsꢀareꢀusedꢀtoꢀcontrolꢀtheꢀCLKOꢀoutputꢀslewꢀrate.
Rev. 1.40
54
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Fast Wake-up
ToꢀminimiseꢀpowerꢀconsumptionꢀtheꢀdevicesꢀcanꢀenterꢀtheꢀSLEEPꢀorꢀIDLE0ꢀMode,ꢀwhereꢀtheꢀ
systemꢀclockꢀsourceꢀtoꢀtheꢀdevicesꢀwillꢀbeꢀstopped.ꢀHoweverꢀwhenꢀtheꢀdevicesꢀareꢀwokenꢀupꢀagain,ꢀ
itꢀcanꢀtakeꢀaꢀconsiderableꢀtimeꢀforꢀtheꢀoriginalꢀsystemꢀoscillatorꢀtoꢀrestart,ꢀstabiliseꢀandꢀallowꢀnormalꢀ
operationꢀtoꢀresume.ꢀToꢀensureꢀtheꢀdevicesꢀareꢀupꢀandꢀrunningꢀasꢀfastꢀasꢀpossibleꢀaꢀFastꢀWake-upꢀ
functionꢀisꢀprovided,ꢀwhichꢀallowsꢀfSUB,ꢀnamelyꢀtheꢀLIRCꢀorꢀLXTꢀoscillator,ꢀtoꢀactꢀasꢀaꢀtemporaryꢀ
clockꢀtoꢀfirstꢀdriveꢀtheꢀsystemꢀuntilꢀtheꢀoriginalꢀsystemꢀoscillatorꢀhasꢀstabilised.ꢀAsꢀtheꢀclockꢀsourceꢀ
forꢀtheꢀFastꢀWake-upꢀfunctionꢀisꢀfSUB,ꢀtheꢀFastꢀWake-upꢀfunctionꢀisꢀonlyꢀavailableꢀinꢀtheꢀSLEEP1ꢀ
andꢀIDLE0ꢀmodes.ꢀWhenꢀtheꢀdevicesꢀareꢀwokenꢀupꢀfromꢀtheꢀSLEEP0ꢀmode,ꢀtheꢀFastꢀWake-upꢀ
functionꢀhasꢀnoꢀeffectꢀbecauseꢀtheꢀfSUBꢀclockꢀisꢀstopped.ꢀTheꢀFastꢀWake-upꢀenable/disableꢀfunctionꢀisꢀ
controlledꢀusingꢀtheꢀFSTENꢀbitꢀinꢀtheꢀSMODꢀregister.
IfꢀtheꢀHXTꢀoscillatorꢀisꢀselectedꢀasꢀtheꢀNORMALꢀModeꢀsystemꢀclockꢀandꢀtheꢀFastꢀWake-upꢀfunctionꢀ
isꢀenabled,ꢀthenꢀitꢀwillꢀtakeꢀoneꢀtoꢀtwoꢀtSUBꢀclockꢀcyclesꢀofꢀtheꢀLIRCꢀorꢀLXTꢀoscillatorꢀforꢀtheꢀsystemꢀ
toꢀwake-up.ꢀTheꢀsystemꢀwillꢀthenꢀinitiallyꢀrunꢀunderꢀtheꢀfSUBꢀclockꢀsourceꢀuntilꢀ1024ꢀHXTꢀclockꢀ
cyclesꢀhaveꢀelapsed,ꢀatꢀwhichꢀpointꢀtheꢀHTOꢀflagꢀwillꢀswitchꢀhighꢀandꢀtheꢀsystemꢀwillꢀswitchꢀoverꢀtoꢀ
operatingꢀfromꢀtheꢀHXTꢀoscillator.
IfꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀisꢀusedꢀasꢀtheꢀsystemꢀoscillatorꢀthenꢀitꢀwillꢀtakeꢀ1024ꢀclockꢀcyclesꢀofꢀ
theꢀLXTꢀoscillatorꢀorꢀ1~2ꢀcyclesꢀofꢀtheꢀLIRCꢀoscillatorꢀtoꢀwakeꢀupꢀtheꢀsystemꢀfromꢀtheꢀSLEEPꢀorꢀ
IDLE0ꢀMode.ꢀTheꢀFastꢀWake-upꢀbit,ꢀFSTENꢀwillꢀhaveꢀnoꢀeffectꢀinꢀtheseꢀcases.
System FSTEN Wake-up Time
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
Oscillator
Bit
(SLEEP0 Mode)
0
10ꢁ4 HXT cꢀcles 10ꢁ4 HXT cꢀcles
1~ꢁ fSUB cꢀcles
1~ꢁ HXT cꢀcles
HXT
(System runs first with fSUB for 10ꢁ4 HXT
cꢀcles and then switches over to run with
the HXT clock)
1
10ꢁ4 HXT cꢀcles
1~ꢁ HXT cꢀcles
LIRC
LXT
x
x
1~ꢁ LIRC cꢀcles 1~ꢁ LIRC cꢀcles
10ꢁ4 LXT cꢀcles 10ꢁ4 LXT cꢀcles
1~ꢁ LIRC cꢀcles
1~ꢁ LXT cꢀcles
“x”: don’t care
Wake-up Times
NoteꢀthatꢀifꢀtheꢀWatchdogꢀTimerꢀisꢀdisabled,ꢀwhichꢀmeansꢀthatꢀtheꢀLIRCꢀorꢀLXTꢀoscillatorꢀisꢀoff,ꢀ
thenꢀthereꢀwillꢀbeꢀnoꢀFastꢀWake-upꢀfunctionꢀavailableꢀwhenꢀtheꢀdevicesꢀwake-upꢀfromꢀtheꢀSLEEP0ꢀ
Mode.
Rev. 1.40
55
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Operating Mode Switching
Theꢀdevicesꢀcanꢀswitchꢀbetweenꢀoperatingꢀmodesꢀdynamicallyꢀallowingꢀtheꢀuserꢀtoꢀselectꢀtheꢀbestꢀ
performance/powerꢀratioꢀforꢀtheꢀpresentꢀtaskꢀinꢀhand.ꢀInꢀthisꢀwayꢀmicrocontrollerꢀoperationsꢀthatꢀ
doꢀnotꢀrequireꢀhighꢀperformanceꢀcanꢀbeꢀexecutedꢀusingꢀslowerꢀclocksꢀthusꢀrequiringꢀlessꢀoperatingꢀ
currentꢀandꢀprolongingꢀbatteryꢀlifeꢀinꢀportableꢀapplications.
Inꢀsimpleꢀterms,ꢀModeꢀSwitchingꢀbetweenꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀModeꢀisꢀexecutedꢀ
usingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀwhileꢀModeꢀSwitchingꢀfromꢀtheꢀ
NORMAL/SLOWꢀModesꢀtoꢀtheꢀSLEEP/IDLEꢀModesꢀisꢀexecutedꢀviaꢀtheꢀHALTꢀinstruction.ꢀWhenꢀ
aꢀHALTꢀinstructionꢀisꢀexecuted,ꢀwhetherꢀtheꢀdevicesꢀenterꢀtheꢀIDLEꢀModeꢀorꢀtheꢀSLEEPꢀModeꢀisꢀ
determinedꢀbyꢀtheꢀconditionꢀofꢀtheꢀIDLENꢀbitꢀinꢀtheꢀSMODꢀregisterꢀandꢀFSYSONꢀinꢀtheꢀWDTCꢀ
register.
WhenꢀtheꢀHLCLKꢀbitꢀswitchesꢀtoꢀaꢀlowꢀlevel,ꢀwhichꢀimpliesꢀthatꢀclockꢀsourceꢀisꢀswitchedꢀfromꢀtheꢀ
highꢀspeedꢀclockꢀsource,ꢀfH,ꢀtoꢀtheꢀclockꢀsource,ꢀfH/2~fH/64ꢀorꢀfL.ꢀIfꢀtheꢀclockꢀisꢀfromꢀtheꢀfL,ꢀtheꢀhighꢀ
speedꢀclockꢀsourceꢀwillꢀstopꢀrunningꢀtoꢀconserveꢀpower.ꢀWhenꢀthisꢀhappensꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀ
fH/16ꢀandꢀfH/64ꢀinternalꢀclockꢀsourcesꢀwillꢀalsoꢀstopꢀrunning,ꢀwhichꢀmayꢀaffectꢀtheꢀoperationꢀofꢀotherꢀ
internalꢀfunctionsꢀsuchꢀasꢀtheꢀTMsꢀandꢀtheꢀSIM.ꢀTheꢀaccompanyingꢀflowchartꢀshowsꢀwhatꢀhappensꢀ
whenꢀtheꢀdevicesꢀmoveꢀbetweenꢀtheꢀvariousꢀoperatingꢀmodes.
I
L
D
1
E
N
R
O
M
A
L
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
f
S
Y
=
S
H
~
f
H
/
f
4
6
C
P
s
U
o
t
p
f
H
o
n
I
L
D
N
E
1
=
C
P
r
U
n
u
F
Y
S
O
S
=
N
1
f
S
Y
S
o
n
f
S
Y
S
o
n
f
S
B
U
o
n
f
S
B
U
o
n
S
E
L
E
P
0
I
L
D
0
E
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
f
S
Y
o
S
f
f
C
P
s
U
o
t
p
C
P
s
U
o
t
p
I
L
D
N
E
1
=
I
L
D
N
E
0
=
F
Y
S
O
S
=
N
0
f
S
U
o
B
f
f
f
S
Y
S
o
f
f
W
T
D
&
L
V
D
o
f
f
f
S
B
U
o
n
S
E
L
E
P
1
S
O
L
W
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
f
S
Y
=
S
L
f
f
S
Y
S
o
f
f
f
S
Y
=
S
S
f
B
U
C
P
s
U
o
t
p
C
P
r
U
n
u
I
L
D
N
E
0
=
f
S
Y
S
o
n
f
S
B
U
o
n
f
S
B
U
o
n
W
T
D
o
r
L
V
D
o
n
f
H
o
f
f
Rev. 1.40
56
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
NORMAL Mode to SLOW Mode Switching
WhenꢀrunningꢀinꢀtheꢀNORMALꢀMode,ꢀwhichꢀusesꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀandꢀthereforeꢀ
consumesꢀmoreꢀpower,ꢀtheꢀsystemꢀclockꢀcanꢀswitchꢀtoꢀrunꢀinꢀtheꢀSLOWꢀModeꢀbyꢀsetꢀtheꢀHLCLKꢀ
bitꢀtoꢀ0ꢀandꢀsetꢀtheꢀCKS2~CKS0ꢀbitsꢀtoꢀ000Bꢀorꢀ001BꢀinꢀtheꢀSMODꢀregister.ꢀThisꢀwillꢀthenꢀuseꢀtheꢀ
lowꢀspeedꢀsystemꢀoscillatorꢀwhichꢀwillꢀconsumeꢀlessꢀpower.ꢀUsersꢀmayꢀdecideꢀtoꢀdoꢀthisꢀforꢀcertainꢀ
operationsꢀwhichꢀdoꢀnotꢀrequireꢀhighꢀperformanceꢀandꢀcanꢀsubsequentlyꢀreduceꢀpowerꢀconsumption.
TheꢀSLOWꢀModeꢀisꢀsourcedꢀfromꢀtheꢀLIRCꢀorꢀLXTꢀoscillatorꢀandꢀthereforeꢀrequiresꢀtheseꢀ
oscillatorsꢀtoꢀbeꢀstableꢀbeforeꢀfullꢀmodeꢀswitchingꢀoccurs.ꢀThisꢀisꢀmonitoredꢀusingꢀtheꢀLTOꢀbitꢀinꢀtheꢀ
SMODꢀregister.
SLOW Mode to NORMAL Mode Switching
InꢀSLOWꢀModeꢀtheꢀsystemꢀusesꢀtheꢀLIRCꢀorꢀLXTꢀlowꢀspeedꢀsystemꢀoscillator.ꢀToꢀswitchꢀbackꢀtoꢀ
theꢀNORMALꢀMode,ꢀwhereꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀused,ꢀtheꢀHLCLKꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ
1ꢀorꢀHLCLKꢀbitꢀisꢀ0ꢀbutꢀCKS2~CKS0ꢀisꢀsetꢀtoꢀ010B,ꢀ011B,ꢀ100B,ꢀ101B,ꢀ110Bꢀorꢀ111B.ꢀAsꢀaꢀcertainꢀ
amountꢀofꢀtimeꢀwillꢀbeꢀrequiredꢀforꢀtheꢀhighꢀfrequencyꢀclockꢀtoꢀstabilise,ꢀtheꢀstatusꢀofꢀtheꢀHTOꢀbitꢀ
isꢀchecked.ꢀTheꢀamountꢀofꢀtimeꢀrequiredꢀforꢀhighꢀspeedꢀsystemꢀoscillatorꢀstabilizationꢀdependsꢀuponꢀ
whichꢀhighꢀspeedꢀsystemꢀoscillatorꢀtypeꢀisꢀused.
N
O
A
R
L
M
M
o
d
e
C
H
S
K
2
~
K
C
0
S
=
0
0
B
&
x
L
K
C
=
0
L
S
O
L
W
M
o
d
e
W
T
D
a
n
L
V
d
D
a
r
e
a
l
o
l
f
f
I
H
L
D
N
E
=
0
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
S
L
E
E
M
o
P
e
d
0
W
T
D
o
r
L
V
D
s
i
o
n
I
H
L
D
N
E
=
0
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
S
L
E
E
M
o
P
e
d
1
I
L
D
N
E
=
1
,
F
S
Y
N
S
0
=
O
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
s
i
e
x
e
c
u
t
e
d
I
E
D
0
L
M
o
d
e
I
L
D
N
E
=
1
,
F
S
Y
N
S
1
=
O
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
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s
e
x
e
t
c
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u
I
L
D
E
M
1
o
d
e
Rev. 1.40
5ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
S
O
L
W
M
o
d
e
C
S
K
~
2
K
C
0
S
¹
0
0
B
0
,
0
0
B
1
a
s
H
L
C
=
L
0
K
o
r
H
L
L
C
=
K
1
N
O
A
R
L
M
M
o
d
e
W
T
D
a
n
L
V
d
D
a
e
r
a
l
o
l
f
f
I
H
L
D
N
E
=
0
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
S
L
E
E
M
o
P
e
d
0
W
T
D
o
r
L
V
D
i
s
o
n
I
H
L
D
N
E
=
0
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
S
L
E
E
M
o
P
e
d
1
I
L
D
N
E
=
1
,
F
S
Y
N
S
0
=
O
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
s
i
e
x
e
c
u
t
e
d
I
L
D
E
M
0
o
d
e
I
L
D
N
E
=
1
,
F
S
Y
N
S
1
=
O
H
L
A
T
n
i
t
s
u
r
t
c
o
i
n
i
s
e
x
e
t
c
d
e
u
I
L
D
E
M
1
o
d
e
Entering the SLEEP0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀSLEEP0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀHALTꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ0ꢀandꢀtheꢀ
WDTꢀandꢀLVDꢀbothꢀoff.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀ
followingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclock,ꢀWDTꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀ
willꢀstopꢀatꢀtheꢀHALTꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Rev. 1.40
58
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Entering the SLEEP1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀSLEEP1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀHALTꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ0ꢀandꢀtheꢀWDTꢀ
orꢀLVDꢀon.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀ
willꢀoccur:
•ꢀ TheꢀsystemꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀ
theꢀHALTꢀinstruction,ꢀbutꢀtheꢀWDTꢀorꢀLVDꢀwillꢀremainꢀwithꢀtheꢀclockꢀsourceꢀcomingꢀfromꢀtheꢀ
fSUBꢀclock.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀfunctionꢀisꢀenabled.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the IDLE0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀHALTꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ1ꢀandꢀ
theꢀFSYSONꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀequalꢀtoꢀ0.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀ
conditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ TheꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀHALTꢀinstruction,ꢀ
butꢀtheꢀTimeꢀBaseꢀclockꢀandꢀfSUBꢀclockꢀwillꢀbeꢀon.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀisꢀenabled.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the IDLE1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀIDLE1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀHALTꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ1ꢀandꢀ
theꢀFSYSONꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀequalꢀtoꢀ1.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀ
conditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclock,ꢀTimeꢀBaseꢀclockꢀandꢀfSUBꢀclockꢀwillꢀbeꢀonꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀ
stopꢀatꢀtheꢀHALTꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀisꢀenabled.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Rev. 1.40
59
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Standby Current Considerations
AsꢀtheꢀmainꢀreasonꢀforꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀtoꢀkeepꢀtheꢀcurrentꢀconsumptionꢀofꢀ
theꢀdevicesꢀtoꢀasꢀlowꢀaꢀvalueꢀasꢀpossible,ꢀperhapsꢀonlyꢀinꢀtheꢀorderꢀofꢀseveralꢀmicro-ampsꢀexceptꢀ
inꢀtheꢀIDLE1ꢀMode,ꢀthereꢀareꢀotherꢀconsiderationsꢀwhichꢀmustꢀalsoꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀtheꢀ
circuitꢀdesignerꢀifꢀtheꢀpowerꢀconsumptionꢀisꢀtoꢀbeꢀminimised.ꢀSpecialꢀattentionꢀmustꢀbeꢀmadeꢀtoꢀ
theꢀI/Oꢀpinsꢀonꢀtheꢀdevices.ꢀAllꢀhigh-impedanceꢀinputꢀpinsꢀmustꢀbeꢀconnectedꢀtoꢀeitherꢀaꢀfixedꢀ
highꢀorꢀlowꢀlevelꢀasꢀanyꢀfloatingꢀinputꢀpinsꢀcouldꢀcreateꢀinternalꢀoscillationsꢀandꢀresultꢀinꢀincreasedꢀ
currentꢀconsumption.ꢀThisꢀalsoꢀappliesꢀtoꢀdevicesꢀwhichꢀhaveꢀdifferentꢀpackageꢀtypes,ꢀasꢀthereꢀmayꢀ
beꢀunbonbedꢀpins.ꢀTheseꢀmustꢀeitherꢀbeꢀsetupꢀasꢀoutputsꢀorꢀifꢀsetupꢀasꢀinputsꢀmustꢀhaveꢀpull-highꢀ
resistorsꢀconnected.
Careꢀmustꢀalsoꢀbeꢀtakenꢀwithꢀtheꢀloads,ꢀwhichꢀareꢀconnectedꢀtoꢀI/Oꢀpins,ꢀwhichꢀareꢀsetupꢀasꢀoutputs.ꢀ
Theseꢀshouldꢀbeꢀplacedꢀinꢀaꢀconditionꢀinꢀwhichꢀminimumꢀcurrentꢀisꢀdrawnꢀorꢀconnectedꢀonlyꢀtoꢀ
externalꢀcircuitsꢀthatꢀdoꢀnotꢀdrawꢀcurrent,ꢀsuchꢀasꢀotherꢀCMOSꢀinputs.ꢀAlsoꢀnoteꢀthatꢀadditionalꢀ
standbyꢀcurrentꢀwillꢀalsoꢀbeꢀrequiredꢀifꢀtheꢀconfigurationꢀoptionsꢀhaveꢀenabledꢀtheꢀLIRCꢀoscillator.
InꢀtheꢀIDLE1ꢀModeꢀtheꢀsystemꢀoscillatorꢀisꢀon,ꢀifꢀtheꢀsystemꢀoscillatorꢀisꢀfromꢀtheꢀhighꢀspeedꢀ
systemꢀoscillator,ꢀtheꢀadditionalꢀstandbyꢀcurrentꢀwillꢀalsoꢀbeꢀperhapsꢀinꢀtheꢀorderꢀofꢀseveralꢀhundredꢀ
micro-amps.
Wake-up
AfterꢀtheꢀsystemꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀitꢀcanꢀbeꢀwokenꢀupꢀfromꢀoneꢀofꢀvariousꢀsourcesꢀ
listedꢀasꢀfollows:
•ꢀ Anꢀexternalꢀreset
•ꢀ AnꢀexternalꢀfallingꢀedgeꢀonꢀPortꢀA
•ꢀ Aꢀsystemꢀinterrupt
•ꢀ AꢀWDTꢀoverflow
Ifꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀexternalꢀreset,ꢀtheꢀdevicesꢀwillꢀexperienceꢀaꢀfullꢀsystemꢀreset,ꢀ
however,ꢀifꢀtheꢀdevicesꢀareꢀwokenꢀupꢀbyꢀaꢀWDTꢀoverflow,ꢀaꢀWatchdogꢀTimerꢀresetꢀwillꢀbeꢀinitiated.ꢀ
Althoughꢀbothꢀofꢀtheseꢀwake-upꢀmethodsꢀwillꢀinitiateꢀaꢀresetꢀoperation,ꢀtheꢀactualꢀsourceꢀofꢀtheꢀ
wake-upꢀcanꢀbeꢀdeterminedꢀbyꢀexaminingꢀtheꢀTOꢀandꢀPDFꢀflags.ꢀTheꢀPDFꢀflagꢀisꢀclearedꢀbyꢀaꢀ
systemꢀpower-upꢀorꢀexecutingꢀtheꢀclearꢀWatchdogꢀTimerꢀinstructionsꢀandꢀisꢀsetꢀwhenꢀexecutingꢀtheꢀ
HALTꢀinstruction.ꢀTheꢀTOꢀflagꢀisꢀsetꢀifꢀaꢀWDTꢀtime-outꢀoccurs,ꢀandꢀcausesꢀaꢀwake-upꢀthatꢀonlyꢀ
resetsꢀtheꢀProgramꢀCounterꢀandꢀStackꢀPointer,ꢀtheꢀotherꢀflagsꢀremainꢀinꢀtheirꢀoriginalꢀstatus.
EachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀusingꢀtheꢀPAWUꢀregisterꢀtoꢀpermitꢀaꢀnegativeꢀtransitionꢀonꢀtheꢀpinꢀ
toꢀwake-upꢀtheꢀsystem.ꢀWhenꢀaꢀPortꢀAꢀpinꢀwake-upꢀoccurs,ꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀ
theꢀinstructionꢀfollowingꢀtheꢀHALTꢀinstruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀinterrupt,ꢀthenꢀtwoꢀ
possibleꢀsituationsꢀmayꢀoccur.ꢀTheꢀfirstꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀdisabledꢀorꢀtheꢀinterruptꢀ
isꢀenabledꢀbutꢀtheꢀstackꢀisꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀtheꢀinstructionꢀ
followingꢀtheꢀHALTꢀinstruction.ꢀInꢀthisꢀsituation,ꢀtheꢀinterruptꢀwhichꢀwoke-upꢀtheꢀdevicesꢀwillꢀnotꢀ
beꢀimmediatelyꢀserviced,ꢀbutꢀwillꢀratherꢀbeꢀservicedꢀlaterꢀwhenꢀtheꢀrelatedꢀinterruptꢀisꢀfinallyꢀenabledꢀ
orꢀwhenꢀaꢀstackꢀlevelꢀbecomesꢀfree.ꢀTheꢀotherꢀsituationꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀenabledꢀandꢀ
theꢀstackꢀisꢀnotꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀregularꢀinterruptꢀresponseꢀtakesꢀplace.ꢀIfꢀanꢀinterruptꢀrequestꢀ
flagꢀisꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀwake-upꢀfunctionꢀofꢀtheꢀrelatedꢀ
interruptꢀwillꢀbeꢀdisabled.
Rev. 1.40
60
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Programming Considerations
TheꢀhighꢀspeedꢀandꢀlowꢀspeedꢀoscillatorsꢀbothꢀuseꢀtheꢀsameꢀSSTꢀcounter.ꢀForꢀexample,ꢀifꢀtheꢀsystemꢀ
isꢀwokenꢀupꢀfromꢀtheꢀSLEEP0ꢀModeꢀandꢀbothꢀtheꢀHXTꢀandꢀLXTꢀoscillatorsꢀneedꢀtoꢀstart-upꢀfromꢀanꢀ
offꢀstate.ꢀTheꢀLXTꢀoscillatorꢀusesꢀtheꢀSSTꢀcounterꢀafterꢀHXTꢀoscillatorꢀhasꢀfinishedꢀitsꢀSSTꢀperiod.
•ꢀ IfꢀtheꢀdevicesꢀareꢀwokenꢀupꢀfromꢀtheꢀSLEEP0ꢀModeꢀtoꢀtheꢀNORMALꢀMode,ꢀtheꢀhighꢀspeedꢀ
systemꢀoscillatorꢀneedsꢀanꢀSSTꢀperiod.ꢀTheꢀdevicesꢀwillꢀexecuteꢀfirstꢀinstructionꢀafterꢀHTOꢀ
isꢀ“1”.ꢀAtꢀthisꢀtime,ꢀtheꢀLXTꢀoscillatorꢀmayꢀnotꢀbeꢀstableꢀifꢀfSUBꢀisꢀfromꢀLXTꢀoscillator.ꢀTheꢀ
sameꢀsituationꢀoccursꢀinꢀtheꢀpower-onꢀstate.ꢀTheꢀLXTꢀoscillatorꢀisꢀnotꢀreadyꢀyetꢀwhenꢀtheꢀfirstꢀ
instructionꢀisꢀexecuted.
•ꢀ IfꢀtheꢀdevicesꢀareꢀwokenꢀupꢀfromꢀtheꢀSLEEP1ꢀModeꢀtoꢀNORMALꢀMode,ꢀandꢀtheꢀsystemꢀclockꢀ
sourceꢀisꢀfromꢀtheꢀHXTꢀoscillatorꢀandꢀFSTENꢀisꢀ1,ꢀtheꢀsystemꢀclockꢀcanꢀfirstꢀbeꢀswitchedꢀtoꢀtheꢀ
fSUBꢀclockꢀafterꢀwakeꢀup.
•ꢀ Thereꢀareꢀperipheralꢀfunctions,ꢀsuchꢀasꢀWDTꢀandꢀTMs,ꢀforꢀwhichꢀtheꢀfSYSꢀisꢀused.ꢀIfꢀtheꢀsystemꢀ
clockꢀsourceꢀisꢀswitchedꢀfromꢀfHꢀtoꢀfSUB,ꢀtheꢀclockꢀsourceꢀtoꢀtheꢀperipheralꢀfunctionsꢀmentionedꢀ
aboveꢀwillꢀchangeꢀaccordingly.
•ꢀ Theꢀon/offꢀconditionꢀofꢀfSUBꢀdependsꢀuponꢀwhetherꢀtheꢀWDTꢀorꢀLVDꢀfunctionꢀisꢀenabledꢀorꢀ
disabledꢀasꢀtheꢀWDTꢀclockꢀsourceꢀisꢀselectedꢀfromꢀfSUB
.
Watchdog Timer
TheꢀWatchdogꢀTimerꢀisꢀprovidedꢀtoꢀpreventꢀprogramꢀmalfunctionsꢀorꢀsequencesꢀfromꢀjumpingꢀtoꢀ
unknownꢀlocations,ꢀdueꢀtoꢀcertainꢀuncontrollableꢀexternalꢀeventsꢀsuchꢀasꢀelectricalꢀnoise.
Watchdog Timer Clock Source
TheꢀWatchdogꢀTimerꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀtheꢀinternalꢀclock,ꢀfSUB.ꢀTheꢀfSUBꢀclockꢀcanꢀbeꢀ
sourcedꢀfromꢀeitherꢀtheꢀLIRCꢀorꢀLXTꢀoscillatorꢀselectedꢀbyꢀaꢀconfigurationꢀoption.ꢀTheꢀLIRCꢀ
internalꢀoscillatorꢀhasꢀanꢀapproximateꢀperiodꢀofꢀ32kHzꢀatꢀaꢀsupplyꢀvoltageꢀofꢀ5V.ꢀHowever,ꢀitꢀ
shouldꢀbeꢀnotedꢀthatꢀthisꢀspecifiedꢀinternalꢀclockꢀperiodꢀcanꢀvaryꢀwithꢀVDD,ꢀtemperatureꢀandꢀprocessꢀ
variations.ꢀTheꢀLXTꢀoscillatorꢀusꢀsuppliedꢀbyꢀanꢀexternalꢀ32.768kHzꢀcrystal.ꢀTheꢀWatchdogꢀTimerꢀ
sourceꢀclockꢀisꢀthenꢀsubdividedꢀbyꢀaꢀratioꢀofꢀ28ꢀtoꢀ218ꢀtoꢀgiveꢀlongerꢀtimeouts,ꢀtheꢀactualꢀvalueꢀbeingꢀ
chosenꢀusingꢀtheꢀWS2~WS0ꢀbitsꢀinꢀtheꢀWDTCꢀregister.
Watchdog Timer Control Register
Aꢀsingleꢀregister,ꢀWDTC,ꢀcontrolsꢀtheꢀrequiredꢀtimeoutꢀperiodꢀasꢀwellꢀasꢀtheꢀenable/disableꢀ
operation.ꢀThisꢀregisterꢀtogetherꢀwithꢀseveralꢀconfigurationꢀoptionsꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀ
theꢀWatchdogꢀTimer.
Rev. 1.40
61
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
WDTC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
WE4
R/W
0
WE3
R/W
1
WEꢁ
R/W
0
WE1
R/W
1
WE0
R/W
0
WSꢁ
R/W
0
WS1
R/W
1
WS0
R/W
1
POR
Bitꢀ7~3
WE4~WE0:ꢀWDTꢀFunctionꢀEnableꢀcontrol
10101:ꢀDisabled
01010:ꢀEnable
OtherꢀValue:ꢀResetꢀMCU
Ifꢀtheseꢀbitsꢀareꢀchangedꢀdueꢀtoꢀadverseꢀenvironmentalꢀconditions,ꢀtheꢀmicrocontrollerꢀ
willꢀbeꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀ2~3ꢀfSUBꢀclockꢀcyclesꢀandꢀtheꢀ
WRFꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ1
Bitꢀ2~0
WS2~WS0:ꢀWDTꢀTime-outꢀperiodꢀselection
000:ꢀ28/fS
001:ꢀ210/fS
010:ꢀ212/fS
011:ꢀ214/fS
100:ꢀ215/fS
101:ꢀ216/fS
110:ꢀ217/fS
111:ꢀ218/fS
TheseꢀthreeꢀbitsꢀdetermineꢀtheꢀdivisionꢀratioꢀofꢀtheꢀWatchdogꢀTimerꢀsourceꢀclock,ꢀ
whichꢀinꢀturnꢀdeterminesꢀtheꢀtimeoutꢀperiod.
CTRL0 Register
Bit
7
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
Name
R/W
FSYSON
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
0
R/W
POR
0
“x”: unknown
Bitꢀ7
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
Describedꢀelsewhere
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
Describedꢀelsewhere
Bitꢀ1
Bitꢀ0
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
Describedꢀelsewhere
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ
program.
Rev. 1.40
6ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Watchdog Timer Operation
TheꢀWatchdogꢀTimerꢀoperatesꢀbyꢀprovidingꢀaꢀdeviceꢀresetꢀwhenꢀitsꢀtimerꢀoverflows.ꢀThisꢀmeansꢀ
thatꢀinꢀtheꢀapplicationꢀprogramꢀandꢀduringꢀnormalꢀoperationꢀtheꢀuserꢀhasꢀtoꢀstrategicallyꢀclearꢀtheꢀ
WatchdogꢀTimerꢀbeforeꢀitꢀoverflowsꢀtoꢀpreventꢀtheꢀWatchdogꢀTimerꢀfromꢀexecutingꢀaꢀreset.ꢀThisꢀisꢀ
doneꢀusingꢀtheꢀclearꢀwatchdogꢀinstructions.ꢀIfꢀtheꢀprogramꢀmalfunctionsꢀforꢀwhateverꢀreason,ꢀjumpsꢀ
toꢀanꢀunknownꢀlocation,ꢀorꢀentersꢀanꢀendlessꢀloop,ꢀtheseꢀclearꢀinstructionsꢀwillꢀnotꢀbeꢀexecutedꢀinꢀtheꢀ
correctꢀmanner,ꢀinꢀwhichꢀcaseꢀtheꢀWatchdogꢀTimerꢀwillꢀoverflowꢀandꢀresetꢀtheꢀdevice.ꢀWithꢀregardꢀtoꢀ
theꢀWatchdogꢀTimerꢀenable/disableꢀfunction,ꢀthereꢀareꢀfiveꢀbits,ꢀWE4~WE0,ꢀinꢀtheꢀWDTCꢀregisterꢀ
toꢀofferꢀtheꢀenable/disableꢀcontrolꢀandꢀresetꢀcontrolꢀofꢀtheꢀWatchdogꢀTimer.ꢀTheꢀWDTꢀfunctionꢀwillꢀ
beꢀdisabledꢀwhenꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀaꢀvalueꢀofꢀ10101BꢀwhileꢀtheꢀWDTꢀfunctionꢀwillꢀ
beꢀenabledꢀifꢀtheꢀWE4~WE0ꢀbitsꢀareꢀequalꢀtoꢀ01010B.ꢀIfꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀanyꢀotherꢀ
values,ꢀotherꢀthanꢀ01010Bꢀandꢀ10101B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀAfterꢀ
powerꢀonꢀtheseꢀbitsꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010B.
WDT Function Control
WE4~WE0 Bits
10101B
WDT Function
Disable
Application Program Enabled
01010B
Enable
Anꢀ other value
Reset �CU
Watchdog Timer Enable/Disable Control
Underꢀnormalꢀprogramꢀoperation,ꢀaꢀWatchdogꢀTimerꢀtime-outꢀwillꢀinitialiseꢀaꢀdeviceꢀresetꢀandꢀsetꢀ
theꢀstatusꢀbitꢀTO.ꢀHowever,ꢀifꢀtheꢀsystemꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀwhenꢀaꢀWatchdogꢀTimerꢀ
time-outꢀoccurs,ꢀtheꢀTOꢀbitꢀinꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀsetꢀandꢀonlyꢀtheꢀProgramꢀCounterꢀandꢀStackꢀ
Pointerꢀwillꢀbeꢀreset.ꢀThreeꢀmethodsꢀcanꢀbeꢀadoptedꢀtoꢀclearꢀtheꢀcontentsꢀofꢀtheꢀWatchdogꢀTimer.ꢀ
TheꢀfirstꢀisꢀaꢀWDTꢀreset,ꢀwhichꢀmeansꢀaꢀcertainꢀvalueꢀexceptꢀ01010Bꢀandꢀ10101Bꢀwrittenꢀintoꢀtheꢀ
WE4~WE0ꢀbitꢀfiled,ꢀtheꢀsecondꢀisꢀusingꢀtheꢀWatchdogꢀTimerꢀsoftwareꢀclearꢀinstructionsꢀandꢀtheꢀ
thirdꢀisꢀviaꢀaꢀHALTꢀinstruction.
ThereꢀisꢀonlyꢀoneꢀmethodꢀofꢀusingꢀsoftwareꢀinstructionꢀtoꢀclearꢀtheꢀWatchdogꢀTimer.ꢀThatꢀisꢀtoꢀuseꢀ
theꢀsingleꢀ"CLRꢀWDT"ꢀinstructionꢀtoꢀclearꢀtheꢀWDT.
WDTC Register WE4~WE0 bits
Reset �CU
CLR
“CLR WDT”Instruction
fS/ꢁ8
�
U
X
LXT
fSUB
8-stage Divider
WSꢁ~WS0
WDT Prescaler
LIRC
fSUB Clock
Configuration option
8-to-1 �UX
WDT Time-out
(ꢁ8/fS ~ ꢁ18/fS)
(fS/ꢁ8 ~ fS/ꢁ18
)
Watchdog Timer
Rev. 1.40
63
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Reset and Initialisation
Aꢀresetꢀfunctionꢀisꢀaꢀfundamentalꢀpartꢀofꢀanyꢀmicrocontrollerꢀensuringꢀthatꢀtheꢀdeviceꢀcanꢀbeꢀsetꢀ
toꢀsomeꢀpredeterminedꢀconditionꢀirrespectiveꢀofꢀoutsideꢀparameters.ꢀTheꢀmostꢀimportantꢀresetꢀ
conditionꢀisꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀtheꢀmicrocontroller.ꢀInꢀthisꢀcase,ꢀinternalꢀcircuitryꢀwillꢀ
ensureꢀthatꢀtheꢀmicrocontroller,ꢀafterꢀaꢀshortꢀdelay,ꢀwillꢀbeꢀinꢀaꢀwellꢀdefinedꢀstateꢀandꢀreadyꢀtoꢀ
executeꢀtheꢀfirstꢀprogramꢀinstruction.ꢀAfterꢀthisꢀpower-onꢀreset,ꢀcertainꢀimportantꢀinternalꢀregistersꢀ
willꢀbeꢀsetꢀtoꢀdefinedꢀstatesꢀbeforeꢀtheꢀprogramꢀcommences.ꢀOneꢀofꢀtheseꢀregistersꢀisꢀtheꢀProgramꢀ
Counter,ꢀwhichꢀwillꢀbeꢀresetꢀtoꢀzeroꢀforcingꢀtheꢀmicrocontrollerꢀtoꢀbeginꢀprogramꢀexecutionꢀfromꢀtheꢀ
lowestꢀProgramꢀMemoryꢀaddress.
Inꢀadditionꢀtoꢀtheꢀpower-onꢀreset,ꢀsituationsꢀmayꢀariseꢀwhereꢀitꢀisꢀnecessaryꢀtoꢀforcefullyꢀapplyꢀ
aꢀresetꢀconditionꢀwhenꢀtheꢀmicrocontrollerꢀisꢀrunning.ꢀOneꢀexampleꢀofꢀthisꢀisꢀwhereꢀafterꢀpowerꢀ
hasꢀbeenꢀappliedꢀandꢀtheꢀmicrocontrollerꢀisꢀalreadyꢀrunning,ꢀtheꢀRESꢀlineꢀisꢀforcefullyꢀpulledꢀlow.ꢀ
Inꢀsuchꢀaꢀcase,ꢀknownꢀasꢀaꢀnormalꢀoperationꢀreset,ꢀsomeꢀofꢀtheꢀmicrocontrollerꢀregistersꢀremainꢀ
unchangedꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀprecedeꢀwithꢀnormalꢀoperationꢀafterꢀtheꢀresetꢀlineꢀisꢀ
allowedꢀtoꢀreturnꢀhigh.
AnotherꢀtypeꢀofꢀresetꢀisꢀwhenꢀtheꢀWatchdogꢀTimerꢀoverflowsꢀandꢀresetsꢀtheꢀmicrocontroller.ꢀAllꢀ
typesꢀofꢀresetꢀoperationsꢀresultꢀinꢀdifferentꢀregisterꢀconditionsꢀbeingꢀsetup.ꢀAnotherꢀresetꢀexistsꢀinꢀ
theꢀformꢀofꢀaꢀLowꢀVoltageꢀReset,ꢀLVR,ꢀwhereꢀaꢀfullꢀreset,ꢀsimilarꢀtoꢀtheꢀRESꢀresetꢀisꢀimplementedꢀinꢀ
situationsꢀwhereꢀtheꢀpowerꢀsupplyꢀvoltageꢀfallsꢀbelowꢀaꢀcertainꢀthreshold.
Reset Functions
Thereꢀareꢀfiveꢀwaysꢀinꢀwhichꢀaꢀmicrocontrollerꢀresetꢀcanꢀoccur,ꢀthroughꢀeventsꢀoccurringꢀbothꢀ
internallyꢀandꢀexternally:
Power-on Reset
Theꢀmostꢀfundamentalꢀandꢀunavoidableꢀresetꢀisꢀtheꢀoneꢀthatꢀoccursꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀ
theꢀmicrocontroller.ꢀAsꢀwellꢀasꢀensuringꢀthatꢀtheꢀProgramꢀMemoryꢀbeginsꢀexecutionꢀfromꢀtheꢀfirstꢀ
memoryꢀaddress,ꢀaꢀpower-onꢀresetꢀalsoꢀensuresꢀthatꢀcertainꢀotherꢀregistersꢀareꢀpresetꢀtoꢀknownꢀ
conditions.ꢀAllꢀtheꢀI/Oꢀportꢀandꢀportꢀcontrolꢀregistersꢀwillꢀpowerꢀupꢀinꢀaꢀhighꢀconditionꢀensuringꢀthatꢀ
allꢀpinsꢀwillꢀbeꢀfirstꢀsetꢀtoꢀinputs.
V
D
D
0
.
V
D
9
D
R
S
E
t
t
R
R
T
T
S
S
D
D
+
+
t
t
S
S
S
S
T
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=50ms
Power-on Reset Timing Chart
RES Pin Reset
AsꢀtheꢀresetꢀpinꢀisꢀsharedꢀwithꢀPB2,ꢀtheꢀresetꢀfunctionꢀmustꢀbeꢀselectedꢀusingꢀaꢀconfigurationꢀ
option.ꢀAlthoughꢀtheꢀmicrocontrollerꢀhasꢀanꢀinternalꢀRCꢀresetꢀfunction,ꢀifꢀtheꢀVDDꢀpowerꢀsupplyꢀ
riseꢀtimeꢀisꢀnotꢀfastꢀenoughꢀorꢀdoesꢀnotꢀstabiliseꢀquicklyꢀatꢀpower-on,ꢀtheꢀinternalꢀresetꢀfunctionꢀ
mayꢀbeꢀincapableꢀofꢀprovidingꢀproperꢀresetꢀoperation.ꢀForꢀthisꢀreasonꢀitꢀisꢀrecommendedꢀthatꢀanꢀ
externalꢀRCꢀnetworkꢀisꢀconnectedꢀtoꢀtheꢀRESꢀpin,ꢀwhoseꢀadditionalꢀtimeꢀdelayꢀwillꢀensureꢀthatꢀtheꢀ
RESꢀpinꢀremainsꢀlowꢀforꢀanꢀextendedꢀperiodꢀtoꢀallowꢀtheꢀpowerꢀsupplyꢀtoꢀstabilise.ꢀDuringꢀthisꢀtimeꢀ
delay,ꢀnormalꢀoperationꢀofꢀtheꢀmicrocontrollerꢀwillꢀbeꢀinhibited.ꢀAfterꢀtheꢀRESꢀlineꢀreachesꢀaꢀcertainꢀ
voltageꢀvalue,ꢀtheꢀresetꢀdelayꢀtimeꢀtRSTDꢀisꢀinvokedꢀtoꢀprovideꢀanꢀextraꢀdelayꢀtimeꢀafterꢀwhichꢀtheꢀ
microcontrollerꢀwillꢀbeginꢀnormalꢀoperation.ꢀTheꢀabbreviationꢀSSTꢀinꢀtheꢀfiguresꢀstandsꢀforꢀSystemꢀ
Rev. 1.40
64
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Start-upꢀTimer.ꢀForꢀmostꢀapplicationsꢀaꢀresistorꢀconnectedꢀbetweenꢀVDDꢀandꢀtheꢀRESꢀpinꢀandꢀaꢀ
capacitorꢀconnectedꢀbetweenꢀVSSꢀandꢀtheꢀRESꢀpinꢀwillꢀprovideꢀaꢀsuitableꢀexternalꢀresetꢀcircuit.ꢀAnyꢀ
wiringꢀconnectedꢀtoꢀtheꢀRESꢀpinꢀshouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossibleꢀtoꢀminimiseꢀanyꢀstrayꢀnoiseꢀ
interference.ꢀForꢀapplicationsꢀthatꢀoperateꢀwithinꢀanꢀenvironmentꢀwhereꢀmoreꢀnoiseꢀisꢀpresentꢀtheꢀ
EnhancedꢀResetꢀCircuitꢀshownꢀisꢀrecommended.
V
D
D
0
.
m
0
F
*
1
*
V
D
D
1
4
N
1
*
4
8
1
k
0
W
~
1
0
W
0
k
R
S
E
/
2
P
B
3
0
0
W
*
0
.
1
1
F
~
V
S
S
Note:ꢀ“*”ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀESDꢀprotection.ꢀ
ꢀꢀꢀꢀꢀ“**”ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀinꢀenvironmentsꢀwhereꢀ
powerꢀlineꢀnoiseꢀisꢀsignificant.
External RES Circuit
MoreꢀinformationꢀregardingꢀexternalꢀresetꢀcircuitsꢀisꢀlocatedꢀinꢀApplicationꢀNoteꢀHA0075Eꢀonꢀtheꢀ
Holtekꢀwebsite.
PullingꢀtheꢀRESꢀPinꢀlowꢀusingꢀexternalꢀhardwareꢀwillꢀalsoꢀexecuteꢀaꢀdeviceꢀreset.ꢀInꢀthisꢀcase,ꢀasꢀinꢀ
theꢀcaseꢀofꢀotherꢀresets,ꢀtheꢀProgramꢀCounterꢀwillꢀresetꢀtoꢀzeroꢀandꢀprogramꢀexecutionꢀinitiatedꢀfromꢀ
thisꢀpoint.
0
.
V
D
9
D
0
.
V
D
4
D
R
S
E
t
R
T
S
D
+
t
S
S
T
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms
RES Reset Timing Chart
Whenꢀtheꢀresetꢀpinꢀisꢀdrivenꢀlowꢀbyꢀexternalꢀhardware,ꢀmostꢀofꢀtheꢀmicrocontrollerꢀpinsꢀwillꢀbeꢀ
forcedꢀintoꢀaꢀhighꢀimpedanceꢀcondition.ꢀHoweverꢀspecialꢀattentionꢀmustꢀbeꢀmadeꢀtoꢀtheꢀPA2/CX/
AN2ꢀasꢀtheꢀpinꢀwillꢀbeꢀforcedꢀintoꢀaꢀlogicalꢀoutputꢀlowꢀconditionꢀwhenꢀtheꢀresetꢀpinꢀisꢀheldꢀlow.ꢀ
Forꢀthisꢀreasonꢀitꢀisꢀrecommendedꢀthatꢀtheꢀpinꢀisꢀnotꢀconnectedꢀtoꢀlowꢀimpedanceꢀsourceꢀinꢀtheꢀ
applicationꢀcircuitꢀtoꢀeliminateꢀtheꢀpossibilityꢀofꢀtheꢀlowꢀimpedanceꢀbeingꢀconnectedꢀtogether.ꢀThisꢀ
situationꢀonlyꢀoccursꢀwhenꢀtheꢀresetꢀpinꢀisꢀpulledꢀlowꢀbyꢀexternalꢀhardwareꢀandꢀnotꢀduringꢀaꢀpowerꢀ
onꢀorꢀotherꢀresetꢀtype.
Pin Name
PAꢁ/CX/ANꢁ
Other pins
Pin Status
Output Low
High Impedance
Reset Pin Forced Low – Pin Status
Rev. 1.40
65
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Low Voltage Reset – LVR
Theꢀmicrocontrollerꢀcontainsꢀaꢀlowꢀvoltageꢀresetꢀcircuitꢀinꢀorderꢀtoꢀmonitorꢀtheꢀsupplyꢀvoltageꢀofꢀtheꢀ
device.ꢀTheꢀLVRꢀfunctionꢀisꢀalwaysꢀenabledꢀwithꢀaꢀspecificꢀLVRꢀvoltage,ꢀVLVR.ꢀIfꢀtheꢀsupplyꢀvoltageꢀ
ofꢀtheꢀdeviceꢀdropsꢀtoꢀwithinꢀaꢀrangeꢀofꢀ0.9V~VLVRꢀsuchꢀasꢀmightꢀoccurꢀwhenꢀchangingꢀtheꢀbattery,ꢀ
theꢀLVRꢀwillꢀautomaticallyꢀresetꢀtheꢀdeviceꢀinternallyꢀandꢀtheꢀLVRFꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀwillꢀ
alsoꢀbeꢀsetꢀtoꢀ1.ꢀForꢀaꢀvalidꢀLVRꢀsignal,ꢀaꢀlowꢀsupplyꢀvoltage,ꢀi.e.,ꢀaꢀvoltageꢀinꢀtheꢀrangeꢀbetweenꢀ
0.9V~VLVRꢀmustꢀexistꢀforꢀaꢀtimeꢀgreaterꢀthanꢀthatꢀspecifiedꢀbyꢀtLVRꢀinꢀtheꢀA.C.ꢀcharacteristics.ꢀIfꢀtheꢀ
lowꢀsupplyꢀvoltageꢀstateꢀdoesꢀnotꢀexceedꢀthisꢀvalue,ꢀtheꢀLVRꢀwillꢀignoreꢀtheꢀlowꢀsupplyꢀvoltageꢀandꢀ
willꢀnotꢀperformꢀaꢀresetꢀfunction.ꢀTheꢀactualꢀVLVRꢀvalueꢀcanꢀbeꢀselectedꢀbyꢀtheꢀLVSꢀbitsꢀinꢀtheꢀLVRCꢀ
register.ꢀIfꢀtheꢀLVS7~LVS0ꢀbitsꢀhaveꢀanyꢀotherꢀvalue,ꢀwhichꢀmayꢀperhapsꢀoccurꢀdueꢀtoꢀadverseꢀ
environmentalꢀconditionsꢀsuchꢀasꢀnoise,ꢀtheꢀLVRꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀ
Whenꢀthisꢀhappens,ꢀtheꢀLRFꢀbitꢀinꢀtheꢀCTRL0ꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ1.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀ
willꢀhaveꢀtheꢀvalueꢀofꢀ01010101B.ꢀNoteꢀthatꢀtheꢀLVRꢀfunctionꢀwillꢀbeꢀautomaticallyꢀdisabledꢀwhenꢀ
theꢀdeviceꢀentersꢀtheꢀpowerꢀdownꢀmode.
L
R
V
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms
Low Voltage Reset Timing Chart
•ꢀ LVRCꢀRegister
Bit
Name
R/W
7
LVSꢃ
R/W
0
6
5
LVS5
R/W
0
4
LVS4
R/W
1
3
LVS3
R/w
0
2
LVSꢁ
R/w
1
1
LVS1
R/W
0
0
LVS0
R/W
1
LVS6
R/W
1
POR
Bitꢀ7~0
LVS7~LVS0:ꢀLVRꢀvoltageꢀselect
01010101:ꢀ2.1V
00110011:ꢀ2.55V
10011001:ꢀ3.15V
10101010:ꢀ3.8V
Anyꢀotherꢀvalues:ꢀGeneratesꢀMCUꢀresetꢀ–ꢀregisterꢀisꢀresetꢀtoꢀPORꢀvalue
Whenꢀanꢀactualꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀasꢀspecifiedꢀbyꢀoneꢀofꢀtheꢀfourꢀdefinedꢀ
LVRꢀvoltageꢀvaluesꢀabove,ꢀanꢀMCUꢀresetꢀwillꢀbeꢀgenerated.ꢀTheꢀresetꢀoperationꢀwillꢀ
beꢀactivatedꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀInꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀ
remainꢀtheꢀsameꢀafterꢀsuchꢀaꢀresetꢀoccurs.
Anyꢀregisterꢀvalue,ꢀotherꢀthanꢀtheꢀfourꢀdefinedꢀregisterꢀvaluesꢀabove,ꢀwillꢀalsoꢀresultꢀ
inꢀtheꢀgenerationꢀofꢀanꢀMCUꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀ2~3ꢀfSUB
ꢀ
clockꢀcycles.ꢀHoweverꢀinꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀbeꢀresetꢀtoꢀtheꢀPORꢀ
value.
Rev. 1.40
66
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ CTRL0ꢀRegister
Bit
Name
R/W
7
FSYSON
R/W
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
0
“x”: unknown
Bitꢀ7ꢀ
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
Describedꢀelsewhere.
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀoccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀwhenꢀaꢀspecificꢀLowꢀVoltageꢀResetꢀsituationꢀconditionꢀoccurs.ꢀThisꢀ
bitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀprogram.
Bitꢀ1
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀoccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnonꢀdefinedꢀLVRꢀvoltageꢀregisterꢀ
values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ
0ꢀbyꢀtheꢀapplicationꢀprogram.
bitꢀ0
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
Describedꢀelsewhere.
Watchdog Time-out Reset during Normal Operation
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀnormalꢀoperationꢀisꢀtheꢀsameꢀasꢀaꢀhardwareꢀRESꢀpinꢀresetꢀ
exceptꢀthatꢀtheꢀWatchdogꢀtime-outꢀflagꢀTOꢀwillꢀbeꢀsetꢀtoꢀ“1”.
W
T
D
T
m
i
-
e
o
u
t
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀaꢀlittleꢀdifferentꢀfromꢀotherꢀkindsꢀ
ofꢀreset.ꢀMostꢀofꢀtheꢀconditionsꢀremainꢀunchangedꢀexceptꢀthatꢀtheꢀProgramꢀCounterꢀandꢀtheꢀStackꢀ
Pointerꢀwillꢀbeꢀclearedꢀtoꢀ“0”ꢀandꢀtheꢀTOꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀReferꢀtoꢀtheꢀA.C.ꢀCharacteristicsꢀforꢀ
tSSTꢀdetails.
W
T
D
T
m
i
-
e
o
u
t
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀTheꢀSSTꢀisꢀ1024ꢀclockꢀcyclesꢀforꢀHXTꢀandꢀLXT.ꢀTheꢀSSTꢀisꢀ1~2ꢀclockꢀcyclesꢀforꢀLIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Rev. 1.40
6ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Reset Initial Conditions
Theꢀdifferentꢀtypesꢀofꢀresetꢀdescribedꢀaffectꢀtheꢀresetꢀflagsꢀinꢀdifferentꢀways.ꢀTheseꢀflags,ꢀknownꢀ
asꢀPDFꢀandꢀTOꢀareꢀlocatedꢀinꢀtheꢀstatusꢀregisterꢀandꢀareꢀcontrolledꢀbyꢀvariousꢀmicrocontrollerꢀ
operations,ꢀsuchꢀasꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀfunctionꢀorꢀWatchdogꢀTimer.ꢀTheꢀresetꢀflagsꢀareꢀ
shownꢀinꢀtheꢀtable:
TO
0
PDF
RESET Conditions
0
u
u
1
Power-on Reset
u
RES or LVR reset during NOR�AL or SLOW �ode operation
WDT time-out reset during NOR�AL or SLOW �ode operation
WDT time-out reset during IDLE or SLEEP �ode operation
Note: “u” stands for unchanged.
1
1
Theꢀfollowingꢀtableꢀindicatesꢀtheꢀwayꢀinꢀwhichꢀtheꢀvariousꢀcomponentsꢀofꢀtheꢀmicrocontrollerꢀareꢀ
affectedꢀafterꢀaꢀpower-onꢀresetꢀoccurs.
Item
Program Counter
Interrupts
Condition After RESET
Reset to zero
All interrupt will be disabled
WDT
Clear after resetꢂ WDT begins counting
Timer Counter will be turned off
Timer/Event Counter
Input/Output Ports
Stack Pointer
I/O ports will be setup as inputs and ANn as A/D input pins
Stack Pointer will point to the top of the stack
Theꢀdifferentꢀkindsꢀofꢀresetsꢀallꢀaffectꢀtheꢀinternalꢀregistersꢀofꢀtheꢀmicrocontrollerꢀinꢀdifferentꢀways.ꢀ
Toꢀensureꢀreliableꢀcontinuationꢀofꢀnormalꢀprogramꢀexecutionꢀafterꢀaꢀresetꢀoccurs,ꢀitꢀisꢀimportantꢀtoꢀ
knowꢀwhatꢀconditionꢀtheꢀmicrocontrollerꢀisꢀinꢀafterꢀaꢀparticularꢀresetꢀoccurs.ꢀTheꢀfollowingꢀtableꢀ
describesꢀhowꢀeachꢀtypeꢀofꢀresetꢀaffectsꢀeachꢀofꢀtheꢀmicrocontrollerꢀinternalꢀregisters.
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
IAR0
●
●
●
●
●
●
●
●
●
●
●
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
0000 0000
- - - - - - - 0
- - - - - - 0 0
- - 0 - - - 0 0
x x x x x x x x
0000 0000
x x x x x x x x
x x x x x x x x
- - - - x x x x
- - - x x x x x
- - x x x x x x
- - 0 0 x x x x
11 0 0 0 11 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - - 0
- - - - - - 0 0
- - 0 - - - 0 0
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - - - u u u u
- - - u u u u u
- - u u u u u u
- - u u u u u u
11 0 0 x 11 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - - 0
- - - - - - 0 0
- - 0 - - - 0 0
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - - - u u u u
- - - u u u u u
- - u u u u u u
- - 1 u u u u u
11 0 0 x 11 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - - u
- - - - - - u u
- - u - - - u u
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - - - u u u u
- - - u u u u u
- - u u u u u u
- - 11 u u u u
uuuu uuuu
�P0
IAR1
�P1
BP
BP
●
BP
●
●
●
●
●
ACC
PCL
●
●
●
●
●
●
●
●
●
TBLP
TBLH
TBHP
TBHP
TBHP
STATUS
S�OD
●
●
●
●
●
●
●
●
Rev. 1.40
68
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
LVDC
●
●
●
●
●
●
●
●
●
●
- - 0 0 - 0 0 0
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
0 0 0 - 0 0 0 -
0000 0000
0000 0000
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - 0 0 0 - 0
- - 0 0 - 0 0 0
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
0 0 0 - 0 0 0 -
0000 0000
0000 0000
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - 0 0 0 - 0
- - 0 0 - 0 0 0
- - - - 0 0 0 0
- 0 0 0 0 0 0 0
0 0 0 - 0 0 0 -
0000 0000
0000 0000
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
1111 1111
1111 1111
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - 0 0 0 - 0
- - u u - u u u
- - - - u u u u
- u u u u u u u
u u u - u u u -
uuuu uuuu
uuuu uuuu
- - u u - - u u
- - u u - - u u
- - u u - - u u
- u u u - u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - u u u u u u
- - u u u u u u
- - u u u u u u
- u u u u u u u
- u u u u u u u
- u u u u u u u
- u u u u u u u
- u u u u u u u
- u u u u u u u
- - u u u u u u
- - u u u u u u
- - u u u u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - u u u u u u
- - u u u u u u
- - u u u u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - u u u u
- - - - u u u u
- - - - u u u u
- - - u u u - u
INTEG
INTC0
INTC1
INTC1
INTCꢁ
�FI0
�FI1
�FIꢁ
�FI3
�FI4
PAWU
PAPU
PA
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
PAC
PBPU
PB
PBC
PBPU
PB
●
●
●
●
●
●
PBC
PCPU
PC
●
●
●
PCC
PCPU
PC
●
●
●
PCC
PCPU
PC
●
●
●
●
●
●
●
●
●
●
●
●
PCC
PDPU
PD
●
●
●
●
●
●
●
●
●
PDC
PEPU
PE
PEC
PFPU
PF
PFC
T�PC
●
Rev. 1.40
69
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
T�PC
●
●
●
●
●
●
- - - 0 0 0 0 0
0 1 0 1 0 0 11
0 0 11 0 111
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- - - - 0 0 0 0
- - - 0 0 0 0 0
0 1 0 1 0 0 11
0 0 11 0 111
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- - - - 0 0 0 0
- - - 0 0 0 0 0
0 1 0 1 0 0 11
0 0 11 0 111
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- - - - 0 0 0 0
- - - u u u u u
uuuu uuuu
uuuu uuuu
- u u u u u u u
uuuu uuuu
uuuu uuuu
- - - - u u u u
WDTC
TBC
EEA
EEA
EED
EEC
●
●
●
●
●
●
●
●
●
●
●
ADRL
(ADRFS=0)
●
●
●
●
●
●
●
●
●
●
●
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
u u u u - - - -
uuuu uuuu
uuuu uuuu
- - - - u u u u
ADRL
(ADRFS=1)
ADRH
(ADRFS=0)
ADRH
(ADRFS=1)
●
●
ADCR0
ADCR0
ADCR1
ACERL
ACERH
CPC
0 11 0 - 0 0 0
0 11 0 0 0 0 0
0 0 - 0 - 0 0 0
1111 1111
1111 1111
1 0 0 0 0 - - 1
0 - - - - x 0 0
- - - 0 - - 0 0
0101 0101
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0 11 0 - 0 0 0
0 11 0 0 0 0 0
0 0 - 0 - 0 0 0
1111 1111
1111 1111
1 0 0 0 0 - - 1
0 - - - - 0 0 0
- - - 0 - - 0 0
uuuu uuuu
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0 11 0 - 0 0 0
0 11 0 0 0 0 0
0 0 - 0 - 0 0 0
1111 1111
1111 1111
1 0 0 0 0 - - 1
0 - - - - 0 0 0
- - - 0 - - 0 0
0101 0101
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
u u u u - u u u
uuuu uuuu
u u - u - u u u
uuuu uuuu
uuuu uuuu
u u u u u - - u
u - - - - u u u
- - - u - - u u
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
uuuu uuuu
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
CTRL0
CTRL1
LVRC
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
T�0RP
T�1C0
T�1C1
T�1DL
T�1DH
T�1AL
T�1AH
T�1RP
T�ꢁC0
T�ꢁC1
T�ꢁDL
T�ꢁDH
●
●
●
●
Rev. 1.40
ꢃ0
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
T�ꢁAL
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
111 0 0 0 0 -
1000 0001
x x x x x x x x
0000 0000
0000 0000
111 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
111 0 0 0 0 -
1000 0001
x x x x x x x x
0000 0000
0000 0000
111 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
111 0 0 0 0 -
1000 0001
x x x x x x x x
0000 0000
0000 0000
111 0 0 0 0 0
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u u u u u u -
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
T�ꢁAH
T�ꢁRP
T�3C0
T�3C1
T�3Cꢁ
T�3DL
T�3DH
T�3AL
T�3AH
T�3BL
T�3BH
T�3RP
SI�C0
SI�C1
SI�D
SI�Cꢁ/SI�A
IꢁCTOC
SPIAC0
SPIAC1
SPIAD
Note:ꢀ“u”ꢀstandsꢀforꢀunchanged
“x”ꢀstandsꢀforꢀ“unknown”
“-“ꢀstandsꢀforꢀunimplemented
Rev. 1.40
ꢃ1
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Input/Output Ports
HoltekꢀmicrocontrollersꢀofferꢀconsiderableꢀflexibilityꢀonꢀtheirꢀI/Oꢀports.ꢀWithꢀtheꢀinputꢀorꢀoutputꢀ
designationꢀofꢀeveryꢀpinꢀfullyꢀunderꢀuserꢀprogramꢀcontrol,ꢀpull-highꢀselectionsꢀforꢀallꢀportsꢀandꢀ
wake-upꢀselectionsꢀonꢀcertainꢀpins,ꢀtheꢀuserꢀisꢀprovidedꢀwithꢀanꢀI/Oꢀstructureꢀtoꢀmeetꢀtheꢀneedsꢀofꢀaꢀ
wideꢀrangeꢀofꢀapplicationꢀpossibilities.
Theꢀdevicesꢀprovideꢀbidirectionalꢀinput/outputꢀlinesꢀlabeledꢀwithꢀportꢀnamesꢀsuchꢀasꢀPAꢀandꢀPB,ꢀ
etc.ꢀTheseꢀI/OꢀportsꢀareꢀmappedꢀtoꢀtheꢀRAMꢀDataꢀMemoryꢀwithꢀspecificꢀaddressesꢀasꢀshownꢀinꢀ
theꢀSpecialꢀPurposeꢀDataꢀMemoryꢀtable.ꢀAllꢀofꢀtheseꢀI/Oꢀportsꢀcanꢀbeꢀusedꢀforꢀinputꢀandꢀoutputꢀ
operations.ꢀForꢀinputꢀoperation,ꢀtheseꢀportsꢀareꢀnon-latching,ꢀwhichꢀmeansꢀtheꢀinputsꢀmustꢀbeꢀreadyꢀ
atꢀtheꢀT2ꢀrisingꢀedgeꢀofꢀinstructionꢀ“MOVꢀA,ꢀ[m]”,ꢀwhereꢀmꢀdenotesꢀtheꢀportꢀaddress.ꢀForꢀoutputꢀ
operation,ꢀallꢀtheꢀdataꢀisꢀlatchedꢀandꢀremainsꢀunchangedꢀuntilꢀtheꢀoutputꢀlatchꢀisꢀrewritten.
I/O Resistor Lists
BC66F840
Bit
Register
Name
7
PAWUꢃ
PAPU6
PAꢃ
PACꢃ
—
6
PAWU6
PAPU6
PA6
PAC6
—
5
4
3
2
1
0
PAWU
PAPU
PA
PAWU5
PAPU5
PA5
PAWU4
PAPU4
PA4
PAWU3
PAPU3
PA3
PAWUꢁ
PAPUꢁ
PAꢁ
PAWU1
PAPU1
PA1
PAWU0
PAPU0
PA0
PAC
PBPU
PB
PAC5
PBPU5
PB5
PAC4
PBPU4
PB4
PAC3
PBPU3
PB3
PACꢁ
PBPUꢁ
PBꢁ
PAC1
PBPU1
PB1
PAC0
PBPU0
PB0
—
—
PBC
PCPU
PC
—
—
PBC5
PCPU5
PC5
PBC4
PCPU4
PC4
PBC3
PCPU3
PC3
PBCꢁ
PCPUꢁ
PCꢁ
PBC1
PCPU1
PC1
PBC0
PCPU0
PC0
—
PCPU6
PC6
PCC6
—
—
PCC
PDPU
PD
—
PCC5
PDPU5
PD5
PCC4
PDPU4
PD4
PCC3
PDPU3
PD3
PCCꢁ
PDPUꢁ
PDꢁ
PCC1
PDPU1
PD1
PCC0
PDPU0
PD0
—
—
—
PDC
—
—
PDC5
PDC4
PDC3
PDCꢁ
PDC1
PDC0
BC66F850
Bit
Register
Name
7
PAWUꢃ
PAPU6
PACꢃ
PAꢃ
—
6
PAWU6
PAPU6
PAC6
PA6
5
4
3
2
1
0
PAWU
PAPU
PAC
PA
PAWU5
PAPU5
PAC5
PA5
PAWU4
PAPU4
PAC4
PA4
PAWU3
PAPU3
PAC3
PA3
PAWUꢁ
PAPUꢁ
PACꢁ
PAꢁ
PAWU1
PAPU1
PAC1
PA1
PAWU0
PAPU0
PAC0
PA0
PBPU
PB
PBPU6
PB6
PBC6
—
PBPU5
PB5
PBPU4
PB4
PBPU3
PB3
PBPUꢁ
PBꢁ
PBPU1
PB1
PBPU0
PB0
—
PBC
PCPU
PC
—
PBC5
PCPU5
PC5
PBC4
PCPU4
PC4
PBC3
PCPU3
PC3
PBCꢁ
PCPUꢁ
PCꢁ
PBC1
PCPU1
PC1
PBC0
PCPU0
PC0
—
—
—
PCC
PDPU
PD
—
—
PCC5
PDPU5
PD5
PCC4
PDPU4
PD4
PCC3
PDPU3
PD3
PCCꢁ
PDPUꢁ
PDꢁ
PCC1
PDPU1
PD1
PCC0
PDPU0
PD0
—
—
—
—
PDC
PEPU
PE
—
—
PDC5
PEPU5
PE5
PDC4
PEPU4
PE4
PDC3
PEPU3
PE3
PDCꢁ
PEPUꢁ
PEꢁ
PDC1
PEPU1
PE1
PDC0
PEPU0
PE0
PEPU6
PEꢃ
PECꢃ
PEPU6
PE6
PEC6
PEC
PEC5
PEC4
PEC3
PECꢁ
PEC1
PEC0
Rev. 1.40
ꢃꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
BC66F860
Register
Bit
Name
7
PAWUꢃ
PAPU6
PACꢃ
PAꢃ
—
6
PAWU6
PAPU6
PAC6
PA6
5
4
3
2
1
0
PAWU
PAPU
PAC
PA
PAWU5
PAPU5
PAC5
PA5
PAWU4
PAPU4
PAC4
PA4
PAWU3
PAPU3
PAC3
PA3
PAWUꢁ
PAPUꢁ
PACꢁ
PAꢁ
PAWU1
PAPU1
PAC1
PA1
PAWU0
PAPU0
PAC0
PA0
PBPU
PB
PBPU6
PB6
PBPU5
PB5
PBPU4
PB4
PBPU3
PB3
PBPUꢁ
PBꢁ
PBPU1
PB1
PBPU0
PB0
—
PBC
PCPU
PC
—
PBC6
PCPU6
PC6
PCC6
—
PBC5
PCPU5
PC5
PBC4
PCPU4
PC4
PBC3
PCPU3
PC3
PBCꢁ
PCPUꢁ
PCꢁ
PBC1
PCPU1
PC1
PBC0
PCPU0
PC0
PCPUꢃ
PCꢃ
PCCꢃ
—
PCC
PDPU
PD
PCC5
PDPU5
PD5
PCC4
PDPU4
PD4
PCC3
PDPU3
PD3
PCCꢁ
PDPUꢁ
PDꢁ
PCC1
PDPU1
PD1
PCC0
PDPU0
PD0
—
—
PDC
PEPU
PE
—
—
PDC5
PEPU5
PE5
PDC4
PEPU4
PE4
PDC3
PEPU3
PE3
PDCꢁ
PEPUꢁ
PEꢁ
PDC1
PEPU1
PE1
PDC0
PEPU0
PE0
PEPU6
PEꢃ
PECꢃ
—
PEPU6
PE6
PEC
PFPU
PF
PEC6
—
PEC5
—
PEC4
—
PEC3
PFPU3
PF3
PECꢁ
PFPUꢁ
PFꢁ
PEC1
PFPU1
PF1
PEC0
PFPU0
PF0
—
—
—
—
PFC
—
—
—
—
PFC3
PFCꢁ
PFC1
PFC0
“—”: Unimplementedꢂ read as “0”
PAWUn:ꢀPAꢀwake-upꢀfunctionꢀcontrol
0:ꢀDisable
1:ꢀEnable
PAn/PBn/PCn/PDn/PEn/PFn:ꢀI/OꢀDataꢀbit
0:ꢀDataꢀ0
1:ꢀDataꢀ1
PACn/PBCn/PCCn/PDCn/PECn/PFCn:ꢀI/Oꢀtypeꢀselection
0:ꢀOutput
1:ꢀInput
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn:ꢀPull-highꢀfunctionꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
ꢃ3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Pull-high Resistors
Manyꢀproductꢀapplicationsꢀrequireꢀpull-highꢀresistorsꢀforꢀtheirꢀswitchꢀinputsꢀusuallyꢀrequiringꢀtheꢀ
useꢀofꢀanꢀexternalꢀresistor.ꢀToꢀeliminateꢀtheꢀneedꢀforꢀtheseꢀexternalꢀresistors,ꢀallꢀI/Oꢀpins,ꢀwhenꢀ
configuredꢀasꢀanꢀinputꢀhaveꢀtheꢀcapabilityꢀofꢀbeingꢀconnectedꢀtoꢀanꢀinternalꢀpull-highꢀresistor.ꢀTheseꢀ
pull-highꢀresistorsꢀareꢀselectedꢀusingꢀregistersꢀPAPU~PFPUꢀandꢀareꢀimplementedꢀusingꢀweakꢀPMOSꢀ
transistors.
Port A Wake-up
TheꢀHALTꢀinstructionꢀforcesꢀtheꢀmicrocontrollerꢀintoꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀwhichꢀpreservesꢀ
power,ꢀaꢀfeatureꢀthatꢀisꢀimportantꢀforꢀbatteryꢀandꢀotherꢀlow-powerꢀapplications.ꢀVariousꢀmethodsꢀ
existꢀtoꢀwake-upꢀtheꢀmicrocontroller,ꢀoneꢀofꢀwhichꢀisꢀtoꢀchangeꢀtheꢀlogicꢀconditionꢀonꢀoneꢀofꢀtheꢀPortꢀ
Aꢀpinsꢀfromꢀhighꢀtoꢀlow.ꢀThisꢀfunctionꢀisꢀespeciallyꢀsuitableꢀforꢀapplicationsꢀthatꢀcanꢀbeꢀwokenꢀupꢀ
viaꢀexternalꢀswitches.ꢀEachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀselectedꢀindividuallyꢀtoꢀhaveꢀthisꢀwake-upꢀfeatureꢀ
usingꢀtheꢀPAWUꢀregister.
PAWU Register
Bit
7
PAWUꢃ
R/W
0
6
PAWU6
R/W
0
5
PAWU5
R/W
0
4
PAWU4
R/W
0
3
PAWU3
R/W
0
2
PAWUꢁ
R/W
0
1
PAWU1
R/W
0
0
PAWU0
R/W
0
Name
R/W
POR
Bitꢀ7~0
PAWU7~PAWU0:ꢀPortꢀAꢀbitꢀ7~bitꢀ0ꢀWake-upꢀControl
0:ꢀDisable
1:ꢀEnable
I/O Port Control Registers
EachꢀI/OꢀportꢀhasꢀitsꢀownꢀcontrolꢀregisterꢀknownꢀasꢀPAC~PFC,ꢀtoꢀcontrolꢀtheꢀinput/outputꢀ
configuration.ꢀWithꢀthisꢀcontrolꢀregister,ꢀeachꢀCMOSꢀoutputꢀorꢀinputꢀcanꢀbeꢀreconfiguredꢀ
dynamicallyꢀunderꢀsoftwareꢀcontrol.ꢀEachꢀpinꢀofꢀtheꢀI/Oꢀportsꢀisꢀdirectlyꢀmappedꢀtoꢀaꢀbitꢀinꢀitsꢀ
associatedꢀportꢀcontrolꢀregister.ꢀForꢀtheꢀI/Oꢀpinꢀtoꢀfunctionꢀasꢀanꢀinput,ꢀtheꢀcorrespondingꢀbitꢀofꢀ
theꢀcontrolꢀregisterꢀmustꢀbeꢀwrittenꢀasꢀ1.ꢀThisꢀwillꢀthenꢀallowꢀtheꢀlogicꢀstateꢀofꢀtheꢀinputꢀpinꢀtoꢀbeꢀ
directlyꢀreadꢀbyꢀinstructions.ꢀWhenꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀisꢀwrittenꢀasꢀ0,ꢀtheꢀ
I/OꢀpinꢀwillꢀbeꢀsetupꢀasꢀaꢀCMOSꢀoutput.ꢀIfꢀtheꢀpinꢀisꢀcurrentlyꢀsetupꢀasꢀanꢀoutput,ꢀinstructionsꢀcanꢀ
stillꢀbeꢀusedꢀtoꢀreadꢀtheꢀoutputꢀregister.ꢀHowever,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀprogramꢀwillꢀinꢀfactꢀ
onlyꢀreadꢀtheꢀstatusꢀofꢀtheꢀoutputꢀdataꢀlatchꢀandꢀnotꢀtheꢀactualꢀlogicꢀstatusꢀofꢀtheꢀoutputꢀpin.
I/O Pin Structures
TheꢀaccompanyingꢀdiagramsꢀillustrateꢀtheꢀinternalꢀstructuresꢀofꢀsomeꢀgenericꢀI/Oꢀpinꢀtypes.ꢀAsꢀ
theꢀexactꢀlogicalꢀconstructionꢀofꢀtheꢀI/Oꢀpinꢀwillꢀdifferꢀfromꢀtheseꢀdrawings,ꢀtheyꢀareꢀsuppliedꢀasꢀaꢀ
guideꢀonlyꢀtoꢀassistꢀwithꢀtheꢀfunctionalꢀunderstandingꢀofꢀtheꢀI/Oꢀpins.ꢀTheꢀwideꢀrangeꢀofꢀpin-sharedꢀ
structuresꢀdoesꢀnotꢀpermitꢀallꢀtypesꢀtoꢀbeꢀshown.
Rev. 1.40
ꢃ4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
V
D
D
P
l
u
-
l
i
H
h
g
C
n
o
r
t
l
o
B
t
i
O
t
p
o
i
n
W
a
e
k
D
t
a
a
B
u
s
D
Q
P
l
u
-
l
p
u
W
i
r
e
t
C
o
n
r
l
o
t
R
e
s
g
e
t
i
r
C
K
Q
S
C
i
h
p
R
e
e
s
t
I
/
O
i
n
P
R
a
e
d
C
o
t
n
o
r
l
R
e
s
g
e
t
i
r
D
t
a
a
B
i
t
D
Q
W
i
r
e
t
D
t
a
a
e
i
g
R
t
s
r
e
C
K
Q
S
M
U
X
R
a
e
d
D
a
a
t
R
e
s
g
e
t
i
r
S
y
e
s
t
m
W
a
e
k
-
u
p
P
A
n
y
l
o
W
k
a
-
e
u
p
O
t
p
o
i
n
Generic Input/Output Structure
V
D
D
P
l
u
-
l
i
H
h
g
C
n
o
r
t
l
o
B
t
i
W
a
e
k
O
t
p
o
i
n
P
l
u
-
l
p
u
D
t
a
a
B
u
s
D
Q
W
i
r
e
t
C
o
n
r
l
o
t
R
e
s
g
e
t
i
r
C
K
Q
S
C
i
h
p
R
e
e
s
t
A
/
n
i
D
p
t
u
i
P
s
n
R
a
e
d
C
o
t
n
o
r
l
R
e
s
g
e
t
i
r
D
t
a
a
B
i
t
D
Q
W
i
r
e
t
D
t
a
a
e
i
g
R
t
s
r
e
C
K
Q
S
M
U
X
R
a
e
d
D
a
a
t
R
e
s
g
e
t
i
r
A
a
n
o
l
g
I
p
n
u
t
S
l
e
c
e
o
t
r
T
o
A
/
o
D
n
t
v
C
r
e
e
r
A
C
~
S
C
A
4
0
S
A/D Input/Output Structure
Rev. 1.40
ꢃ5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Programming Considerations
Withinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀfirstꢀthingsꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀofꢀ
theꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀwillꢀbeꢀsetꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀdefaultꢀtoꢀ
anꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀonꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀpull-highꢀ
selectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀcontrolꢀregistersꢀareꢀthenꢀprogrammedꢀtoꢀsetupꢀsomeꢀpinsꢀ
asꢀoutputs,ꢀtheseꢀoutputꢀpinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀportꢀdataꢀ
registersꢀareꢀfirstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀWithinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀ
firstꢀthingsꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀofꢀtheꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀ
willꢀbeꢀsetꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀdefaultꢀtoꢀanꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀ
onꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀpull-highꢀselectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀ
controlꢀregisters,ꢀPACꢀandꢀPBC,ꢀareꢀthenꢀprogrammedꢀtoꢀsetupꢀsomeꢀpinsꢀasꢀoutputs,ꢀtheseꢀoutputꢀ
pinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀportꢀdataꢀregisters,ꢀPAꢀandꢀPB,ꢀareꢀ
firstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀandꢀwhichꢀareꢀoutputsꢀcanꢀbeꢀachievedꢀbyte-wideꢀ
byꢀloadingꢀtheꢀcorrectꢀvaluesꢀintoꢀtheꢀappropriateꢀportꢀcontrolꢀregisterꢀorꢀbyꢀprogrammingꢀindividualꢀ
bitsꢀinꢀtheꢀportꢀcontrolꢀregisterꢀusingꢀtheꢀSETꢀ[m].iꢀandꢀCLRꢀ[m].iꢀinstructions.ꢀNoteꢀthatꢀwhenꢀusingꢀ
theseꢀbitꢀcontrolꢀinstructions,ꢀaꢀread-modify-writeꢀoperationꢀtakesꢀplace.ꢀTheꢀmicrocontrollerꢀmustꢀ
firstꢀreadꢀinꢀtheꢀdataꢀonꢀtheꢀentireꢀport,ꢀmodifyꢀitꢀtoꢀtheꢀrequiredꢀnewꢀbitꢀvaluesꢀandꢀthenꢀrewriteꢀthisꢀ
dataꢀbackꢀtoꢀtheꢀoutputꢀports.
Theꢀpower-onꢀresetꢀconditionꢀofꢀtheꢀA/DꢀconverterꢀcontrolꢀregistersꢀensuresꢀthatꢀanyꢀA/Dꢀinputꢀpinsꢀ
–ꢀwhichꢀareꢀalwaysꢀsharedꢀwithꢀotherꢀI/Oꢀfunctionsꢀ–ꢀwillꢀbeꢀsetupꢀasꢀanalogꢀinputsꢀafterꢀaꢀreset.ꢀ
AlthoughꢀtheseꢀpinsꢀwillꢀbeꢀconfiguredꢀasꢀA/Dꢀinputsꢀafterꢀaꢀreset,ꢀtheꢀA/Dꢀconverterꢀwillꢀnotꢀbeꢀ
switchedꢀon.ꢀItꢀisꢀthereforeꢀimportantꢀtoꢀnoteꢀthatꢀifꢀitꢀisꢀrequiredꢀtoꢀuseꢀtheseꢀpinsꢀasꢀI/Oꢀdigitalꢀ
inputꢀpinsꢀorꢀasꢀotherꢀfunctions,ꢀtheꢀA/Dꢀconverterꢀcontrolꢀregistersꢀmustꢀbeꢀcorrectlyꢀprogrammedꢀ
toꢀremoveꢀtheꢀA/Dꢀfunction.ꢀNoteꢀalsoꢀthatꢀasꢀtheꢀA/Dꢀchannelꢀisꢀenabled,ꢀanyꢀinternalꢀpull-highꢀ
resistorꢀconnectionsꢀwillꢀbeꢀremoved.
PortꢀAꢀhasꢀtheꢀadditionalꢀcapabilityꢀofꢀprovidingꢀwake-upꢀfunctions.ꢀWhenꢀtheꢀdevicesꢀareꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode,ꢀvariousꢀmethodsꢀareꢀavailableꢀtoꢀwakeꢀtheꢀdevicesꢀup.ꢀOneꢀofꢀtheseꢀisꢀaꢀhighꢀ
toꢀlowꢀtransitionꢀofꢀanyꢀofꢀtheꢀPortꢀAꢀpins.ꢀSingleꢀorꢀmultipleꢀpinsꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀtoꢀhaveꢀthisꢀ
function.
Rev. 1.40
ꢃ6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Timer Modules – TM
Oneꢀofꢀtheꢀmostꢀfundamentalꢀfunctionsꢀinꢀanyꢀmicrocontrollerꢀdevicesꢀisꢀtheꢀabilityꢀtoꢀcontrolꢀandꢀ
measureꢀtime.ꢀToꢀimplementꢀtimeꢀrelatedꢀfunctionsꢀeachꢀdeviceꢀincludesꢀseveralꢀTimerꢀModules,ꢀ
abbreviatedꢀtoꢀtheꢀnameꢀTM.ꢀTheꢀTMsꢀareꢀmulti-purposeꢀtimingꢀunitsꢀandꢀserveꢀtoꢀprovideꢀ
operationsꢀsuchꢀasꢀTimer/Counter,ꢀInputꢀCapture,ꢀCompareꢀMatchꢀOutputꢀandꢀSingleꢀPulseꢀOutputꢀ
asꢀwellꢀasꢀbeingꢀtheꢀfunctionalꢀunitꢀforꢀtheꢀgenerationꢀofꢀPWMꢀsignals.ꢀEachꢀofꢀtheꢀTMsꢀhasꢀeitherꢀ
twoꢀindividualꢀinterrupts.ꢀTheꢀadditionꢀofꢀinputꢀandꢀoutputꢀpinsꢀforꢀeachꢀTMꢀensuresꢀthatꢀusersꢀareꢀ
providedꢀwithꢀtimingꢀunitsꢀwithꢀaꢀwideꢀandꢀflexibleꢀrangeꢀofꢀfeatures.
TheꢀcommonꢀfeaturesꢀofꢀtheꢀdifferentꢀTMꢀtypesꢀareꢀdescribedꢀhereꢀwithꢀmoreꢀdetailedꢀinformationꢀ
providedꢀinꢀtheꢀindividualꢀCompact,ꢀStandardꢀandꢀEnhancedꢀTMꢀsections.
Introduction
TheꢀdevicesꢀcontainꢀupꢀtoꢀfourꢀTMsꢀwithꢀeachꢀTMꢀhavingꢀaꢀreferenceꢀnameꢀofꢀTM0,ꢀTM1,ꢀTM2ꢀandꢀ
TM3.ꢀEachꢀindividualꢀTMꢀcanꢀbeꢀcategorisedꢀasꢀaꢀcertainꢀtype,ꢀnamelyꢀCompactꢀTypeꢀTMꢀ(CTM),ꢀ
StandardꢀTypeꢀTMꢀ(STM)ꢀorꢀEnhancedꢀTypeꢀTMꢀ(ETM).ꢀAlthoughꢀsimilarꢀinꢀnature,ꢀtheꢀdifferentꢀ
TMꢀtypesꢀvaryꢀinꢀtheirꢀfeatureꢀcomplexity.ꢀTheꢀcommonꢀfeaturesꢀtoꢀallꢀofꢀtheꢀCompact,ꢀStandardꢀ
andꢀEnhancedꢀTMsꢀwillꢀbeꢀdescribedꢀinꢀthisꢀsectionꢀandꢀtheꢀdetailedꢀoperationꢀregardingꢀeachꢀofꢀtheꢀ
TMꢀtypesꢀwillꢀbeꢀdescribedꢀinꢀseparateꢀsections.ꢀTheꢀmainꢀfeaturesꢀandꢀdifferencesꢀbetweenꢀtheꢀthreeꢀ
typesꢀofꢀTMsꢀareꢀsummarisedꢀinꢀtheꢀaccompanyingꢀtable.
Function
Timer/Counter
CTM
STM
ETM
√
√
√
I/P Capture
—
√
√
Compare �atch Output
PW� Channels
√
√
√
1
—
1
ꢁ
Single Pulse Output
PW� Alignment
1
ꢁ
Edge
Edge
Edge & Centre
Dutꢀ or Period
PW� Adjustment Period & Dutꢀ
Dutꢀ or Period
Dutꢀ or Period
TM Function Summary
EachꢀdeviceꢀinꢀtheꢀseriesꢀcontainsꢀaꢀspecificꢀnumberꢀofꢀeitherꢀCompactꢀType,ꢀStandardꢀTypeꢀandꢀ
EnhancedꢀTypeꢀTMꢀunitsꢀwhichꢀareꢀshownꢀinꢀtheꢀtableꢀtogetherꢀwithꢀtheirꢀindividualꢀreferenceꢀname,ꢀ
TM0~TM3.
Device
TM0
TM1
—
TM2
TM3
BC66F840
BC66F850
BC66F860
16-bit CT�
16-bit CT�
16-bit CT�
16-bit ST�
16-bit ST�
16-bit ST�
16-bit ET�
16-bit ET�
16-bit ET�
16-bit CT�
16-bit CT�
TM Name/Type Reference
TM Operation
TheꢀthreeꢀdifferentꢀtypesꢀofꢀTMꢀofferꢀaꢀdiverseꢀrangeꢀofꢀfunctions,ꢀfromꢀsimpleꢀtimingꢀoperationsꢀ
toꢀPWMꢀsignalꢀgeneration.ꢀTheꢀkeyꢀtoꢀunderstandingꢀhowꢀtheꢀTMꢀoperatesꢀisꢀtoꢀseeꢀitꢀinꢀtermsꢀofꢀ
aꢀfreeꢀrunningꢀcounterꢀwhoseꢀvalueꢀisꢀthenꢀcomparedꢀwithꢀtheꢀvalueꢀofꢀpre-programmedꢀinternalꢀ
comparators.ꢀWhenꢀtheꢀfreeꢀrunningꢀcounterꢀhasꢀtheꢀsameꢀvalueꢀasꢀtheꢀpre-programmedꢀcomparator,ꢀ
knownꢀasꢀaꢀcompareꢀmatchꢀsituation,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀbeꢀgeneratedꢀwhichꢀcanꢀclearꢀtheꢀ
counterꢀandꢀperhapsꢀalsoꢀchangeꢀtheꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀinternalꢀTMꢀcounterꢀisꢀ
drivenꢀbyꢀaꢀuserꢀselectableꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀanꢀinternalꢀclockꢀorꢀanꢀexternalꢀpin.
Rev. 1.40
ꢃꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TM Clock Source
TheꢀclockꢀsourceꢀwhichꢀdrivesꢀtheꢀmainꢀcounterꢀinꢀeachꢀTMꢀcanꢀoriginateꢀfromꢀvariousꢀsources.ꢀ
TheꢀselectionꢀofꢀtheꢀrequiredꢀclockꢀsourceꢀisꢀimplementedꢀusingꢀtheꢀTnCK2~TnCK0ꢀbitsꢀinꢀtheꢀTMꢀ
controlꢀregisters.ꢀTheꢀclockꢀsourceꢀcanꢀbeꢀaꢀratioꢀofꢀeitherꢀtheꢀsystemꢀclockꢀfSYSꢀorꢀtheꢀinternalꢀhighꢀ
clockꢀfH,ꢀtheꢀfSUBꢀclockꢀsourceꢀorꢀtheꢀexternalꢀTCKnꢀpin.ꢀNoteꢀthatꢀsettingꢀtheseꢀbitsꢀtoꢀtheꢀvalueꢀ101ꢀ
willꢀselectꢀaꢀreservedꢀclockꢀinput,ꢀinꢀeffectꢀdisconnectingꢀtheꢀTMꢀclockꢀsource.ꢀTheꢀTCKnꢀpinꢀclockꢀ
sourceꢀisꢀusedꢀtoꢀallowꢀanꢀexternalꢀsignalꢀtoꢀdriveꢀtheꢀTMꢀasꢀanꢀexternalꢀclockꢀsourceꢀorꢀforꢀeventꢀ
counting.
TM Interrupts
TheꢀCompactꢀandꢀStandardꢀtypeꢀTMsꢀeachꢀhaveꢀtwoꢀinternalꢀinterrupts,ꢀoneꢀforꢀeachꢀofꢀtheꢀinternalꢀ
comparatorꢀAꢀorꢀcomparatorꢀP,ꢀwhichꢀgenerateꢀaꢀTMꢀinterruptꢀwhenꢀaꢀcompareꢀmatchꢀconditionꢀ
occurs.ꢀAsꢀtheꢀEnhancedꢀtypeꢀTMꢀhasꢀthreeꢀinternalꢀcomparatorsꢀandꢀcomparatorꢀAꢀorꢀcomparatorꢀBꢀ
orꢀcomparatorꢀPꢀcompareꢀmatchꢀfunctions,ꢀitꢀconsequentlyꢀhasꢀthreeꢀinternalꢀinterrupts.ꢀWhenꢀaꢀ
TMꢀinterruptꢀisꢀgeneratedꢀitꢀcanꢀbeꢀusedꢀtoꢀclearꢀtheꢀcounterꢀandꢀalsoꢀtoꢀchangeꢀtheꢀstateꢀofꢀtheꢀTMꢀ
outputꢀpin.
TM External Pins
EachꢀofꢀtheꢀTMs,ꢀirrespectiveꢀofꢀwhatꢀtype,ꢀhasꢀoneꢀTMꢀinputꢀpin,ꢀwithꢀtheꢀlabelꢀTCKn.ꢀTheꢀTMꢀ
inputꢀpinꢀisꢀessentiallyꢀaꢀclockꢀsourceꢀforꢀtheꢀTMꢀandꢀisꢀselectedꢀusingꢀtheꢀTnCK2~TnCK0ꢀbitsꢀinꢀ
theꢀTMnC0ꢀregister.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀallowsꢀanꢀexternalꢀclockꢀsourceꢀtoꢀdriveꢀtheꢀinternalꢀ
TM.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀisꢀsharedꢀwithꢀotherꢀfunctionsꢀbutꢀwillꢀbeꢀconnectedꢀtoꢀtheꢀinternalꢀ
TMꢀifꢀselectedꢀusingꢀtheꢀTnCK2~TnCK0ꢀbits.ꢀTheꢀTMꢀinputꢀpinꢀcanꢀbeꢀchosenꢀtoꢀhaveꢀeitherꢀaꢀ
risingꢀorꢀfallingꢀactiveꢀedge.
TheꢀTMsꢀeachꢀhaveꢀoneꢀorꢀmoreꢀoutputꢀpinsꢀwithꢀtheꢀlabelꢀTPn.ꢀWhenꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀ
MatchꢀOutputꢀMode,ꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀTMꢀtoꢀswitchꢀtoꢀaꢀhighꢀorꢀlowꢀlevelꢀorꢀtoꢀ
toggleꢀwhenꢀaꢀcompareꢀmatchꢀsituationꢀoccurs.ꢀTheꢀexternalꢀTPnꢀoutputꢀpinꢀisꢀalsoꢀtheꢀpinꢀwhereꢀ
theꢀTMꢀgeneratesꢀtheꢀPWMꢀoutputꢀwaveform.ꢀAsꢀtheꢀTMꢀoutputꢀpinsꢀareꢀpin-sharedꢀwithꢀotherꢀ
function,ꢀtheꢀTMꢀoutputꢀfunctionꢀmustꢀfirstꢀbeꢀsetupꢀusingꢀregisters.ꢀAꢀsingleꢀbitꢀinꢀoneꢀofꢀtheꢀ
registersꢀdeterminesꢀifꢀitsꢀassociatedꢀpinꢀisꢀtoꢀbeꢀusedꢀasꢀanꢀexternalꢀTMꢀoutputꢀpinꢀorꢀifꢀitꢀisꢀtoꢀhaveꢀ
anotherꢀfunction.ꢀTheꢀnumberꢀofꢀoutputꢀpinsꢀforꢀeachꢀTMꢀtypeꢀandꢀdeviceꢀisꢀdifferent,ꢀtheꢀdetailsꢀareꢀ
providedꢀinꢀtheꢀaccompanyingꢀtable.
Device
CTM
TP0
STM
ETM
Register
T�PC
BC66F840
BC66F850
BC66F860
TPꢁ
TP3Aꢂ TP3B
TP3Aꢂ TP3B
TP3Aꢂ TP3B
TP0ꢂ TP1
TP0ꢂ TP1
TPꢁ
TPꢁ
T�PC
T�PC
TM Input/Output Pins
Rev. 1.40
ꢃ8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TM Input/Output Pin Control Registers
SelectingꢀtoꢀhaveꢀaꢀTMꢀinput/outputꢀorꢀwhetherꢀtoꢀretainꢀitsꢀotherꢀsharedꢀfunctionꢀisꢀimplementedꢀ
usingꢀoneꢀregister,ꢀwithꢀaꢀsingleꢀbitꢀinꢀeachꢀregisterꢀcorrespondingꢀtoꢀaꢀTMꢀinput/outputꢀpin.ꢀSettingꢀ
theꢀbitꢀhighꢀwillꢀsetupꢀtheꢀcorrespondingꢀpinꢀasꢀaꢀTMꢀinput/output,ꢀifꢀresetꢀtoꢀzeroꢀtheꢀpinꢀwillꢀretainꢀ
itsꢀoriginalꢀotherꢀfunction.
TMPC Register
Bit
Device
7
6
5
4
3
2
1
0
BC66F840
BC66F850
BC66F860
—
—
—
—
—
—
—
—
—
T3BCP
T3BCP
T3BCP
T3ACP
T3ACP
T3ACP
TꢁCP
TꢁCP
TꢁCP
—
T0CP
T0CP
T0CP
T1CP
T1CP
TM Input/Output Pin Control Register List
“–”:ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
T3BCP:ꢀ
T3ACP:ꢀ
T2CP:ꢀ
T1CP:ꢀ
T0CP:ꢀ
TP3BꢀpinꢀenableꢀControl
0:ꢀDisable
1:ꢀEnable
TP3AꢀpinꢀenableꢀControl
0:ꢀDisable
1:ꢀEnable
TP2ꢀpinꢀenableꢀControl
0:ꢀDisable
1:ꢀEnable
TP1ꢀpinꢀenableꢀControl
0:ꢀDisable
1:ꢀEnable
TP0ꢀpinꢀenableꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
ꢃ9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
PC4 output function
0
1
CCRA Output
0
PC4/TP0
PC5/TCK0
PC5/TPꢁ
1
CT�
(T�0)
T0CP
PC4
TCK Input
PC5 output function
0
1
CCRA Output
0
1
TꢁCP
ST�
(T�ꢁ)
PC5
1
0
Capture Input
TCK Input
PC4/TCKꢁ
PB5/TP3A
PB5 output function
0
1
CCRA Output
0
1
T3ACP
PB5
1
0
CCRA Capture Input
PC6 output function
ET�
(T�3)
0
1
CCRB Output
PC6/TP3B
0
1
T3BCP
PC6
1
0
CCRB Capture Input
TCK Input
PC4/TCK3
BC66F840 TM Function Pin Control Block Diagram
Rev. 1.40
80
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
PEꢁ output function
0
1
CCRA Output
0
PEꢁ/TP0
PE4/TCK0
PE3/TP1
PE4/TCK1
PE4/TPꢁ
1
CT�
(T�0)
T0CP
PEꢁ
TCK Input
PE3 output function
0
1
CCRA Output
0
1
CT�
(T�1)
T1CP
PE3
TCK Input
PE4 output function
0
1
CCRA Output
0
1
TꢁCP
ST�
(T�ꢁ)
PE4
1
0
Capture Input
TCK Input
PEꢁ/TCKꢁ
PE6/TP3A
PE6 output function
0
1
CCRA Output
0
1
T3ACP
PE6
1
0
CCRA Capture Input
PE5 output function
ET�
(T�3)
0
1
CCRB Output
0
1
PE5/TP3B
T3BCP
PE5
1
0
CCRB Capture Input
TCK Input
PEꢁ/TCK3
BC66F850 TM Function Pin Control Block Diagram
Rev. 1.40
81
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
PC4 output function
0
1
CCRA Output
0
PC4/TP0
PC5/TCK0
PF0/TP1
PC5/TCK1
PC5/TPꢁ
1
CT�
(T�0)
T0CP
PC4
TCK Input
PF0 output function
0
1
CCRA Output
0
1
CT�
(T�1)
T1CP
PF0
TCK Input
PC5 output function
0
1
CCRA Output
0
1
TꢁCP
ST�
(T�ꢁ)
PC5
1
0
Capture Input
TCK Input
PC4/TCKꢁ
PCꢃ/TP3A
PCꢃ output function
0
1
CCRA Output
0
1
T3ACP
PCꢃ
1
0
CCRA Capture Input
PC6 output function
ET�
(T�3)
0
1
CCRB Output
0
1
PC6/TP3B
T3BCP
PC6
1
0
CCRB Capture Input
TCK Input
PC4/TCK3
BC66F860 TM Function Pin Control Block Diagram
Rev. 1.40
8ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Programming Considerations
TheꢀTMꢀCounterꢀRegistersꢀandꢀtheꢀCapture/CompareꢀCCRAꢀandꢀCCRBꢀregisters,ꢀbeingꢀ16-bit,ꢀallꢀ
haveꢀaꢀlowꢀandꢀhighꢀbyteꢀstructure.ꢀTheꢀhighꢀbytesꢀcanꢀbeꢀdirectlyꢀaccessed,ꢀbutꢀasꢀtheꢀlowꢀbytesꢀ
canꢀonlyꢀbeꢀaccessedꢀviaꢀanꢀinternalꢀ8-bitꢀbuffer,ꢀreadingꢀorꢀwritingꢀtoꢀtheseꢀregisterꢀpairsꢀmustꢀbeꢀ
carriedꢀoutꢀinꢀaꢀspecificꢀway.ꢀTheꢀimportantꢀpointꢀtoꢀnoteꢀisꢀthatꢀdataꢀtransferꢀtoꢀandꢀfromꢀtheꢀ8-bitꢀ
bufferꢀandꢀitsꢀrelatedꢀlowꢀbyteꢀonlyꢀtakesꢀplaceꢀwhenꢀaꢀwriteꢀorꢀreadꢀoperationꢀtoꢀitsꢀcorrespondingꢀ
highꢀbyteꢀisꢀexecuted.ꢀAsꢀtheꢀCCRAꢀandꢀCCRBꢀregistersꢀareꢀimplementedꢀinꢀtheꢀwayꢀshownꢀinꢀtheꢀ
followingꢀdiagramꢀandꢀaccessingꢀtheseꢀregisterꢀpairsꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀdescribedꢀabove,ꢀ
itꢀisꢀrecommendedꢀtoꢀuseꢀtheꢀ“MOV”ꢀinstructionꢀtoꢀaccessꢀtheꢀCCRAꢀandꢀCCRBꢀlowꢀbyteꢀregisters,ꢀ
namedꢀTMxALꢀandꢀTMxBL,ꢀusingꢀtheꢀfollowingꢀaccessꢀprocedures.ꢀAccessingꢀtheꢀCCRAꢀorꢀCCRBꢀ
lowꢀbyteꢀregistersꢀwithoutꢀfollowingꢀtheseꢀaccessꢀproceduresꢀwillꢀresultꢀinꢀunpredictableꢀvalues.
T� Counter Register (Read onlꢀ)
T�xDL T�xDH
8-bit
Buffer
T�xAL T�xAH
T� CCRA Register (Read/Write)
T�xBL T�xBH
T� CCRB Register (Read/Write)
Data
Bus
Theꢀfollowingꢀstepsꢀshowꢀtheꢀreadꢀandꢀwriteꢀprocedures:
•ꢀ WritingꢀDataꢀtoꢀCCRBꢀorꢀCCRA
ꢀ
♦
WriteꢀdataꢀtoꢀLowꢀByteꢀTMxALꢀorꢀTMxBLꢀ–ꢀnoteꢀthatꢀhereꢀdataꢀisꢀonlyꢀwrittenꢀtoꢀtheꢀ8-bitꢀ
buffer.
ꢀ
♦
WriteꢀdataꢀtoꢀHighꢀByteꢀTMxAHꢀorꢀTMxBHꢀ–ꢀhereꢀdataꢀisꢀwrittenꢀdirectlyꢀtoꢀtheꢀhighꢀbyteꢀ
registersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀfromꢀtheꢀ8-bitꢀbufferꢀtoꢀtheꢀLowꢀByteꢀregisters.
•ꢀ ReadingꢀDataꢀfromꢀtheꢀCounterꢀRegistersꢀandꢀCCRBꢀorꢀCCRA
ꢀ
♦
ReadꢀdataꢀfromꢀtheꢀHighꢀByteꢀTMxDH,ꢀTMxAHꢀorꢀTMxBHꢀ–ꢀhereꢀdataꢀisꢀreadꢀdirectlyꢀfromꢀ
theꢀHighꢀByteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀfromꢀtheꢀLowꢀByteꢀregisterꢀintoꢀtheꢀ
8-bitꢀbuffer.
ꢀ
♦
ReadꢀdataꢀfromꢀtheꢀLowꢀByteꢀTMxDL,ꢀTMxALꢀorꢀTMxBLꢀ–ꢀthisꢀstepꢀreadsꢀdataꢀfromꢀtheꢀ8-bitꢀ
buffer.
Rev. 1.40
83
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Compact Type TM – CTM
AlthoughꢀtheꢀsimplestꢀformꢀofꢀtheꢀthreeꢀTMꢀtypes,ꢀtheꢀCompactꢀTMꢀtypeꢀstillꢀcontainsꢀthreeꢀ
operatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/EventꢀCounterꢀandꢀPWMꢀOutputꢀmodes.ꢀ
TheꢀCompactꢀTMꢀcanꢀalsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀoneꢀexternalꢀoutputꢀ
pin.
CTM
Name
TM No.
TM Input Pin TM Output Pin
BC66F840
16-bit CT�
0
TCK0
TP0
BC66F850/
BC66F860
16-bit CT�
0ꢂ 1
TCK0ꢂ TCK1
TP0ꢂ TP1
Compact TM Operation
Atꢀitsꢀcoreꢀisꢀaꢀ16-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀ
source.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀ
TheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAregisters.ꢀTheꢀCCRPꢀ
isꢀ8-bitꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀwithꢀtheꢀhighestꢀeightꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀCCRAꢀisꢀ
16-bitꢀwideꢀandꢀthereforeꢀcomparesꢀwithꢀallꢀcounterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀCompactꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
C
C
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o
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P
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a
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T
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f
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Y
/
4
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
T
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b
8
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1
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6
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6
1
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6
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8
T
O
n
N
b
0
~
b
1
5
T
M
n
,
1
n
T
M
0
T
P
n
L
O
T
C
n
C
R
L
T
K
C
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T
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A
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1
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,
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m
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o
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T
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C
C
R
A
Compact Type TM Block Diagram (n=0 or 1)
Rev. 1.40
84
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Compact Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀCompactꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ
theꢀinternalꢀ16-bitꢀCCRAꢀvalue.ꢀThereꢀisꢀalsoꢀaꢀread/writeꢀregisterꢀusedꢀtoꢀstoreꢀtheꢀinternalꢀ8-bitꢀ
CCRPꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀ
andꢀcontrolꢀmodes.
Bit
Register
Name
7
6
5
4
3
2
—
1
0
T�nC0
T�nC1
T�nDL
T�nDH
T�nAL
T�nAH
T�nRP
TnPAU
Tn�1
Dꢃ
TnCKꢁ
Tn�0
D6
TnCK1
TnIO1
D5
TnCK0
TnIO0
D4
TnON
TnOC
D3
—
—
TnPOL
Dꢁ
TnDPX TnCCLR
D1
D9
D0
D8
D15
D14
D13
D1ꢁ
D11
D10
Dꢁ
Dꢃ
D6
D5
D4
D3
D1
D0
D15
D14
D13
D1ꢁ
D11
D10
TnRPꢁ
D9
D8
TnRPꢃ
TnRP6
TnRP5
TnRP4
TnRP3
TnRP1
TnRP0
(n=0ꢀforꢀBC66F840ꢀwhileꢀn=0~1ꢀforꢀBC66F850/BC66F860)
16-bit Compact TM Register List
TMnDL Register
Bit
7
Dꢃ
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
Dꢁ
R
1
D1
R
0
D0
R
Name
R/W
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDL:ꢀTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0
TMnDH Register
Bit
Name
R/W
7
D15
R
6
D14
R
5
D13
R
4
D1ꢁ
R
3
D11
R
2
D10
R
1
D9
R
0
D8
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDH:ꢀTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8
TMnAL Register
Bit
Name
R/W
7
Dꢃ
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
Dꢁ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnAL:ꢀTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0
Rev. 1.40
85
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D13
R/W
0
D1ꢁ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
TMnAH:ꢀTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8
TMnC0 Register
Bit
7
6
TnCKꢁ
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
1
0
Name
R/W
TnPAU
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
TnPAU:ꢀTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
TnCK2~TnCK0:ꢀSelectꢀTMnꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀfH/8
110:ꢀTCKnꢀrisingꢀedgeꢀclock
111:ꢀTCKnꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
TnON:ꢀTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrunꢀandꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ
stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalue.
IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀTnOCꢀbit,ꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀ
lowꢀtoꢀhigh.
Bitꢀ2~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
86
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnC1 Register
Bit
Name
R/W
7
Tn�1
R/W
0
6
Tn�0
R/W
0
5
TnIO1
R/W
0
4
TnIO0
R/W
0
3
TnOC
R/W
0
2
TnPOL
R/W
0
1
0
TnDPX TnCCLR
R/W
0
R/W
0
POR
Bitꢀ7~6
TnM1~TnM0:ꢀSelectꢀTMnꢀOperationꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀUndefined
10:ꢀPWMꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnIO1~TnIO0:ꢀSelectꢀTPnꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀUndefined
Timer/CounterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
TMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ
setupꢀusingꢀtheꢀTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀ
aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ
initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀ
ofꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMnꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Rev. 1.40
8ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ3
TnOC:ꢀTPnꢀoutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀwhetherꢀ
TMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode.ꢀItꢀhasꢀnoꢀ
effectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀ
determinesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀoutputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀ
PWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
TnPOL:ꢀTPnꢀoutputꢀPolarityꢀcontrol
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
TnDPX:ꢀTMnꢀPWMꢀperiod/dutyꢀControl
0:ꢀCCRPꢀ–ꢀperiod;ꢀCCRAꢀ–ꢀduty
1:ꢀCCRPꢀ–ꢀduty;ꢀCCRAꢀ–ꢀperiod
Thisꢀbit,ꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ
dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.
TnCCLR:ꢀSelectꢀTMnꢀCounterꢀclearꢀcondition
0:ꢀTMnꢀComparatorꢀPꢀmatch
1:ꢀTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
CompactꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWMꢀMode.
TMnRP Register
Bit
7
6
TnRP6
R/W
0
5
TnRP5
R/W
0
4
TnRP4
R/W
0
3
TnRP3
R/W
0
2
TnRPꢁ
R/W
0
1
TnRP1
R/W
0
0
TnRP0
R/W
0
Name
R/W
TnRPꢃ
R/W
0
POR
Bitꢀ7~0
TnRP7~TnRP0:ꢀTMnꢀCCRPꢀregisterꢀbitꢀ7~bitꢀ0,ꢀcompareꢀwithꢀtheꢀTMnꢀcounterꢀ
bitꢀ15~bitꢀ8
ComparatorꢀPꢀMatchꢀPeriod
0:ꢀ65536ꢀTMnꢀclocks
1~255:ꢀ(1~255)×256ꢀTMnꢀclocks
TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀTnCCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀTnCCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀeightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀeightꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
Rev. 1.40
88
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Compact Type TM Operation Modes
TheꢀCompactꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀthreeꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀoperatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bitsꢀinꢀtheꢀTMnC1ꢀregister.
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ00Bꢀrespectively.ꢀ
Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ
aꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ
WhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀ
aꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀ
allowsꢀtheꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀTnAFꢀandꢀTnPFꢀinterruptꢀrequestꢀflagsꢀforꢀtheꢀComparatorꢀ
AꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀIfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀ
counterꢀwillꢀoverflowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ16-bit,ꢀFFFFꢀHex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀ
TnAFꢀinterruptꢀrequestꢀflagꢀwillꢀnotꢀbeꢀgenerated.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpinꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀTnAFꢀinterruptꢀrequestꢀflagꢀ
isꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀTnPFꢀinterruptꢀrequestꢀflag,ꢀ
generatedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀTMꢀoutputꢀ
pin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ
TnIO1ꢀandꢀTnIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀtheꢀ
TnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀ
bitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.40
89
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter
overflow
TnCCLR = 0; Tn�[1:0] = 00
Counter Value
CCRP = 0
CCRP > 0
Counter cleared bꢀ CCRP value
0xFFFF
CCRP
CCRA
CCRP > 0
Pause Resume
Counter
Reset
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
Output inverts
when TnPOL is high
Output not affected bꢀ
TnAF flag. Remains High
until reset bꢀ TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Output Pin
Now TnIO1ꢂ TnIO0 = 10
Active High Output
Select
Reset to initial value
Output controlled
bꢀ other pin-shared function
Here TnIO1ꢂ TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=0,ꢀ1
Rev. 1.40
90
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TnCCLR = 1; Tn�[1:0] = 00
Counter Value
CCRA = 0
Counter overflows
CCRA > 0 Counter cleared bꢀ CCRA value
0xFFFF
CCRA
CCRA = 0
Pause Resume
Counter
Reset
Stop
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
Output does
not change
TnPF not
generated
T� O/P Pin
Output not affected bꢀ
TnAF flag remains High
until reset bꢀ TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Output inverts
when TnPOL is high
Now TnIO1ꢂ TnIO0 = 10
Active High Output
Select
Output controlled bꢀ
other pin-shared function
Output Pin
Reset to initial value
Here TnIO1ꢂ TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=0,ꢀ1
Rev. 1.40
91
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀTMꢀoutputꢀ
pinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀmode,ꢀ
theꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀ
TheꢀPWMꢀfunctionꢀwithinꢀtheꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀ
control,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀfrequencyꢀbutꢀ
ofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀTMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀ
varyingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀonꢀtheꢀPWMꢀ
operation.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀ
registerꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀ
theꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀ
orꢀdutyꢀcycleꢀisꢀdeterminedꢀusingꢀtheꢀTnDPXꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀ
frequencyꢀandꢀdutyꢀcycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀusedꢀtoꢀ
selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀusedꢀtoꢀ
enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnPOLꢀbitꢀisꢀ
usedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Period
Dutꢀ
1~255
0
CCRP×ꢁ56
65536
CCRA
IfꢀfSYS=16MHz,ꢀTMꢀclockꢀsourceꢀisꢀfSYS/4,ꢀCCRP=2ꢀandꢀCCRA=128
TheꢀCTMꢀPWMꢀoutputꢀfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,ꢀduty=128/ꢀ(2×256)=25%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.
16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
Dutꢀ
1~255
0
CCRA
CCRP×ꢁ56
65536
TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ
whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdefinedꢀbyꢀtheꢀ(CCRP×256)ꢀexceptꢀwhenꢀtheꢀCCRPꢀvalueꢀisꢀequalꢀtoꢀ0.
Rev. 1.40
9ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
Counter cleared
bꢀ CCRP
TnDPX = 0; Tn� [1:0] = 10
Counter Reset when
TnON returns high
CCRP
CCRA
Counter Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Dutꢀ Cꢀcle
set bꢀ CCRA
PW� resumes
operation
Output controlled bꢀ
other pin-shared function
Output Inverts
when TnPOL= 1
PW� Period
set bꢀ CCRP
PWM Mode – TnDPX=0
Note:ꢀ1.ꢀHereꢀTnDPX=0ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=0,ꢀ1
Rev. 1.40
93
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnDPX = 1; Tn� [1:0] = 10
Counter cleared
bꢀ CCRA
Counter Reset when
TnON returns high
CCRA
CCRP
Counter Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Dutꢀ Cꢀcle
set bꢀ CCRP
PW� resumes
operation
Output controlled bꢀ
other pin-shared function
Output Inverts
when TnPOL= 1
PW� Period
set bꢀ CCRA
PWM Mode – TnDPX=1
Note:ꢀ1.ꢀHereꢀTnDPX=1ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRA
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=0,ꢀ1
Rev. 1.40
94
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Standard Type TM – STM
TheꢀStandardꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/
EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀStandardꢀTMꢀcanꢀ
alsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀoneꢀexternalꢀoutputꢀpin.
STM
Name
TM No. TM Input Pin TM Output Pin
TCKꢁ TPꢁ
BC66F840
BC66F850
BC66F860
16-bit ST�
ꢁ
Standard TM Operation
Atꢀitsꢀcoreꢀisꢀaꢀ16-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀ
source.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀandꢀComparatorꢀ
P.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀ
CCRPꢀcomparatorꢀisꢀ8-bitꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀwithꢀtheꢀhighestꢀeightꢀbitsꢀinꢀtheꢀcounterꢀ
whileꢀtheꢀCCRAꢀisꢀ16-bitꢀwideꢀandꢀthereforeꢀcomparesꢀwithꢀallꢀcounterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀStandardꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
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Standard Type TM Block Diagram (n=2)
Rev. 1.40
95
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Standard Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀStandardꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ
theꢀinternalꢀ16-bitꢀCCRAꢀvalue.ꢀThereꢀisꢀalsoꢀaꢀread/writeꢀregisterꢀusedꢀtoꢀstoreꢀtheꢀinternalꢀ8-bitꢀ
CCRPꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀ
andꢀcontrolꢀmodes.
Bit
Register
Name
7
6
5
4
3
2
—
1
0
T�nC0
T�nC1
T�nDL
T�nDH
T�nAL
T�nAH
T�nRP
TnPAU
Tn�1
Dꢃ
TnCKꢁ
Tn�0
D6
TnCK1
TnIO1
D5
TnCK0
TnIO0
D4
TnON
TnOC
D3
—
—
TnPOL
Dꢁ
TnDPX TnCCLR
D1
D9
D0
D8
D15
D14
D13
D1ꢁ
D11
D10
Dꢁ
Dꢃ
D6
D5
D4
D3
D1
D0
D15
D14
D13
D1ꢁ
D11
D10
TnRPꢁ
D9
D8
TnRPꢃ
TnRP6
TnRP5
TnRP4
TnRP3
TnRP1
TnRP0
16-bit Standard TM Register List (n=2)
TMnDL Register
Bit
Name
R/W
7
Dꢃ
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
Dꢁ
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDL:ꢀTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0
TMnDH Register
Bit
Name
R/W
7
D15
R
6
D14
R
5
D13
R
4
D1ꢁ
R
3
D11
R
2
D10
R
1
D9
R
0
D8
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDH:ꢀTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8
TMnAL Register
Bit
Name
R/W
7
Dꢃ
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
Dꢁ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnAL:ꢀTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0
Rev. 1.40
96
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D13
R/W
0
D1ꢁ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
TMnAH:ꢀTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8
TMnC0 Register
Bit
7
6
TnCKꢁ
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
1
0
Name
R/W
TnPAU
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
TnPAU:ꢀTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
TnCK2~TnCK0:ꢀSelectꢀTMnꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀfH/8
110:ꢀTCKnꢀrisingꢀedgeꢀclock
111:ꢀTCKnꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
TnON:ꢀTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrunꢀandꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ
stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalue.
IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀTnOCꢀbit,ꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀ
lowꢀtoꢀhigh.
Bitꢀ2~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
9ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnC1 Register
Bit
7
6
Tn�0
R/W
0
5
TnIO1
R/W
0
4
TnIO0
R/W
0
3
TnOC
R/W
0
2
TnPOL
R/W
0
1
0
Name
R/W
Tn�1
R/W
0
TnDPX TnCCLR
R/W
0
R/W
0
POR
Bitꢀ7~6
TnM1~TnM0:ꢀSelectꢀTMnꢀOperationꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnIO1~TnIO0:ꢀSelectꢀTPnꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀinputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTPn
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTPn
01:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTPn
11:ꢀInputꢀcaptureꢀdisabled
Timer/CounterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
TMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ
setupꢀusingꢀtheꢀTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀ
aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ
initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀ
ofꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Rev. 1.40
98
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ3
TnOC:ꢀTPnꢀoutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ
Mode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/Counterꢀ
Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀ
outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀ
PWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
TnPOL:ꢀTPnꢀoutputꢀPolarityꢀcontrol
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
TnDPX:ꢀTMnꢀPWMꢀperiod/dutyꢀControl
0:ꢀCCRPꢀ–ꢀperiod;ꢀCCRAꢀ–ꢀduty
1:ꢀCCRPꢀ–ꢀduty;ꢀCCRAꢀ–ꢀperiod
Thisꢀbit,ꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ
dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.
TnCCLR:ꢀSelectꢀTMnꢀCounterꢀclearꢀcondition
0:ꢀTMnꢀComparatorꢀPꢀmatch
1:ꢀTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
StandardꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWMꢀMode,ꢀSingleꢀPulseꢀorꢀInputꢀCaptureꢀMode.
TMnRP Register
Bit
7
6
TnRP6
R/W
0
5
TnRP5
R/W
0
4
TnRP4
R/W
0
3
TnRP3
R/W
0
2
TnRPꢁ
R/W
0
1
TnRP1
R/W
0
0
TnRP0
R/W
0
Name
R/W
TnRPꢃ
R/W
0
POR
Bitꢀ7~0
TnRP7~TnRP0:ꢀTMnꢀCCRPꢀregisterꢀbitꢀ7~bitꢀ0,ꢀcompareꢀwithꢀtheꢀTMnꢀcounterꢀbitꢀ
15~bitꢀ8
ComparatorꢀPꢀMatchꢀPeriod
0:ꢀ65536ꢀTMnꢀclocks
1~255:ꢀ(1~255)×256ꢀTMnꢀclocks
TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀTnCCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀTnCCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀeightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀeightꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
Rev. 1.40
99
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Standard Type TM Operation Modes
TheꢀStandardꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀ
Mode,ꢀPWMꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnM1ꢀandꢀTnM0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ00ꢀrespectively.ꢀ
Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ
aꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ
WhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀ
aꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀallowsꢀ
theꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀTnAFꢀandꢀTnPFꢀinterruptꢀrequestꢀflagsꢀforꢀComparatorꢀAandꢀ
ComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀ
Mode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ0.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀTnAFꢀinterruptꢀrequestꢀflagꢀ
isꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀTnPFꢀinterruptꢀrequestꢀflag,ꢀ
generatedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀTMꢀoutputꢀ
pin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ
TnIO1ꢀandꢀTnIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀtheꢀ
TnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀ
bitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.40
100
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter
overflow
TnCCLR = 0; Tn�[1:0] = 00
Counter Value
CCRP = 0
CCRP > 0
Counter cleared bꢀ CCRP value
0xFFFF
CCRP
CCRA
CCRP > 0
Pause Resume
Counter
Reset
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
Output inverts
when TnPOL is high
Output not affected bꢀ
TnAF flag. Remains High
until reset bꢀ TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Output Pin
Now TnIO1ꢂ TnIO0 = 10
Active High Output
Select
Reset to initial value
Output controlled
bꢀ other pin-shared function
Here TnIO1ꢂ TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀAꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=2
Rev. 1.40
101
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TnCCLR = 1; Tn�[1:0] = 00
Counter Value
CCRA = 0
Counter overflows
CCRA > 0 Counter cleared bꢀ CCRA value
0xFFFF
CCRA
CCRA = 0
Pause Resume
Counter
Reset
Stop
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
Output does
not change
TnPF not
generated
T� O/P Pin
Output not affected bꢀ
TnAF flag remains High
until reset bꢀ TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
with TnAF flag
Output inverts
when TnPOL is high
Now TnIO1ꢂ TnIO0 = 10
Active High Output
Select
Output controlled bꢀ
other pin-shared function
Output Pin
Reset to initial value
Here TnIO1ꢂ TnIO0 = 11
Toggle Output Select
Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀAꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀAꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=2
Rev. 1.40
10ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀTMꢀoutputꢀ
pinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀmode,ꢀ
theꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀ
TheꢀPWMꢀfunctionꢀwithinꢀtheꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀ
control,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀfrequencyꢀbutꢀ
ofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀTMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀ
varyingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀonꢀtheꢀPWMꢀ
operation.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀ
registerꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀ
theꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀ
orꢀdutyꢀcycleꢀisꢀdeterminedꢀusingꢀtheꢀTnDPXꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀ
frequencyꢀandꢀdutyꢀcycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀusedꢀtoꢀ
selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀusedꢀtoꢀ
enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnPOLꢀbitꢀisꢀ
usedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Period
Dutꢀ
1~255
0
CCRP × ꢁ56
65536
CCRA
IfꢀfSYS=16MHz,ꢀTMꢀclockꢀsourceꢀisꢀfSYS/4,ꢀCCRP=2ꢀandꢀCCRA=128
TheꢀSTMꢀPWMꢀoutputꢀfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,ꢀduty=128/(2×256)=25%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
Dutꢀ
1~255
0
CCRA
CCRP × ꢁ56
65536
TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ
whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdefinedꢀbyꢀtheꢀ(CCRP×256)ꢀexceptꢀwhenꢀtheꢀCCRPꢀvalueꢀisꢀequalꢀtoꢀ0.
Rev. 1.40
103
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnDPX = 0; Tn� [1:0] = 10
Counter cleared
bꢀ CCRP
Counter Reset when
TnON returns high
CCRP
CCRA
Counter Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Dutꢀ Cꢀcle
set bꢀ CCRA
PW� resumes
operation
Output controlled bꢀ
other pin-shared function
Output Inverts
when TnPOL= 1
PW� Period
set bꢀ CCRP
PWM Mode – TnDPX=0
Note:ꢀ1.ꢀHereꢀTnDPX=0ꢀ--ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=2
Rev. 1.40
104
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
Counter cleared
bꢀ CCRA
TnDPX = 1; Tn� [1:0] = 10
Counter Reset when
TnON returns high
CCRA
CCRP
Counter Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Dutꢀ Cꢀcle
set bꢀ CCRP
PW� resumes
operation
Output controlled bꢀ
other pin-shared function
Output Inverts
when TnPOL= 1
PW� Period
set bꢀ CCRA
PWM Mode – TnDPX=1
Note:ꢀ1.ꢀHereꢀTnDPX=1ꢀ--ꢀCounterꢀclearedꢀbyꢀCCRA
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=2
Rev. 1.40
105
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Single Pulse Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀ
andꢀalsoꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀMode,ꢀ
asꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀtriggerꢀforꢀtheꢀ
pulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀTnONꢀbit,ꢀwhichꢀcanꢀbeꢀimplementedꢀ
usingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀTnONꢀbitꢀcanꢀalsoꢀbeꢀmadeꢀ
toꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀTCKnꢀpin,ꢀwhichꢀwillꢀinꢀturnꢀinitiateꢀ
theꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀwillꢀstartꢀrunningꢀ
andꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀTnONꢀbitꢀshouldꢀremainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀ
inꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀwhenꢀtheꢀTnONꢀbitꢀisꢀclearedꢀ
toꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀ
fromꢀComparatorꢀA.
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Single Pulse Generation
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀTnONꢀbitꢀandꢀthusꢀ
generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀ
theꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀTMꢀinterrupt.ꢀTheꢀcounterꢀ
canꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀcounterꢀ
restarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀTnCCLRꢀandꢀTnDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀ
thisꢀMode.
Rev. 1.40
106
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
Counter stopped
by CCRA
TnM [1:0] = 10 ; TnIO [1:0] = 11
Counter Reset when
TnON returns high
CCRA
CCRP
Counter Stops
by software
Resume
Pause
Time
TnON
Auto. set by
TCKn pin
Software Cleared by
Trigger CCRA match
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
TCKn pin
TnPAU
TCKn pin
Trigger
TnPOL
No CCRP Interrupts
generated
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
Output Inverts
when TnPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀtriggeredꢀbyꢀtheꢀTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀTnONꢀbitꢀhigh
4.ꢀAꢀTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀTnONꢀbitꢀhigh
5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀTnIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ11ꢀandꢀcanꢀnotꢀbeꢀchanged
6.ꢀn=2
Rev. 1.40
10ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀ
Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ
andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀ
isꢀsuppliedꢀonꢀtheꢀTPnꢀpin,ꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀ
risingꢀandꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀ
inꢀtheꢀTMnC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ
initiatedꢀusingꢀtheꢀapplicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀTPnꢀpin,ꢀtheꢀpresentꢀvalueꢀinꢀtheꢀcounterꢀwillꢀbeꢀ
latchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀonꢀ
theꢀTPnꢀpinꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀ
aꢀCCRPꢀcompareꢀmatchꢀoccurs,ꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀ
canꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀfromꢀ
ComparatorꢀP,ꢀaꢀTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀnumberꢀofꢀoverflowꢀinterruptꢀ
signalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀwidths.ꢀTheꢀTnIO1ꢀandꢀ
TnIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀTPnꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀ
edgeꢀtypes.ꢀIfꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀplaceꢀ
irrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀTPnꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀcontinueꢀ
toꢀrun.
AsꢀtheꢀTPnꢀpinꢀisꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀInputꢀCaptureꢀ
Mode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀpinꢀmayꢀcauseꢀanꢀ
inputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀTnCCLRꢀandꢀTnDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀMode.
Tn� [1:0] = 01
Counter
Value
Counter
overflow
Counter
Reset
CCRP
Stop
YY
XX
Pause Resume
Time
TnON
edge
TnPAU
Active
Active
edge
Active
edge
T� Capture
Pin TPn_x
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnIO [1:0]
Value
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
Capture Input Mode
Note:ꢀ1.ꢀTnMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnIOꢀ[1:0]ꢀbits
2.ꢀAꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ--ꢀTnOCꢀandꢀTnPOLꢀbitsꢀareꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero
6.ꢀn=2
Rev. 1.40
108
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Enhanced Type TM – ETM
TheꢀEnhancedꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/
EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀEnhancedꢀTMꢀcanꢀ
alsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀthreeꢀorꢀfourꢀexternalꢀoutputꢀpins.
ETM
Name
TM No.
TM Input Pin TM Output Pin
TCK3 TP3
BC66F840
BC66F850 16-bit ET�
BC66F860
3
Enhanced TM Operation
Atꢀitsꢀcoreꢀisꢀaꢀ16-bitꢀcount-up/count-downꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀ
orꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀthreeꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀA,ꢀ
ComparatorꢀBꢀandꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀtheꢀ
CCRA,ꢀCCRBꢀandꢀCCRPꢀregisters.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ8ꢀbitsꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀ
withꢀtheꢀhighestꢀ8ꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀCCRAꢀandꢀCCRBꢀareꢀ16ꢀbitsꢀwideꢀandꢀthereforeꢀ
comparedꢀwithꢀallꢀcounterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀEnhancedꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀoutputꢀpins.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
C
C
P
R
C
m
o
p
a
r
a
P
t
a
c
M
o
t
h
r
8
-
t
C
b
m
o
i
p
a
r
a
P
t
o
r
T
P
n
F
I
t
n
r
e
r
p
u
t
b
8
~
b
1
5
T
A
n
C
O
f
S
Y
/
S
4
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
S
Y
S
f
/
6
1
C
u
o
n
t
e
r
O
t
u
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p
t
P
l
o
r
a
t
i
y
f
/
4
6
T
n
P
A
0
C
e
l
a
r
C
o
n
r
l
o
t
C
o
n
r
l
o
t
1
6
t
-
p
b
D
U
/
i
o
w
C
o
n
u
n
t
e
r
f
S
B
U
1
f
H
/
8
T
A
n
M
1
,
T
n
M
A
0
T
A
n
O
P
L
T
O
n
N
T
C
n
C
R
L
T
K
C
n
1
1
1
T
A
n
O
I
,
1
T
A
n
O
I
0
b
0
~
b
1
5
T
P
n
U
A
T
A
n
F
C
m
o
p
a
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a
A
M
t
t
o
a
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c
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1
6
t
-
b
i
T
C
n
2
K
T
~
C
n
0
K
I
t
n
r
e
r
p
u
t
C
m
o
p
a
r
a
A
t
o
r
T
A
n
O
I
,
1
T
A
n
O
I
0
C
C
A
R
E
d
g
e
D
t
e
c
e
o
t
r
T
B
n
C
O
O
t
u
u
p
t
P
l
o
r
a
t
i
y
T
n
P
B
C
m
o
p
a
r
a
B
M
t
t
o
a
h
c
r
1
6
t
-
b
i
C
o
n
r
l
o
t
C
o
n
r
l
o
t
C
m
o
p
a
r
a
B
t
o
r
T
B
n
F
I
t
n
r
e
r
p
u
t
T
B
n
M
1
,
T
n
M
B
0
T
B
n
O
P
L
C
C
B
R
T
B
n
O
I
,
1
T
B
n
O
I
0
E
d
g
e
D
t
e
c
e
o
t
r
T
I
n
1
O
,
T
n
O
I
0
Enhanced Type TM Block Diagram (n=3)
Rev. 1.40
109
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Enhanced Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀEnhancedꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀtwoꢀread/writeꢀregisterꢀpairsꢀexistꢀtoꢀstoreꢀ
theꢀinternalꢀ16-bitꢀCCRAꢀandꢀCCRBꢀvalue.ꢀTheꢀremainingꢀthreeꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀ
setupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodesꢀasꢀwellꢀasꢀtheꢀeightꢀCCRPꢀbits.
Bit
Register
Name
7
6
5
4
3
2
1
0
T�nC0
T�nC1
T�nCꢁ
T�nDL
T�nDH
T�nAL
T�nAH
T�nBL
T�nBH
T�nRP
TnPAU
TnA�1
TnB�1
Dꢃ
TnCKꢁ
TnA�0
TnB�0
D6
TnCK1
TnAIO1
TnBIO1
D5
TnCK0
TnAIO0
TnBIO0
D4
TnON
—
—
—
TnAOC TnAPOL TnCDN TnCCLR
TnBOC TnBPOL TnPW�1 TnPW�0
D3
D11
D3
Dꢁ
D10
Dꢁ
D1
D9
D0
D8
D15
D14
D13
D1ꢁ
Dꢃ
D6
D5
D4
D1
D0
D15
D14
D13
D1ꢁ
D11
D3
D10
Dꢁ
D9
D8
Dꢃ
D6
D5
D4
D1
D0
D15
D14
D13
D1ꢁ
D11
TnRP3
D10
TnRPꢁ
D9
D8
TnRPꢃ
TnRP6
TnRP5
TnRP4
TnRP1
TnRP0
16-bit Enhanced TM Register List (n=3)
TMnDL Register
Bit
Name
R/W
7
Dꢃ
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
Dꢁ
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDL:ꢀTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0
TMnDH Register
Bit
Name
R/W
7
D15
R
6
D14
R
5
D13
R
4
D1ꢁ
R
3
D11
R
2
D10
R
1
D9
R
0
D8
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDH:ꢀTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8
Rev. 1.40
110
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnAL Register
Bit
Name
R/W
7
Dꢃ
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
Dꢁ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnAL:ꢀTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D13
R/W
0
D1ꢁ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
TMnAH:ꢀTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8
TMnBL Register
Bit
Name
R/W
7
Dꢃ
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
Dꢁ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnBL:ꢀTMnꢀCCRBꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRBꢀbitꢀ7~bitꢀ0
TMnBH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~0
TMnBH:ꢀTMnꢀCCRBꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRBꢀbitꢀ15~bitꢀ8
Rev. 1.40
111
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnC0 Register
Bit
7
6
TnCKꢁ
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
1
0
Name
R/W
TnPAU
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
TnPAU:ꢀTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
TnCK2~TnCK0:ꢀSelectꢀTMnꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀfH/8
110:ꢀTCKnꢀrisingꢀedgeꢀclock
111:ꢀTCKnꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
TnON:ꢀTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrunꢀwhileꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀ
willꢀstopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.
IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀTnOCꢀbit,ꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀ
lowꢀtoꢀhigh.
Bitꢀ7~2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
11ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnC1 Register
Bit
Name
R/W
7
TnA�1
R/W
0
6
TnA�0
R/W
0
5
TnAIO1
R/W
0
4
TnAIO0
R/W
0
3
2
1
0
TnAOC TnAPOL TnCDN TnCCLR
R/W
0
R/W
0
R
0
R/W
0
POR
Bitꢀ7~6
TnAM1~TnAM0:ꢀSelectꢀTMnꢀCCRAꢀOperationꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnAM1ꢀandꢀ
TnAM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnAIO1~TnAIO0:ꢀSelectꢀTPnAꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀinputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTPnA
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTPnA
01:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTPnA
11:ꢀInputꢀcaptureꢀdisabled
Timer/CounterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀdetermineꢀhowꢀ
theꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ
A.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnAOCꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀ
valueꢀsetupꢀusingꢀtheꢀTnAOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀ
whenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀ
theꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Rev. 1.40
113
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ3
TnAOC:ꢀTPnAꢀoutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode/
SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀ
theꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀoutputꢀpinꢀ
beforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀ
activeꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
TnAPOL:ꢀTPnAꢀoutputꢀPolarityꢀcontrol
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnAꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
TnCDN:ꢀTMnꢀCounterꢀcountꢀupꢀorꢀdownꢀflag
0:ꢀCountꢀUp
1:ꢀCountꢀDown
TnCCLR:ꢀSelectꢀTMnꢀCounterꢀclearꢀcondition
0:ꢀTMnꢀComparatorꢀPꢀmatch
1:ꢀTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀ
theꢀEnhancedꢀTMꢀcontainsꢀthreeꢀcomparators,ꢀComparatorꢀA,ꢀComparatorꢀBꢀandꢀ
ComparatorꢀP,ꢀbutꢀonlyꢀComparatorꢀAꢀorꢀComparatorꢀPꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀ
internalꢀcounter.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀ
beꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀ
overflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀonlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀ
bitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀusedꢀinꢀtheꢀSingleꢀPulseꢀorꢀInputꢀ
CaptureꢀMode.
Rev. 1.40
114
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TMnC2 Register
Bit
Name
R/W
7
TnB�1
R/W
0
6
TnB�0
R/W
0
5
TnBIO1
R/W
0
4
TnBIO0
R/W
0
3
2
1
0
TnBOC TnBPOL TnPW�1 TnPW�0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
TnBM1~TnBM0:ꢀSelectꢀTMnꢀCCRBꢀOperationꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnBM1ꢀandꢀ
TnBM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnBIO1~TnBIO0:ꢀSelectꢀTPnBꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀinputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTPnB
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTPnB
01:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTPnB
11:ꢀInputꢀcaptureꢀdisabled
Timer/CounterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnBIO1ꢀandꢀTnBIO0ꢀbitsꢀdetermineꢀhowꢀ
theꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ
A.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnBOCꢀbitꢀinꢀtheꢀTMnC2ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnBIO1ꢀandꢀTnBIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀ
valueꢀsetupꢀusingꢀtheꢀTnBOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀ
whenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnBIO1ꢀandꢀTnBIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀ
theꢀTnBIO1ꢀandꢀTnBIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnBIO1ꢀandꢀTnBIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Rev. 1.40
115
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ3
TnBOC:ꢀTPnBꢀoutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode/
SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀ
theꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀoutputꢀpinꢀ
beforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀ
activeꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
TnBPOL:ꢀTPnBꢀoutputꢀPolarityꢀcontrol
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnBꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1~0
TnPWM1~TnPWM0:ꢀSelectꢀPWMꢀMode
00:ꢀEdgeꢀaligned
01:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀup
10:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀdown
11:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀupꢀorꢀdown
TMnRP Register
Bit
7
6
TnRP6
R/W
0
5
TnRP5
R/W
0
4
TnRP4
R/W
0
3
TnRP3
R/W
0
2
TnRPꢁ
R/W
0
1
TnRP1
R/W
0
0
TnRP0
R/W
0
Name
R/W
TnRPꢃ
R/W
0
POR
Bitꢀ7~0
TnRP7~TnRP0:ꢀTMnꢀCCRPꢀregisterꢀbitꢀ7~bitꢀ0,ꢀcompareꢀwithꢀtheꢀTMnꢀcounterꢀbitꢀ
15~bitꢀ8
ComparatorꢀPꢀMatchꢀPeriod
0:ꢀ65536ꢀTMnꢀclocks
1~255:ꢀ(1~255)×256ꢀTMnꢀclocks
TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀTnCCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀTnCCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀeightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀeightꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
Rev. 1.40
116
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Enhanced Type TM Operation Modes
TheꢀEnhancedꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnAM1ꢀandꢀTnAM0ꢀbitsꢀinꢀtheꢀTMnC1,ꢀandꢀtheꢀTnBM1ꢀandꢀ
TnBM0ꢀbitsꢀinꢀtheꢀTMnC2ꢀregister.
CCRA Compare
Match Output Mode Counter Mode Output Mode
CCRA Timer/ CCRA PWM CCRA Single Pulse CCRA Input
ETM Operating Mode
Output Mode
Capture Mode
CCRB Compare �atch Output �ode
CCRB Timer/Counter �ode
CCRB PW� Output �ode
√
—
√
—
—
√
—
—
—
√
—
—
—
—
√
—
—
—
—
—
—
—
CCRB Single Pulse Output �ode
CCRB Input Capture �ode
—
—
—
“√”: permitted, “—”: not permitted
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀinꢀtheꢀTMnC1/TMnC2ꢀregistersꢀ
shouldꢀbeꢀallꢀclearedꢀtoꢀzero.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀ
byꢀthreeꢀmethods.ꢀTheseꢀareꢀaꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀ
matchꢀfromꢀComparatorꢀP.ꢀWhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀ
canꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀ
CCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀtheꢀTnAFꢀandꢀTnPFꢀinterruptꢀ
requestꢀflagsꢀforꢀComparatorꢀAꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀTnAFꢀorꢀTnBFꢀinterruptꢀ
requestꢀflagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀAꢀorꢀComparatorꢀB.ꢀTheꢀ
TnPFꢀinterruptꢀrequestꢀflag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀ
effectꢀonꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀisꢀdeterminedꢀbyꢀtheꢀ
conditionꢀofꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregisterꢀforꢀETMꢀCCRA,ꢀandꢀtheꢀTnBIO1ꢀ
andꢀTnBIO0ꢀbitsꢀinꢀtheꢀTMnC2ꢀregisterꢀforꢀETMꢀCCRB.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀ
theꢀTnAIO1,ꢀTnAIO0ꢀbitsꢀforꢀtheꢀTPnAꢀpinꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀforꢀtheꢀTPnBꢀpinꢀtoꢀgoꢀhigh,ꢀ
toꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀAꢀ
orꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀB.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀ
isꢀsetupꢀafterꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnAOCꢀorꢀTnBOCꢀbitꢀforꢀ
TPnAꢀorꢀTPnBꢀoutputꢀpin.ꢀNoteꢀthatꢀifꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀareꢀzeroꢀ
thenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.40
11ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter overflow
Counter Value
CCRP=0
TnCCLR = 0; TnA� [1:0] = 00
CCRP > 0
Counter cleared bꢀ CCRP value
0xFFFF
CCRP > 0
Counter
Restart
Resume
CCRP
CCRA
Pause
Stop
Time
TnON
TnPAU
TnAPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TPnA O/P
Pin
Output not affected bꢀ TnAF
flag. Remains High until reset
bꢀ TnON bit
Output Inverts
when TnAPOL is high
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Output controlled bꢀ
other pin-shared function
Note TnAIO [1:0] = 10
Active High Output select
Here TnAIO [1:0] = 11
Toggle Output select
ETM CCRA Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=3
Rev. 1.40
118
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter overflow
Counter Value
CCRP=0
TnCCLR = 0; TnB� [1:0] = 00
CCRP > 0
Counter cleared bꢀ CCRP value
0xFFFF
CCRP > 0
Counter
Restart
Resume
CCRP
CCRB
Pause
Stop
Time
TnON
TnPAU
TnBPOL
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affected bꢀ TnBF
flag. Remains High until reset
bꢀ TnON bit
Output Inverts
when TnBPOL is high
Output pin set to
initial Level Low
if TnBOC=0
Output Toggle with
TnBF flag
Output Pin
Reset to Initial value
Output controlled bꢀ
other pin-shared function
Note TnBIO [1:0] = 10
Active High Output select
Here TnBIO [1:0] = 11
Toggle Output select
ETM CCRB Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnBFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=3
Rev. 1.40
119
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnCCLR = 1; TnA� [1:0] = 00
CCRA = 0
CCRA > 0 Counter cleared bꢀ CCRA value
Counter overflow
0xFFFF
CCRA=0
Resume
Pause
CCRA
CCRP
Stop Counter Restart
Time
TnON
TnPAU
TnAPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TPnA O/P
Pin
Output not affected bꢀ
TnAF flag. Remains High
until reset bꢀ TnON bit
Output Inverts
when TnAPOL is high
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Output controlled bꢀ
other pin-shared function
Note TnAIO [1:0] = 10
Active High Output select
Here TnAIO [1:0] = 11
Toggle Output select
ETM CCRA Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=3
Rev. 1.40
1ꢁ0
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnCCLR = 1; TnB� [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared bꢀ CCRA value
0xFFFF
CCRA
CCRB
CCRA=0
Resume
Pause
Stop Counter Restart
Time
TnON
TnPAU
TnBPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affected bꢀ
TnBF flag. Remains High
until reset bꢀ TnON bit
Output Toggle with
TnBF flag
Output Inverts
when TnBPOL is high
Output pin set to
initial Level Low
if TnBOC=0
Output Pin
Reset to Initial value
Output controlled bꢀ
other pin-shared function
Note TnBIO [1:0] = 10
Active High Output select
Here TnBIO [1:0] = 11
Toggle Output select
ETM CCRB Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnBFꢀflag
3.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=3
Rev. 1.40
1ꢁ1
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregisterꢀ
shouldꢀallꢀbeꢀsetꢀhigh.ꢀTheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀ
MatchꢀOutputꢀModeꢀgeneratingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/Counterꢀ
ModeꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀ
CompareꢀMatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀ
usedꢀinꢀthisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀtheꢀrequiredꢀbitꢀpairs,ꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀshouldꢀbeꢀsetꢀ
toꢀ10ꢀrespectivelyꢀandꢀalsoꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀ
respectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀtheꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀ
suchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀ
frequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀTMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀ
generatedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀisꢀusedꢀtoꢀdetermineꢀinꢀwhichꢀ
wayꢀtheꢀPWMꢀperiodꢀisꢀcontrolled.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀtheꢀPWMꢀperiodꢀcanꢀbeꢀfinelyꢀ
controlledꢀusingꢀtheꢀCCRAꢀregisters.ꢀInꢀthisꢀcaseꢀtheꢀCCRBꢀregistersꢀareꢀusedꢀtoꢀsetꢀtheꢀPWMꢀdutyꢀ
valueꢀ(forꢀTPnBꢀoutputꢀpins).ꢀTheꢀCCRPꢀbitsꢀareꢀnotꢀusedꢀandꢀTPnAꢀoutputꢀpinꢀisꢀnotꢀused.ꢀTheꢀ
PWMꢀoutputꢀcanꢀonlyꢀbeꢀgeneratedꢀonꢀtheꢀTPnBꢀoutputꢀpins.ꢀWithꢀtheꢀTnCCLRꢀbitꢀclearedꢀtoꢀzero,ꢀ
theꢀPWMꢀperiodꢀisꢀsetꢀusingꢀtheꢀeightꢀCCRPꢀbits,ꢀinꢀmultiplesꢀofꢀ256.ꢀNowꢀbothꢀCCRAꢀandꢀCCRBꢀ
registersꢀcanꢀbeꢀusedꢀtoꢀsetupꢀdifferentꢀdutyꢀcycleꢀvaluesꢀtoꢀprovideꢀdualꢀPWMꢀoutputsꢀonꢀtheirꢀ
relativeꢀTPnAꢀandꢀTPnBꢀpins.
TheꢀTnPWM1ꢀandꢀTnPWM0ꢀbitsꢀdetermineꢀtheꢀPWMꢀalignmentꢀtype,ꢀwhichꢀcanꢀbeꢀeitherꢀedgeꢀ
orꢀcentreꢀtype.ꢀInꢀedgeꢀalignment,ꢀtheꢀleadingꢀedgeꢀofꢀtheꢀPWMꢀsignalsꢀwillꢀallꢀbeꢀgeneratedꢀ
concurrentlyꢀwhenꢀtheꢀcounterꢀisꢀresetꢀtoꢀzero.ꢀWithꢀallꢀpowerꢀcurrentsꢀswitchingꢀonꢀatꢀtheꢀsameꢀ
time,ꢀthisꢀmayꢀgiveꢀriseꢀtoꢀproblemsꢀinꢀhigherꢀpowerꢀapplications.ꢀInꢀcentreꢀalignmentꢀtheꢀcentreꢀ
ofꢀtheꢀPWMꢀactiveꢀsignalsꢀwillꢀoccurꢀsequentially,ꢀthusꢀreducingꢀtheꢀlevelꢀofꢀsimultaneousꢀpowerꢀ
switchingꢀcurrents.
Interruptꢀflags,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRA,ꢀCCRBꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀeitherꢀtheꢀComparatorꢀA,ꢀComparatorꢀBꢀorꢀComparatorꢀP.ꢀTheꢀTnAOCꢀandꢀ
TnBOCꢀbitsꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregisterꢀareꢀusedꢀtoꢀselectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀ
waveformꢀwhileꢀtheꢀtwoꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀpairsꢀareꢀusedꢀtoꢀenableꢀtheꢀ
PWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnAPOLꢀandꢀTnBPOLꢀ
bitꢀareꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
Rev. 1.40
1ꢁꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
CCRP
Period
A Dutꢀ
B Dutꢀ
1
2
…
127
128
…
254
255
1×ꢁ56
ꢁ×ꢁ56
…
1ꢁꢃ×ꢁ56 1ꢁ8×ꢁ56
CCRA
…
ꢁ54×ꢁ56 ꢁ55×ꢁ56
CCRB
IfꢀfSYS=16MHz,ꢀTMꢀclockꢀsourceꢀselectꢀfSYS/4,ꢀCCRP=2,ꢀCCRA=128ꢀandꢀCCRB=256,
TheꢀTP1AꢀPWMꢀoutputꢀfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,ꢀduty=128/512=25%.
TheꢀTP1BꢀPWMꢀoutputꢀfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,ꢀduty=256/512=50%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀCCRAꢀorꢀCCRBꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀ
thenꢀtheꢀPWMꢀoutputꢀdutyꢀisꢀ100%.
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
CCRA
Period
B Dutꢀ
1
2
…
32767
32768
…
65534
65535
1
ꢁ
…
3ꢁꢃ6ꢃ
3ꢁꢃ68
…
65534
65535
CCRB
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
CCRP
Period
A Dutꢀ
B Dutꢀ
1
2
…
127
128
…
254
255
1×ꢁ56
ꢁ×ꢁ56
…
1ꢁꢃ×ꢁ56 1ꢁ8×ꢁ56
(CCRA × ꢁ) - 1
…
ꢁ54×ꢁ56 ꢁ55×ꢁ56
(CCRB × ꢁ) - 1
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
CCRA
Period
B Dutꢀ
1
2
…
32767
32768
…
65534
65535
ꢁ
4
…
65534
65536
…
131068
1310ꢃ0
(CCRB × ꢁ) - 1
Rev. 1.40
1ꢁ3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnCCLR = 0; TnPW� [1:0] = 00;
TnA� [1:0] = 10ꢂ TnB� [1:0] = 10
Counter Cleared bꢀ CCRP
CCRP
CCRA
CCRB
Counter
Restart
Resume
Stop
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Dutꢀ Cꢀcle
set bꢀ CCRA
Dutꢀ Cꢀcle
set bꢀ CCRA
Dutꢀ Cꢀcle
set bꢀ CCRA
Output Inverts
when TnAPOL
is high
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Dutꢀ Cꢀcle
set bꢀ CCRB
Output controlled bꢀ
other pin-shared function Reset to Initial value
Output Pin
PW� Period set bꢀ CCRP
ETM PWM Mode – Edge Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=0ꢀthereforeꢀCCRPꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnAIOꢀ[1:0]ꢀ(orꢀTnBIOꢀ[1:0])=00ꢀorꢀ01
3.ꢀCCRAꢀcontrolsꢀtheꢀTPnAꢀPWMꢀdutyꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
4.ꢀn=3
Rev. 1.40
1ꢁ4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnCCLR = 1; TnPW� [1:0] = 00;
TnB� [1:0] = 10
Counter Cleared bꢀ CCRA
CCRA
CCRB
Counter
Restart
Resume
Stop
Pause
Time
TnON
TnPAU
TnBPOL
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Dutꢀ Cꢀcle
set bꢀ CCRB
Output Pin
Reset to
Initial value
Output Inverts
when TnBPOL
is high
Output controlled bꢀ
other pin-shared function
PW� Period set bꢀ CCRA
ETM PWM Mode – Edge Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=1ꢀthereforeꢀCCRAꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnBIOꢀ[1:0]=00ꢀorꢀ01
3.ꢀCCRAꢀcontrolsꢀtheꢀTPnBꢀPWMꢀperiodꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
4.ꢀHereꢀtheꢀTMꢀpinꢀcontrolꢀregisterꢀshouldꢀnotꢀenableꢀtheꢀTPnAꢀpinꢀasꢀaꢀTMꢀoutputꢀpin
5.ꢀn=3
Rev. 1.40
1ꢁ5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnCCLR = 0; TnPW� [1:0] = 11;
TnA� [1:0] = 10ꢂ TnB� [1:0] = 10
CCRP
CCRA
CCRB
Counter
Restart
Stop
Resume
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Dutꢀ Cꢀcle set bꢀ CCRA
Output Inverts
when TnAPOL
is high
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Dutꢀ Cꢀcle set bꢀ CCRB
PW� Period set bꢀ CCRP
Output controlled bꢀ
Other pin-shared function
Output Pin
Reset to Initial value
ETM PWM Mode – Centre Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=0ꢀthereforeꢀCCRPꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTnPWMꢀ[1:0]=11ꢀthereforeꢀtheꢀPWMꢀisꢀcentreꢀaligned
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnAIOꢀ[1:0]ꢀ(orꢀTnBIOꢀ[1:0])=00ꢀorꢀ01
4.ꢀCCRAꢀcontrolsꢀtheꢀTPnAꢀPWMꢀdutyꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
5.ꢀCCRPꢀwillꢀgenerateꢀanꢀinterruptꢀrequestꢀwhenꢀtheꢀcounterꢀdecrementsꢀtoꢀitsꢀzeroꢀvalue
6.ꢀn=3
Rev. 1.40
1ꢁ6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
CCRA
TnCCLR = 1; TnPW� [1:0] = 11;
TnB� [1:0] = 10
Counter
Restart
Stop
Resume
Pause
CCRB
Time
TnON
TnPAU
TnBPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Output controlled
bꢀ other pin-shared
function
Output Inverts
when TnBPOL is high
Output Pin
Reset to Initial value
Dutꢀ Cꢀcle set bꢀ CCRB
PW� Period set bꢀ CCRA
ETM PWM Mode – Centre Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=1ꢀthereforeꢀCCRAꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTnPWMꢀ[1:0]=11ꢀthereforeꢀtheꢀPWMꢀisꢀcentreꢀaligned
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnBIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀCCRAꢀcontrolsꢀtheꢀTPnBꢀPWMꢀperiodꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
5.ꢀCCRPꢀwillꢀgenerateꢀanꢀinterruptꢀrequestꢀwhenꢀtheꢀcounterꢀdecrementsꢀtoꢀitsꢀzeroꢀvalue
6.ꢀn=3
Rev. 1.40
1ꢁꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Single Pulse Output Mode
Toꢀselectꢀthisꢀmode,ꢀtheꢀrequiredꢀbitꢀpairs,ꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀshouldꢀbeꢀsetꢀtoꢀ
10ꢀrespectivelyꢀandꢀalsoꢀtheꢀcorrespondingꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀshouldꢀbeꢀ
setꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀ
shotꢀpulseꢀonꢀtheꢀTMꢀoutputꢀpin.
TheꢀtriggerꢀforꢀtheꢀpulseꢀTPnAꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀTnONꢀbit,ꢀwhichꢀ
canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀTheꢀtriggerꢀforꢀtheꢀpulseꢀTPnBꢀoutputꢀleadingꢀ
edgeꢀisꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀB,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀ
program.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀTnONꢀbitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀ
changeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀTCKnꢀpin,ꢀwhichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀ
outputꢀofꢀTPnA.ꢀWhenꢀtheꢀTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀwillꢀstartꢀrunningꢀandꢀ
theꢀpulseꢀleadingꢀedgeꢀofꢀTPnAꢀwillꢀbeꢀgenerated.ꢀTheꢀTnONꢀbitꢀshouldꢀremainꢀhighꢀwhenꢀtheꢀpulseꢀ
isꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀofꢀTPnAꢀandꢀTPnBꢀwillꢀbeꢀgeneratedꢀwhenꢀ
theꢀTnONꢀbitꢀisꢀclearedꢀtoꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀ
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀTnONꢀbitꢀandꢀthusꢀ
generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedgeꢀofꢀTPnAꢀandꢀTPnB.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀ
beꢀusedꢀtoꢀcontrolꢀtheꢀpulseꢀwidthꢀofꢀTPnA.ꢀTheꢀCCRA-CCRBꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀ
pulseꢀwidthꢀofꢀTPnB.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀComparatorꢀBꢀwillꢀalsoꢀgenerateꢀ
TMꢀinterrupts.ꢀTheꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀ
highꢀwhenꢀtheꢀcounterꢀrestarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀTnCCLRꢀbitꢀisꢀalsoꢀ
notꢀused.
Counter Value
CCRA
CCRB
Time
0
CCRA
CCRA
Leading Edge
Trailing Edge
S/W Command
SET“TnON”
or
S/W Command
CLR“TnON”
or
CCRA Compare
�atch
TnON bit
TnON bit
0
1
1
0
TCKn Pin
Transition
TPnA Output Pin
TPnB Output Pin
Pulse Width = CCRA Value
Pulse Width = (CCRA-CCRB) Value
S/W Command
CLR“TnON”
TnON bit
CCRB Compare
�atch
TnON = 1
CCRB
or
1
0
CCRA Compare
�atch
CCRB
Leading Edge
Trailing Edge
Single Pulse Generation
Rev. 1.40
1ꢁ8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
Counter stopped
bꢀ CCRA
TnA� [1:0] = 10ꢂ TnB� [1:0] = 10;
TnAIO [1:0] = 11ꢂ TnBIO [1:0] = 11
Counter Reset
when TnON
returns high
CCRA
CCRB
Counter Stops
bꢀ software
Resume
Pause
Time
TnON
Auto. set bꢀ
TCKn pin
Software Cleared bꢀ
Trigger CCRA match
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
TCKn pin
TnPAU
TCKn pin
Trigger
TnAPOL
TnBPOL
CCRB Int.
Flag TnBF
CCRA Int.
Flag TnAF
TPnA Pin
(TnAOC=1)
Pulse Width
set bꢀ CCRA
TPnA Pin
(TnAOC=0)
Output Inverts
when TnAPOL=1
TPnB Pin
(TnBOC=1)
TPnB Pin
Pulse Width set
bꢀ (CCRA-CCRB)
(TnBOC=0)
Output Inverts
when TnBPOL=1
Single Pulse Mode
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀisꢀtriggeredꢀbyꢀtheꢀTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀTnONꢀbitꢀhigh
4.ꢀAꢀTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀbyꢀtheꢀTnONꢀbitꢀhigh
5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀTnAIOꢀ[1:0]ꢀandꢀTnBIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcanꢀnotꢀbeꢀchanged
6.ꢀn=3
Rev. 1.40
1ꢁ9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregistersꢀ
shouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀThisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀ
presentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀandꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀ
measurements.ꢀTheꢀexternalꢀsignalꢀisꢀsuppliedꢀonꢀtheꢀTPnAꢀandꢀTPnBꢀpins,ꢀwhoseꢀactiveꢀedgeꢀcanꢀ
beꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀ
typeꢀisꢀselectedꢀusingꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀ
registers.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀinitiatedꢀ
usingꢀtheꢀapplicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀTPnAꢀandꢀTPnBꢀpinsꢀtheꢀpresentꢀvalueꢀinꢀ
theꢀcounterꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀCCRAꢀandꢀCCRBꢀregistersꢀandꢀaꢀTMꢀinterruptꢀgenerated.ꢀ
IrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀonꢀtheꢀTPnAꢀandꢀTPnBꢀpinsꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀ
untilꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀ
resetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀ
WhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀaꢀTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀ
CountingꢀtheꢀnumberꢀofꢀoverflowꢀinterruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀ
measuringꢀlongꢀpulseꢀwidths.ꢀTheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀ
triggerꢀedgeꢀonꢀtheꢀTPnAꢀandꢀTPnBꢀpinsꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀedgeꢀtypes.ꢀIfꢀtheꢀ
TnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ
placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀTPnAꢀandꢀTPnBꢀpins,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀ
counterꢀwillꢀcontinueꢀtoꢀrun.
AsꢀtheꢀTPnAꢀandꢀTPnBꢀpinsꢀareꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀTMꢀisꢀinꢀ
theꢀCaptureꢀInputꢀMode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀ
pinꢀmayꢀcauseꢀanꢀinputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀTnCCLR,ꢀTnAOC,ꢀTnBOC,ꢀTnAPOLꢀ
andꢀTnBPOLꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀmode.
Rev. 1.40
130
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnA� [1:0] = 01
Counter cleared
bꢀ CCRP
Counter Counter
Stop Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
T� capture
Pin TPnA
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnAIO [1:0]
Value
00 – Rising edge
01 – Falling edge 10 – Both edges
11 – Disable Capture
ETM CCRA Capture Input Mode
Note:ꢀ1.ꢀTnAMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnAIOꢀ[1:0]ꢀbits
2.ꢀTheꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀTnAOCꢀandꢀTnAPOLꢀbitsꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero
6.ꢀn=3
Rev. 1.40
131
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Counter Value
TnBM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
TM capture
Pin TPnB
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
CCRB
Value
XX
YY
XX
YY
TnBIO [1:0]
Value
00 – Rising edge
01 – Falling edge 10 – Both edges
11 – Disable Capture
ETM CCRB Capture Input Mode
Note:ꢀ1.ꢀTnBMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnBIOꢀ[1:0]ꢀbits
2.ꢀTheꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRB
3.ꢀTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀTnBOCꢀandꢀTnBPOLꢀbitsꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero
6.ꢀn=3
Rev. 1.40
13ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Analog to Digital Converter
Theꢀneedꢀtoꢀinterfaceꢀtoꢀrealꢀworldꢀanalogꢀsignalsꢀisꢀaꢀcommonꢀrequirementꢀforꢀmanyꢀelectronicꢀ
systems.ꢀHowever,ꢀtoꢀproperlyꢀprocessꢀtheseꢀsignalsꢀbyꢀaꢀmicrocontroller,ꢀtheyꢀmustꢀfirstꢀbeꢀ
convertedꢀintoꢀdigitalꢀsignalsꢀbyꢀA/Dꢀconverters.ꢀByꢀintegratingꢀtheꢀA/Dꢀconversionꢀelectronicꢀ
circuitryꢀintoꢀtheꢀmicrocontroller,ꢀtheꢀneedꢀforꢀexternalꢀcomponentsꢀisꢀreducedꢀsignificantlyꢀwithꢀtheꢀ
correspondingꢀfollow-onꢀbenefitsꢀofꢀlowerꢀcostsꢀandꢀreducedꢀcomponentꢀspaceꢀrequirements.
A/D Overview
Theꢀdevicesꢀcontainꢀaꢀmulti-channelꢀanalogꢀtoꢀdigitalꢀconverterꢀwhichꢀcanꢀdirectlyꢀinterfaceꢀtoꢀ
externalꢀanalogꢀsignals,ꢀsuchꢀasꢀthatꢀfromꢀsensorsꢀorꢀotherꢀcontrolꢀsignalsꢀandꢀconvertꢀtheseꢀsignalsꢀ
directlyꢀintoꢀeitherꢀaꢀ12-bitꢀdigitalꢀvalue.
Part No.
Input Channels A/D Channel Select Bits
Input Pins
BC66F840
8
ACS4ꢂ ACSꢁ~ACS0
ACS4~ACS0
AN0~ANꢃ
BC66F850/
BC66F860
16
AN0~AN15
TheꢀaccompanyingꢀblockꢀdiagramꢀshowsꢀtheꢀoverallꢀinternalꢀstructureꢀofꢀtheꢀA/Dꢀconverter,ꢀtogetherꢀ
withꢀitsꢀassociatedꢀregisters.
V
DD
f
SYS
N
ꢁ
ADCKꢁ~ADCK0
PB3/VREF
(N=0~6)
ADOFF
Bit
ACE15~ACE0
VREFS
Bit
A/D Clock
A/D Reference Voltage
AN15
AN14
...
AN1
AN0
ADRL
ADRH
A/D Data
Registers
A/D Converter
V
SS
ADRFS
bit
VBG
ACS4ꢂ
VBGEN
ACS3~ACS0
START EOCB ADOFF
A/D Converter Structure
Rev. 1.40
133
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A/D Converter Register Description
OverallꢀoperationꢀofꢀtheꢀA/Dꢀconverterꢀisꢀcontrolledꢀusingꢀfiveꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀpairꢀ
existsꢀtoꢀstoreꢀtheꢀADCꢀdataꢀ12-bitꢀvalue.ꢀTheꢀremainingꢀthreeꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀ
setupꢀtheꢀoperatingꢀandꢀcontrolꢀfunctionꢀofꢀtheꢀA/Dꢀconverter.
Bit
Register Name
7
6
5
4
3
2
1
0
ADRL
(ADRFS=0)
D3
Dꢁ
D1
D0
—
—
—
—
ADRL
(ADRFS=1)
Dꢃ
D11
—
D6
D10
—
D5
D9
—
D4
D8
—
D3
Dꢃ
Dꢁ
D6
D1
D5
D0
D4
ADRH
(ADRFS=0)
ADRH
(ADRFS=1)
D11
D10
D9
D8
ADCR0
ADCR1
ACERL
START
ACS4
ACEꢃ
EOCB
VBGEN
ACE6
ADOFF ADRFS
—
—
ACSꢁ
ACS1
ACS0
—
VREFS
ACE4
ADCKꢁ ADCK1 ADCK0
ACE5
ACE3
ACEꢁ
ACE1
ACE0
A/D Converter Register List – BC66F840
Bit
Register Name
7
6
5
4
3
2
1
0
ADRL
(ADRFS=0)
D3
Dꢁ
D1
D0
—
—
—
—
ADRL
(ADRFS=1)
Dꢃ
D11
—
D6
D10
—
D5
D9
—
D4
D8
—
D3
Dꢃ
Dꢁ
D6
D1
D5
D0
D4
ADRH
(ADRFS=0)
ADRH
(ADRFS=1)
D11
D10
D9
D8
ADCR0
ADCR1
ACERL
ACERH
START EOCB
ACS4 VBGEN
ADOFF ADRFS
ACS3
—
ACSꢁ
ACS1
ACS0
—
VREFS
ACE4
ADCKꢁ ADCK1 ADCK0
ACEꢃ
ACE6
ACE5
ACE13
ACE3
ACE11
ACEꢁ
ACE1
ACE9
ACE0
ACE8
ACE15 ACE14
ACE1ꢁ
ACE10
A/D Converter Register List – BC66F850/BC66F860
Rev. 1.40
134
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A/D Converter Data Registers – ADRL, ADRH
Asꢀtheꢀdevicesꢀcontainꢀanꢀinternalꢀ12-bitꢀA/Dꢀconverter,ꢀtheyꢀrequireꢀtwoꢀdataꢀregistersꢀtoꢀstoreꢀtheꢀ
convertedꢀvalue.ꢀTheseꢀareꢀaꢀhighꢀbyteꢀregister,ꢀknownꢀasꢀADRH,ꢀandꢀaꢀlowꢀbyteꢀregister,ꢀknownꢀ
asꢀADRL.ꢀAfterꢀtheꢀconversionꢀprocessꢀtakesꢀplace,ꢀtheseꢀregistersꢀcanꢀbeꢀdirectlyꢀreadꢀbyꢀtheꢀ
microcontrollerꢀtoꢀobtainꢀtheꢀdigitisedꢀconversionꢀvalue.ꢀAsꢀonlyꢀ12ꢀbitsꢀofꢀtheꢀ16-bitꢀregisterꢀspaceꢀ
isꢀutilised,ꢀtheꢀformatꢀinꢀwhichꢀtheꢀdataꢀisꢀstoredꢀisꢀcontrolledꢀbyꢀtheꢀADRFSꢀbitꢀinꢀtheꢀADCR0ꢀ
registerꢀasꢀshownꢀinꢀtheꢀaccompanyingꢀtable.ꢀD0~D11ꢀareꢀtheꢀA/Dꢀconversionꢀresultꢀdataꢀbits.ꢀAnyꢀ
unusedꢀbitsꢀwillꢀbeꢀreadꢀasꢀzero.
A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERH
ToꢀcontrolꢀtheꢀfunctionꢀandꢀoperationꢀofꢀtheꢀA/Dꢀconverter,ꢀupꢀtoꢀfourꢀcontrolꢀregistersꢀknownꢀasꢀ
ADCR0,ꢀADCR1,ꢀACERLꢀandꢀACERHꢀareꢀprovided.ꢀTheseꢀ8-bitꢀregistersꢀdefineꢀfunctionsꢀsuchꢀ
asꢀtheꢀselectionꢀofꢀwhichꢀanalogꢀchannelꢀisꢀconnectedꢀtoꢀtheꢀinternalꢀA/Dꢀconverter,ꢀtheꢀdigitisedꢀ
dataꢀformat,ꢀtheꢀA/DꢀclockꢀsourceꢀasꢀwellꢀasꢀcontrollingꢀtheꢀstartꢀfunctionꢀandꢀmonitoringꢀtheꢀA/Dꢀ
converterꢀendꢀofꢀconversionꢀstatus.ꢀTheꢀACSꢀbitꢀfieldꢀinꢀtheꢀADCR0ꢀregisterꢀandꢀACS4ꢀbitꢀisꢀtheꢀ
ADCR1ꢀregisterꢀdefineꢀtheꢀADCꢀinputꢀchannelꢀnumber.ꢀAsꢀtheꢀdevicesꢀcontainꢀonlyꢀoneꢀactualꢀ
analogꢀtoꢀdigitalꢀconverterꢀhardwareꢀcircuit,ꢀeachꢀofꢀtheꢀindividualꢀanalogꢀinputsꢀmustꢀbeꢀroutedꢀtoꢀ
theꢀconverter.ꢀItꢀisꢀtheꢀfunctionꢀofꢀtheꢀACS4ꢀandꢀACSꢀbitꢀfieldꢀtoꢀdetermineꢀwhichꢀanalogꢀchannelꢀ
inputꢀpinsꢀorꢀinternalꢀbandgapꢀreferenceꢀvoltageꢀisꢀactuallyꢀconnectedꢀtoꢀtheꢀinternalꢀA/Dꢀconverter.
TheꢀACERLꢀandꢀACERHꢀcontrolꢀregistersꢀcontainꢀtheꢀACEꢀbitꢀfieldꢀwhichꢀdeterminesꢀwhichꢀ
pinsꢀonꢀI/OꢀportsꢀareꢀusedꢀasꢀanalogꢀinputsꢀforꢀtheꢀA/Dꢀconverterꢀinputꢀandꢀwhichꢀpinsꢀareꢀnotꢀtoꢀ
beꢀusedꢀasꢀtheꢀA/Dꢀconverterꢀinput.ꢀSettingꢀtheꢀcorrespondingꢀbitꢀhighꢀwillꢀselectꢀtheꢀA/Dꢀinputꢀ
function,ꢀclearingꢀtheꢀbitꢀtoꢀzeroꢀwillꢀselectꢀeitherꢀtheꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunction.ꢀWhenꢀtheꢀ
pinꢀisꢀselectedꢀtoꢀbeꢀanꢀA/Dꢀinput,ꢀitsꢀoriginalꢀfunctionꢀwhetherꢀitꢀisꢀanꢀI/Oꢀorꢀotherꢀpin-sharedꢀ
functionꢀwillꢀbeꢀremoved.ꢀInꢀaddition,ꢀanyꢀinternalꢀpull-highꢀresistorsꢀconnectedꢀtoꢀtheseꢀpinsꢀwillꢀbeꢀ
automaticallyꢀremovedꢀifꢀtheꢀpinꢀisꢀselectedꢀtoꢀbeꢀanꢀA/Dꢀinput.
Rev. 1.40
135
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ADCR0 Register – BC66F840
Bit
Name
R/W
7
START
R/W
0
6
EOCB
R
5
ADOFF
R/W
1
4
ADRFS
R/W
0
3
2
ACSꢁ
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
—
—
—
POR
1
Bitꢀ7
START:ꢀStartꢀtheꢀA/Dꢀconversion
0→1→0:ꢀstart
0→1:ꢀResetꢀtheꢀA/DꢀconverterꢀandꢀsetꢀEOCBꢀtoꢀ“1”
ThisꢀbitꢀisꢀusedꢀtoꢀinitiateꢀanꢀA/Dꢀconversionꢀprocess.ꢀTheꢀbitꢀisꢀnormallyꢀlowꢀbutꢀifꢀsetꢀ
highꢀandꢀthenꢀclearedꢀlowꢀagain,ꢀtheꢀA/Dꢀconverterꢀwillꢀinitiateꢀaꢀconversionꢀprocess.ꢀ
WhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀA/Dꢀconverterꢀwillꢀbeꢀreset.
Bitꢀ6
Bitꢀ5
EOCB:ꢀEndꢀofꢀA/Dꢀconversionꢀflag
0:ꢀA/Dꢀconversionꢀended
1:ꢀA/Dꢀconversionꢀinꢀprogress
ThisꢀreadꢀonlyꢀflagꢀisꢀusedꢀtoꢀindicateꢀwhenꢀanꢀA/Dꢀconversionꢀprocessꢀhasꢀcompleted.ꢀ
Whenꢀtheꢀconversionꢀprocessꢀisꢀrunning,ꢀtheꢀbitꢀwillꢀbeꢀhigh.
ADOFF:ꢀA/Dꢀmoduleꢀon/offꢀcontrolꢀbit
0:ꢀA/Dꢀmoduleꢀpowerꢀon
1:ꢀA/Dꢀmoduleꢀpowerꢀoff
ThisꢀbitꢀcontrolsꢀtheꢀpowerꢀtoꢀtheꢀA/Dꢀinternalꢀfunction.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀ
toꢀzeroꢀtoꢀenableꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀA/Dꢀconverterꢀwillꢀ
beꢀswitchedꢀoffꢀreducingꢀtheꢀdevicesꢀpowerꢀconsumption.ꢀAsꢀtheꢀA/Dꢀconverterꢀwillꢀ
consumeꢀaꢀlimitedꢀamountꢀofꢀpower,ꢀevenꢀwhenꢀnotꢀexecutingꢀaꢀconversion,ꢀthisꢀmayꢀ
beꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
Note:ꢀ1.ꢀItꢀisꢀrecommendedꢀtoꢀsetꢀADOFF=1ꢀbeforeꢀenteringꢀIDLE/SLEEPꢀModeꢀforꢀ
savingꢀpower.
2.ꢀADOFF=1ꢀwillꢀpowerꢀdownꢀtheꢀADCꢀmodule.
Bitꢀ4
ADRFS:ꢀA/DꢀDataꢀFormatꢀcontrolꢀbit
0:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ7,ꢀLSBꢀisꢀADRLꢀbitꢀ4
1:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ3,ꢀLSBꢀisꢀADRLꢀbitꢀ0
Thisꢀbitꢀcontrolsꢀtheꢀformatꢀofꢀtheꢀ12-bitꢀconvertedꢀA/DꢀvalueꢀinꢀtheꢀtwoꢀA/Dꢀdataꢀ
registers.ꢀDetailsꢀareꢀprovidedꢀinꢀtheꢀA/Dꢀdataꢀregisterꢀsection.
Bitꢀ3ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ2~0
ACS2~ACS0:ꢀSelectꢀA/Dꢀchannelꢀ(whenꢀACS4ꢀisꢀ0)
000:ꢀAN0
001:ꢀAN1
010:ꢀAN2
011:ꢀAN3
100:ꢀAN4
101:ꢀAN5
110:ꢀAN6
111:ꢀAN7
Rev. 1.40
136
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ADCR0 Register – BC66F850/BC66F860
Bit
Name
R/W
7
START
R/W
0
6
EOCB
R
5
ADOFF
R/W
1
4
ADRFS
R/W
0
3
ACS3
R/W
0
2
ACSꢁ
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
POR
1
Bitꢀ7
START:ꢀStartꢀtheꢀA/Dꢀconversion
0→1→0:ꢀstart
0→1:ꢀResetꢀtheꢀA/DꢀconverterꢀandꢀsetꢀEOCBꢀtoꢀ“1”
ThisꢀbitꢀisꢀusedꢀtoꢀinitiateꢀanꢀA/Dꢀconversionꢀprocess.ꢀTheꢀbitꢀisꢀnormallyꢀlowꢀbutꢀifꢀsetꢀ
highꢀandꢀthenꢀclearedꢀlowꢀagain,ꢀtheꢀA/Dꢀconverterꢀwillꢀinitiateꢀaꢀconversionꢀprocess.ꢀ
WhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀA/Dꢀconverterꢀwillꢀbeꢀreset.
Bitꢀ6
Bitꢀ5
EOCB:ꢀEndꢀofꢀA/Dꢀconversionꢀflag
0:ꢀA/Dꢀconversionꢀended
1:ꢀA/Dꢀconversionꢀinꢀprogress
ThisꢀreadꢀonlyꢀflagꢀisꢀusedꢀtoꢀindicateꢀwhenꢀanꢀA/Dꢀconversionꢀprocessꢀhasꢀcompleted.ꢀ
Whenꢀtheꢀconversionꢀprocessꢀisꢀrunning,ꢀtheꢀbitꢀwillꢀbeꢀhigh.
ADOFF:ꢀA/Dꢀmoduleꢀon/offꢀcontrolꢀbit
0:ꢀA/Dꢀmoduleꢀpowerꢀon
1:ꢀA/Dꢀmoduleꢀpowerꢀoff
ThisꢀbitꢀcontrolsꢀtheꢀpowerꢀtoꢀtheꢀA/Dꢀinternalꢀfunction.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀ
toꢀzeroꢀtoꢀenableꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀA/Dꢀconverterꢀwillꢀ
beꢀswitchedꢀoffꢀreducingꢀtheꢀdevicesꢀpowerꢀconsumption.ꢀAsꢀtheꢀA/Dꢀconverterꢀwillꢀ
consumeꢀaꢀlimitedꢀamountꢀofꢀpower,ꢀevenꢀwhenꢀnotꢀexecutingꢀaꢀconversion,ꢀthisꢀmayꢀ
beꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
Note:ꢀ1.ꢀItꢀisꢀrecommendedꢀtoꢀsetꢀADOFF=1ꢀbeforeꢀenteringꢀIDLE/SLEEPꢀModeꢀforꢀ
savingꢀpower.
2.ꢀADOFF=1ꢀwillꢀpowerꢀdownꢀtheꢀADCꢀmodule.
Bitꢀ4
ADRFS:ꢀA/DꢀDataꢀFormatꢀcontrolꢀbit
0:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ7,ꢀLSBꢀisꢀADRLꢀbitꢀ4
1:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ3,ꢀLSBꢀisꢀADRLꢀbitꢀ0
Thisꢀbitꢀcontrolsꢀtheꢀformatꢀofꢀtheꢀ12-bitꢀconvertedꢀA/DꢀvalueꢀinꢀtheꢀtwoꢀA/Dꢀdataꢀ
registers.ꢀDetailsꢀareꢀprovidedꢀinꢀtheꢀA/Dꢀdataꢀregisterꢀsection.
Bitꢀ3~0
ACS3~ACS0:ꢀSelectꢀA/Dꢀchannelꢀ(whenꢀACS4ꢀisꢀ0)
0000:ꢀAN0
0001:ꢀAN1
0010:ꢀAN2
0011:ꢀAN3
0100:ꢀAN4
0101:ꢀAN5
0110:ꢀAN6
0111:ꢀAN7
1000:ꢀAN8
1001:ꢀAN9
1010:ꢀAN10
1011:ꢀAN11
1100:ꢀAN12
1101:ꢀAN13
1110:ꢀAN14
1111:ꢀAN15
Rev. 1.40
13ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ADCR1 Register
Bit
7
6
VBGEN
R/W
0
5
4
VREFS
R/W
0
3
2
ADCKꢁ
R/W
0
1
ADCK1
R/W
0
0
ADCK0
R/W
0
Name
R/W
ACS4
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7
ACS4:ꢀSelectꢀinternalꢀbandgapꢀreferenceꢀvoltageꢀasꢀADCꢀinputꢀControl
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀenablesꢀtheꢀinternalꢀbandgapꢀreferenceꢀvoltageꢀtoꢀbeꢀconnectedꢀtoꢀtheꢀA/Dꢀ
converter.ꢀTheꢀVBGENꢀbitꢀmustꢀfirstꢀhaveꢀbeenꢀsetꢀtoꢀenableꢀtheꢀbandgapꢀcircuitꢀ
referenceꢀvoltageꢀtoꢀbeꢀusedꢀbyꢀtheꢀA/Dꢀconverter.ꢀWhenꢀtheꢀACS4ꢀbitꢀisꢀsetꢀhigh,ꢀtheꢀ
BandgapꢀreferenceꢀvoltageꢀwillꢀbeꢀroutedꢀtoꢀtheꢀA/DꢀconverterꢀandꢀtheꢀotherꢀA/Dꢀinputꢀ
channelsꢀdisconnected.
Bitꢀ6
VBGEN:ꢀInternalꢀBandgapꢀreferenceꢀvoltageꢀControl
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀcontrolsꢀtheꢀinternalꢀBandgapꢀcircuitꢀon/offꢀfunctionꢀtoꢀtheꢀA/Dꢀconverter.ꢀ
WhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀbandgapꢀvoltageꢀcanꢀbeꢀusedꢀbyꢀtheꢀA/Dꢀconverter.ꢀIfꢀ
theꢀbandgapꢀvoltageꢀisꢀnotꢀusedꢀbyꢀtheꢀA/DꢀconverterꢀandꢀtheꢀLVR/LVDꢀfunctionꢀ
isꢀdisabledꢀthenꢀtheꢀbandgapꢀreferenceꢀcircuitꢀwillꢀbeꢀautomaticallyꢀswitchedꢀoffꢀtoꢀ
conserveꢀpower.ꢀWhenꢀtheꢀbandgapꢀreferenceꢀvoltageꢀisꢀswitchedꢀonꢀforꢀuseꢀbyꢀtheꢀ
A/Dꢀconverter,ꢀaꢀtimeꢀtBGꢀshouldꢀbeꢀallowedꢀforꢀtheꢀbandgapꢀcircuitꢀtoꢀstabiliseꢀbeforeꢀ
implementingꢀanꢀA/Dꢀconversion.
Bitꢀ5ꢀ
Bitꢀ4
Unimplemented,ꢀreadꢀasꢀ“0”
VREFS:ꢀSelectꢀADCꢀreferenceꢀvoltage
0:ꢀInternalꢀADCꢀpower
1:ꢀVREFꢀpin
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀreferenceꢀvoltageꢀforꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀA/DꢀconverterꢀreferenceꢀvoltageꢀisꢀsuppliedꢀonꢀtheꢀexternalꢀVREFꢀpin.ꢀIfꢀtheꢀ
pinꢀisꢀlow,ꢀthenꢀtheꢀinternalꢀreferenceꢀisꢀusedꢀwhichꢀisꢀtakenꢀfromꢀtheꢀpowerꢀsupplyꢀpinꢀ
VDD.
Bitꢀ3ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ2~0
ADCK2~ADCK0:ꢀSelectꢀADCꢀconverterꢀclockꢀsource
000:ꢀfSYS
001:ꢀfSYS/2
010:ꢀfSYS/4
011:ꢀfSYS/8
100:ꢀfSYS/16
101:ꢀfSYS/32
110:ꢀfSYS/64
111:ꢀUndefined,ꢀcanꢀnotꢀbeꢀused
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter.
Rev. 1.40
138
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ACERL Register
Bit
Name
R/W
7
ACEꢃ
R/W
1
6
ACE6
R/W
1
5
ACE5
R/W
1
4
ACE4
R/W
1
3
ACE3
R/W
1
2
ACEꢁ
R/W
1
1
ACE1
R/W
1
0
ACE0
R/W
1
POR
Bitꢀ7
ACE7:ꢀDefineꢀAN7ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN7
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
ACE6:ꢀDefineꢀAN6ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN6
ACE5:ꢀDefineꢀAN5ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN5
ACE4:ꢀDefineꢀAN4ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN4
ACE3:ꢀDefineꢀAN3ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN3
ACE2:ꢀDefineꢀAN2ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN2
ACE1:ꢀDefineꢀAN1ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN1
ACE0:ꢀDefineꢀAN0ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN0
Rev. 1.40
139
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ACERH Register – BC66F850/BC66F860
Bit
Name
R/W
7
ACE15
R/W
1
6
ACE14
R/W
1
5
ACE13
R/W
1
4
ACE1ꢁ
R/W
1
3
ACE11
R/W
1
2
ACE10
R/W
1
1
ACE9
R/W
1
0
ACE8
R/W
1
POR
Bitꢀ7
ACE15:ꢀDefineꢀAN15ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN15
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
ACE14:ꢀDefineꢀAN14ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN14
ACE13:ꢀDefineꢀAN13ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN13
ACE12:ꢀDefineꢀAN12ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN12
ACE11:ꢀDefineꢀAN11ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN11
ACE10:ꢀDefineꢀAN10ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN10
ACE9:ꢀDefineꢀAN9ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN9
ACE8:ꢀDefineꢀAN8ꢀisꢀA/Dꢀinputꢀorꢀnot
0:ꢀNotꢀA/Dꢀinput
1:ꢀA/Dꢀinput,ꢀAN8
Rev. 1.40
140
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A/D Operation
TheꢀSTARTꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀstartꢀandꢀresetꢀtheꢀA/Dꢀconverter.ꢀWhenꢀtheꢀ
microcontrollerꢀsetsꢀthisꢀbitꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀlowꢀagain,ꢀanꢀanalogꢀtoꢀdigitalꢀconversionꢀ
cycleꢀwillꢀbeꢀinitiated.ꢀWhenꢀtheꢀSTARTꢀbitꢀisꢀbroughtꢀfromꢀlowꢀtoꢀhighꢀbutꢀnotꢀlowꢀagain,ꢀtheꢀ
EOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀwillꢀbeꢀsetꢀhighꢀandꢀtheꢀanalogꢀtoꢀdigitalꢀconverterꢀwillꢀbeꢀreset.ꢀ
ItꢀisꢀtheꢀSTARTꢀbitꢀthatꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀstartꢀoperationꢀofꢀtheꢀinternalꢀanalogꢀtoꢀdigitalꢀ
converter.ꢀ
TheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀindicateꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀ
processꢀisꢀcomplete.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀsetꢀtoꢀ0ꢀbyꢀtheꢀmicrocontrollerꢀafterꢀaꢀconversionꢀ
cycleꢀhasꢀended.ꢀInꢀaddition,ꢀtheꢀcorrespondingꢀA/Dꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀsetꢀinꢀtheꢀinterruptꢀ
controlꢀregister,ꢀandꢀifꢀtheꢀinterruptsꢀareꢀenabled,ꢀanꢀappropriateꢀinternalꢀinterruptꢀsignalꢀwillꢀbeꢀ
generated.ꢀThisꢀA/DꢀinternalꢀinterruptꢀsignalꢀwillꢀdirectꢀtheꢀprogramꢀflowꢀtoꢀtheꢀassociatedꢀA/Dꢀ
internalꢀinterruptꢀaddressꢀforꢀprocessing.ꢀIfꢀtheꢀA/Dꢀinternalꢀinterruptꢀisꢀdisabled,ꢀtheꢀmicrocontrollerꢀ
canꢀbeꢀusedꢀtoꢀpollꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀtoꢀcheckꢀwhetherꢀitꢀhasꢀbeenꢀclearedꢀasꢀanꢀ
alternativeꢀmethodꢀofꢀdetectingꢀtheꢀendꢀofꢀanꢀA/Dꢀconversionꢀcycle.ꢀ
TheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter,ꢀwhichꢀoriginatesꢀfromꢀtheꢀsystemꢀclockꢀfSYS,ꢀcanꢀbeꢀchosenꢀ
toꢀbeꢀeitherꢀfSYSꢀorꢀaꢀsubdividedꢀversionꢀofꢀfSYS.ꢀTheꢀdivisionꢀratioꢀvalueꢀisꢀdeterminedꢀbyꢀtheꢀ
ADCK2~ADCK0ꢀbitsꢀinꢀtheꢀADCR1ꢀregister.
AlthoughꢀtheꢀA/DꢀclockꢀsourceꢀisꢀdeterminedꢀbyꢀtheꢀsystemꢀclockꢀfSYS,ꢀandꢀbyꢀbitsꢀADCK2~ADCK0,ꢀ
thereꢀareꢀsomeꢀlimitationsꢀonꢀtheꢀA/Dꢀclockꢀsourceꢀspeedꢀrangeꢀthatꢀcanꢀbeꢀselected.ꢀAsꢀtheꢀ
recommendedꢀrangeꢀofꢀpermissibleꢀA/Dꢀclockꢀperiod,ꢀtADCK,ꢀisꢀfromꢀ0.5μsꢀtoꢀ10μs,ꢀcareꢀmustꢀbeꢀ
takenꢀforꢀselectedꢀsystemꢀclockꢀfrequencies.ꢀForꢀexample,ꢀifꢀtheꢀsystemꢀclockꢀoperatesꢀatꢀaꢀfrequencyꢀ
ofꢀ4MHz,ꢀtheꢀADCK2~ADCK0ꢀbitsꢀshouldꢀnotꢀbeꢀsetꢀtoꢀ000Bꢀorꢀ110B.ꢀDoingꢀsoꢀwillꢀgiveꢀA/Dꢀ
clockꢀperiodsꢀthatꢀareꢀlessꢀthanꢀtheꢀminimumꢀA/DꢀclockꢀperiodꢀorꢀgreaterꢀthanꢀtheꢀmaximumꢀA/Dꢀ
clockꢀperiodꢀwhichꢀmayꢀresultꢀinꢀinaccurateꢀA/Dꢀconversionꢀvalues.ꢀReferꢀtoꢀtheꢀfollowingꢀtableꢀforꢀ
examples,ꢀwhereꢀvaluesꢀmarkedꢀwithꢀanꢀasteriskꢀ*ꢀshowꢀwhere,ꢀdependingꢀuponꢀtheꢀdevices,ꢀspecialꢀ
careꢀmustꢀbeꢀtaken,ꢀasꢀtheꢀvaluesꢀmayꢀbeꢀlessꢀthanꢀtheꢀspecifiedꢀminimumꢀA/DꢀClockꢀPeriod.
A/D Clock Period (tADCK
)
ADCK2, ADCK2, ADCK2, ADCK2, ADCK2, ADCK2, ADCK2,
ADCK1, ADCK1, ADCK1, ADCK1, ADCK1, ADCK1, ADCK1,
ADCK2,
ADCK1,
ADCK0
=111
fSYS
ADCK0
=000
ADCK0
=001
ADCK0
=010
ADCK0
=011
ADCK0
=100
ADCK0
=101
ADCK0
=110
(fSYS
)
(fSYS/2)
(fSYS/4)
(fSYS/8)
(fSYS/16)
(fSYS/32)
(fSYS/64)
1�Hz
ꢁ�Hz
1μs
2μs
4μs
2μs
8μs
4μs
16μs*
8μs
32μs*
16μs*
8μs
64μs*
32μs*
16μs*
8μs
Undefined
Undefined
Undefined
Undefined
500ns
1μs
4�Hz 250ns*
8�Hz 125ns*
1ꢁ�Hz 83ns*
16�Hz 63ns*
500ns
250ns*
167ns*
125ns*
1μs
2μs
4μs
500ns
333ns*
250ns*
1μs
2μs
4μs
66ꢃns
500ns
1.33μs
1μs
2.67μs
2μs
5.33μs Undefined
4μs
Undefined
A/D Clock Period Examples
Rev. 1.40
141
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Controllingꢀtheꢀpowerꢀon/offꢀfunctionꢀofꢀtheꢀA/Dꢀconverterꢀcircuitryꢀisꢀimplementedꢀusingꢀtheꢀ
ADOFFꢀbitꢀinꢀtheꢀADCR0ꢀregister.ꢀThisꢀbitꢀmustꢀbeꢀzeroꢀtoꢀpowerꢀonꢀtheꢀA/Dꢀconverter.ꢀWhenꢀ
theꢀADOFFꢀbitꢀisꢀclearedꢀtoꢀzeroꢀtoꢀpowerꢀonꢀtheꢀA/Dꢀconverterꢀinternalꢀcircuitryꢀaꢀcertainꢀdelay,ꢀ
asꢀindicatedꢀinꢀtheꢀtimingꢀdiagram,ꢀmustꢀbeꢀallowedꢀbeforeꢀanꢀA/Dꢀconversionꢀisꢀinitiated.ꢀEvenꢀifꢀ
noꢀpinsꢀareꢀselectedꢀforꢀuseꢀasꢀA/DꢀinputsꢀbyꢀclearingꢀtheꢀACE15~ACE0ꢀbitsꢀinꢀtheꢀACERLꢀandꢀ
ACERHꢀregisters,ꢀifꢀtheꢀADOFFꢀbitꢀisꢀzeroꢀthenꢀsomeꢀpowerꢀwillꢀstillꢀbeꢀconsumed.ꢀInꢀpowerꢀ
consciousꢀapplicationsꢀitꢀisꢀthereforeꢀrecommendedꢀthatꢀtheꢀADOFFꢀisꢀsetꢀhighꢀtoꢀreduceꢀpowerꢀ
consumptionꢀwhenꢀtheꢀA/Dꢀconverterꢀfunctionꢀisꢀnotꢀbeingꢀused.
TheꢀreferenceꢀvoltageꢀsupplyꢀtoꢀtheꢀA/DꢀConverterꢀcanꢀbeꢀsuppliedꢀfromꢀeitherꢀtheꢀpositiveꢀpowerꢀ
supplyꢀpin,ꢀVDD,ꢀorꢀfromꢀanꢀexternalꢀreferenceꢀsourcesꢀsuppliedꢀonꢀpinꢀVREF.ꢀTheꢀdesiredꢀselectionꢀ
isꢀmadeꢀusingꢀtheꢀVREFSꢀbit.ꢀAsꢀtheꢀVREFꢀpinꢀisꢀpin-sharedꢀwithꢀotherꢀfunctions,ꢀwhenꢀtheꢀVREFSꢀ
bitꢀisꢀsetꢀhigh,ꢀtheꢀVREFꢀpinꢀfunctionꢀwillꢀbeꢀselectedꢀandꢀtheꢀotherꢀpinꢀfunctionsꢀwillꢀbeꢀdisabledꢀ
automatically.
A/D Input Pins
AllꢀofꢀtheꢀA/Dꢀanalogꢀinputꢀpinsꢀareꢀpin-sharedꢀwithꢀtheꢀI/Oꢀpinsꢀasꢀwellꢀasꢀotherꢀfunctions.ꢀTheꢀ
ACE7~ACE0ꢀbitsꢀinꢀtheꢀACERLꢀregisterꢀtogetherꢀwithꢀtheꢀACE15~ACE8ꢀbitsꢀinꢀtheꢀACERHꢀ
registerꢀforꢀBC66F850ꢀandꢀBC66F860ꢀdevicesꢀdetermineꢀwhetherꢀtheꢀinputꢀpinsꢀareꢀsetupꢀasꢀA/Dꢀ
converterꢀanalogꢀinputsꢀorꢀwhetherꢀtheyꢀhaveꢀotherꢀfunctions.ꢀIfꢀtheꢀACE15~ACE0ꢀbitsꢀforꢀitsꢀ
correspondingꢀpinꢀisꢀsetꢀhighꢀthenꢀtheꢀpinꢀwillꢀbeꢀsetupꢀtoꢀbeꢀanꢀA/Dꢀconverterꢀinputꢀandꢀtheꢀoriginalꢀ
pinꢀfunctionsꢀdisabled.ꢀInꢀthisꢀway,ꢀpinsꢀcanꢀbeꢀchangedꢀunderꢀprogramꢀcontrolꢀtoꢀchangeꢀtheirꢀ
functionꢀbetweenꢀA/Dꢀinputsꢀandꢀotherꢀfunctions.ꢀAllꢀpull-highꢀresistors,ꢀwhichꢀareꢀsetupꢀthroughꢀ
registerꢀprogramming,ꢀwillꢀbeꢀautomaticallyꢀdisconnectedꢀifꢀtheꢀpinsꢀareꢀsetupꢀasꢀA/Dꢀinputs.ꢀNoteꢀ
thatꢀitꢀisꢀnotꢀnecessaryꢀtoꢀfirstꢀsetupꢀtheꢀA/Dꢀpinꢀasꢀanꢀinputꢀinꢀtheꢀportꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀ
A/DꢀinputꢀasꢀwhenꢀtheꢀACE15~ACE0ꢀbitsꢀenableꢀanꢀA/Dꢀinput,ꢀtheꢀstatusꢀofꢀtheꢀportꢀcontrolꢀregisterꢀ
willꢀbeꢀoverridden.
TheꢀA/DꢀconverterꢀhasꢀitsꢀownꢀreferenceꢀvoltageꢀpinꢀVREFꢀhoweverꢀtheꢀreferenceꢀvoltageꢀcanꢀ
alsoꢀbeꢀsuppliedꢀfromꢀtheꢀpowerꢀsupplyꢀpin,ꢀaꢀchoiceꢀwhichꢀisꢀmadeꢀthroughꢀtheꢀVREFSꢀbitꢀinꢀtheꢀ
ADCR1ꢀregister.ꢀTheꢀanalogꢀinputꢀvaluesꢀmustꢀnotꢀbeꢀallowedꢀtoꢀexceedꢀtheꢀvalueꢀofꢀVREF
.
P
A
A
0
0
N
/
P
E
A
7
1
N
/
5
V
B
G
A
C
~
S
C
A
4
0
S
I
p
n
u
V
o
t
t
l
g
a
e
B
f
u
e
f
r
V
B
N
G
E
I
n
r
n
t
a
e
l
V
R
S
E
F
1
-
2
i
t
b
D
A
C
R
f
e
r
e
e
n
e
c
V
l
t
o
g
a
e
V
D
D
V
R
F
E
P
A
/
R
3
V
F
E
A/D Input Structure
Rev. 1.40
14ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Summary of A/D Conversion Steps
Theꢀfollowingꢀsummarisesꢀtheꢀindividualꢀstepsꢀthatꢀshouldꢀbeꢀexecutedꢀinꢀorderꢀtoꢀimplementꢀanꢀ
A/Dꢀconversionꢀprocess.
•ꢀ Stepꢀ1
SelectꢀtheꢀrequiredꢀA/DꢀconversionꢀclockꢀbyꢀcorrectlyꢀprogrammingꢀbitsꢀADCK2~ADCK0ꢀinꢀtheꢀ
ADCR1ꢀregister.
•ꢀ Stepꢀ2
EnableꢀtheꢀA/DꢀbyꢀclearingꢀtheꢀADOFFꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀtoꢀzero.
•ꢀ Stepꢀ3
SelectꢀwhichꢀchannelꢀisꢀtoꢀbeꢀconnectedꢀtoꢀtheꢀinternalꢀA/Dꢀconverterꢀbyꢀcorrectlyꢀprogrammingꢀ
theꢀACS4ꢀandꢀACS3~ACS0ꢀbitsꢀwhichꢀareꢀalsoꢀcontainedꢀinꢀtheꢀADCR1ꢀandꢀADCR0ꢀregisters.
•ꢀ Stepꢀ4
SelectꢀwhichꢀpinsꢀareꢀtoꢀbeꢀusedꢀasꢀA/Dꢀinputsꢀandꢀconfigureꢀthemꢀbyꢀcorrectlyꢀprogrammingꢀtheꢀ
ACE15~ACE0ꢀbitsꢀinꢀtheꢀACERLꢀandꢀACERHꢀregisters.
•ꢀ Stepꢀ5
Ifꢀtheꢀinterruptsꢀareꢀtoꢀbeꢀused,ꢀtheꢀinterruptꢀcontrolꢀregistersꢀmustꢀbeꢀcorrectlyꢀconfiguredꢀtoꢀ
ensureꢀtheꢀA/Dꢀconverterꢀinterruptꢀfunctionꢀisꢀactive.ꢀTheꢀmasterꢀinterruptꢀcontrolꢀbit,ꢀEMI,ꢀandꢀ
theꢀA/Dꢀconverterꢀinterruptꢀbit,ꢀADE,ꢀmustꢀbothꢀbeꢀsetꢀtoꢀhighꢀtoꢀdoꢀthis.
•ꢀ Stepꢀ6
TheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀcanꢀnowꢀbeꢀinitialisedꢀbyꢀsettingꢀtheꢀSTARTꢀbitꢀinꢀtheꢀ
ADCR0ꢀregisterꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀtoꢀlowꢀagain.ꢀNoteꢀthatꢀthisꢀbitꢀshouldꢀhaveꢀbeenꢀ
originallyꢀclearedꢀtoꢀ0.
•ꢀ Stepꢀ7
Toꢀcheckꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀcomplete,ꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀ
registerꢀcanꢀbeꢀpolled.ꢀTheꢀconversionꢀprocessꢀisꢀcompleteꢀwhenꢀthisꢀbitꢀgoesꢀlow.ꢀWhenꢀthisꢀ
occurs,ꢀtheꢀA/DꢀdataꢀregistersꢀADRLꢀandꢀADRHꢀcanꢀbeꢀreadꢀtoꢀobtainꢀtheꢀconversionꢀvalue.ꢀAsꢀ
anꢀalternativeꢀmethodꢀifꢀtheꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀtheꢀprogramꢀcanꢀwaitꢀ
forꢀanꢀA/Dꢀinterruptꢀtoꢀoccur.
Note:ꢀWhenꢀcheckingꢀforꢀtheꢀendꢀofꢀtheꢀconversionꢀprocess,ꢀifꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCBꢀ
bitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀused,ꢀtheꢀinterruptꢀenableꢀstepꢀaboveꢀcanꢀbeꢀomitted.
Theꢀaccompanyingꢀdiagramꢀshowsꢀgraphicallyꢀtheꢀvariousꢀstagesꢀinvolvedꢀinꢀanꢀanalogꢀtoꢀdigitalꢀ
conversionꢀprocessꢀandꢀitsꢀassociatedꢀtiming.ꢀAfterꢀanꢀA/Dꢀconversionꢀprocessꢀhasꢀbeenꢀinitiatedꢀ
byꢀtheꢀapplicationꢀprogram,ꢀtheꢀmicrocontrollerꢀinternalꢀhardwareꢀwillꢀbeginꢀtoꢀcarryꢀoutꢀtheꢀ
conversion,ꢀduringꢀwhichꢀtimeꢀtheꢀprogramꢀcanꢀcontinueꢀwithꢀotherꢀfunctions.ꢀTheꢀtimeꢀtakenꢀforꢀtheꢀ
A/Dꢀconversionꢀisꢀ16ꢀtADCKꢀwhereꢀtADCKꢀisꢀequalꢀtoꢀtheꢀA/Dꢀclockꢀperiod.
Rev. 1.40
143
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A
O
D
F
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2
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A
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0
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1
1
0
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0
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1
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1
0
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A/D Conversion Timing
Programming Considerations
DuringꢀmicrocontrollerꢀoperatesꢀwhereꢀtheꢀA/Dꢀconverterꢀisꢀnotꢀbeingꢀused,ꢀtheꢀA/Dꢀinternalꢀ
circuitryꢀcanꢀbeꢀswitchedꢀoffꢀtoꢀreduceꢀpowerꢀconsumption,ꢀbyꢀsettingꢀbitꢀADOFFꢀhighꢀinꢀtheꢀ
ADCR0ꢀregister.ꢀWhenꢀthisꢀhappens,ꢀtheꢀinternalꢀA/Dꢀconverterꢀcircuitsꢀwillꢀnotꢀconsumeꢀpowerꢀ
irrespectiveꢀofꢀwhatꢀanalogꢀvoltageꢀisꢀappliedꢀtoꢀtheirꢀinputꢀlines.ꢀIfꢀtheꢀA/Dꢀconverterꢀinputꢀlinesꢀareꢀ
usedꢀasꢀnormalꢀI/Os,ꢀthenꢀcareꢀmustꢀbeꢀtakenꢀasꢀifꢀtheꢀinputꢀvoltageꢀisꢀnotꢀatꢀaꢀvalidꢀlogicꢀlevel,ꢀthenꢀ
thisꢀmayꢀleadꢀtoꢀsomeꢀincreaseꢀinꢀpowerꢀconsumption.
Theꢀpower-onꢀresetꢀconditionꢀofꢀtheꢀA/Dꢀconverterꢀcontrolꢀregistersꢀwillꢀensureꢀthatꢀtheꢀsharedꢀ
functionꢀpinsꢀareꢀsetupꢀasꢀA/Dꢀconverterꢀinputs.ꢀIfꢀanyꢀofꢀtheꢀA/Dꢀconverterꢀinputꢀpinsꢀareꢀtoꢀbeꢀusedꢀ
forꢀotherꢀfunctions,ꢀthenꢀtheꢀA/Dꢀconverterꢀcontrolꢀregisterꢀbitsꢀmustꢀbeꢀproperlyꢀsetupꢀtoꢀdisableꢀtheꢀ
A/Dꢀinputꢀconfiguration.
A/D Transfer Function
Asꢀtheꢀdevicesꢀcontainꢀaꢀ12-bitꢀA/Dꢀconverter,ꢀitsꢀfull-scaleꢀconvertedꢀdigitisedꢀvalueꢀisꢀequalꢀtoꢀ
FFFH.ꢀSinceꢀtheꢀfull-scaleꢀanalogꢀinputꢀvalueꢀisꢀequalꢀtoꢀtheꢀVDDꢀorꢀVREFꢀvoltage,ꢀthisꢀgivesꢀaꢀsingleꢀ
bitꢀanalogꢀinputꢀvalueꢀofꢀVDDꢀorꢀVREFꢀdividedꢀbyꢀ4096.
1ꢀLSB=ꢀ(VDDꢀorꢀVREF)÷4096
TheꢀA/DꢀConverterꢀinputꢀvoltageꢀvalueꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:
A/Dꢀinputꢀvoltageꢀ=ꢀA/Dꢀoutputꢀdigitalꢀvalueꢀ×ꢀ(VDDꢀorꢀVREF)÷4096
Theꢀdiagramꢀshowsꢀtheꢀidealꢀtransferꢀfunctionꢀbetweenꢀtheꢀanalogꢀinputꢀvalueꢀandꢀtheꢀdigitisedꢀ
outputꢀvalueꢀforꢀtheꢀA/Dꢀconverter.ꢀExceptꢀforꢀtheꢀdigitisedꢀzeroꢀvalue,ꢀtheꢀsubsequentꢀdigitisedꢀ
valuesꢀwillꢀchangeꢀatꢀaꢀpointꢀ0.5ꢀLSBꢀbelowꢀwhereꢀtheyꢀwouldꢀchangeꢀwithoutꢀtheꢀoffset,ꢀandꢀtheꢀ
lastꢀfullꢀscaleꢀdigitisedꢀvalueꢀwillꢀchangeꢀatꢀaꢀpointꢀ1.5ꢀLSBꢀbelowꢀtheꢀVDDꢀorꢀVREFꢀlevel.
Rev. 1.40
144
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
1
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Ideal A/D Transfer Function
A/D Programming Examples
TheꢀfollowingꢀtwoꢀprogrammingꢀexamplesꢀillustrateꢀhowꢀtoꢀsetupꢀandꢀimplementꢀanꢀA/Dꢀconversion.ꢀ
Inꢀtheꢀfirstꢀexample,ꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀdetectꢀ
whenꢀtheꢀconversionꢀcycleꢀisꢀcomplete,ꢀwhereasꢀinꢀtheꢀsecondꢀexample,ꢀtheꢀA/Dꢀinterruptꢀisꢀusedꢀtoꢀ
determineꢀwhenꢀtheꢀconversionꢀisꢀcomplete.
Example 1: using an EOCB polling method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
mov ADCR1,a
; select fSYS/8 as A/D clock and switch off the internal Bandgap
; reference voltage
clr ADOFF
mov a,0Fh
mov ACERL,a
mov a,00h
mov ADCR0,a
:
; setup ACERL to configure pins AN0~AN3
; enable and connect AN0 channel to A/D converter
:
start_conversion:
clr START
set START
clr START
; high pulse on start bit to initiate conversion
; reset A/D
; start A/D
polling_EOC:
sz EOCB
; poll the ADCR0 register EOCB bit to detect end of A/D conversion
; continue polling
; read low byte conversion result value
; save result to user defined register
; read high byte conversion result value
; save result to user defined register
jmp polling_EOC
mov a,ADRL
mov ADRL_buffer,a
mov a,ADRH
mov ADRH_buffer,a
:
:
jmp start_conversion ; start next a/d conversion
Rev. 1.40
145
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Example 2: using the interrupt method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
mov ADCR1,a
; select fSYS/8 as A/D clock and switch off the internal Bandgap
; reference voltage
clr ADOFF
mov a,0Fh
mov ACERL,a
mov a,00h
; setup ACERL to configure pins AN0~AN3
mov ADCR0,a
; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START
set START
clr START
clr ADF
set ADE
set EMI
:
; high pulse on START bit to initiate conversion
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
:
; ADC interrupt service routine
; save ACC to user defined memory
; save STATUS to user defined memory
ADC_ISR:
mov acc_stack,a
mov a,STATUS
mov status_stack,a
:
:
mov a,ADRL
mov adrl_buffer,a
mov a,ADRH
mov adrh_buffer,a
:
; read low byte conversion result value
; save result to user defined register
; read high byte conversion result value
; save result to user defined register
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a
mov a,acc_stack
reti
; restore STATUS from user defined memory
; restore ACC from user defined memory
Rev. 1.40
146
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Comparators
Anꢀanalogꢀcomparatorꢀisꢀcontainedꢀwithinꢀtheseꢀdevices.ꢀTheseꢀfunctionsꢀofferꢀflexibilityꢀviaꢀtheirꢀ
registerꢀcontrolledꢀfeaturesꢀsuchꢀasꢀpower-down,ꢀpolarityꢀselect,ꢀhysteresisꢀetc.ꢀInꢀsharingꢀtheirꢀpinsꢀ
withꢀnormalꢀI/OꢀpinsꢀtheꢀcomparatorsꢀdoꢀnotꢀwasteꢀpreciousꢀI/Oꢀpinsꢀifꢀthereꢀfunctionsꢀareꢀotherwiseꢀ
unused.
C
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Comparator
Comparator Operation
Theꢀdevicesꢀcontainꢀaꢀcomparatorꢀfunctionꢀwhichꢀisꢀusedꢀtoꢀcompareꢀtwoꢀanalogꢀvoltagesꢀandꢀ
provideꢀanꢀoutputꢀbasedꢀonꢀtheirꢀdifference.ꢀFullꢀcontrolꢀoverꢀtheꢀinternalꢀcomparatorsꢀisꢀprovidedꢀ
viaꢀtheꢀcontrolꢀregisterꢀCPCꢀassignedꢀtoꢀtheꢀcomparator.ꢀTheꢀcomparatorꢀoutputꢀisꢀrecordedꢀviaꢀaꢀbitꢀ
inꢀtheꢀcontrolꢀregister,ꢀbutꢀcanꢀalsoꢀbeꢀtransferredꢀoutꢀontoꢀaꢀsharedꢀI/Oꢀpin.ꢀAdditionalꢀcomparatorꢀ
functionsꢀinclude,ꢀoutputꢀpolarity,ꢀhysteresisꢀfunctionsꢀandꢀpowerꢀdownꢀcontrol.
Anyꢀpull-highꢀresistorsꢀconnectedꢀtoꢀtheꢀsharedꢀcomparatorꢀinputꢀpinsꢀwillꢀbeꢀautomaticallyꢀ
disconnectedꢀwhenꢀtheꢀcomparatorꢀisꢀenabled.ꢀAsꢀtheꢀcomparatorꢀinputsꢀapproachꢀtheirꢀswitchingꢀ
level,ꢀsomeꢀspuriousꢀoutputꢀsignalsꢀmayꢀbeꢀgeneratedꢀonꢀtheꢀcomparatorꢀoutputꢀdueꢀtoꢀtheꢀslowꢀ
risingꢀorꢀfallingꢀnatureꢀofꢀtheꢀinputꢀsignals.ꢀThisꢀcanꢀbeꢀminimisedꢀbyꢀselectingꢀtheꢀhysteresisꢀ
functionꢀwillꢀapplyꢀaꢀsmallꢀamountꢀofꢀpositiveꢀfeedbackꢀtoꢀtheꢀcomparator.ꢀIdeallyꢀtheꢀcomparatorꢀ
shouldꢀswitchꢀatꢀtheꢀpointꢀwhereꢀtheꢀpositiveꢀandꢀnegativeꢀinputsꢀsignalsꢀareꢀatꢀtheꢀsameꢀvoltageꢀ
level,ꢀhowever,ꢀunavoidableꢀinputꢀoffsetsꢀintroduceꢀsomeꢀuncertaintiesꢀhere.ꢀTheꢀhysteresisꢀfunction,ꢀ
ifꢀenabled,ꢀalsoꢀincreasesꢀtheꢀswitchingꢀoffsetꢀvalue.
Comparator Interrupt
Theꢀcomparatorꢀpossessesꢀitsꢀownꢀinterruptꢀfunction.ꢀWhenꢀtheꢀcomparatorꢀoutputꢀchangesꢀstate,ꢀ
itsꢀrelevantꢀinterruptꢀflagꢀwillꢀbeꢀset,ꢀandꢀifꢀtheꢀcorrespondingꢀinterruptꢀenableꢀbitꢀisꢀset,ꢀthenꢀaꢀjumpꢀ
toꢀitsꢀrelevantꢀinterruptꢀvectorꢀwillꢀbeꢀexecuted.ꢀNoteꢀthatꢀitꢀisꢀtheꢀchangingꢀstateꢀofꢀtheꢀCOUTꢀbitꢀ
andꢀnotꢀtheꢀoutputꢀpinꢀwhichꢀgeneratesꢀanꢀinterrupt.ꢀIfꢀtheꢀmicrocontrollerꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀ
ModeꢀandꢀtheꢀComparatorꢀisꢀenabled,ꢀthenꢀifꢀtheꢀexternalꢀinputꢀlinesꢀcauseꢀtheꢀComparatorꢀoutputꢀtoꢀ
changeꢀstate,ꢀtheꢀresultingꢀgeneratedꢀinterruptꢀflagꢀwillꢀalsoꢀgenerateꢀaꢀwake-up.ꢀIfꢀitꢀisꢀrequiredꢀtoꢀ
disableꢀaꢀwake-upꢀfromꢀoccurring,ꢀthenꢀtheꢀinterruptꢀflagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode.
Programming Considerations
Ifꢀtheꢀcomparatorꢀisꢀenabled,ꢀitꢀwillꢀremainꢀactiveꢀwhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀ
IDLEꢀMode,ꢀhoweverꢀasꢀitꢀwillꢀconsumeꢀaꢀcertainꢀamountꢀofꢀpower,ꢀtheꢀuserꢀmayꢀwishꢀtoꢀconsiderꢀ
disablingꢀitꢀbeforeꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀentered.
AsꢀcomparatorꢀpinsꢀareꢀsharedꢀwithꢀnormalꢀI/OꢀpinsꢀtheꢀI/Oꢀregistersꢀforꢀtheseꢀpinsꢀwillꢀbeꢀreadꢀasꢀ
zeroꢀ(portꢀcontrolꢀregisterꢀisꢀ"1")ꢀorꢀreadꢀasꢀportꢀdataꢀregisterꢀvalueꢀ(portꢀcontrolꢀregisterꢀisꢀ"0")ꢀifꢀtheꢀ
comparatorꢀfunctionꢀisꢀenabled.
Rev. 1.40
14ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
CPC Register
Bit
Name
R/W
7
CSEL
R/W
1
6
5
CPOL
R/W
0
4
COUT
R/W
0
3
2
1
0
CHYEN
R/W
1
CEN
R/W
0
COS
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7ꢀꢀ
CSEL:ꢀSelectꢀComparatorꢀpinsꢀorꢀI/Oꢀpins
0:ꢀI/Oꢀpinꢀselect
1:ꢀComparatorꢀpinꢀselect
ThisꢀisꢀtheꢀComparatorꢀpinꢀorꢀI/Oꢀpinꢀselectꢀbit.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀcomparatorꢀwillꢀ
beꢀselectedꢀandꢀtheꢀtwoꢀcomparatorꢀinputꢀpinsꢀwillꢀbeꢀenabled.ꢀAsꢀaꢀresult,ꢀtheseꢀtwoꢀ
pinsꢀwillꢀloseꢀtheirꢀI/Oꢀpinꢀfunctions.ꢀAnyꢀpull-highꢀconfigurationꢀoptionsꢀassociatedꢀ
withꢀtheꢀcomparatorꢀsharedꢀpinsꢀwillꢀalsoꢀbeꢀautomaticallyꢀdisconnected.
CEN:ꢀComparatorꢀOn/Offꢀcontrol
Bitꢀ6ꢀꢀ
0:ꢀOff
1:ꢀOn
ThisꢀisꢀtheꢀComparatorꢀon/offꢀcontrolꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀtheꢀcomparatorꢀwillꢀbeꢀ
switchedꢀoffꢀandꢀnoꢀpowerꢀconsumedꢀevenꢀifꢀanalogꢀvoltagesꢀareꢀappliedꢀtoꢀitsꢀinputs.ꢀ
Forꢀpowerꢀsensitiveꢀapplicationsꢀthisꢀbitꢀshouldꢀbeꢀclearedꢀtoꢀzeroꢀifꢀtheꢀcomparatorꢀisꢀ
notꢀusedꢀorꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀmode.
CPOL:ꢀComparatorꢀoutputꢀpolarity
Bitꢀ5ꢀ
Bitꢀ4ꢀ
0:ꢀOutputꢀnotꢀinverted
1:ꢀOutputꢀinverted
Thisꢀisꢀtheꢀcomparatorꢀpolarityꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀthenꢀtheꢀCOUTꢀbitꢀwillꢀreflectꢀ
theꢀnon-invertedꢀoutputꢀconditionꢀofꢀtheꢀcomparator.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀcomparatorꢀ
COUTꢀbitꢀwillꢀbeꢀinverted.
COUT:ꢀComparatorꢀoutputꢀbit
CPOL=0
0:ꢀC+ꢀ<ꢀC-
1:ꢀC+ꢀ>ꢀC-
CPOL=1
0:ꢀC+ꢀ>ꢀC-
1:ꢀC+ꢀ<ꢀC-
Thisꢀbitꢀstoresꢀtheꢀcomparatorꢀoutputꢀbit.ꢀTheꢀpolarityꢀofꢀtheꢀbitꢀisꢀdeterminedꢀbyꢀtheꢀ
voltagesꢀonꢀtheꢀcomparatorꢀinputsꢀandꢀbyꢀtheꢀconditionꢀofꢀtheꢀCPOLꢀbit.
Bitꢀ3ꢀ
COS:ꢀOutputꢀpathꢀselect
0:ꢀCXꢀpin
1:ꢀInternalꢀuse
Thisꢀisꢀtheꢀcomparatorꢀoutputꢀpathꢀselectꢀcontrolꢀbit.ꢀIfꢀtheꢀbitꢀisꢀsetꢀtoꢀ"0"ꢀandꢀtheꢀ
CSELꢀbitꢀisꢀ"1"ꢀtheꢀcomparatorꢀoutputꢀisꢀconnectedꢀtoꢀanꢀexternalꢀCXꢀpin.ꢀIfꢀtheꢀbitꢀisꢀ
setꢀtoꢀ"1"ꢀorꢀtheꢀCSELꢀbitꢀisꢀ"0"ꢀtheꢀcomparatorꢀoutputꢀsignalꢀisꢀonlyꢀusedꢀinternallyꢀ
byꢀtheꢀdeviceꢀallowingꢀtheꢀsharedꢀcomparatorꢀoutputꢀpinꢀtoꢀretainꢀitsꢀnormalꢀI/Oꢀ
operation.
Bitꢀ2~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
CHYEN:ꢀHysteresisꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀisꢀtheꢀhysteresisꢀcontrolꢀbitꢀandꢀifꢀsetꢀhighꢀwillꢀapplyꢀaꢀlimitedꢀamountꢀofꢀ
hysteresisꢀtoꢀtheꢀcomparator,ꢀasꢀspecifiedꢀinꢀtheꢀComparatorꢀElectricalꢀCharacteristicsꢀ
table.ꢀTheꢀpositiveꢀfeedbackꢀinducedꢀbyꢀhysteresisꢀreducesꢀtheꢀeffectꢀofꢀspuriousꢀ
switchingꢀnearꢀtheꢀcomparatorꢀthreshold.
Rev. 1.40
148
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Serial Interface Module – SIM
TheseꢀdevicesꢀcontainꢀaꢀSerialꢀInterfaceꢀModule,ꢀwhichꢀincludesꢀbothꢀtheꢀfourꢀlineꢀSPIꢀinterfaceꢀandꢀ
theꢀtwoꢀlineꢀI2Cꢀinterfaceꢀtypes,ꢀtoꢀallowꢀanꢀeasyꢀmethodꢀofꢀcommunicationꢀwithꢀexternalꢀperipheralꢀ
hardware.ꢀHavingꢀrelativelyꢀsimpleꢀcommunicationꢀprotocols,ꢀtheseꢀserialꢀinterfaceꢀtypesꢀallowꢀ
theꢀmicrocontrollerꢀtoꢀinterfaceꢀtoꢀexternalꢀSPIꢀorꢀI2Cꢀbasedꢀhardwareꢀsuchꢀasꢀsensors,ꢀFlashꢀorꢀ
EEPROMꢀmemory,ꢀetc.ꢀTheꢀSIMꢀinterfaceꢀpinsꢀareꢀpin-sharedꢀwithꢀotherꢀI/OꢀpinsꢀthereforeꢀtheꢀSIMꢀ
interfaceꢀfunctionꢀmustꢀfirstꢀbeꢀselectedꢀusingꢀaꢀconfigurationꢀoption.ꢀAsꢀbothꢀinterfaceꢀtypesꢀshareꢀ
theꢀsameꢀpinsꢀandꢀregisters,ꢀtheꢀchoiceꢀofꢀwhetherꢀtheꢀSPIꢀorꢀI2CꢀtypeꢀisꢀusedꢀisꢀmadeꢀusingꢀtheꢀSIMꢀ
operatingꢀmodeꢀcontrolꢀbits,ꢀnamedꢀSIM2~SIM0,ꢀinꢀtheꢀSIMC0ꢀregister.ꢀTheseꢀpull-highꢀresistorsꢀ
ofꢀtheꢀSIMꢀpin-sharedꢀI/Oꢀpinsꢀareꢀselectedꢀusingꢀpull-highꢀcontrolꢀregistersꢀandꢀalsoꢀifꢀtheꢀSIMꢀ
functionꢀisꢀenabled.
SPI Interface
TheꢀSPIꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
FlashꢀorꢀEEPROMꢀmemoryꢀdevicesꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIꢀ
interfaceꢀisꢀaꢀsynchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀ
simplifyingꢀtheꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀtheseꢀdevicesꢀprovidedꢀonlyꢀoneꢀSCSꢀpin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ
multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinꢀtoꢀselectꢀtheꢀslaveꢀdevices.
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SPI Block Diagram
Rev. 1.40
149
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPI Interface Operation
TheꢀSPIꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ
namesꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS.ꢀPinsꢀSDIꢀandꢀSDOꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀDataꢀ
Outputꢀlines,ꢀSCKꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀSPIꢀinterfaceꢀ
pinsꢀareꢀpin-sharedꢀwithꢀnormalꢀI/OꢀpinsꢀandꢀwithꢀtheꢀI2Cꢀfunctionꢀpins,ꢀtheꢀSPIꢀinterfaceꢀmustꢀ
firstꢀbeꢀenabledꢀbyꢀselectingꢀtheꢀSIMꢀenableꢀconfigurationꢀoptionꢀandꢀsettingꢀtheꢀcorrectꢀbitsꢀinꢀtheꢀ
SIMC0ꢀandꢀSIMC2ꢀregisters.ꢀAfterꢀtheꢀSPIꢀconfigurationꢀoptionꢀhasꢀbeenꢀconfiguredꢀitꢀcanꢀalsoꢀ
beꢀadditionallyꢀdisabledꢀorꢀenabledꢀusingꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregister.ꢀCommunicationꢀ
betweenꢀdevicesꢀconnectedꢀtoꢀtheꢀSPIꢀinterfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀ
transferꢀinitiationsꢀbeingꢀimplementedꢀbyꢀtheꢀmaster.ꢀTheꢀMasterꢀalsoꢀcontrolsꢀtheꢀclockꢀsignal.ꢀ
AsꢀtheꢀdevicesꢀonlyꢀcontainꢀaꢀsingleꢀSCSꢀpinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilized.ꢀTheꢀSCSꢀpinꢀisꢀ
controlledꢀbyꢀsoftware,ꢀsetꢀCSENꢀbitꢀtoꢀ1ꢀtoꢀenableꢀSCSꢀpinꢀfunction,ꢀsetꢀCSENꢀbitꢀtoꢀ0ꢀtheꢀSCSꢀpinꢀ
willꢀbeꢀfloatingꢀstate.
TheꢀSPIꢀfunctionꢀinꢀtheseꢀdevicesꢀofferꢀtheꢀfollowingꢀfeatures:
•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransfer
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodes
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodes
•ꢀ Transmissionꢀcompleteꢀflag
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedge
•ꢀ WCOLꢀandꢀCSENꢀbitꢀenabledꢀorꢀdisableꢀselect
TheꢀstatusꢀofꢀtheꢀSPIꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀdevicesꢀ
areꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀCSENꢀandꢀ
SIMEN.
ThereꢀareꢀseveralꢀconfigurationꢀoptionsꢀassociatedꢀwithꢀtheꢀSPIꢀinterface.ꢀOneꢀofꢀtheseꢀisꢀtoꢀ
enableꢀtheꢀSIMꢀfunctionꢀwhichꢀselectsꢀtheꢀSIMꢀpinsꢀratherꢀthanꢀnormalꢀI/Oꢀpins.ꢀNoteꢀthatꢀifꢀtheꢀ
configurationꢀoptionꢀdoesꢀnotꢀselectꢀtheꢀSIMꢀfunctionꢀthenꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregisterꢀwillꢀ
haveꢀnoꢀeffect.ꢀAnotherꢀtwoꢀSPIꢀconfigurationꢀoptionsꢀdetermineꢀifꢀtheꢀCSENꢀandꢀWCOLꢀbitsꢀareꢀtoꢀ
beꢀused.
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SPI Master/Slave Connection
Rev. 1.40
150
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPI Registers
ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIꢀinterface.ꢀTheseꢀareꢀ
theꢀSIMDꢀdataꢀregisterꢀandꢀtwoꢀregistersꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC1ꢀregisterꢀisꢀonlyꢀ
usedꢀbyꢀtheꢀI2Cꢀinterface.
Bit
Register
Name
7
SI�ꢁ
Dꢃ
6
SI�1
D6
5
SI�0
D5
4
3
2
1
0
—
SI�C0
SI�D
PCKEN
D4
PCKP1
D3
PCKP0
Dꢁ
SI�EN
D1
D0
TRF
SI�Cꢁ
Dꢃ
D6
CKPOLB
CKEG
�LS
CSEN
WCOL
SIM Registers List
SIMD Register
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀusedꢀ
byꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdevicesꢀwriteꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀ
beꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIꢀbus,ꢀtheꢀ
devicesꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIꢀbusꢀ
mustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
• SIMD Register
Bit
Name
R/W
7
Dꢃ
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
Dꢁ
R/W
x
1
D1
R/W
x
0
D0
R/W
x
POR
“x”: unknown
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIꢀinterface,ꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC2ꢀ
registerꢀalsoꢀhasꢀtheꢀnameꢀSIMAꢀwhichꢀisꢀusedꢀbyꢀtheꢀI2Cꢀfunction.ꢀTheꢀSIMC1ꢀregisterꢀisꢀnotꢀusedꢀ
byꢀtheꢀSPIꢀfunction,ꢀonlyꢀbyꢀtheꢀI2Cꢀfunction.ꢀRegisterꢀSIMC0ꢀisꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀ
functionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀAlthoughꢀnotꢀconnectedꢀwithꢀtheꢀSPIꢀ
function,ꢀtheꢀSIMC0ꢀregisterꢀisꢀalsoꢀusedꢀtoꢀcontrolꢀtheꢀPeripheralꢀClockꢀPrescaler.ꢀRegisterꢀSIMC2ꢀ
isꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀflagꢀetc.
Rev. 1.40
151
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SIMC0 Register
Bit
Name
R/W
7
SI�ꢁ
R/W
1
6
SI�1
R/W
1
5
SI�0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SI�EN
R/W
0
0
—
—
—
POR
Bitꢀ7~5
SIM2, SIM1, SIM0: SIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀTM0.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀ
theꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4
PCKEN:ꢀPCKꢀOutputꢀPinꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ3~2
PCKP1, PCKP0:ꢀSelectꢀPCKꢀoutputꢀpinꢀfrenquency
00:ꢀfSYS
01:ꢀfSYS/4
10:ꢀfSYS/8
11:ꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
15ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SIMC2 Register
Bit
Name
R/W
7
Dꢃ
R/W
0
6
D6
R/W
0
5
CKPOLB
R/W
4
CKEG
R/W
0
3
2
CSEN
R/W
0
1
WCOL
R/W
0
0
�LS
R/W
0
TRF
R/W
0
POR
0
Bitꢀ7~6ꢀ
Bitꢀ5
Undefinedꢀbit
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀtheꢀuserꢀsoftwareꢀprogram.
CKPOLB:ꢀDeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline
0:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀCKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4
CKEG:ꢀDeterminesꢀSPIꢀSCKꢀactiveꢀclockꢀedgeꢀtype
CKPOLB=0
0:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
1:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
CKPOLB=1
0:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
1:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
TheꢀCKEGꢀandꢀCKPOLBꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀoutputsꢀ
andꢀinputsꢀdataꢀonꢀtheꢀSPIꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀdataꢀtransferꢀ
isꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀCKPOLBꢀbitꢀ
determinesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀSCKꢀlineꢀ
willꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀlow,ꢀthenꢀtheꢀSCKꢀ
lineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀCKEGꢀbitꢀdeterminesꢀactiveꢀclockꢀ
edgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀCKPOLBꢀbit.
Bitꢀ3
Bitꢀ2
MLS:ꢀSPIꢀDataꢀshiftꢀorder
0:ꢀLSB
1:ꢀMSB
Thisꢀisꢀtheꢀdataꢀshiftꢀselectꢀbitꢀandꢀisꢀusedꢀtoꢀselectꢀhowꢀtheꢀdataꢀisꢀtransferred,ꢀeitherꢀ
MSBꢀorꢀLSBꢀfirst.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀselectꢀMSBꢀfirstꢀandꢀlowꢀforꢀLSBꢀfirst.
CSEN:ꢀSPIꢀSCSꢀpinꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀCSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀtheꢀ
SCSꢀpinꢀwillꢀbeꢀdisabledꢀandꢀplacedꢀintoꢀaꢀfloatingꢀcondition.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀSCSꢀ
pinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.
NoteꢀthatꢀusingꢀtheꢀCSENꢀbitꢀcanꢀbeꢀdisabledꢀorꢀenabledꢀviaꢀconfigurationꢀoption.
Bitꢀ1
WCOL:ꢀSPIꢀWriteꢀCollisionꢀflag
0:ꢀNoꢀcollision
1:ꢀCollision
TheꢀWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀitꢀ
meansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSIMDꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
NoteꢀthatꢀusingꢀtheꢀWCOLꢀbitꢀcanꢀbeꢀdisabledꢀorꢀenabledꢀviaꢀconfigurationꢀoption.
Bitꢀ0
TRF:ꢀSPIꢀTransmit/ReceiveꢀCompleteꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀTRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀ“1”ꢀautomaticallyꢀwhenꢀ
anꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀsetꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
Itꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
Rev. 1.40
153
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPI Communication
AfterꢀtheꢀSPIꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSIMENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSIMDꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀTRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSIMDꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀtheꢀ
SIMDꢀregister.
TheꢀmasterꢀshouldꢀoutputꢀanꢀSCSꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀclockꢀsignalꢀisꢀprovided.ꢀ
Theꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀmomentꢀrelativeꢀ
toꢀtheꢀSCSꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀbitꢀandꢀCKEGꢀbit.ꢀTheꢀ
accompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSꢀsignalꢀforꢀ
variousꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀandꢀCKEGꢀbits.ꢀTheꢀSPIꢀwillꢀcontinueꢀtoꢀfunctionꢀevenꢀinꢀ
theꢀIDLEꢀMode.
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1
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2
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3
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SPI Master Mode Timing
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SPI Slave Mode Timing – CKEG=0
Rev. 1.40
154
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
S
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SPI Transfer Control Flowchart
Rev. 1.40
155
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
I2C Interface
TheꢀI2Cꢀinterfaceꢀisꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
EEPROMꢀmemoryꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀPhilips,ꢀitꢀisꢀaꢀtwoꢀlineꢀlowꢀspeedꢀserialꢀinterfaceꢀ
forꢀsynchronousꢀserialꢀdataꢀtransfer.ꢀTheꢀadvantageꢀofꢀonlyꢀtwoꢀlinesꢀforꢀcommunication,ꢀrelativelyꢀ
simpleꢀcommunicationꢀprotocolꢀandꢀtheꢀabilityꢀtoꢀaccommodateꢀmultipleꢀdevicesꢀonꢀtheꢀsameꢀbusꢀ
hasꢀmadeꢀitꢀanꢀextremelyꢀpopularꢀinterfaceꢀtypeꢀforꢀmanyꢀapplications.
V
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I2C Master Slave Bus Connection
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I2C Block Diagram
I2C Interface Operation
TheꢀI2Cꢀserialꢀinterfaceꢀisꢀaꢀtwoꢀlineꢀinterface,ꢀaꢀserialꢀdataꢀline,ꢀSDA,ꢀandꢀserialꢀclockꢀline,ꢀSCL.ꢀAsꢀ
manyꢀdevicesꢀmayꢀbeꢀconnectedꢀtogetherꢀonꢀtheꢀsameꢀbus,ꢀtheirꢀoutputsꢀareꢀbothꢀopenꢀdrainꢀtypes.ꢀ
Forꢀthisꢀreasonꢀitꢀisꢀnecessaryꢀthatꢀexternalꢀpull-highꢀresistorsꢀareꢀconnectedꢀtoꢀtheseꢀoutputs.ꢀNoteꢀ
thatꢀnoꢀchipꢀselectꢀlineꢀexists,ꢀasꢀeachꢀdeviceꢀonꢀtheꢀI2Cꢀbusꢀisꢀidentifiedꢀbyꢀaꢀuniqueꢀaddressꢀwhichꢀ
willꢀbeꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.
WhenꢀtwoꢀdevicesꢀcommunicateꢀwithꢀeachꢀotherꢀonꢀtheꢀbidirectionalꢀI2Cꢀbus,ꢀoneꢀisꢀknownꢀasꢀtheꢀ
masterꢀdeviceꢀandꢀoneꢀasꢀtheꢀslaveꢀdevice.ꢀBothꢀmasterꢀandꢀslaveꢀcanꢀtransmitꢀandꢀreceiveꢀdata.ꢀ
However,ꢀitꢀisꢀtheꢀmasterꢀdeviceꢀthatꢀhasꢀoverallꢀcontrolꢀofꢀtheꢀbus.ꢀForꢀtheseꢀdevices,ꢀwhichꢀonlyꢀ
operatesꢀinꢀslaveꢀmode,ꢀthereꢀareꢀtwoꢀmethodsꢀofꢀtransferringꢀdataꢀonꢀtheꢀI2Cꢀbus,ꢀtheꢀslaveꢀtransmitꢀ
modeꢀandꢀtheꢀslaveꢀreceiveꢀmode.
ThereꢀareꢀseveralꢀconfigurationꢀoptionsꢀassociatedꢀwithꢀtheꢀI2Cꢀinterface.ꢀOneꢀofꢀtheseꢀisꢀtoꢀenableꢀ
theꢀfunctionꢀwhichꢀselectsꢀtheꢀSIMꢀpinsꢀratherꢀthanꢀnormalꢀI/Oꢀpins.ꢀNoteꢀthatꢀifꢀtheꢀconfigurationꢀ
optionꢀdoesꢀnotꢀselectꢀtheꢀSIMꢀfunctionꢀthenꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregisterꢀwillꢀhaveꢀnoꢀ
effect.ꢀAꢀconfigurationꢀoptionꢀdeterminesꢀtheꢀdebounceꢀtimeꢀofꢀtheꢀI2Cꢀinterface.ꢀThisꢀusesꢀtheꢀ
systemꢀclockꢀtoꢀinꢀeffectꢀaddꢀaꢀdebounceꢀtimeꢀtoꢀtheꢀexternalꢀclockꢀtoꢀreduceꢀtheꢀpossibilityꢀofꢀ
glitchesꢀonꢀtheꢀclockꢀlineꢀcausingꢀerroneousꢀoperation.ꢀTheꢀdebounceꢀtime,ꢀifꢀselected,ꢀcanꢀbeꢀ
chosenꢀtoꢀbeꢀeitherꢀ2ꢀorꢀ4ꢀsystemꢀclocks.ꢀToꢀachieveꢀtheꢀrequiredꢀI2Cꢀdataꢀtransferꢀspeed,ꢀthereꢀ
existsꢀaꢀrelationshipꢀbetweenꢀtheꢀsystemꢀclock,ꢀfSYS,ꢀandꢀtheꢀI2Cꢀdebounceꢀtime.ꢀForꢀeitherꢀtheꢀI2Cꢀ
StandardꢀorꢀFastꢀmodeꢀoperation,ꢀusersꢀmustꢀtakeꢀcareꢀofꢀtheꢀselectedꢀsystemꢀclockꢀfrequencyꢀandꢀ
theꢀconfiguredꢀdebounceꢀtimeꢀtoꢀmatchꢀtheꢀcriterionꢀshownꢀinꢀtheꢀfollowingꢀtable.
Rev. 1.40
156
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
I2C Debounce Time Selection
No debounce
I2C Standard Mode (100kHz)
fSYS > ꢁ�Hz
I2C Fast Mode (400kHz)
fSYS > 5�Hz
ꢁ sꢀstem clock debounce
4 sꢀstem clock debounce
fSYS > 4�Hz
fSYS > 10�Hz
fSYS > 8�Hz
fSYS > ꢁ0�Hz
I2C Minimum fSYS Frequency
S
T
T
A
s
g
R
i
n
a
l
f
o
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m
M
a
t
s
r
e
S
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s
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l
v
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b
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m
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w
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P
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f
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m
M
a
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e
I2C Registers
ThereꢀareꢀthreeꢀcontrolꢀregistersꢀassociatedꢀwithꢀtheꢀI2Cꢀbus,ꢀSIMC0,ꢀSIMC1ꢀandꢀSIMAꢀandꢀoneꢀ
dataꢀregister,ꢀSIMD.ꢀTheꢀSIMDꢀregister,ꢀwhichꢀisꢀshownꢀinꢀtheꢀaboveꢀSPIꢀsection,ꢀisꢀusedꢀtoꢀstoreꢀ
theꢀdataꢀbeingꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.ꢀBeforeꢀtheꢀmicrocontrollerꢀwritesꢀdataꢀtoꢀ
theꢀI2Cꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀ
receivedꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀmicrocontrollerꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀ
orꢀreceptionꢀofꢀdataꢀfromꢀtheꢀI2CꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
NoteꢀthatꢀtheꢀSIMAꢀregisterꢀalsoꢀhasꢀtheꢀnameꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀfunction.ꢀBitꢀSIMENꢀ
andꢀbitsꢀSIM2~SIM0ꢀinꢀregisterꢀSIMC0ꢀareꢀusedꢀbyꢀtheꢀI2Cꢀinterface.
Bit
Register
Name
7
6
5
4
3
2
1
0
—
SI�C0
SI�C1
SI�D
SI�ꢁ
HCF
Dꢃ
SI�1
HAAS
D6
SI�0
HBB
D5
PCKEN
HTX
PCKP1
TXAK
D3
PCKP0
SRW
Dꢁ
SI�EN
IA�WU
D1
RXAK
D0
D4
SI�A
IICA6
IICA5
IICA4
IICA3
IICAꢁ
IICA1
IICA0
—
IꢁCTOC IꢁCTOEN IꢁCTOF IꢁCTOS5 IꢁCTOS4 IꢁCTOS3 IꢁCTOSꢁ IꢁCTOS1 IꢁCTOS0
I2C Registers List
Rev. 1.40
15ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SIMC0 Register
Bit
Name
R/W
7
SI�ꢁ
R/W
1
6
SI�1
R/W
1
5
SI�0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SI�EN
R/W
0
0
—
—
—
POR
Bitꢀ7~5
SIM2, SIM1, SIM0: SIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀTM0.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀ
theꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4
PCKEN:ꢀPCKꢀOutputꢀPinꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ3~2
PCKP1, PCKP0:ꢀSelectꢀPCKꢀoutputꢀpinꢀfrenquency
00:ꢀfSYS
01:ꢀfSYS/4
10:ꢀfSYS/8
11:ꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
158
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SIMC1 Register
Bit
Name
R/W
7
HCF
R
6
HAAS
R
5
HBB
R
4
3
TXAK
R/W
0
2
SRW
R
1
IA�WU
R/W
0
0
RXAK
R
HTX
R/W
0
POR
1
0
0
0
1
Bitꢀ7
HCF:ꢀI2CꢀBusꢀdataꢀtransferꢀcompletionꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀCompletionꢀofꢀanꢀ8-bitꢀdataꢀtransfer
TheꢀHCFꢀflagꢀisꢀtheꢀdataꢀtransferꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀzeroꢀwhenꢀdataꢀisꢀbeingꢀ
transferred.ꢀUponꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀtransferꢀtheꢀflagꢀwillꢀgoꢀhighꢀandꢀanꢀ
interruptꢀwillꢀbeꢀgenerated.
Bitꢀ6
Bitꢀ5
HAAS:ꢀI2CꢀBusꢀaddressꢀmatchꢀflag
0:ꢀNotꢀaddressꢀmatch
1:ꢀAddressꢀmatch
TheꢀHAASꢀflagꢀisꢀtheꢀaddressꢀmatchꢀflag.ꢀThisꢀflagꢀisꢀusedꢀtoꢀdetermineꢀifꢀtheꢀslaveꢀ
deviceꢀaddressꢀisꢀtheꢀsameꢀasꢀtheꢀmasterꢀtransmitꢀaddress.ꢀIfꢀtheꢀaddressesꢀmatchꢀthenꢀ
thisꢀbitꢀwillꢀbeꢀhigh,ꢀifꢀthereꢀisꢀnoꢀmatchꢀthenꢀtheꢀflagꢀwillꢀbeꢀlow.
HBB:ꢀI2CꢀBusꢀbusyꢀflag
0:ꢀI2CꢀBusꢀisꢀnotꢀbusy
1:ꢀI2CꢀBusꢀisꢀbusy
TheꢀHBBꢀflagꢀisꢀtheꢀI2Cꢀbusyꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀ“1”ꢀwhenꢀtheꢀI2Cꢀbusꢀisꢀbusyꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀSTARTꢀsignalꢀisꢀdetected.ꢀTheꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“0”ꢀwhenꢀ
theꢀbusꢀisꢀfreeꢀwhichꢀwillꢀoccurꢀwhenꢀaꢀSTOPꢀsignalꢀisꢀdetected.
Bitꢀ4
Bitꢀ3
HTX:ꢀSelectꢀI2Cꢀslaveꢀdeviceꢀisꢀtransmitterꢀorꢀreceiver
0:ꢀSlaveꢀdeviceꢀisꢀtheꢀreceiver
1:ꢀSlaveꢀdeviceꢀisꢀtheꢀtransmitter
TXAK:ꢀI2CꢀBusꢀtransmitꢀacknowledgeꢀflag
0:ꢀSlaveꢀsendꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoꢀnotꢀsendꢀacknowledgeꢀflag
TheꢀTXAKꢀbitꢀisꢀtheꢀtransmitꢀacknowledgeꢀflag.ꢀAfterꢀtheꢀslaveꢀdeviceꢀreceiptꢀofꢀ8-bitsꢀ
ofꢀdata,ꢀthisꢀbitꢀwillꢀbeꢀtransmittedꢀtoꢀtheꢀbusꢀonꢀtheꢀ9thꢀclockꢀfromꢀtheꢀslaveꢀdevice.ꢀ
TheꢀslaveꢀdeviceꢀmustꢀalwaysꢀsetꢀTXAKꢀbitꢀtoꢀ“0”ꢀbeforeꢀfurtherꢀdataꢀisꢀreceived.
Bitꢀ2
SRW:ꢀI2CꢀSlaveꢀRead/Writeꢀflag
0:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀreceiveꢀmode
1:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode
TheꢀSRWꢀflagꢀisꢀtheꢀI2CꢀSlaveꢀRead/Writeꢀflag.ꢀThisꢀflagꢀdeterminesꢀwhetherꢀ
theꢀmasterꢀdeviceꢀwishesꢀtoꢀtransmitꢀorꢀreceiveꢀdataꢀfromꢀtheꢀI2Cꢀbus.ꢀWhenꢀtheꢀ
transmittedꢀaddressꢀandꢀslaveꢀaddressꢀisꢀmatch,ꢀthatꢀisꢀwhenꢀtheꢀHAASꢀflagꢀisꢀsetꢀhigh,ꢀ
theꢀslaveꢀdeviceꢀwillꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀwhetherꢀitꢀshouldꢀbeꢀinꢀtransmitꢀ
modeꢀorꢀreceiveꢀmode.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀhigh,ꢀtheꢀmasterꢀisꢀrequestingꢀtoꢀreadꢀdataꢀ
fromꢀtheꢀbus,ꢀsoꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode.ꢀWhenꢀtheꢀSRWꢀflagꢀ
isꢀzero,ꢀtheꢀmasterꢀwillꢀwriteꢀdataꢀtoꢀtheꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀ
receiveꢀmodeꢀtoꢀreadꢀthisꢀdata.
Bitꢀ1
IAMWU:ꢀI2CꢀAddressꢀMatchꢀWake-upꢀControl
0:ꢀDisable
1:ꢀEnableꢀ–ꢀmustꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogramꢀafterꢀwake-up
Thisꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ1ꢀtoꢀenableꢀtheꢀI2CꢀaddressꢀmatchꢀwakeꢀupꢀfromꢀtheꢀSLEEPꢀ
orꢀIDLEꢀMode.ꢀIfꢀtheꢀIAMWUꢀbitꢀhasꢀbeenꢀsetꢀbeforeꢀenteringꢀeitherꢀtheꢀSLEEPꢀorꢀ
IDLEꢀmodeꢀtoꢀenableꢀtheꢀI2Cꢀaddressꢀmatchꢀwakeꢀup,ꢀthenꢀthisꢀbitꢀmustꢀbeꢀclearedꢀbyꢀ
theꢀapplicationꢀprogramꢀafterꢀwake-upꢀtoꢀensureꢀcorrectionꢀdeviceꢀoperation.
Rev. 1.40
159
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ0
RXAK:ꢀI2CꢀBusꢀReceiveꢀacknowledgeꢀflag
0:ꢀSlaveꢀreceiveꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoesꢀnotꢀreceiveꢀacknowledgeꢀflag
TheꢀRXAKꢀflagꢀisꢀtheꢀreceiverꢀacknowledgeꢀflag.ꢀWhenꢀtheꢀRXAKꢀflagꢀisꢀ“0”,ꢀitꢀ
meansꢀthatꢀaꢀacknowledgeꢀsignalꢀhasꢀbeenꢀreceivedꢀatꢀtheꢀ9thꢀclock,ꢀafterꢀ8ꢀbitsꢀofꢀdataꢀ
haveꢀbeenꢀtransmitted.ꢀWhenꢀtheꢀslaveꢀdeviceꢀinꢀtheꢀtransmitꢀmode,ꢀtheꢀslaveꢀdeviceꢀ
checksꢀtheꢀRXAKꢀflagꢀtoꢀdetermineꢀifꢀtheꢀmasterꢀreceiverꢀwishesꢀtoꢀreceiveꢀtheꢀnextꢀ
byte.ꢀTheꢀslaveꢀtransmitterꢀwillꢀthereforeꢀcontinueꢀsendingꢀoutꢀdataꢀuntilꢀtheꢀRXAKꢀ
flagꢀisꢀ“1”.ꢀWhenꢀthisꢀoccurs,ꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀ
theꢀmasterꢀtoꢀsendꢀaꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2CꢀBus.
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀ
usedꢀbyꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdevicesꢀwriteꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀ
dataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀ
SPIꢀbus,ꢀtheꢀdevicesꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀ
fromꢀtheꢀSPIꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
SIMD Register
Bit
7
Dꢃ
R/W
x
6
D6
R/W
X
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
Dꢁ
R/W
x
1
D1
R/W
x
0
Name
R/W
D0
R/W
x
POR
“x”: unknown
SIMA Register
Bit
Name
R/W
7
IICA6
R/W
x
6
IICA5
R/W
X
5
IICA4
R/W
x
4
IICA3
R/W
x
3
IICAꢁ
R/W
x
2
IICA1
R/W
x
1
IICA0
R/W
x
0
—
—
—
POR
“x”: unknown
Bitꢀ7~1
IICA6~IICA0:ꢀI2Cꢀslaveꢀaddress
IICA6~IICA0ꢀisꢀtheꢀI2Cꢀslaveꢀaddressꢀbitꢀ6~bitꢀ0
TheꢀSIMAꢀregisterꢀisꢀalsoꢀusedꢀbyꢀtheꢀSPIꢀinterfaceꢀbutꢀhasꢀtheꢀnameꢀSIMC2.ꢀTheꢀ
SIMAꢀregisterꢀisꢀtheꢀlocationꢀwhereꢀtheꢀ7-bitꢀslaveꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀisꢀ
stored.ꢀBitsꢀ7~1ꢀofꢀtheꢀSIMAꢀregisterꢀdefineꢀtheꢀdeviceꢀslaveꢀaddress.ꢀBitꢀ0ꢀisꢀnotꢀ
defined.
Whenꢀaꢀmasterꢀdevice,ꢀwhichꢀisꢀconnectedꢀtoꢀtheꢀI2Cꢀbus,ꢀsendsꢀoutꢀanꢀaddress,ꢀwhichꢀ
matchesꢀtheꢀslaveꢀaddressꢀinꢀtheꢀSIMAꢀregister,ꢀtheꢀslaveꢀdeviceꢀwillꢀbeꢀselected.ꢀNoteꢀ
thatꢀtheꢀSIMAꢀregisterꢀisꢀtheꢀsameꢀregisterꢀaddressꢀasꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀ
interface.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀuserꢀsoftwareꢀprogram.
Rev. 1.40
160
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
I2C Bus Communication
CommunicationꢀonꢀtheꢀI2Cꢀbusꢀrequiresꢀfourꢀseparateꢀsteps,ꢀaꢀSTARTꢀsignal,ꢀaꢀslaveꢀdeviceꢀaddressꢀ
transmission,ꢀaꢀdataꢀtransmissionꢀandꢀfinallyꢀaꢀSTOPꢀsignal.ꢀWhenꢀaꢀSTARTꢀsignalꢀisꢀplacedꢀonꢀ
theꢀI2Cꢀbus,ꢀallꢀdevicesꢀonꢀtheꢀbusꢀwillꢀreceiveꢀthisꢀsignalꢀandꢀbeꢀnotifiedꢀofꢀtheꢀimminentꢀarrivalꢀofꢀ
dataꢀonꢀtheꢀbus.ꢀTheꢀfirstꢀsevenꢀbitsꢀofꢀtheꢀdataꢀwillꢀbeꢀtheꢀslaveꢀaddressꢀwithꢀtheꢀfirstꢀbitꢀbeingꢀtheꢀ
MSB.ꢀIfꢀtheꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀmatchesꢀthatꢀofꢀtheꢀtransmittedꢀaddress,ꢀtheꢀHAASꢀbitꢀinꢀtheꢀ
SIMC1ꢀregisterꢀwillꢀbeꢀsetꢀandꢀanꢀI2Cꢀinterruptꢀwillꢀbeꢀgenerated.ꢀAfterꢀenteringꢀtheꢀinterruptꢀserviceꢀ
routine,ꢀtheꢀslaveꢀdeviceꢀmustꢀfirstꢀcheckꢀtheꢀconditionꢀofꢀtheꢀHAASꢀbitꢀtoꢀdetermineꢀwhetherꢀtheꢀ
interruptꢀsourceꢀoriginatesꢀfromꢀanꢀaddressꢀmatchꢀorꢀfromꢀtheꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀtransfer.ꢀ
Duringꢀaꢀdataꢀtransfer,ꢀnoteꢀthatꢀafterꢀtheꢀ7-bitꢀslaveꢀaddressꢀhasꢀbeenꢀtransmitted,ꢀtheꢀfollowingꢀbit,ꢀ
whichꢀisꢀtheꢀ8thꢀbit,ꢀisꢀtheꢀread/writeꢀbitꢀwhoseꢀvalueꢀwillꢀbeꢀplacedꢀinꢀtheꢀSRWꢀbit.ꢀThisꢀbitꢀwillꢀbeꢀ
checkedꢀbyꢀtheꢀslaveꢀdeviceꢀtoꢀdetermineꢀwhetherꢀtoꢀgoꢀintoꢀtransmitꢀorꢀreceiveꢀmode.ꢀBeforeꢀanyꢀ
transferꢀofꢀdataꢀtoꢀorꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀmicrocontrollerꢀmustꢀinitialiseꢀtheꢀbus,ꢀtheꢀfollowingꢀareꢀ
stepsꢀtoꢀachieveꢀthis:
Step 1
SetꢀtheꢀSIM2~SIM0ꢀandꢀSIMENꢀbitsꢀinꢀtheꢀSIMC0ꢀregisterꢀtoꢀ1ꢀtoꢀenableꢀtheꢀI2Cꢀbus.
Step 2
WriteꢀtheꢀslaveꢀaddressꢀofꢀtheꢀdevicesꢀtoꢀtheꢀI2CꢀbusꢀaddressꢀregisterꢀSIMA.
Step 3
SetꢀtheꢀSIMEꢀandꢀSIMꢀMulti-Functionꢀinterruptꢀenableꢀbitꢀofꢀtheꢀinterruptꢀcontrolꢀregisterꢀtoꢀenableꢀ
theꢀSIMꢀinterruptꢀandꢀMulti-functionꢀinterrupt.
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I2C Bus Initialisation Flow Chart
Rev. 1.40
161
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
I2C Bus Start Signal
TheꢀSTARTꢀsignalꢀcanꢀonlyꢀbeꢀgeneratedꢀbyꢀtheꢀmasterꢀdeviceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀandꢀnotꢀbyꢀ
theꢀslaveꢀdevice.ꢀThisꢀSTARTꢀsignalꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀconnectedꢀtoꢀtheꢀI2Cꢀbus.ꢀWhenꢀ
detected,ꢀthisꢀindicatesꢀthatꢀtheꢀI2CꢀbusꢀisꢀbusyꢀandꢀthereforeꢀtheꢀHBBꢀbitꢀwillꢀbeꢀset.ꢀAꢀSTARTꢀ
conditionꢀoccursꢀwhenꢀaꢀhighꢀtoꢀlowꢀtransitionꢀonꢀtheꢀSDAꢀlineꢀtakesꢀplaceꢀwhenꢀtheꢀSCLꢀlineꢀ
remainsꢀhigh.
SCL
SDA
Start Bit
Slave Address
TheꢀtransmissionꢀofꢀaꢀSTARTꢀsignalꢀbyꢀtheꢀmasterꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀonꢀtheꢀI2Cꢀbus.ꢀ
Toꢀdetermineꢀwhichꢀslaveꢀdeviceꢀtheꢀmasterꢀwishesꢀtoꢀcommunicateꢀwith,ꢀtheꢀaddressꢀofꢀtheꢀslaveꢀ
deviceꢀwillꢀbeꢀsentꢀoutꢀimmediatelyꢀfollowingꢀtheꢀSTARTꢀsignal.ꢀAllꢀslaveꢀdevices,ꢀafterꢀreceivingꢀ
thisꢀ7-bitꢀaddressꢀdata,ꢀwillꢀcompareꢀitꢀwithꢀtheirꢀownꢀ7-bitꢀslaveꢀaddress.ꢀIfꢀtheꢀaddressꢀsentꢀoutꢀbyꢀ
theꢀmasterꢀmatchesꢀtheꢀinternalꢀaddressꢀofꢀtheꢀmicrocontrollerꢀslaveꢀdevice,ꢀthenꢀanꢀinternalꢀI2Cꢀbusꢀ
interruptꢀsignalꢀwillꢀbeꢀgenerated.ꢀTheꢀnextꢀbitꢀfollowingꢀtheꢀaddress,ꢀwhichꢀisꢀtheꢀ8thꢀbit,ꢀdefinesꢀ
theꢀread/writeꢀstatusꢀandꢀwillꢀbeꢀsavedꢀtoꢀtheꢀSRWꢀbitꢀofꢀtheꢀSIMC1ꢀregister.ꢀTheꢀslaveꢀdeviceꢀwillꢀ
thenꢀtransmitꢀanꢀacknowledgeꢀbit,ꢀwhichꢀisꢀaꢀlowꢀlevel,ꢀasꢀtheꢀ9thꢀbit.ꢀTheꢀslaveꢀdeviceꢀwillꢀalsoꢀsetꢀ
theꢀstatusꢀflagꢀHAASꢀwhenꢀtheꢀaddressesꢀmatch.
AsꢀanꢀI2Cꢀbusꢀinterruptꢀcanꢀcomeꢀfromꢀtwoꢀsources,ꢀwhenꢀtheꢀprogramꢀentersꢀtheꢀinterruptꢀ
subroutine,ꢀtheꢀHAASꢀbitꢀshouldꢀbeꢀexaminedꢀtoꢀseeꢀwhetherꢀtheꢀinterruptꢀsourceꢀhasꢀcomeꢀfromꢀ
aꢀmatchingꢀslaveꢀaddressꢀorꢀfromꢀtheꢀcompletionꢀofꢀaꢀdataꢀbyteꢀtransfer.ꢀWhenꢀaꢀslaveꢀaddressꢀisꢀ
matched,ꢀtheꢀdeviceꢀmustꢀbeꢀplacedꢀinꢀeitherꢀtheꢀtransmitꢀmodeꢀandꢀthenꢀwriteꢀdataꢀtoꢀtheꢀSIMDꢀ
register,ꢀorꢀinꢀtheꢀreceiveꢀmodeꢀwhereꢀitꢀmustꢀimplementꢀaꢀdummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀ
releaseꢀtheꢀSCLꢀline.
I2C Bus Read/Write Signal
TheꢀSRWꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀdefinesꢀwhetherꢀtheꢀslaveꢀdeviceꢀwishesꢀtoꢀreadꢀdataꢀfromꢀtheꢀ
I2CꢀbusꢀorꢀwriteꢀdataꢀtoꢀtheꢀI2Cꢀbus.ꢀTheꢀslaveꢀdeviceꢀshouldꢀexamineꢀthisꢀbitꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀ
beꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ1,ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀdeviceꢀwishesꢀ
toꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀbusꢀasꢀ
aꢀtransmitter.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ0,ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀwishesꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀ
bus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbusꢀasꢀaꢀreceiver.
I2C Bus Slave Address Acknowledge Signal
Afterꢀtheꢀmasterꢀhasꢀtransmittedꢀaꢀcallingꢀaddress,ꢀanyꢀslaveꢀdeviceꢀonꢀtheꢀI2Cꢀbus,ꢀwhoseꢀ
ownꢀinternalꢀaddressꢀmatchesꢀtheꢀcallingꢀaddress,ꢀmustꢀgenerateꢀanꢀacknowledgeꢀsignal.ꢀTheꢀ
acknowledgeꢀsignalꢀwillꢀinformꢀtheꢀmasterꢀthatꢀaꢀslaveꢀdeviceꢀhasꢀacceptedꢀitsꢀcallingꢀaddress.ꢀIfꢀnoꢀ
acknowledgeꢀsignalꢀisꢀreceivedꢀbyꢀtheꢀmasterꢀthenꢀaꢀSTOPꢀsignalꢀmustꢀbeꢀtransmittedꢀbyꢀtheꢀmasterꢀ
toꢀendꢀtheꢀcommunication.ꢀWhenꢀtheꢀHAASꢀflagꢀisꢀhigh,ꢀtheꢀaddressesꢀhaveꢀmatchedꢀandꢀtheꢀslaveꢀ
deviceꢀmustꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀbeꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀ
isꢀhigh,ꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀtoꢀbeꢀaꢀtransmitterꢀsoꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀ
shouldꢀbeꢀsetꢀtoꢀ1.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀlow,ꢀthenꢀtheꢀmicrocontrollerꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀasꢀaꢀ
receiverꢀandꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ0.
Rev. 1.40
16ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
I2C Bus Data and Acknowledge Signal
Theꢀtransmittedꢀdataꢀisꢀ8-bitsꢀwideꢀandꢀisꢀtransmittedꢀafterꢀtheꢀslaveꢀdeviceꢀhasꢀacknowledgedꢀ
receiptꢀofꢀitsꢀslaveꢀaddress.ꢀTheꢀorderꢀofꢀserialꢀbitꢀtransmissionꢀisꢀtheꢀMSBꢀfirstꢀandꢀtheꢀLSBꢀlast.ꢀ
Afterꢀreceiptꢀofꢀ8-bitsꢀofꢀdata,ꢀtheꢀreceiverꢀmustꢀtransmitꢀanꢀacknowledgeꢀsignal,ꢀlevelꢀ0,ꢀbeforeꢀitꢀ
canꢀreceiveꢀtheꢀnextꢀdataꢀbyte.ꢀIfꢀtheꢀslaveꢀtransmitterꢀdoesꢀnotꢀreceiveꢀanꢀacknowledgeꢀbitꢀsignalꢀ
fromꢀtheꢀmasterꢀreceiver,ꢀthenꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀtheꢀmasterꢀ
toꢀsendꢀaꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2CꢀBus.ꢀTheꢀcorrespondingꢀdataꢀwillꢀbeꢀstoredꢀinꢀtheꢀSIMDꢀ
register.ꢀIfꢀsetupꢀasꢀaꢀtransmitter,ꢀtheꢀslaveꢀdeviceꢀmustꢀfirstꢀwriteꢀtheꢀdataꢀtoꢀbeꢀtransmittedꢀintoꢀtheꢀ
SIMDꢀregister.ꢀIfꢀsetupꢀasꢀaꢀreceiver,ꢀtheꢀslaveꢀdeviceꢀmustꢀreadꢀtheꢀtransmittedꢀdataꢀfromꢀtheꢀSIMDꢀ
register.
Whenꢀtheꢀslaveꢀreceiverꢀreceivesꢀtheꢀdataꢀbyte,ꢀitꢀmustꢀgenerateꢀanꢀacknowledgeꢀbit,ꢀknownꢀasꢀ
TXAK,ꢀonꢀtheꢀ9thꢀclock.ꢀTheꢀslaveꢀdevice,ꢀwhichꢀisꢀsetupꢀasꢀaꢀtransmitterꢀwillꢀcheckꢀtheꢀRXAKꢀbitꢀ
inꢀtheꢀSIMC1ꢀregisterꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀsendꢀanotherꢀdataꢀbyte,ꢀifꢀnotꢀthenꢀitꢀwillꢀreleaseꢀtheꢀ
SDAꢀlineꢀandꢀawaitꢀtheꢀreceiptꢀofꢀaꢀSTOPꢀsignalꢀfromꢀtheꢀmaster.
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dummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀreleaseꢀtheꢀSCLꢀline.
I2C Communication Timing Diagram
Rev. 1.40
163
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
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I2C Bus ISR Flow Chart
I2C Time-out Control
InꢀorderꢀtoꢀreduceꢀtheꢀI2Cꢀlockupꢀproblemꢀdueꢀtoꢀreceptionꢀofꢀerroneousꢀclockꢀsources,ꢀaꢀtime-outꢀ
functionꢀisꢀprovided.ꢀIfꢀtheꢀclockꢀsourceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀisꢀnotꢀreceivedꢀforꢀaꢀwhile,ꢀthenꢀtheꢀ
I2Cꢀcircuitryꢀandꢀregistersꢀwillꢀbeꢀresetꢀafterꢀaꢀcertainꢀtime-outꢀperiod.ꢀTheꢀtime-outꢀcounterꢀstartsꢀ
toꢀcountꢀonꢀanꢀI2Cꢀbusꢀ“START”ꢀ&ꢀ“addressꢀmatch”ꢀcondition,ꢀandꢀisꢀclearedꢀbyꢀanꢀSCLꢀfallingꢀ
edge.ꢀBeforeꢀtheꢀnextꢀSCLꢀfallingꢀedgeꢀarrives,ꢀifꢀtheꢀtimeꢀelapsedꢀisꢀgreaterꢀthanꢀtheꢀtime-outꢀperiodꢀ
specifiedꢀbyꢀtheꢀI2CTOCꢀregister,ꢀthenꢀaꢀtime-outꢀconditionꢀwillꢀoccur.ꢀTheꢀtime-outꢀfunctionꢀwillꢀ
stopꢀwhenꢀanꢀI2Cꢀ“STOP”ꢀconditionꢀoccurs.
Rev. 1.40
164
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
S
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I2C Time-out
WhenꢀanꢀI2Cꢀtime-outꢀcounterꢀoverflowꢀoccurs,ꢀtheꢀcounterꢀwillꢀstopꢀandꢀtheꢀI2CTOENꢀbitꢀwillꢀbeꢀ
clearedꢀtoꢀzeroꢀandꢀtheꢀI2CTFꢀbitꢀwillꢀbeꢀsetꢀhighꢀtoꢀindicateꢀthatꢀaꢀtime-outꢀconditionꢀhasꢀoccurred.ꢀ
Theꢀtime-outꢀconditionꢀwillꢀalsoꢀgenerateꢀanꢀinterruptꢀwhichꢀusesꢀtheꢀI2Cꢀinterruptꢀvector.ꢀWhenꢀanꢀ
I2Cꢀtime-outꢀoccurs,ꢀtheꢀI2Cꢀinternalꢀcircuitryꢀwillꢀbeꢀresetꢀandꢀtheꢀregistersꢀwillꢀbeꢀresetꢀintoꢀtheꢀ
followingꢀcondition:
Register
SI�Dꢂ SI�Aꢂ SI�C0
SI�C1
After I2C Time-out
No change
Reset to POR condition
I2C Registers after Time-out
TheꢀI2CTOFꢀflagꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀThereꢀareꢀ64ꢀtime-outꢀperiodꢀselectionsꢀ
whichꢀcanꢀbeꢀselectedꢀusingꢀtheꢀI2CTOSꢀbitsꢀinꢀtheꢀI2CTOCꢀregister.ꢀTheꢀtime-outꢀdurationꢀisꢀ
calculatedꢀbyꢀtheꢀformula:ꢀ((1~64)×(32/fSUB)).ꢀThisꢀgivesꢀaꢀtime-outꢀperiodꢀwhichꢀrangesꢀfromꢀaboutꢀ
1msꢀtoꢀ64ms.
I2CTOC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
IꢁCTOEN IꢁCTOF IꢁCTOS5 IꢁCTOS4 IꢁCTOS3 IꢁCTOSꢁ IꢁCTOS1 IꢁCTOS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7
I2CTOEN:ꢀI2CꢀTime-outꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6
I2CTOF:ꢀI2CꢀTime-outꢀflag
0:ꢀNoꢀtime-outꢀoccurred
1:ꢀtime-outꢀoccurred
Bitꢀ5~0
I2CTOS5~I2CTOS0:ꢀI2CꢀTime-outꢀTimeꢀSelection
I2CꢀTime-outꢀclockꢀsourceꢀisꢀfSUB/32
I2CꢀTime-outꢀtimeꢀisꢀgivenꢀby:ꢀ(I2CTOSꢀ[5:0]ꢀ+1)×(32/fSUB
)
Rev. 1.40
165
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Peripheral Clock Output
TheꢀPeripheralꢀClockꢀOutputꢀallowsꢀtheꢀdevicesꢀtoꢀsupplyꢀexternalꢀhardwareꢀwithꢀaꢀclockꢀsignalꢀ
synchronisedꢀtoꢀtheꢀmicrocontrollerꢀclock.
Peripheral Clock Operation
Asꢀtheꢀperipheralꢀclockꢀoutputꢀpin,ꢀPCK,ꢀisꢀsharedꢀwithꢀI/Oꢀline,ꢀtheꢀrequiredꢀpinꢀfunctionꢀisꢀchosenꢀ
viaꢀPCKENꢀinꢀtheꢀSIMC0ꢀregister.ꢀTheꢀPeripheralꢀClockꢀfunctionꢀisꢀcontrolledꢀusingꢀtheꢀSIMC0ꢀ
register.ꢀTheꢀclockꢀsourceꢀforꢀtheꢀPeripheralꢀClockꢀOutputꢀcanꢀoriginateꢀfromꢀeitherꢀtheꢀTM0ꢀCCRPꢀ
matchꢀfrequency/2ꢀorꢀaꢀdividedꢀratioꢀofꢀtheꢀinternalꢀfSYSꢀclock.ꢀTheꢀPCKENꢀbitꢀinꢀtheꢀSIMC0ꢀ
registerꢀisꢀtheꢀoverallꢀon/offꢀcontrol,ꢀsettingꢀPCKENꢀbitꢀtoꢀ1ꢀenablesꢀtheꢀPeripheralꢀClockꢀandꢀsettingꢀ
PCKENꢀbitꢀtoꢀ0ꢀdisablesꢀit.ꢀTheꢀrequiredꢀdivisionꢀratioꢀofꢀtheꢀsystemꢀclockꢀisꢀselectedꢀusingꢀtheꢀ
PCKP1ꢀandꢀPCKP0ꢀbitsꢀinꢀtheꢀsameꢀregister.ꢀIfꢀtheꢀdevicesꢀenterꢀtheꢀSLEEPꢀMode,ꢀthisꢀwillꢀdisableꢀ
theꢀPeripheralꢀClockꢀoutput.
SIMC0 Register
Bit
7
SI�ꢁ
R/W
1
6
SI�1
R/W
1
5
SI�0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SI�EN
R/W
0
0
Name
R/W
—
—
—
POR
Bitꢀ7~5
SIM2, SIM1, SIM0: SIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀTM0.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀ
theꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4
PCKEN:ꢀPCKꢀOutputꢀPinꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ3~2
PCKP1, PCKP0:ꢀSelectꢀPCKꢀoutputꢀpinꢀfrenquency
00:ꢀfSYS
01:ꢀfSYS/4
10:ꢀfSYS/8
11:ꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
Rev. 1.40
166
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Serial Interface – SPIA
TheꢀdevicesꢀcontainꢀanꢀindependentꢀSPIꢀfunction.ꢀItꢀisꢀimportantꢀnotꢀtoꢀconfuseꢀthisꢀindependentꢀSPIꢀ
functionꢀwithꢀtheꢀadditionalꢀoneꢀcontainedꢀwithinꢀtheꢀcombinedꢀSIMꢀfunction,ꢀwhichꢀisꢀdescribedꢀ
inꢀanotherꢀsectionꢀofꢀthisꢀdatasheet.ꢀThisꢀindependentꢀSPIꢀfunctionꢀwillꢀcarryꢀtheꢀnameꢀSPIAꢀtoꢀ
distinguishꢀitꢀfromꢀtheꢀotherꢀoneꢀinꢀtheꢀSIM.
ThisꢀSPIAꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
FlashꢀorꢀEEPROMꢀmemoryꢀdevices,ꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfour-lineꢀSPIꢀ
interfaceꢀisꢀaꢀsynchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀ
simplifyingꢀtheꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIAꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀtheseꢀdevicesꢀareꢀprovidedꢀonlyꢀoneꢀSCSAꢀline.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ
multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinsꢀtoꢀselectꢀtheꢀslaveꢀdevices.
Rev. 1.40
16ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIA Interface Operation
TheꢀSPIAꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀ
pinꢀnamesꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSA.ꢀSignalsꢀSDIAꢀandꢀSDOAꢀareꢀtheꢀSerialꢀDataꢀInputꢀ
andꢀSerialꢀDataꢀOutputꢀlines,ꢀSCKAꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSAꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀ
theꢀSPIAꢀinterfaceꢀlinesꢀareꢀpin-sharedꢀwithꢀotherꢀfunctions,ꢀtheꢀSPIAꢀinterfaceꢀlinesꢀmustꢀfirstꢀbeꢀ
enabledꢀbyꢀselectingꢀtheꢀSPIAꢀinterfaceꢀenableꢀconfigurationꢀoptionꢀandꢀsettingꢀtheꢀcorrectꢀbitsꢀinꢀ
theꢀSPIAC0ꢀandꢀSPIAC1ꢀregisters.ꢀAfterꢀtheꢀSPIAꢀenableꢀconfigurationꢀoptionꢀhasꢀbeenꢀconfigured,ꢀ
theꢀSPIAꢀinterfaceꢀfunctionꢀcanꢀalsoꢀbeꢀadditionallyꢀdisabledꢀorꢀenabledꢀusingꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀ
SPIAC0ꢀregister.ꢀCommunicationꢀbetweenꢀdevicesꢀconnectedꢀtoꢀtheꢀSPIAꢀinterfaceꢀisꢀcarriedꢀoutꢀinꢀ
aꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀtransferꢀinitiationsꢀbeingꢀimplementedꢀbyꢀtheꢀmaster.ꢀTheꢀmasterꢀ
alsoꢀcontrolsꢀtheꢀclock/signal.ꢀAsꢀtheꢀdevicesꢀonlyꢀcontainꢀaꢀsingleꢀSCSAꢀpinꢀonlyꢀoneꢀslaveꢀdeviceꢀ
canꢀbeꢀutilised.
TheꢀSCSAꢀlineꢀisꢀcontrolledꢀbyꢀtheꢀapplicationꢀprogram,ꢀsetꢀtheꢀSACSENꢀbitꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀ
SCSAꢀlineꢀfunctionꢀandꢀclearꢀtheꢀSACSENꢀbitꢀtoꢀ“0”ꢀtoꢀplaceꢀtheꢀSCSAꢀpinꢀintoꢀotherꢀpin-sharedꢀ
functions.
TheꢀSPIAꢀSerialꢀInterfaceꢀfunctionꢀincludesꢀtheꢀfollowingꢀfeatures:
•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransfer
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodes
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodes
•ꢀ Transmissionꢀcompleteꢀflag
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedge
•ꢀ SAWCOLꢀandꢀSACSENꢀbitꢀenabledꢀorꢀdisableꢀselect
TheꢀstatusꢀofꢀtheꢀSPIAꢀinterfaceꢀlinesꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀ
devicesꢀareꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀ
SACSENꢀandꢀSPIAEN.
ThereꢀareꢀseveralꢀconfigurationꢀoptionsꢀassociatedꢀwithꢀtheꢀSPIAꢀinterface.ꢀOneꢀofꢀtheseꢀisꢀtoꢀ
enableꢀtheꢀSPIAꢀfunctionꢀwhichꢀselectsꢀtheꢀSPIAꢀlinesꢀratherꢀthanꢀnormalꢀI/Oꢀpins.ꢀNoteꢀthatꢀifꢀ
theꢀconfigurationꢀoptionꢀdoesꢀnotꢀselectꢀtheꢀSPIAꢀfunctionꢀthenꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀ
registerꢀwillꢀhaveꢀnoꢀeffect.ꢀAnotherꢀtwoꢀSPIAꢀconfigurationꢀoptionsꢀdetermineꢀifꢀtheꢀSACSENꢀandꢀ
SAWCOLꢀbitsꢀareꢀtoꢀbeꢀused.
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SPIA Master/Slave Connection
Rev. 1.40
168
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
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SPIA Block Diagram
SPIA Registers
ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIAꢀinterface.ꢀTheseꢀareꢀ
theꢀSPIADꢀdataꢀregisterꢀandꢀtwoꢀregistersꢀSPIAC0ꢀandꢀSPIAC1.
Bit
Register
Name
7
6
5
4
3
2
1
0
SPIAC0 SASPIꢁ SASPI1
SASPI0
—
—
—
SPIAEN
—
SPIAC1
SPIAD
—
—
SACKPOL SACKEG SA�LS SACSEN SAWCOL SATRF
D5 D4 D3 Dꢁ D1 D0
SPIA Registers List
Dꢃ
D6
TheꢀSPIADꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀBeforeꢀtheꢀdevicesꢀ
writeꢀdataꢀtoꢀtheꢀSPIAꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSPIADꢀregister.ꢀ
AfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIAꢀbus,ꢀtheꢀdevicesꢀcanꢀreadꢀitꢀfromꢀtheꢀSPIADꢀregister.ꢀAnyꢀ
transmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIAꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSPIADꢀregister.
Rev. 1.40
169
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIAD Register
Bit
Name
R/W
7
Dꢃ
R/W
×
6
D6
R/W
×
5
D5
R/W
×
4
D4
R/W
×
3
D3
R/W
×
2
Dꢁ
R/W
×
1
D1
R/W
×
0
D0
R/W
POR
×
“×” unknown
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIAꢀinterface,ꢀSPIAC0ꢀandꢀSPIAC1.ꢀRegisterꢀSPIAC0ꢀ
isꢀusedꢀtoꢀcontrolꢀtheꢀenableꢀorꢀdisableꢀfunctionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀ
RegisterꢀSPIAC1ꢀisꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀ
flag,ꢀetc.
SPIAC0 Register
Bit
Name
R/W
7
SASPIꢁ
R/W
1
6
SASPI1
R/W
1
5
SASPI0
R/W
1
4
3
2
1
SPIAEN
R/W
0
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~5
SASPI2~SASPI0:ꢀSPIAꢀMaster/SlaveꢀClockꢀSelect
000:ꢀSPIAꢀmaster,ꢀfSYS/4
001:ꢀSPIAꢀmaster,ꢀfSYS/16
010:ꢀSPIAꢀmaster,ꢀfSYS/64
011:ꢀSPIAꢀmaster,ꢀfSUB
100:ꢀSPIAꢀmaster,ꢀTM0ꢀCCRPꢀmatchꢀfrequency/2ꢀ(PFD)
101:ꢀSPIAꢀslave
11x:ꢀReserved
Bitꢀ4~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAEN:ꢀSPIAꢀenableꢀorꢀdisable
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSPIAꢀinterface.ꢀWhenꢀtheꢀSPIAENꢀbitꢀ
isꢀclearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSPIAꢀinterface,ꢀtheꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSAꢀ
linesꢀwillꢀloseꢀtheirꢀSPIꢀfunctionꢀandꢀtheꢀSPIAꢀoperatingꢀcurrentꢀwillꢀbeꢀreducedꢀtoꢀaꢀ
minimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhigh,ꢀtheꢀSPIAꢀinterfaceꢀisꢀenabled.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.40
1ꢃ0
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIAC1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
SACKPOL SACKEG SA�LS SACSEN SAWCOL SATRF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
SACKPOL:ꢀDeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline
0:ꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀSACKPOLꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4ꢀ
SACKEG:ꢀDeterminesꢀtheꢀSPIAꢀSCKAꢀactiveꢀclockꢀedgeꢀtype
SACKPOL=0:ꢀ
0:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedgeꢀ
1:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedge
SACKPOL=1:ꢀ
0:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedgeꢀ
1:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedge
TheꢀSACKEGꢀandꢀSACKPOLꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀ
outputsꢀandꢀinputsꢀdataꢀonꢀtheꢀSPIAꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀaꢀ
dataꢀtransferꢀisꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀ
SACKPOLꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀ
SCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLꢀbitꢀisꢀlow,ꢀthenꢀ
theꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀSACKEGꢀbitꢀdeterminesꢀ
activeꢀclockꢀedgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀtheꢀSACKPOLꢀbit.
Bitꢀ3
SAMLS:ꢀdataꢀshiftꢀorder
0:ꢀtheꢀLSBꢀofꢀdataꢀisꢀtransmittedꢀfirst
1:ꢀtheꢀMSBꢀofꢀdataꢀisꢀtransmittedꢀfirst
Bitꢀ2ꢀ
SACSEN:ꢀSPIAꢀSCSAꢀpinꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀSACSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSAꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀ
theꢀSCSAꢀpinꢀfunctionꢀwillꢀbeꢀdisabledꢀandꢀusedꢀasꢀanꢀI/Oꢀfunction.ꢀIfꢀtheꢀbitꢀisꢀhighꢀ
theꢀSCSAꢀpinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.ꢀNoteꢀthatꢀusingꢀtheꢀSACSENꢀbitꢀ
canꢀbeꢀdisabledꢀorꢀenabledꢀviaꢀaꢀconfigurationꢀoption.
Bitꢀ1ꢀ
SAWCOL:ꢀSPIAꢀWriteꢀCollisionꢀflag
0:ꢀCollisionꢀfree
1:ꢀCollisionꢀdetected
TheꢀSAWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀ
itꢀmeansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSPIADꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀNoteꢀthatꢀusingꢀtheꢀSAWCOLꢀbitꢀ
canꢀbeꢀdisabledꢀorꢀenabledꢀviaꢀaꢀconfigurationꢀoption.
Bitꢀ0ꢀ
SATRF:ꢀSPIAꢀTransmit/ReceiveꢀCompleteꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀSATRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀtoꢀ“1”ꢀautomaticallyꢀ
whenꢀanꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀ
applicationꢀprogram.ꢀItꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
Rev. 1.40
1ꢃ1
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIA Communication
AfterꢀtheꢀSPIAꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSPIAENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSPIADꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀSATRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSPIADꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIAꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ
theꢀSPIADꢀregisters.
TheꢀmasterꢀshouldꢀoutputꢀaꢀSCSAꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀclockꢀsignalꢀisꢀprovided.ꢀ
Theꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀmomentꢀrelativeꢀtoꢀ
theꢀSCSAꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀSACKPOLꢀbitꢀandꢀSACKEGꢀbit.ꢀTheꢀ
accompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSAꢀsignalꢀforꢀ
variousꢀconfigurationsꢀofꢀtheꢀSACKPOLꢀandꢀSACKEGꢀbits.
TheꢀSPIAꢀwillꢀcontinueꢀtoꢀfunctionꢀevenꢀinꢀtheꢀIDLEꢀMode.
SPIA Bus Enable/Disable
ToꢀenableꢀtheꢀSPIAꢀbus,ꢀsetꢀSACSEN=1ꢀandꢀSCSA=0,ꢀthenꢀwaitꢀforꢀdataꢀtoꢀbeꢀwrittenꢀintoꢀtheꢀ
SPIADꢀ(TXRXꢀbuffer)ꢀregister.ꢀForꢀtheꢀMasterꢀMode,ꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀSPIADꢀ
(TXRXꢀbuffer)ꢀregister,ꢀthenꢀtransmissionꢀorꢀreceptionꢀwillꢀstartꢀautomatically.ꢀWhenꢀallꢀtheꢀdataꢀhasꢀ
beenꢀtransferredꢀtheꢀSATRFꢀbitꢀshouldꢀbeꢀset.ꢀForꢀtheꢀSlaveꢀMode,ꢀwhenꢀclockꢀpulsesꢀareꢀreceivedꢀ
onꢀSCKA,ꢀdataꢀinꢀtheꢀTXRXꢀbufferꢀwillꢀbeꢀshiftedꢀoutꢀorꢀdataꢀonꢀSDIAꢀwillꢀbeꢀshiftedꢀin.
ToꢀdisableꢀtheꢀSPIAꢀbusꢀtheꢀSCKA,ꢀSDIA,ꢀSDOAꢀandꢀSCSAꢀlinesꢀwillꢀbecomeꢀI/Oꢀpinsꢀorꢀotherꢀpin-
sharedꢀfunctions.
Rev. 1.40
1ꢃꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIA master mode
SPIAEN
=1ꢂ SACSEN
=0(external pull-high)
=1
SCSA
SPIAEN
=1ꢂSACSEN
1
0
SACKPOL=
(
SCKA
)
)
)
)
SACKEG
=
0
0
SACKPOL=
(
SCKA
SCKA
SACKEG
=
1
1
=
=
SACKPOL
SACKEG
(
SACKPOL
0
=
SCKA
(
SACKEG
= 1
SDOA ( SACKEG= 0)
SDOA (SACKEG= 1)
Dꢃ/D0 D6/D1 D5/Dꢁ D4/D3 D3/D4 Dꢁ/D5 D1/D6 D0/Dꢃ
Dꢃ/D0 D6/D1 D5/Dꢁ D4/D3 D3/D4 Dꢁ/D5 D1/D6 D0/Dꢃ
SDIA Data capture
Write to SPIAD
SPIA slave mode (SACKEG=0)
SCSA
SCKA
(
=1 )
SACKPOL
SCKA (SACKPOL=0 )
SDOA
Dꢃ/D0 D6/D1 D5/Dꢁ D4/D3 D3/D4 Dꢁ/D5 D1/D6 D0/Dꢃ
SDIA Data capture
Write to SPIAD
(SDOA not change until first SCKA edge)
)
(SACKEG
=1
SPIA slave mode
SCSA
SCKA
(
=1)
SACKPOL
SCKA (SACKPOL=0)
SDOA
Dꢃ/D0 D6/D1 D5/Dꢁ D4/D3 D3/D4 Dꢁ/D5 D1/D6 D0/Dꢃ
SDIA Data capture
Write to SPIAD
(SDOA change as soon as writing occur; SDOA = floating if SCSA=1)
Note:ꢀForꢀSPIAꢀslaveꢀmode,ꢀifꢀSPIAEN=1ꢀandꢀSACSEN=0,ꢀSPIAꢀisꢀalwaysꢀenabledꢀꢀ
andꢀignoreꢀtheꢀSCSAꢀlevel.
SPIA Master/Slave Mode Timing Diagram
Rev. 1.40
1ꢃ3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIA Operation
Allꢀcommunicationꢀisꢀcarriedꢀoutꢀusingꢀtheꢀ4-lineꢀinterfaceꢀforꢀeitherꢀMasterꢀorꢀSlaveꢀMode.
TheꢀSACSENꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀcontrolsꢀtheꢀoverallꢀfunctionꢀofꢀtheꢀSPIAꢀinterface.ꢀSettingꢀ
thisꢀbitꢀhighꢀwillꢀenableꢀtheꢀSPIAꢀinterfaceꢀbyꢀallowingꢀtheꢀSCSAꢀlineꢀtoꢀbeꢀactive,ꢀwhichꢀcanꢀthenꢀ
beꢀusedꢀtoꢀcontrolꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀisꢀlow,ꢀtheꢀSPIAꢀinterfaceꢀwillꢀbeꢀdisabledꢀ
andꢀtheꢀSCSAꢀlineꢀwillꢀbeꢀanꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunctionsꢀandꢀcanꢀthereforeꢀnotꢀbeꢀusedꢀforꢀ
controlꢀofꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀandꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀregisterꢀareꢀsetꢀ
high,ꢀthisꢀwillꢀplaceꢀtheꢀSDIAꢀlineꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSDOAꢀlineꢀhigh.ꢀIfꢀinꢀMasterꢀModeꢀ
theꢀSCKAꢀlineꢀwillꢀbeꢀeitherꢀhighꢀorꢀlowꢀdependingꢀuponꢀtheꢀclockꢀpolarityꢀselectionꢀbitꢀSACKPOLꢀ
inꢀtheꢀSPIAC1ꢀregister.ꢀIfꢀinꢀSlaveꢀModeꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀinꢀaꢀfloatingꢀcondition.ꢀIfꢀSPIAENꢀisꢀ
lowꢀthenꢀtheꢀbusꢀwillꢀbeꢀdisabledꢀandꢀSCSA,ꢀSDIA,ꢀSDOAꢀandꢀSCKAꢀlinesꢀwillꢀallꢀbecomeꢀI/Oꢀpinsꢀ
orꢀotherꢀpin-sharedꢀfunctions.ꢀInꢀtheꢀMasterꢀModeꢀtheꢀMasterꢀwillꢀalwaysꢀgenerateꢀtheꢀclockꢀsignal.ꢀ
TheꢀclockꢀandꢀdataꢀtransmissionꢀwillꢀbeꢀinitiatedꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀintoꢀtheꢀSPIADꢀregister.ꢀ
InꢀtheꢀSlaveꢀMode,ꢀtheꢀclockꢀsignalꢀwillꢀbeꢀreceivedꢀfromꢀanꢀexternalꢀmasterꢀdeviceꢀforꢀbothꢀdataꢀ
transmissionꢀandꢀreception.ꢀTheꢀfollowingꢀsequencesꢀshowꢀtheꢀorderꢀtoꢀbeꢀfollowedꢀforꢀdataꢀtransferꢀ
inꢀbothꢀMasterꢀandꢀSlaveꢀMode:
Master Mode
•ꢀ Stepꢀ1
SelectꢀtheꢀclockꢀsourceꢀandꢀMasterꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀ
register
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀshiftedꢀ
first,ꢀthisꢀmustꢀbeꢀsameꢀasꢀtheꢀSlaveꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀuseꢀtheꢀSCKAꢀandꢀSCSAꢀlinesꢀtoꢀoutputꢀtheꢀdata.ꢀAfterꢀthisꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀzeroꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Rev. 1.40
1ꢃ4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Slave Mode
•ꢀ Stepꢀ1
SelectꢀtheꢀSPIꢀSlaveꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregister
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀshiftedꢀ
first,ꢀthisꢀsettingꢀmustꢀbeꢀtheꢀsameꢀwithꢀtheꢀMasterꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀwaitꢀforꢀtheꢀmasterꢀclockꢀSCKAꢀandꢀSCSAꢀsignal.ꢀAfterꢀthis,ꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀzeroꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Rev. 1.40
1ꢃ5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
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SPIA Transfer Control Flowchart
Error Detection
TheꢀSAWCOLꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀisꢀprovidedꢀtoꢀindicateꢀerrorsꢀduringꢀdataꢀtransfer.ꢀTheꢀbitꢀ
isꢀsetꢀbyꢀtheꢀSPIAꢀserialꢀInterfaceꢀbutꢀmustꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀThisꢀbitꢀindicatesꢀ
aꢀdataꢀcollisionꢀhasꢀoccurredꢀwhichꢀhappensꢀifꢀaꢀwriteꢀtoꢀtheꢀSPIADꢀregisterꢀtakesꢀplaceꢀduringꢀaꢀ
dataꢀtransferꢀoperationꢀandꢀwillꢀpreventꢀtheꢀwriteꢀoperationꢀfromꢀcontinuing.
Rev. 1.40
1ꢃ6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Interrupts
Interruptsꢀareꢀanꢀimportantꢀpartꢀofꢀanyꢀmicrocontrollerꢀsystem.ꢀWhenꢀanꢀexternalꢀeventꢀorꢀanꢀ
internalꢀfunctionꢀsuchꢀasꢀaꢀTimerꢀModuleꢀorꢀanꢀA/Dꢀconverterꢀrequiresꢀmicrocontrollerꢀattention,ꢀ
theirꢀcorrespondingꢀinterruptꢀwillꢀenforceꢀaꢀtemporaryꢀsuspensionꢀofꢀtheꢀmainꢀprogramꢀallowingꢀtheꢀ
microcontrollerꢀtoꢀdirectꢀattentionꢀtoꢀtheirꢀrespectiveꢀneeds.ꢀTheꢀdevicesꢀcontainꢀseveralꢀexternalꢀ
interruptꢀandꢀinternalꢀinterruptsꢀfunctions.ꢀTheꢀexternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀtheꢀactionꢀofꢀtheꢀ
externalꢀINT0ꢀandꢀINT1ꢀpinsꢀwhileꢀtheꢀinternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀvariousꢀinternalꢀfunctionsꢀ
suchꢀasꢀtheꢀTMs,ꢀTimeꢀBase,ꢀLVDꢀandꢀtheꢀA/Dꢀconverter,ꢀetc.
Interrupt Registers
Overallꢀinterruptꢀcontrol,ꢀwhichꢀbasicallyꢀmeansꢀtheꢀsettingꢀofꢀrequestꢀflagsꢀwhenꢀcertainꢀ
microcontrollerꢀconditionsꢀoccurꢀandꢀtheꢀsettingꢀofꢀinterruptꢀenableꢀbitsꢀbyꢀtheꢀapplicationꢀprogram,ꢀ
isꢀcontrolledꢀbyꢀaꢀseriesꢀofꢀregisters,ꢀlocatedꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemory,ꢀasꢀshownꢀinꢀtheꢀ
accompanyingꢀtable.ꢀTheꢀnumberꢀofꢀregistersꢀdependsꢀuponꢀtheꢀdevicesꢀchosenꢀbutꢀfallꢀintoꢀthreeꢀ
categories.ꢀTheꢀfirstꢀisꢀtheꢀINTC0~INTC2ꢀregistersꢀwhichꢀsetupꢀtheꢀprimaryꢀinterrupts,ꢀtheꢀsecondꢀ
isꢀtheꢀMFI0~MFI4ꢀregistersꢀwhichꢀsetupꢀtheꢀMulti-functionꢀinterrupts.ꢀFinallyꢀthereꢀisꢀanꢀINTEGꢀ
registerꢀtoꢀsetupꢀtheꢀexternalꢀinterruptꢀtriggerꢀedgeꢀtype.
Eachꢀregisterꢀcontainsꢀaꢀnumberꢀofꢀenableꢀbitsꢀtoꢀenableꢀorꢀdisableꢀindividualꢀregistersꢀasꢀwellꢀasꢀ
interruptꢀflagsꢀtoꢀindicateꢀtheꢀpresenceꢀofꢀanꢀinterruptꢀrequest.ꢀTheꢀnamingꢀconventionꢀofꢀtheseꢀ
followsꢀaꢀspecificꢀpattern.ꢀFirstꢀisꢀlistedꢀanꢀabbreviatedꢀinterruptꢀtype,ꢀthenꢀtheꢀ(optional)ꢀnumberꢀofꢀ
thatꢀinterruptꢀfollowedꢀbyꢀeitherꢀanꢀ”E”ꢀforꢀenable/disableꢀbitꢀorꢀ“F”ꢀforꢀrequestꢀflag.
Function
Global
Enable Bit
E�I
Request Flag
—
Notes
—
INTn Pins
Comparator
�ulti-function
A/D converter
Time Base
LVD
INTnE
CPE
INTnF
CPF
n=0 or 1
—
�FnE
ADE
�FnF
ADF
n=0~4
—
TBnE
LVE
TBnF
LVF
n=0 or 1
—
EEPRO�
SI�
DEE
DEF
—
—
—
SI�E
SPIAE
TnPE
TnAE
TnBE
SI�F
SPIAF
TnPF
TnAF
TnBF
SPIA
n=0~3
n=3
T�
Interrupt Register Bit Naming Conventions
Rev. 1.40
1ꢃꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Bit
Register Name
7
—
6
5
4
3
2
1
0
INTEG
INTC0
INTC1
INTCꢁ
�FI0
—
—
—
INT1S1 INT1S0 INT0S1 INT0S0
—
�F0F
�F3F
TB1F
—
CPF
�FꢁF
TB0F
T0AF
TꢁAF
T3AF
DEF
INT0F
�F1F
ADF
T0PF
TꢁPF
T3PF
LVF
�F0E
�F4E
INT1E
—
CPE
�F3E
TB1E
—
INT0E
�FꢁE
TB0E
T0AE
TꢁAE
T3AE
DEE
E�I
�F1E
ADE
�F4F
INT1F
—
T0PE
TꢁPE
T3PE
LVE
�FIꢁ
—
—
—
—
�FI3
—
T3BF
SI�F
—
T3BE
SI�E
�FI4
SPIAF
SPIAE
BC66F840 Interrupt Register List
Bit
Register Name
7
—
6
5
4
3
2
1
0
INTEG
INTC0
INTC1
INTCꢁ
�FI0
—
—
—
INT1S1 INT1S0 INT0S1 INT0S0
—
�F0F
�F3F
TB1F
—
CPF
�FꢁF
TB0F
T0AF
T1AF
TꢁAF
T3AF
DEF
INT0F
�F1F
ADF
T0PF
T1PF
TꢁPF
T3PF
LVF
�F0E
�F4E
INT1E
—
CPE
�F3E
TB1E
—
INT0E
�FꢁE
TB0E
T0AE
T1AE
TꢁAE
T3AE
DEE
E�I
�F1E
ADE
�F4F
INT1F
—
T0PE
T1PE
TꢁPE
T3PE
LVE
�FI1
—
—
—
—
�FIꢁ
—
—
—
—
�FI3
—
T3BF
SI�F
—
T3BE
SI�E
�FI4
SPIAF
SPIAE
BC66F850/BC66F860 Interrupt Register List
INTEG Register
Bit
7
6
5
4
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3~2
Unimplemented,ꢀreadꢀasꢀ“0”
INT1S1~INT1S0:ꢀinterruptꢀedgeꢀcontrolꢀforꢀINT1ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀBothꢀrisingꢀandꢀfallingꢀedges
Bitꢀ1~0
INT0S1~INT0S0:ꢀinterruptꢀedgeꢀcontrolꢀforꢀINT0ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀBothꢀrisingꢀandꢀfallingꢀedges
Rev. 1.40
1ꢃ8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
INTC0 Register
Bit
Name
R/W
7
6
�F0F
R/W
0
5
4
INT0F
R/W
0
3
�F0E
R/W
0
2
1
INT0E
R/W
0
0
—
—
—
CPF
R/W
0
CPE
R/W
0
E�I
R/W
0
POR
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
MF0F:ꢀMulti-functionꢀ0ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
CPF:ꢀComparatorꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT0F:ꢀINT0ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF0E:ꢀMulti-functionꢀ0ꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
CPE:ꢀComparatorꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
INT0E:ꢀINT0ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
EMI:ꢀGlobalꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
1ꢃ9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
INTC1 Register
Bit
Name
R/W
7
�F4F
R/W
0
6
�F3F
R/W
0
5
�FꢁF
R/W
0
4
�F1F
R/W
0
3
�F4E
R/W
0
2
�F3E
R/W
0
1
�FꢁE
R/W
0
0
�F1E
R/W
0
POR
Bitꢀ7
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
MF4F:ꢀMulti-functionꢀ4ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF3F:ꢀMulti-functionꢀ3ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF2F:ꢀMulti-functionꢀ2ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF1F:ꢀMulti-functionꢀ1ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF4E:ꢀMulti-functionꢀ4ꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF3E:ꢀMulti-functionꢀ3ꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF2E:ꢀMulti-functionꢀ2ꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF1E:ꢀMulti-functionꢀ1ꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
180
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
INTC2 Register
Bit
Name
R/W
7
INT1F
R/W
0
6
TB1F
R/W
0
5
TB0F
R/W
0
4
3
INT1E
R/W
0
2
TB1E
R/W
0
1
TB0E
R/W
0
0
ADF
R/W
0
ADE
R/W
0
POR
Bitꢀ7
INT1F:ꢀINT1ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
TB1F:ꢀTimeꢀBaseꢀ1ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
TB0F:ꢀTimeꢀBaseꢀ0ꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
ADF:ꢀA/DꢀConverterꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT1E:ꢀINT1ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
TB1E:ꢀTimeꢀBaseꢀ1ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
TB0E:ꢀTimeꢀBaseꢀ0ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
ADE:ꢀA/DꢀConverterꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
181
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
MFI0 Register
Bit
Name
R/W
7
6
5
T0AF
R/W
0
4
T0PF
R/W
0
3
2
1
T0AE
R/W
0
0
T0PE
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
T0AF:ꢀTM0ꢀComparatorꢀAꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ4
T0PF:ꢀTM0ꢀComparatorꢀPꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
T0AE:ꢀTM0ꢀComparatorꢀAꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ0
T0PE:ꢀTM0ꢀComparatorꢀPꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MFI1 Register – BC66F850/BC66F860
Bit
Name
R/W
7
6
5
T1AF
R/W
0
4
T1PF
R/W
0
3
2
1
T1AE
R/W
0
0
T1PE
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
T1AF:ꢀTM1ꢀComparatorꢀAꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ4
T1PF:ꢀTM1ꢀComparatorꢀPꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
T1AE:ꢀTM1ꢀComparatorꢀAꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ0
T1PE:ꢀTM1ꢀComparatorꢀPꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
18ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
MFI2 Register
Bit
Name
R/W
7
6
5
TꢁAF
R/W
0
4
TꢁPF
R/W
0
3
2
1
TꢁAE
R/W
0
0
TꢁPE
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
T2AF:ꢀTM2ꢀComparatorꢀAꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ4
T2PF:ꢀTM2ꢀComparatorꢀPꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
T2AE:ꢀTM2ꢀComparatorꢀAꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ0
T2PE:ꢀTM2ꢀComparatorꢀPꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MFI3 Register
Bit
Name
R/W
7
6
T3BF
R/W
0
5
T3AF
R/W
0
4
T3PF
R/W
0
3
2
T3BE
R/W
0
1
T3AE
R/W
0
0
T3PE
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
Bitꢀ6
Unimplemented,ꢀreadꢀasꢀ“0”
T3BF:ꢀTM3ꢀComparatorꢀBꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5
Bitꢀ4
T3AF:ꢀTM3ꢀComparatorꢀAꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T3PF:ꢀTM3ꢀComparatorꢀPꢀmatchꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ“0”
T3BE:ꢀTM3ꢀComparatorꢀBꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ1
Bitꢀ0
T3AE:ꢀTM3ꢀComparatorꢀAꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T3PE:ꢀTM3ꢀComparatorꢀPꢀmatchꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
183
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
MFI4 Register
Bit
Name
R/W
7
SPIAF
R/W
0
6
SI�F
R/W
0
5
4
3
SPIAE
R/W
0
2
SI�E
R/W
0
1
0
DEF
R/W
0
LVF
R/W
0
DEE
R/W
0
LVE
R/W
0
POR
Bitꢀ7
Bitꢀ6
Bitꢀ5
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
SPIAF:ꢀSPIAꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
SIMF:ꢀSIMꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
DEF:ꢀDataꢀEEPROMꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
LVF:ꢀLVDꢀInterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
SPIAE:ꢀSPIAꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
SIME:ꢀSIMꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
DEE:ꢀDataꢀEEPROMꢀInterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
LVE:ꢀLVDꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
184
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Interrupt Operation
Whenꢀtheꢀconditionsꢀforꢀanꢀinterruptꢀeventꢀoccur,ꢀsuchꢀasꢀaꢀTMꢀComparatorꢀPꢀorꢀComparatorꢀAꢀ
matchꢀorꢀA/Dꢀconversionꢀcompletionꢀetc,ꢀtheꢀrelevantꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset.ꢀWhetherꢀ
theꢀrequestꢀflagꢀactuallyꢀgeneratesꢀaꢀprogramꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvectorꢀisꢀdeterminedꢀbyꢀ
theꢀconditionꢀofꢀtheꢀinterruptꢀenableꢀbit.ꢀIfꢀtheꢀenableꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀ
itsꢀrelevantꢀvector;ꢀifꢀtheꢀenableꢀbitꢀisꢀzeroꢀthenꢀalthoughꢀtheꢀinterruptꢀrequestꢀflagꢀisꢀsetꢀanꢀactualꢀ
interruptꢀwillꢀnotꢀbeꢀgeneratedꢀandꢀtheꢀprogramꢀwillꢀnotꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvector.ꢀTheꢀ
globalꢀinterruptꢀenableꢀbit,ꢀifꢀclearedꢀtoꢀzero,ꢀwillꢀdisableꢀallꢀinterrupts.
Whenꢀanꢀinterruptꢀisꢀgenerated,ꢀtheꢀProgramꢀCounter,ꢀwhichꢀstoresꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀ
toꢀbeꢀexecuted,ꢀwillꢀbeꢀtransferredꢀontoꢀtheꢀstack.ꢀTheꢀProgramꢀCounterꢀwillꢀthenꢀbeꢀloadedꢀwithꢀaꢀ
newꢀaddressꢀwhichꢀwillꢀbeꢀtheꢀvalueꢀofꢀtheꢀcorrespondingꢀinterruptꢀvector.ꢀTheꢀmicrocontrollerꢀwillꢀ
thenꢀfetchꢀitsꢀnextꢀinstructionꢀfromꢀthisꢀinterruptꢀvector.ꢀTheꢀinstructionꢀatꢀthisꢀvectorꢀwillꢀusuallyꢀ
beꢀaꢀJMPꢀwhichꢀwillꢀjumpꢀtoꢀanotherꢀsectionꢀofꢀprogramꢀwhichꢀisꢀknownꢀasꢀtheꢀinterruptꢀserviceꢀ
routine.ꢀHereꢀisꢀlocatedꢀtheꢀcodeꢀtoꢀcontrolꢀtheꢀappropriateꢀinterrupt.ꢀTheꢀinterruptꢀserviceꢀroutineꢀ
mustꢀbeꢀterminatedꢀwithꢀaꢀRETI,ꢀwhichꢀretrievesꢀtheꢀoriginalꢀProgramꢀCounterꢀaddressꢀfromꢀtheꢀ
stackꢀandꢀallowsꢀtheꢀmicrocontrollerꢀtoꢀcontinueꢀwithꢀnormalꢀexecutionꢀatꢀtheꢀpointꢀwhereꢀtheꢀ
interruptꢀoccurred.
Theꢀvariousꢀinterruptꢀenableꢀbits,ꢀtogetherꢀwithꢀtheirꢀassociatedꢀrequestꢀflags,ꢀareꢀshownꢀinꢀtheꢀ
accompanyingꢀdiagramsꢀwithꢀtheirꢀorderꢀofꢀpriority.ꢀSomeꢀinterruptꢀsourcesꢀhaveꢀtheirꢀownꢀ
individualꢀvectorꢀwhileꢀothersꢀshareꢀtheꢀsameꢀMulti-functionꢀInterruptꢀvector.ꢀOnceꢀanꢀinterruptꢀ
subroutineꢀisꢀserviced,ꢀallꢀtheꢀotherꢀinterruptsꢀwillꢀbeꢀblocked,ꢀasꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀ
EMIꢀbitꢀwillꢀbeꢀclearedꢀautomatically.ꢀThisꢀwillꢀpreventꢀanyꢀfurtherꢀinterruptꢀnestingꢀfromꢀoccurring.ꢀ
However,ꢀifꢀotherꢀinterruptꢀrequestsꢀoccurꢀduringꢀthisꢀinterval,ꢀalthoughꢀtheꢀinterruptꢀwillꢀnotꢀbeꢀ
immediatelyꢀserviced,ꢀtheꢀrequestꢀflagꢀwillꢀstillꢀbeꢀrecorded.
Ifꢀanꢀinterruptꢀrequiresꢀimmediateꢀservicingꢀwhileꢀtheꢀprogramꢀisꢀalreadyꢀinꢀanotherꢀinterruptꢀserviceꢀ
routine,ꢀtheꢀEMIꢀbitꢀshouldꢀbeꢀsetꢀafterꢀenteringꢀtheꢀroutine,ꢀtoꢀallowꢀinterruptꢀnesting.ꢀIfꢀtheꢀstackꢀ
isꢀfull,ꢀtheꢀinterruptꢀrequestꢀwillꢀnotꢀbeꢀacknowledged,ꢀevenꢀifꢀtheꢀrelatedꢀinterruptꢀisꢀenabled,ꢀuntilꢀ
theꢀStackꢀPointerꢀisꢀdecremented.ꢀIfꢀimmediateꢀserviceꢀisꢀdesired,ꢀtheꢀstackꢀmustꢀbeꢀpreventedꢀfromꢀ
becomingꢀfull.ꢀInꢀcaseꢀofꢀsimultaneousꢀrequests,ꢀtheꢀaccompanyingꢀdiagramꢀshowsꢀtheꢀpriorityꢀthatꢀ
isꢀapplied.ꢀAllꢀofꢀtheꢀinterruptꢀrequestꢀflagsꢀwhenꢀsetꢀwillꢀwake-upꢀtheꢀdevicesꢀifꢀitꢀisꢀinꢀSLEEPꢀorꢀ
IDLEꢀMode,ꢀhoweverꢀtoꢀpreventꢀaꢀwake-upꢀfromꢀoccurringꢀtheꢀcorrespondingꢀflagꢀshouldꢀbeꢀsetꢀ
beforeꢀtheꢀdevicesꢀareꢀinꢀSLEEPꢀorꢀIDLEꢀMode.
Rev. 1.40
185
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Legend
EMI auto disabled in ISR
xxF Request Flag, no auto reset in ISR
xxF Request Flag, auto reset in ISR
xxE Enable Bits
Interrupt
Name
Request
Flags
Enable
Bits
Master
Enable
Priority
High
Vector
INT0 Pin
INT0F
INT0E
EMI
EMI
EMI
04H
Comparator
CPF
CPE
08H
0CH
TM0 P
TM0 A
TM2 P
TM2 A
TM3 P
TM3 A
TM3 B
SPIA
T0PF
T0AF
T2PF
T2AF
T3PF
T3AF
T3BF
SPIAF
SIMF
DEF
T0PE
T0AE
T2PE
T2AE
T3PE
T3AE
T3BE
SPIAE
SIME
DEE
M. Funct. 0 MF0F
MF0E
M. Funct. 2 MF2F
M. Funct. 3 MF3F
M. Funct. 4 MF4F
MF2E
MF3E
MF4E
ADE
EMI
EMI
EMI
EMI
EMI
EMI
EMI
14H
18H
1CH
20H
24H
28H
2CH
A/D
ADF
SIM
Time Base 0 TB0F
Time Base 1 TB1F
TB0E
TB1E
INT1E
EEPROM
LVD
LVF
LVE
Interrupts contained within
Multi-Function Interrupts
INT1 Pin
INT1F
Low
Interrupt Structure – BC66F840
Legend
EMI auto disabled in ISR
xxF Request Flag, no auto reset in ISR
xxF Request Flag, auto reset in ISR
xxE Enable Bits
Interrupt
Name
Request
Flags
Enable
Master
Enable
Priority
High
Vector
Bits
INT0 Pin
INT0F
INT0E
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
04H
TM0 P
TM0 A
TM1 P
TM1 A
TM2 P
TM2 A
TM3 P
TM3 A
TM3 B
SPIA
T0PF
T0AF
T1PF
T1AF
T2PF
T2AF
T3PF
T3AF
T3BF
SPIAF
SIMF
DEF
T0PE
T0AE
T1PE
T1AE
T2PE
T2AE
T3PE
T3AE
T3BE
SPIAE
SIME
DEE
Comparator
CPF
CPE
MF0E
MF1E
MF2E
MF3E
MF4E
ADE
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
M. Funct. 0 MF0F
M. Funct. 1 MF1F
M. Funct. 2 MF2F
M. Funct. 3 MF3F
M. Funct. 4 MF4F
A/D
ADF
SIM
Time Base 0 TB0F
Time Base 1 TB1F
TB0E
TB1E
INT1E
EEPROM
LVD
LVF
LVE
Interrupts contained within
Multi-Function Interrupts
INT1 Pin
INT1F
Low
Interrupt Structure – BC66F850/BC66F860
Rev. 1.40
186
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
External Interrupt
TheꢀexternalꢀinterruptsꢀareꢀcontrolledꢀbyꢀsignalꢀtransitionsꢀonꢀtheꢀINT0~INT1ꢀpins.ꢀAnꢀexternalꢀ
interruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀexternalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT1F,ꢀareꢀset,ꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀtransition,ꢀwhoseꢀtypeꢀisꢀchosenꢀbyꢀtheꢀedgeꢀselectꢀbits,ꢀappearsꢀonꢀtheꢀ
externalꢀinterruptꢀpins.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀ
globalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀrespectiveꢀexternalꢀinterruptꢀenableꢀbit,ꢀINT0E~INT1E,ꢀmustꢀ
firstꢀbeꢀset.ꢀAdditionallyꢀtheꢀcorrectꢀinterruptꢀedgeꢀtypeꢀmustꢀbeꢀselectedꢀusingꢀtheꢀINTEGꢀregisterꢀtoꢀ
enableꢀtheꢀexternalꢀinterruptꢀfunctionꢀandꢀtoꢀchooseꢀtheꢀtriggerꢀedgeꢀtype.ꢀAsꢀtheꢀexternalꢀinterruptꢀ
pinsꢀareꢀpin-sharedꢀwithꢀI/Oꢀpins,ꢀtheyꢀcanꢀonlyꢀbeꢀconfiguredꢀasꢀexternalꢀinterruptꢀpinsꢀifꢀtheirꢀ
externalꢀinterruptꢀenableꢀbitꢀinꢀtheꢀcorrespondingꢀinterruptꢀregisterꢀhasꢀbeenꢀset.ꢀTheꢀpinꢀmustꢀalsoꢀ
beꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀinꢀtheꢀportꢀcontrolꢀregister.ꢀWhenꢀtheꢀinterruptꢀ
isꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀcorrectꢀtransitionꢀtypeꢀappearsꢀonꢀtheꢀexternalꢀinterruptꢀpin,ꢀ
aꢀsubroutineꢀcallꢀtoꢀtheꢀexternalꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀ
externalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT1F,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀ
automaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀNoteꢀthatꢀanyꢀpull-highꢀresistorꢀselectionsꢀonꢀtheꢀ
externalꢀinterruptꢀpinsꢀwillꢀremainꢀvalidꢀevenꢀifꢀtheꢀpinꢀisꢀusedꢀasꢀanꢀexternalꢀinterruptꢀinput.
TheꢀINTEGꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀtypeꢀofꢀactiveꢀedgeꢀthatꢀwillꢀtriggerꢀtheꢀexternalꢀinterrupt.ꢀ
Aꢀchoiceꢀofꢀeitherꢀrisingꢀorꢀfallingꢀorꢀbothꢀedgeꢀtypesꢀcanꢀbeꢀchosenꢀtoꢀtriggerꢀanꢀexternalꢀinterrupt.ꢀ
NoteꢀthatꢀtheꢀINTEGꢀregisterꢀcanꢀalsoꢀbeꢀusedꢀtoꢀdisableꢀtheꢀexternalꢀinterruptꢀfunction.ꢀTheꢀINT1ꢀ
pinꢀisꢀinternallyꢀconnectedꢀtoꢀtheꢀ2.4GHzꢀRFꢀTransceiverꢀinterruptꢀoutput.ꢀTheꢀcorrectꢀinterruptꢀedgeꢀ
typeꢀmustꢀbeꢀselectedꢀusingꢀtheꢀINTEGꢀregisterꢀtoꢀensureꢀtheꢀcorrectꢀinterruptꢀoperation.
Comparator Interrupt
Theꢀcomparatorꢀinterruptꢀisꢀcontrolledꢀbyꢀtheꢀinternalꢀcomparator.ꢀAꢀcomparatorꢀinterruptꢀrequestꢀ
willꢀtakeꢀplaceꢀwhenꢀtheꢀcomparatorꢀinterruptꢀrequestꢀflag,ꢀCPF,ꢀisꢀset,ꢀaꢀsituationꢀthatꢀwillꢀoccurꢀ
whenꢀtheꢀcomparatorꢀoutputꢀchangesꢀstate.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀ
vectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀcomparatorꢀinterruptꢀenableꢀbit,ꢀCPE,ꢀmustꢀ
firstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀcomparatorꢀinputsꢀgenerateꢀ
aꢀcomparatorꢀoutputꢀtransition,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀcomparatorꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀ
Whenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀcomparatorꢀinterruptꢀrequestꢀflag,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀ
theꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
Multi-function Interrupt
WithinꢀtheseꢀdevicesꢀthereꢀareꢀupꢀtoꢀfiveꢀMulti-functionꢀinterrupts.ꢀUnlikeꢀtheꢀotherꢀindependentꢀ
interrupts,ꢀtheseꢀinterruptsꢀhaveꢀnoꢀindependentꢀsource,ꢀbutꢀratherꢀareꢀformedꢀfromꢀotherꢀexistingꢀ
interruptꢀsources,ꢀnamelyꢀtheꢀTM,ꢀLVD,ꢀEEPROM,ꢀSIMꢀandꢀSPIAꢀinterrupts.
AꢀMulti-functionꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀ
flags,ꢀMFnFꢀareꢀset.ꢀTheꢀMulti-functionꢀinterruptꢀflagsꢀwillꢀbeꢀsetꢀwhenꢀanyꢀofꢀtheirꢀincludedꢀ
functionsꢀgenerateꢀanꢀinterruptꢀrequestꢀflag.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀ
interruptꢀvectorꢀaddress,ꢀwhenꢀtheꢀMulti-functionꢀinterruptꢀisꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀandꢀ
eitherꢀoneꢀofꢀtheꢀinterruptsꢀcontainedꢀwithinꢀeachꢀofꢀMulti-functionꢀinterruptꢀoccurs,ꢀaꢀsubroutineꢀ
callꢀtoꢀoneꢀofꢀtheꢀMulti-functionꢀinterruptꢀvectorsꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀ
relatedꢀMulti-Functionꢀrequestꢀflag,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀdisableꢀotherꢀinterrupts.
However,ꢀitꢀmustꢀbeꢀnotedꢀthat,ꢀalthoughꢀtheꢀMulti-functionꢀInterruptꢀflagsꢀwillꢀbeꢀautomaticallyꢀ
resetꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrequestꢀflagsꢀfromꢀtheꢀoriginalꢀsourceꢀofꢀtheꢀMulti-functionꢀ
interrupts,ꢀnamelyꢀtheꢀTM,ꢀLVD,ꢀEEPROM,ꢀSIMꢀandꢀSPIAꢀinterrupts,ꢀwillꢀnotꢀbeꢀautomaticallyꢀ
resetꢀandꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.40
18ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
A/D Converter Interrupt
TheꢀA/DꢀConverterꢀInterruptꢀisꢀcontrolledꢀbyꢀtheꢀterminationꢀofꢀanꢀA/Dꢀconversionꢀprocess.ꢀAnꢀA/Dꢀ
ConverterꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀA/DꢀConverterꢀInterruptꢀrequestꢀflag,ꢀADF,ꢀisꢀ
set,ꢀwhichꢀoccursꢀwhenꢀtheꢀA/Dꢀconversionꢀprocessꢀfinishes.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀ
respectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀA/DꢀInterruptꢀenableꢀbit,ꢀ
ADE,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀA/Dꢀconversionꢀ
processꢀhasꢀended,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀA/DꢀConverterꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀ
interruptꢀisꢀserviced,ꢀtheꢀA/DꢀConverterꢀInterruptꢀflag,ꢀADF,ꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀTheꢀEMIꢀ
bitꢀwillꢀalsoꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
Time Base Interrupt
TheꢀfunctionꢀofꢀtheꢀTimeꢀBaseꢀInterruptsꢀisꢀtoꢀprovideꢀregularꢀtimeꢀsignalꢀinꢀtheꢀformꢀofꢀanꢀinternalꢀ
interrupt.ꢀTheyꢀareꢀcontrolledꢀbyꢀtheꢀoverflowꢀsignalsꢀfromꢀtheirꢀrespectiveꢀtimerꢀfunctions.ꢀWhenꢀ
theseꢀhappensꢀtheirꢀrespectiveꢀinterruptꢀrequestꢀflags,ꢀTB0FꢀorꢀTB1Fꢀwillꢀbeꢀset.ꢀToꢀallowꢀtheꢀ
programꢀtoꢀbranchꢀtoꢀtheirꢀrespectiveꢀinterruptꢀvectorꢀaddresses,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMIꢀ
andꢀTimeꢀBaseꢀenableꢀbits,ꢀTB0EꢀorꢀTB1E,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀ
isꢀnotꢀfullꢀandꢀtheꢀTimeꢀBaseꢀoverflows,ꢀaꢀsubroutineꢀcallꢀtoꢀtheirꢀrespectiveꢀvectorꢀlocationsꢀwillꢀ
takeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrespectiveꢀinterruptꢀrequestꢀflag,ꢀTB0FꢀorꢀTB1F,ꢀwillꢀ
beꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
TheꢀpurposeꢀofꢀtheꢀTimeꢀBaseꢀInterruptꢀisꢀtoꢀprovideꢀanꢀinterruptꢀsignalꢀatꢀfixedꢀtimeꢀperiods.ꢀTheirꢀ
clockꢀsourcesꢀoriginateꢀfromꢀtheꢀinternalꢀclockꢀsourceꢀfTB.ꢀThisꢀfTBꢀinputꢀclockꢀpassesꢀthroughꢀaꢀ
divider,ꢀtheꢀdivisionꢀratioꢀofꢀwhichꢀisꢀselectedꢀbyꢀprogrammingꢀtheꢀappropriateꢀbitsꢀinꢀtheꢀTBCꢀ
registerꢀtoꢀobtainꢀlongerꢀinterruptꢀperiodsꢀwhoseꢀvalueꢀranges.ꢀTheꢀclockꢀsourceꢀthatꢀgeneratesꢀfTB,ꢀ
whichꢀinꢀturnꢀcontrolsꢀtheꢀTimeꢀBaseꢀinterruptꢀperiod,ꢀcanꢀoriginateꢀfromꢀseveralꢀdifferentꢀsources,ꢀ
asꢀshownꢀinꢀtheꢀSystemꢀOperatingꢀModeꢀsection.
TB0ꢁ~TB00
÷ꢁ8 ~ ÷ꢁ15
Time Base 0 Interrupt
�
U
X
fSUB
fTB
fSYS/4
÷ꢁ1ꢁ ~ ÷ꢁ15
Time Base 1 Interrupt
TBCK
TB11~TB10
Time Base Interrupt
Rev. 1.40
188
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
TBC Register
Bit
Name
R/W
7
TBON
R/W
0
6
TBCK
R/W
0
5
TB11
R/W
1
4
TB10
R/W
1
3
LXTLP
R/W
0
2
TB0ꢁ
R/W
1
1
TB01
R/W
1
0
TB00
R/W
1
POR
Bitꢀ7
TBON:ꢀTimeꢀBaseꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ6
TBCK:ꢀTimeꢀBaseꢀclockꢀfTBꢀselection
0:ꢀfSUB
1:ꢀfSYS/4
Bitꢀ5~4
TB11~TB10:ꢀSelectꢀTimeꢀBaseꢀ1ꢀTime-outꢀPeriod
00:ꢀ4096/fTB
01:ꢀ8192/fTB
10:ꢀ16384/fTB
11:ꢀ32768/fTB
Bitꢀ3
LXTLP:ꢀLXTꢀOscillatorꢀLowꢀPowerꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ2~0
TB02~TB00:ꢀSelectꢀTimeꢀBaseꢀ0ꢀTime-outꢀPeriod
000:ꢀ256/fTB
001:ꢀ512/fTB
010:ꢀ1024/fTB
011:ꢀ2048/fTB
100:ꢀ4096/fTB
101:ꢀ8192/fTB
110:ꢀ16384/fTB
111:ꢀ32768/fTB
Rev. 1.40
189
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
EEPROM Interrupt
TheꢀEEPROMꢀInterrupt,ꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀEEPROMꢀInterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀEEPROMꢀInterruptꢀrequestꢀflag,ꢀDEF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀ
anꢀEEPROMꢀWriteꢀcycleꢀends.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀ
address,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀEEPROMꢀInterruptꢀenableꢀbit,ꢀDEE,ꢀandꢀassociatedꢀ
Multi-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀ
fullꢀandꢀanꢀEEPROMꢀWriteꢀcycleꢀends,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀMulti-functionꢀInterruptꢀ
vector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀEEPROMꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
alsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀDEFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀ
theꢀapplicationꢀprogram.
LVD Interrupt
TheꢀLowꢀVoltageꢀDetectorꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀLVDꢀ
InterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀLVDꢀInterruptꢀrequestꢀflag,ꢀLVF,ꢀisꢀset,ꢀwhichꢀoccursꢀ
whenꢀtheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀdetectsꢀaꢀlowꢀpowerꢀsupplyꢀvoltage.ꢀToꢀallowꢀtheꢀprogramꢀ
toꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀLowꢀVoltageꢀ
Interruptꢀenableꢀbit,ꢀLVE,ꢀandꢀassociatedꢀMulti-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀ
theꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀ
theꢀMulti-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀLowꢀVoltageꢀInterruptꢀisꢀserviced,ꢀtheꢀ
EMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀLVFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀ
cleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
Serial Interface Module Interrupt
TheꢀSerialꢀInterfaceꢀModuleꢀInterrupt,ꢀalsoꢀknownꢀasꢀtheꢀSIMꢀinterrupt,ꢀisꢀcontainedꢀwithinꢀtheꢀ
Multi-functionꢀInterrupt.ꢀAꢀSIMꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀSIMꢀInterruptꢀrequestꢀ
flag,ꢀSIMF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀreceivedꢀorꢀtransmittedꢀbyꢀtheꢀSIMꢀ
interface.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀ
interruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSerialꢀInterfaceꢀInterruptꢀenableꢀbit,ꢀSIME,ꢀandꢀMulti-functionꢀ
interruptꢀenableꢀbits,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀbyteꢀ
ofꢀdataꢀhasꢀbeenꢀtransmittedꢀorꢀreceivedꢀbyꢀtheꢀSIMꢀinterface,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀ
Multi-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀSerialꢀInterfaceꢀInterruptꢀisꢀserviced,ꢀtheꢀ
EMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀSIMFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀ
cleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.40
190
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPIA Interface Interrupt
TheꢀSPIAꢀInterfaceꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAꢀSPIAꢀInterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀSPIAꢀInterruptꢀrequestꢀflag,ꢀSPIAF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀ
byteꢀofꢀdataꢀhasꢀbeenꢀreceivedꢀorꢀtransmittedꢀbyꢀtheꢀSPIAꢀinterface.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀ
toꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSPIAꢀInterfaceꢀ
Interruptꢀenableꢀbit,ꢀSPIAE,ꢀandꢀMulti-functionꢀinterruptꢀenableꢀbits,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀ
interruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀtransmittedꢀorꢀreceivedꢀbyꢀtheꢀ
SPIAꢀinterface,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀMulti-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀ
WhenꢀtheꢀSPIAꢀInterfaceꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀ
otherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀ
cleared.ꢀAsꢀtheꢀSPIAFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀ
program.
TM Interrupt
TheꢀCompactꢀandꢀStandardꢀTypeꢀTMsꢀhaveꢀtwoꢀinterruptsꢀeachꢀwhileꢀtheꢀEnhancedꢀTypeꢀTMꢀhasꢀ
threeꢀinterrupts.ꢀAllꢀofꢀtheꢀTMꢀinterruptsꢀareꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupts.ꢀForꢀeachꢀ
ofꢀtheꢀCompactꢀandꢀStandardꢀTypeꢀTMsꢀthereꢀareꢀtwoꢀinterruptꢀrequestꢀflagsꢀTnPFꢀandꢀTnAFꢀandꢀ
twoꢀenableꢀbitsꢀTnPEꢀandꢀTnAE.ꢀForꢀtheꢀEnhancedꢀTypeꢀTMꢀthereꢀareꢀthreeꢀinterruptꢀrequestꢀflagsꢀ
TnPF,ꢀTnAFꢀandꢀTnBFꢀandꢀthreeꢀenableꢀbitsꢀTnPE,ꢀTnAEꢀandꢀTnBE.ꢀAꢀTMꢀinterruptꢀrequestꢀwillꢀ
takeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀTMꢀrequestꢀflagsꢀareꢀset,ꢀaꢀsituationꢀwhichꢀoccursꢀwhenꢀaꢀTMꢀcomparatorꢀ
P,ꢀAꢀorꢀBꢀmatchꢀsituationꢀhappens.
Toꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀ
bit,ꢀEMI,ꢀrespectiveꢀTMꢀInterruptꢀenableꢀbit,ꢀandꢀrelevantꢀMulti-functionꢀInterruptꢀenableꢀbit,ꢀMFnE,ꢀ
mustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀTMꢀcomparatorꢀmatchꢀ
situationꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrelevantꢀMulti-functionꢀInterruptꢀvectorꢀlocations,ꢀwillꢀtakeꢀ
place.ꢀWhenꢀtheꢀTMꢀinterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀ
interrupts,ꢀhoweverꢀonlyꢀtheꢀrelatedꢀMFnFꢀflagꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀTMꢀinterruptꢀ
requestꢀflagsꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀtheyꢀhaveꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
Interrupt Wake-up Function
Eachꢀofꢀtheꢀinterruptꢀfunctionsꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode.ꢀAꢀwake-upꢀisꢀgeneratedꢀwhenꢀanꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀ
toꢀhighꢀandꢀisꢀindependentꢀofꢀwhetherꢀtheꢀinterruptꢀisꢀenabledꢀorꢀnot.ꢀTherefore,ꢀevenꢀthoughꢀtheꢀ
devicesꢀareꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀandꢀitsꢀsystemꢀoscillatorꢀstopped,ꢀsituationsꢀsuchꢀasꢀ
externalꢀedgeꢀtransitionsꢀonꢀtheꢀexternalꢀinterruptꢀpins,ꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀorꢀcomparatorꢀ
outputꢀchangeꢀmayꢀcauseꢀtheirꢀrespectiveꢀinterruptꢀflagꢀtoꢀbeꢀsetꢀhighꢀandꢀconsequentlyꢀgenerateꢀ
anꢀinterrupt.ꢀCareꢀmustꢀthereforeꢀbeꢀtakenꢀifꢀspuriousꢀwake-upꢀsituationsꢀareꢀtoꢀbeꢀavoided.ꢀIfꢀanꢀ
interruptꢀwake-upꢀfunctionꢀisꢀtoꢀbeꢀdisabledꢀthenꢀtheꢀcorrespondingꢀinterruptꢀrequestꢀflagꢀshouldꢀbeꢀ
setꢀhighꢀbeforeꢀtheꢀdevicesꢀenterꢀtheꢀSLEEPꢀorꢀIDLEꢀMode.ꢀTheꢀinterruptꢀenableꢀbitsꢀhaveꢀnoꢀeffectꢀ
onꢀtheꢀinterruptꢀwake-upꢀfunction.
Rev. 1.40
191
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Programming Considerations
Byꢀdisablingꢀtheꢀrelevantꢀinterruptꢀenableꢀbits,ꢀaꢀrequestedꢀinterruptꢀcanꢀbeꢀpreventedꢀfromꢀbeingꢀ
serviced,ꢀhowever,ꢀonceꢀanꢀinterruptꢀrequestꢀflagꢀisꢀset,ꢀitꢀwillꢀremainꢀinꢀthisꢀconditionꢀinꢀtheꢀ
interruptꢀregisterꢀuntilꢀtheꢀcorrespondingꢀinterruptꢀisꢀservicedꢀorꢀuntilꢀtheꢀrequestꢀflagꢀisꢀclearedꢀbyꢀ
theꢀapplicationꢀprogram.
WhereꢀaꢀcertainꢀinterruptꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀinterrupt,ꢀthenꢀwhenꢀtheꢀinterruptꢀ
serviceꢀroutineꢀisꢀexecuted,ꢀasꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflags,ꢀMFnF,ꢀwillꢀbeꢀ
automaticallyꢀcleared,ꢀtheꢀindividualꢀrequestꢀflagꢀforꢀtheꢀfunctionꢀneedsꢀtoꢀbeꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.
ItꢀisꢀrecommendedꢀthatꢀprogramsꢀdoꢀnotꢀuseꢀtheꢀCALLꢀinstructionꢀwithinꢀtheꢀinterruptꢀserviceꢀ
subroutine.ꢀInterruptsꢀoftenꢀoccurꢀinꢀanꢀunpredictableꢀmannerꢀorꢀneedꢀtoꢀbeꢀservicedꢀimmediately.ꢀ
Ifꢀonlyꢀoneꢀstackꢀisꢀleftꢀandꢀtheꢀinterruptꢀisꢀnotꢀwellꢀcontrolled,ꢀtheꢀoriginalꢀcontrolꢀsequenceꢀwillꢀbeꢀ
damagedꢀonceꢀaꢀCALLꢀsubroutineꢀisꢀexecutedꢀinꢀtheꢀinterruptꢀsubroutine.
EveryꢀinterruptꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀitꢀisꢀinꢀSLEEPꢀorꢀIDLEꢀ
Mode,ꢀtheꢀwakeꢀupꢀbeingꢀgeneratedꢀwhenꢀtheꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀtoꢀhigh.ꢀIfꢀitꢀisꢀ
requiredꢀtoꢀpreventꢀaꢀcertainꢀinterruptꢀfromꢀwakingꢀupꢀtheꢀmicrocontrollerꢀthenꢀitsꢀrespectiveꢀrequestꢀ
flagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀenterꢀSLEEPꢀorꢀIDLEꢀMode.
AsꢀonlyꢀtheꢀProgramꢀCounterꢀisꢀpushedꢀontoꢀtheꢀstack,ꢀthenꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀifꢀtheꢀ
contentsꢀofꢀtheꢀaccumulator,ꢀstatusꢀregisterꢀorꢀotherꢀregistersꢀareꢀalteredꢀbyꢀtheꢀinterruptꢀserviceꢀ
program,ꢀtheirꢀcontentsꢀshouldꢀbeꢀsavedꢀtoꢀtheꢀmemoryꢀatꢀtheꢀbeginningꢀofꢀtheꢀinterruptꢀserviceꢀ
routine.
Toꢀreturnꢀfromꢀanꢀinterruptꢀsubroutine,ꢀeitherꢀaꢀRETꢀorꢀRETIꢀinstructionꢀmayꢀbeꢀexecuted.ꢀTheꢀRETIꢀ
instructionꢀinꢀadditionꢀtoꢀexecutingꢀaꢀreturnꢀtoꢀtheꢀmainꢀprogramꢀalsoꢀautomaticallyꢀsetsꢀtheꢀEMIꢀ
bitꢀhighꢀtoꢀallowꢀfurtherꢀinterrupts.ꢀTheꢀRETꢀinstructionꢀhoweverꢀonlyꢀexecutesꢀaꢀreturnꢀtoꢀtheꢀmainꢀ
programꢀleavingꢀtheꢀEMIꢀbitꢀinꢀitsꢀpresentꢀzeroꢀstateꢀandꢀthereforeꢀdisablingꢀtheꢀexecutionꢀofꢀfurtherꢀ
interrupts.
Rev. 1.40
19ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Low Voltage Detector – LVD
EachꢀdeviceꢀhasꢀaꢀLowꢀVoltageꢀDetectorꢀfunction,ꢀalsoꢀknownꢀasꢀLVD.ꢀThisꢀenabledꢀtheꢀdevicesꢀtoꢀ
monitorꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀandꢀprovideꢀaꢀwarningꢀsignalꢀshouldꢀitꢀfallꢀbelowꢀaꢀcertainꢀ
level.ꢀThisꢀfunctionꢀmayꢀbeꢀespeciallyꢀusefulꢀinꢀbatteryꢀapplicationsꢀwhereꢀtheꢀsupplyꢀvoltageꢀwillꢀ
graduallyꢀreduceꢀasꢀtheꢀbatteryꢀages,ꢀasꢀitꢀallowsꢀanꢀearlyꢀwarningꢀbatteryꢀlowꢀsignalꢀtoꢀbeꢀgenerated.ꢀ
TheꢀLowꢀVoltageꢀDetectorꢀalsoꢀhasꢀtheꢀcapabilityꢀofꢀgeneratingꢀanꢀinterruptꢀsignal.
LVD Register
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀcontrolledꢀusingꢀaꢀsingleꢀregisterꢀwithꢀtheꢀnameꢀLVDC.ꢀThreeꢀ
bitsꢀinꢀthisꢀregister,ꢀVLVD2~VLVD0,ꢀareꢀusedꢀtoꢀselectꢀoneꢀofꢀeightꢀfixedꢀvoltagesꢀbelowꢀwhichꢀaꢀ
lowꢀvoltageꢀconditionꢀwillꢀbeꢀdetemined.ꢀAꢀlowꢀvoltageꢀconditionꢀisꢀindicatedꢀwhenꢀtheꢀLVDOꢀbitꢀisꢀ
set.ꢀIfꢀtheꢀLVDOꢀbitꢀisꢀlow,ꢀthisꢀindicatesꢀthatꢀtheꢀVDDꢀvoltageꢀisꢀaboveꢀtheꢀpresetꢀlowꢀvoltageꢀvalue.ꢀ
TheꢀLVDENꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀlowꢀvoltageꢀdetector.ꢀSettingꢀtheꢀ
bitꢀhighꢀwillꢀenableꢀtheꢀlowꢀvoltageꢀdetector.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀwillꢀswitchꢀoffꢀtheꢀinternalꢀlowꢀ
voltageꢀdetectorꢀcircuits.ꢀAsꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀconsumeꢀaꢀcertainꢀamountꢀofꢀpower,ꢀitꢀmayꢀ
beꢀdesirableꢀtoꢀswitchꢀoffꢀtheꢀcircuitꢀwhenꢀnotꢀinꢀuse,ꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀ
batteryꢀpoweredꢀapplications.
LVDC Register
Bit
7
6
5
LVDO
R
4
LVDEN
R/W
0
3
2
VLVDꢁ
R/W
0
1
VLVD1
R/W
0
0
VLVD0
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~6ꢀ
Bitꢀ5
Unimplemented,ꢀreadꢀasꢀ“0”
LVDO:ꢀLVDꢀOutputꢀFlag
0:ꢀNoꢀLowꢀVoltageꢀDetect
1:ꢀLowꢀVoltageꢀDetect
Bitꢀ4
LVDEN:ꢀLowꢀVoltageꢀDetectorꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ3ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ2~0
VLVD2~VLVD0:ꢀSelectꢀLVDꢀVoltage
000:ꢀ2.0V
001:ꢀ2.2V
010:ꢀ2.4V
011:ꢀ2.7V
100:ꢀ3.0V
101:ꢀ3.3V
110:ꢀ3.6V
111:ꢀ4.0V
Rev. 1.40
193
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
LVD Operation
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀoperatesꢀbyꢀcomparingꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀwithꢀaꢀ
pre-specifiedꢀvoltageꢀlevelꢀstoredꢀinꢀtheꢀLVDCꢀregister.ꢀThisꢀhasꢀaꢀrangeꢀofꢀbetweenꢀ2.0Vꢀandꢀ4.0V.ꢀ
Whenꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀfallsꢀbelowꢀthisꢀpre-determinedꢀvalue,ꢀtheꢀLVDOꢀbitꢀwillꢀbeꢀ
setꢀhighꢀindicatingꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀcondition.ꢀTheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀ
suppliedꢀbyꢀaꢀreferenceꢀvoltageꢀwhichꢀwillꢀbeꢀautomaticallyꢀenabled.ꢀWhenꢀtheꢀdevicesꢀareꢀpoweredꢀ
downꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀremainꢀactiveꢀifꢀtheꢀLVDENꢀbitꢀisꢀhigh.ꢀAfterꢀenablingꢀtheꢀLowꢀ
VoltageꢀDetector,ꢀaꢀtimeꢀdelayꢀtLVDSꢀshouldꢀbeꢀallowedꢀforꢀtheꢀcircuitryꢀtoꢀstabiliseꢀbeforeꢀreadingꢀtheꢀ
LVDOꢀbit.ꢀNoteꢀalsoꢀthatꢀasꢀtheꢀVDDꢀvoltageꢀmayꢀriseꢀandꢀfallꢀratherꢀslowly,ꢀatꢀtheꢀvoltageꢀnearsꢀthatꢀ
ofꢀVLVD,ꢀthereꢀmayꢀbeꢀmultipleꢀbitꢀLVDOꢀtransitions.ꢀ
TheꢀLowꢀVoltageꢀDetectorꢀalsoꢀhasꢀitsꢀownꢀinterruptꢀwhichꢀisꢀcontainedꢀwithinꢀoneꢀofꢀtheꢀMulti-
functionꢀinterrupts,ꢀprovidingꢀanꢀalternativeꢀmeansꢀofꢀlowꢀvoltageꢀdetection,ꢀinꢀadditionꢀtoꢀpollingꢀ
theꢀLVDOꢀbit.ꢀTheꢀinterruptꢀwillꢀonlyꢀbeꢀgeneratedꢀafterꢀaꢀdelayꢀofꢀtLVDꢀafterꢀtheꢀLVDOꢀbitꢀhasꢀbeenꢀ
setꢀhighꢀbyꢀaꢀlowꢀvoltageꢀcondition.ꢀWhenꢀtheꢀdevicesꢀareꢀpoweredꢀdownꢀtheꢀLowꢀVoltageꢀDetectorꢀ
willꢀremainꢀactiveꢀifꢀtheꢀLVDENꢀbitꢀisꢀhigh.ꢀInꢀthisꢀcase,ꢀtheꢀLVFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀset,ꢀ
causingꢀanꢀinterruptꢀtoꢀbeꢀgeneratedꢀifꢀVDDꢀfallsꢀbelowꢀtheꢀpresetꢀLVDꢀvoltage.ꢀThisꢀwillꢀcauseꢀtheꢀ
devicesꢀtoꢀwake-upꢀfromꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀhoweverꢀifꢀtheꢀLowꢀVoltageꢀDetectorꢀwakeꢀupꢀ
functionꢀisꢀnotꢀrequiredꢀthenꢀtheꢀLVFꢀflagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀtheꢀdevicesꢀenterꢀtheꢀSLEEPꢀ
orꢀIDLEꢀMode.
V
D
D
V
L
D
V
L
D
V
N
E
L
D
V
O
t
L
D
V
S
LVD Operation
Rev. 1.40
194
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver
TheꢀRFꢀtransceiverꢀoperatesꢀinꢀtheꢀworldꢀwideꢀISMꢀfrequencyꢀbandꢀofꢀ2400~2483.5MHz.ꢀBurstꢀ
modeꢀtransmissionꢀandꢀupꢀtoꢀ2Mbpsꢀairꢀdataꢀrateꢀmakeꢀthemꢀsuitableꢀforꢀapplicationsꢀrequiringꢀultraꢀ
lowꢀpowerꢀconsumption.ꢀItꢀoperatesꢀasꢀeitherꢀaꢀtransmitterꢀorꢀaꢀreceiverꢀinꢀtheꢀTimeꢀDivisionꢀDuplexꢀ
mode,ꢀabbreviatedꢀasꢀTDD.
TheꢀRFꢀchannelꢀfrequencyꢀdeterminesꢀtheꢀcenterꢀofꢀtheꢀchannelꢀusedꢀbyꢀtheꢀtransceiver.ꢀTheꢀ
frequencyꢀisꢀsetꢀbyꢀconfiguringꢀtheꢀRF_CHꢀregisterꢀinꢀregisterꢀbankꢀ0ꢀaccordingꢀtoꢀtheꢀfollowingꢀ
formula:ꢀF0=2400ꢀ+ꢀRF_CHꢀ(MHz).ꢀTheꢀresolutionꢀofꢀtheꢀRFꢀchannelꢀfrequencyꢀisꢀ1MHz.
AꢀtransmitterꢀandꢀaꢀreceiverꢀmustꢀbeꢀprogrammedꢀwithꢀtheꢀsameꢀRFꢀchannelꢀfrequencyꢀtoꢀbeꢀableꢀtoꢀ
communicateꢀwithꢀeachꢀother.ꢀTheꢀoutputꢀpowerꢀofꢀtheꢀtransceiverꢀisꢀsetꢀbyꢀtheꢀRF_PWRꢀbitsꢀinꢀtheꢀ
RF_SETUPꢀregister.ꢀDemodulationꢀisꢀimplementedꢀwithꢀtheꢀembeddedꢀdataꢀslicerꢀandꢀbitꢀrecoveryꢀ
logic.ꢀTheꢀairꢀdataꢀrateꢀcanꢀbeꢀprogrammedꢀtoꢀbeꢀ250Kbps,ꢀ1Mbpsꢀorꢀ2Mbpsꢀbyꢀconfiguringꢀtheꢀ
RF_DR_HIGHꢀandꢀRF_DR_LOWꢀregisters.ꢀAꢀtransmitterꢀandꢀaꢀreceiverꢀmustꢀbeꢀprogrammedꢀwithꢀ
theꢀsameꢀsetting.
CSN
SCK
RX FIFO
RFP1
RFN1
F�
Demodulator
�OSI
�ISO
Data Slicer
Packet
Processing
&
Integrated
TDD RF
Transceiver
IRQ
CE
Power
�anagement
State Control
F�
�odulator
Gaussian
Shaping
TX FIFO
CLKO
RF Transceiver Block Diagram
Rev. 1.40
195
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Abbreviations
ACK
Acknowledgement
ARC
ARD
CD
CE
Auto Retransmission Count
Auto Retransmission Delay
Carrier Detection
Chip Enable
CRC
CSN
Cyclic Redundancy Check
Chip Select Not
DPL
Dynamic Payload Length
First-In-First-Out
Gaussian Frequency Shift Keying
Gigahertz
FIFO
GFSK
GHz
LNA
IRQ
ISM
LSB
MAX_RT
Mbps
MCU
Low Noise Amplifier
Interrupt Request
Industrial-Scientific-Medical
Least Significant Bit
Maximum Retransmit
Megabit per second
Microcontroller Unit
Megahertz
MHz
MISO
MOSI
MSB
Master In Slave Out
Master Out Slave In
Most Significant Bit
Power Amplifier
PA
PID
PLD
Packet Identity Bits
Payload
PRX
Primary RX
PTX
Primary TX
PWD_DWN
PWD_UP
RF_CH
RSSI
RX
Power Down
Power Up
Radio Frequency Channel
Received Signal Strength Indicator
Receive
RX_DR
SCK
Receive Data Ready
SPI Clock
SPI
TDD
TX
Serial Peripheral Interface
Time Division Duplex
Transmit
TX_DS
XTAL
Transmit Data Sent
Crystal
Rev. 1.40
196
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver State Control
TheꢀRFꢀtransceiverꢀblockꢀincludesꢀanꢀintegratedꢀaꢀstateꢀmachineꢀthatꢀcontrolsꢀtheꢀstateꢀtransitionꢀ
betweenꢀdifferentꢀmodes.ꢀWhenꢀtheꢀautoꢀacknowledgeꢀfeatureꢀisꢀdisabled,ꢀtheꢀstateꢀtransitionꢀwillꢀbeꢀ
fullyꢀcontrolledꢀbyꢀtheꢀMCU.
•ꢀ SPIꢀregister:ꢀPWR_UP,ꢀPRIM_RX,ꢀEN_AA,ꢀNO_ACK,ꢀARC,ꢀARD
•ꢀ Systemꢀinformation:ꢀTimeꢀout,ꢀACKꢀreceived,ꢀARDꢀelapsed,ꢀARC_CNT,ꢀTXꢀFIFOꢀempty,ꢀACKꢀ
packetꢀtransmitted,ꢀPacketꢀreceived
•ꢀ Primary Transmission State Control – PTX, PRIM_RX=0
VDD>1.9V
Power Down
PWR_UP=1
PWR_UP=0
Start up time 1.5ms
üüü
-I
TX FIFO not emptꢀ
CE=1 for more than 15µs
ARD elapsed and ARC_CNT<ARC
TX setting 130µs
Time out or ACK received
TX FIFO not emptꢀ
CE=1
TX setting 130µs
TX finished
CE=0
RX
TX
TX FIFO emptꢀ
CE=1
üüü
-II
EN_AA=1
NO_ACK=0
RX setting 130µs
Primary Transmission State Diagram
Rev. 1.40
19ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Primary Reception State Control – PRX, PRIM_RX=1
VDD>1.9V
Power Down
PWR_UP=1
Start up time 1.5ms
PWR_UP=0
üüü
-I
CE=0
CE=1
RX setting 130µs
CE=0
RX
TX
ACK packet transmitted
CE=1
RX setting 130µs
Packet received
EN_AA=1
NO_ACK=0
TX setting 130µs
Primary Reception State Diagram
Power Down Mode
TheꢀPowerꢀdownꢀmodeꢀofꢀtheꢀRFꢀTransceiverꢀisꢀenteredꢀbyꢀsettingꢀtheꢀPWR_UPꢀbitꢀinꢀtheꢀCONFIGꢀ
registerꢀtoꢀlow.ꢀInꢀtheꢀpowerꢀdownꢀmodeꢀtheꢀtransceiverꢀblockꢀisꢀinꢀtheꢀsleepꢀmodeꢀwhereꢀitꢀhasꢀ
minimalꢀcurrentꢀconsumption.ꢀHowever,ꢀtheꢀSPIꢀinterfaceꢀisꢀstillꢀactiveꢀinꢀthisꢀmodeꢀandꢀallꢀregisterꢀ
valuesꢀcanꢀbeꢀconfiguredꢀbyꢀtheꢀSPIꢀinterface.
TheꢀMCUꢀandꢀRFꢀTransceiverꢀareꢀpoweredꢀdownꢀindependentlyꢀofꢀeachꢀother.ꢀTheꢀmethodꢀofꢀ
poweringꢀdownꢀtheꢀMCUꢀisꢀcoveredꢀinꢀtheꢀpreviousꢀMCUꢀsectionꢀofꢀtheꢀdatasheet.ꢀTheꢀRFꢀ
TransceiverꢀmustꢀbeꢀpoweredꢀdownꢀbeforeꢀtheꢀMCUꢀisꢀpoweredꢀdown.ꢀThisꢀisꢀimplementedꢀbyꢀfirstꢀ
clearingꢀtheꢀPWR_UPꢀbitꢀinꢀtheꢀCONFIGꢀregisterꢀtoꢀdisableꢀtheꢀRFꢀTransceiverꢀcircuitryꢀandꢀthenꢀ
pullingꢀtheꢀSCSAꢀlineꢀtoꢀhighꢀtoꢀdisableꢀtheꢀRFꢀSPIꢀinterfaceꢀcircuitry.ꢀAfterꢀtheꢀRFꢀtransceiverꢀisꢀ
completelyꢀpoweredꢀdown,ꢀtheꢀMCUꢀcanꢀbeꢀpoweredꢀdownꢀtoꢀminimiseꢀtheꢀpowerꢀconsumption.
Standby-I Mode
ByꢀsettingꢀtheꢀPWR_UPꢀbitꢀinꢀtheꢀCONFIGꢀregisterꢀtoꢀ1ꢀandꢀde-assertingꢀtheꢀCEꢀsignalꢀtoꢀaꢀlowꢀ
state,ꢀtheꢀdevicesꢀenterꢀtheꢀStandby-Iꢀmode.ꢀTheꢀStandby-Iꢀmodeꢀisꢀusedꢀtoꢀminimiseꢀtheꢀaverageꢀ
currentꢀconsumptionꢀandꢀalsoꢀtoꢀmaintainꢀaꢀshorterꢀstart-upꢀtime.ꢀInꢀthisꢀmode,ꢀtheꢀclockꢀisꢀstillꢀ
active.ꢀWhenꢀtheꢀCEꢀsignalꢀisꢀsetꢀtoꢀaꢀlowꢀstate,ꢀtheꢀtransceiverꢀwillꢀreturnꢀtoꢀtheꢀStandby-Iꢀmodeꢀ
regardlessꢀofꢀwhetherꢀitꢀisꢀinꢀtheꢀTXꢀorꢀRXꢀmode.
Rev. 1.40
198
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Standby-II Mode
InꢀtheꢀStandby-IIꢀmodeꢀmoreꢀRFꢀTransceiverꢀcircuitryꢀisꢀactiveꢀthanꢀinꢀtheꢀStandby-Iꢀmodeꢀandꢀ
thereforeꢀmoreꢀcurrentꢀisꢀconsumed.ꢀTheꢀtransceiverꢀwillꢀenterꢀtheꢀStandby-IIꢀmodeꢀfromꢀtheꢀTXꢀ
modeꢀwhenꢀtheꢀCEꢀsignalꢀisꢀsetꢀtoꢀaꢀhighꢀstateꢀandꢀtheꢀTXꢀFIFOꢀisꢀempty.ꢀIfꢀaꢀnewꢀdataꢀpacketꢀisꢀ
uploadedꢀintoꢀtheꢀTXꢀFIFO,ꢀtheꢀdevicesꢀwillꢀautomaticallyꢀreturnꢀtoꢀtheꢀTXꢀmodeꢀandꢀtheꢀpacketꢀ
willꢀbeꢀtransmitted.
TX Mode
•ꢀ Primary Transmit Device – PTX, PRIM_RX=0
TheꢀTXꢀmodeꢀisꢀanꢀactiveꢀmodeꢀwhereꢀtheꢀPTXꢀdeviceꢀtransmitsꢀaꢀdataꢀpacket.ꢀToꢀenterꢀthisꢀmodeꢀ
fromꢀpowerꢀdownꢀmode,ꢀtheꢀPTXꢀdeviceꢀmustꢀsetꢀtheꢀPWR_UPꢀbitꢀtoꢀhigh,ꢀtheꢀPRIM_RXꢀbitꢀtoꢀ
low,ꢀaꢀpayloadꢀinꢀtheꢀTXꢀFIFOꢀandꢀgenerateꢀaꢀhighꢀpulseꢀonꢀtheꢀCEꢀlineꢀforꢀmoreꢀthanꢀ15μs.
TheꢀPTXꢀdeviceꢀstaysꢀinꢀtheꢀTXꢀmodeꢀuntilꢀitꢀfinishesꢀtransmittingꢀtheꢀcurrentꢀpacketꢀandꢀthenꢀentersꢀ
theꢀStandby-IIꢀmode.ꢀIfꢀtheꢀCEꢀsignalꢀisꢀinꢀaꢀlowꢀstate,ꢀitꢀwillꢀreturnꢀtoꢀStandby-Iꢀmode.ꢀIfꢀtheꢀCEꢀ
signalꢀisꢀinꢀaꢀhighꢀstate,ꢀtheꢀnextꢀactionꢀwillꢀbeꢀdeterminedꢀbyꢀtheꢀstatusꢀofꢀtheꢀTXꢀFIFO.ꢀIfꢀtheꢀTXꢀ
FIFOꢀisꢀnotꢀempty,ꢀtheꢀPTXꢀdeviceꢀwillꢀenterꢀtheꢀTXꢀmodeꢀandꢀthenꢀtransmitꢀtheꢀnextꢀpacket.ꢀIfꢀtheꢀ
TXꢀFIFOꢀisꢀempty,ꢀtheꢀPTXꢀdeviceꢀwillꢀremainꢀinꢀtheꢀStandby-IIꢀmode.ꢀItꢀisꢀimportantꢀtoꢀnoteꢀthatꢀitꢀ
neverꢀremainsꢀinꢀtheꢀTXꢀmodeꢀforꢀmoreꢀthanꢀ4msꢀduringꢀaꢀtransmitꢀoperation.
IfꢀtheꢀautoꢀretransmitꢀisꢀenabledꢀbyꢀsettingꢀtheꢀEN_AAꢀbitꢀtoꢀ1ꢀandꢀanꢀautoꢀacknowledgeꢀisꢀrequiredꢀ
byꢀsettingꢀtheꢀNO_ACKꢀbitꢀtoꢀ0,ꢀtheꢀPTXꢀdeviceꢀwillꢀenterꢀtheꢀTXꢀmodeꢀfromꢀtheꢀStandby-Iꢀmodeꢀ
whenꢀtheꢀARDꢀhasꢀelapsedꢀandꢀtheꢀnumberꢀofꢀretryꢀisꢀlessꢀthanꢀtheꢀARC.
TheꢀPTXꢀdeviceꢀwillꢀenterꢀtheꢀRXꢀmodeꢀfromꢀtheꢀTXꢀmodeꢀonlyꢀwhenꢀtheꢀEN_AAꢀbitꢀisꢀsetꢀtoꢀ1ꢀandꢀ
theꢀNO_ACKꢀbitꢀisꢀclearedꢀtoꢀ0ꢀtoꢀreceiveꢀtheꢀacknowledgeꢀpacket.
RX Mode
•ꢀ Primary Receive Device – PRX, PRIM_RX=1
TheꢀRXꢀmodeꢀisꢀanꢀactiveꢀmodeꢀwhereꢀtheꢀtransceiverꢀisꢀconfiguredꢀasꢀaꢀreceiver.ꢀToꢀenterꢀthisꢀRXꢀ
modeꢀfromꢀtheꢀStandby-Iꢀmode,ꢀtheꢀPRXꢀdeviceꢀmustꢀsetꢀtheꢀPWR_UPꢀbitꢀtoꢀhigh,ꢀtheꢀPRIM_RXꢀ
bitꢀtoꢀhighꢀandꢀtheꢀCEꢀsignalꢀtoꢀhigh.ꢀInꢀthisꢀmodeꢀtheꢀreceiverꢀdemodulatesꢀtheꢀsignalsꢀfromꢀtheꢀRFꢀ
channel,ꢀconstantlyꢀpresentingꢀtheꢀdemodulatedꢀdataꢀtoꢀtheꢀpacketꢀprocessingꢀengine.ꢀTheꢀpacketꢀ
processingꢀengineꢀcontinuouslyꢀsearchesꢀforꢀaꢀvalidꢀpacket.ꢀIfꢀaꢀvalidꢀpacketꢀisꢀfoundꢀbyꢀaꢀmatchingꢀ
addressꢀandꢀaꢀvalidꢀCRC,ꢀtheꢀpacketꢀpayloadꢀisꢀpresentedꢀtoꢀaꢀvacantꢀslotꢀinꢀtheꢀRXꢀFIFO.ꢀIfꢀtheꢀRXꢀ
FIFOꢀisꢀfull,ꢀtheꢀreceivedꢀpacketꢀwillꢀbeꢀdiscarded.
TheꢀPRXꢀdeviceꢀremainsꢀinꢀtheꢀRXꢀmodeꢀuntilꢀtheꢀMCUꢀconfiguresꢀitꢀtoꢀenterꢀtheꢀStandby-Iꢀmodeꢀ
orꢀPowerꢀDownꢀmode.ꢀInꢀtheꢀRXꢀmodeꢀaꢀcarrierꢀdetectionꢀsignal,ꢀCD,ꢀisꢀmadeꢀavailable.ꢀTheꢀCDꢀ
signalꢀisꢀsetꢀhighꢀwhenꢀanꢀRFꢀsignalꢀisꢀdetectedꢀonꢀtheꢀreceivingꢀfrequencyꢀchannel.ꢀTheꢀinternalꢀCDꢀ
signalꢀisꢀfilteredꢀbeforeꢀbeingꢀwrittenꢀintoꢀtheꢀCDꢀregister.ꢀTheꢀRFꢀsignalꢀmustꢀbeꢀpresentꢀforꢀatꢀleastꢀ
128μsꢀbeforeꢀtheꢀCDꢀsignalꢀisꢀsetꢀhigh.
TheꢀPRXꢀdeviceꢀwillꢀenterꢀtheꢀTXꢀmodeꢀfromꢀtheꢀRXꢀmodeꢀonlyꢀwhenꢀtheꢀEN_AAꢀbitꢀisꢀsetꢀtoꢀ1ꢀ
andꢀtheꢀNO_ACKꢀbitꢀisꢀclearedꢀtoꢀ0ꢀinꢀtheꢀreceivedꢀpacketꢀtoꢀtransmitꢀanꢀacknowledgeꢀpacketꢀwithꢀaꢀ
pendingꢀpayloadꢀinꢀtheꢀTXꢀFIFO.
Rev. 1.40
199
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Packet Processing
Packet Format
Theꢀcompleteꢀpacketꢀincludesꢀaꢀpreamble,ꢀ3~5ꢀaddressꢀbytes,ꢀaꢀpacketꢀcontrolꢀfield,ꢀ0~32ꢀpayloadꢀ
bytesꢀandꢀaꢀCRCꢀfield.
Preamble
(1 byte)
Address
(3~5 bytes)
Packet Control
(9/0 bits)
Payload
(0~32 bytes)
CRC
(2/1 bytes)
Payload Length
(6 bits)
PID
(2 bits)
NO_ACK
(1 bit)
Packet Format
Preamble
Theꢀpreambleꢀisꢀaꢀbitꢀsequenceꢀusedꢀtoꢀdetectꢀtheꢀ“0”ꢀandꢀ“1”ꢀlevelsꢀinꢀtheꢀreceiver.ꢀTheꢀpreambleꢀ
isꢀoneꢀbyteꢀlongꢀwhoseꢀvalueꢀisꢀeitherꢀ01010101ꢀorꢀ10101010.ꢀIfꢀtheꢀfirstꢀbitꢀinꢀtheꢀaddressꢀisꢀ1,ꢀtheꢀ
preambleꢀisꢀautomaticallyꢀsetꢀtoꢀ10101010ꢀwhileꢀifꢀtheꢀfirstꢀbitꢀisꢀ0,ꢀtheꢀpreambleꢀisꢀautomaticallyꢀ
setꢀtoꢀ01010101.ꢀThisꢀisꢀdoneꢀtoꢀensureꢀthereꢀareꢀenoughꢀtransitionsꢀinꢀtheꢀpreambleꢀtoꢀstabiliseꢀtheꢀ
receiver.
Address
Thisꢀfieldꢀisꢀtheꢀaddressꢀforꢀtheꢀreceiver.ꢀAnꢀaddressꢀensuresꢀthatꢀtheꢀpacketꢀisꢀdetectedꢀbyꢀtheꢀtargetꢀ
receiver.ꢀTheꢀaddressꢀfieldꢀcanꢀbeꢀconfiguredꢀtoꢀbeꢀ3,ꢀ4ꢀorꢀ5ꢀbytesꢀlongꢀbyꢀtheꢀAWꢀregister.ꢀTheꢀPRXꢀ
deviceꢀcanꢀopenꢀupꢀtoꢀsixꢀdataꢀpipesꢀtoꢀsupportꢀupꢀtoꢀsixꢀPTXꢀdevicesꢀwithꢀspecificꢀaddresses.ꢀAllꢀsixꢀ
PTXꢀdeviceꢀaddressesꢀareꢀsearchedꢀsimultaneously.ꢀInꢀtheꢀPRXꢀdevice,ꢀtheꢀdataꢀpipesꢀareꢀenabledꢀ
withꢀtheꢀcorrespondingꢀcontrolꢀbitsꢀinꢀtheꢀEN_RXADDRꢀregister.ꢀTheꢀdefaultꢀstatusꢀisꢀthatꢀonlyꢀ
dataꢀpipeꢀ0ꢀandꢀpipeꢀ1ꢀareꢀenabled.ꢀEachꢀdataꢀpipeꢀaddressꢀcanꢀbeꢀconfiguredꢀinꢀtheꢀRX_ADDR_PXꢀ
registers.ꢀEachꢀpipeꢀcanꢀhaveꢀupꢀtoꢀaꢀ5ꢀbyteꢀconfigurableꢀaddress.ꢀDataꢀpipeꢀ0ꢀhasꢀaꢀuniqueꢀ5-byteꢀ
address.ꢀDataꢀpipesꢀ1~5ꢀshareꢀtheꢀ4ꢀmostꢀsignificantꢀaddressꢀbytes.ꢀTheꢀleastꢀsignificantꢀbyteꢀmustꢀbeꢀ
uniqueꢀforꢀallꢀ6ꢀpipes.
ToꢀensureꢀthatꢀtheꢀACKꢀpacketꢀfromꢀtheꢀPRXꢀisꢀtransmittedꢀtoꢀtheꢀcorrectꢀPTX,ꢀtheꢀPRXꢀtakesꢀtheꢀ
dataꢀpipeꢀaddressꢀwhereꢀitꢀreceivedꢀtheꢀpacketꢀandꢀusesꢀitꢀasꢀtheꢀTXꢀaddressꢀwhenꢀtransmittingꢀtheꢀ
ACKꢀpacket.
OnꢀtheꢀPRXꢀdeviceꢀtheꢀRX_ADDR_Pnꢀdefinedꢀasꢀtheꢀpipeꢀaddressꢀmustꢀbeꢀunique.ꢀOnꢀtheꢀPTXꢀ
deviceꢀtheꢀTX_ADDRꢀmustꢀbeꢀtheꢀsameꢀasꢀtheꢀRX_ADDR_P0ꢀonꢀtheꢀPTX,ꢀandꢀasꢀtheꢀpipeꢀaddressꢀ
forꢀtheꢀdesignatedꢀpipeꢀonꢀtheꢀPRX.ꢀNoꢀotherꢀdataꢀpipeꢀcanꢀreceiveꢀdataꢀuntilꢀaꢀcompleteꢀpacketꢀisꢀ
receivedꢀbyꢀaꢀdataꢀpipeꢀthatꢀhasꢀdetectedꢀitsꢀaddress.ꢀWhenꢀmultipleꢀPTXꢀdevicesꢀareꢀtransmittingꢀ
toꢀaꢀPRX,ꢀtheꢀARDꢀcanꢀbeꢀusedꢀtoꢀskewꢀtheꢀautoꢀretransmissionꢀsoꢀthatꢀtheyꢀonlyꢀblockꢀeachꢀotherꢀ
once.
Rev. 1.40
ꢁ00
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Packet Control
WhenꢀtheꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀisꢀenabled,ꢀtheꢀpacketꢀcontrolꢀfieldꢀcontainsꢀaꢀ6-bitꢀ
payloadꢀlengthꢀfield,ꢀaꢀ2-bitꢀPacketꢀIdentity,ꢀPID,ꢀfieldꢀandꢀaꢀ1-bitꢀNO_ACKꢀflag.
•ꢀ Payload Length
TheꢀpayloadꢀlengthꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀpayloadꢀlengthꢀandꢀonlyꢀusedꢀifꢀtheꢀDynamicꢀPayloadꢀ
Lengthꢀfunctionꢀisꢀenabled.
•ꢀ PID
Theꢀ2-bitꢀPIDꢀfieldꢀisꢀusedꢀtoꢀdetectꢀwhetherꢀtheꢀreceivedꢀpacketꢀisꢀnewꢀorꢀretransmitted.ꢀTheꢀPIDꢀ
preventsꢀtheꢀPRXꢀdeviceꢀfromꢀpresentingꢀtheꢀsameꢀpayloadꢀmoreꢀthanꢀonceꢀtoꢀtheꢀMCU.ꢀTheꢀPIDꢀ
fieldꢀisꢀincrementedꢀatꢀtheꢀTXꢀsideꢀforꢀeachꢀnewꢀpacketꢀreceivedꢀthroughꢀtheꢀSPIꢀinterface.ꢀTheꢀPIDꢀ
andꢀCRCꢀfieldsꢀareꢀusedꢀbyꢀtheꢀPRXꢀdeviceꢀtoꢀdetermineꢀwhetherꢀaꢀpacketꢀisꢀoldꢀorꢀnew.ꢀWhenꢀ
severalꢀdataꢀpacketsꢀareꢀlostꢀonꢀtheꢀlink,ꢀtheꢀPIDꢀfieldsꢀmayꢀbecomeꢀequalꢀtoꢀtheꢀlastꢀreceivedꢀPID.ꢀIfꢀ
aꢀpacketꢀhasꢀtheꢀsameꢀPIDꢀasꢀtheꢀpreviousꢀpacket,ꢀtheꢀtransceiverꢀcomparesꢀtheꢀCRCꢀsumsꢀfromꢀbothꢀ
packets.ꢀIfꢀtheꢀCRCꢀsumsꢀareꢀalsoꢀtheꢀsame,ꢀtheꢀlastꢀreceivedꢀpacketꢀwillꢀbeꢀconsideredꢀaꢀcopyꢀofꢀtheꢀ
previouslyꢀreceivedꢀpacketꢀandꢀbeꢀdiscarded.
•ꢀ NO_ACK
TheꢀNO_ACKꢀflagꢀisꢀusedꢀonlyꢀwhenꢀtheꢀautoꢀacknowledgementꢀfeatureꢀisꢀused.ꢀSettingꢀtheꢀflagꢀ
highꢀinformsꢀtheꢀreceiverꢀthatꢀtheꢀpacketꢀisꢀnotꢀtoꢀbeꢀautoꢀacknowledged.ꢀTheꢀPTXꢀdeviceꢀcanꢀsetꢀ
theꢀNO_ACKꢀflagꢀbitꢀinꢀtheꢀPacketꢀControlꢀFieldꢀwithꢀtheꢀcommand:ꢀW_TX_PAYLOAD_NOACK.ꢀ
However,ꢀtheꢀfunctionꢀmustꢀfirstꢀbeꢀenabledꢀinꢀtheꢀFEATUREꢀregisterꢀbyꢀsettingꢀtheꢀEN_DYN_ACKꢀ
bit.ꢀWhenꢀtheꢀautoꢀacknowledgementꢀfunctionꢀisꢀused,ꢀtheꢀPTXꢀwillꢀdirectlyꢀenterꢀtoꢀtheꢀStandby-Iꢀ
modeꢀafterꢀtheꢀpacketꢀisꢀtransmittedꢀandꢀtheꢀPRXꢀdeviceꢀdoesꢀnotꢀtransmitꢀanꢀACKꢀpacketꢀwhenꢀitꢀ
receivesꢀtheꢀPTXꢀtransmittedꢀpacket.
Payload
Theꢀpayloadꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀcontentsꢀofꢀtheꢀpacket.ꢀItꢀcanꢀbeꢀfromꢀ0ꢀtoꢀ32ꢀbytesꢀwideꢀ
andꢀtransmittedꢀon-airꢀasꢀitꢀisꢀuploadedꢀ(unmodified)ꢀtoꢀtheꢀdevice.ꢀTheꢀtransceiverꢀprovidesꢀtwoꢀ
alternativesꢀforꢀhandlingꢀpayloadꢀlengths,ꢀstaticꢀandꢀdynamicꢀpayloadꢀlength.ꢀTheꢀstaticꢀpayloadꢀ
lengthꢀofꢀtheꢀsixꢀdataꢀpipesꢀcanꢀbeꢀindividuallyꢀset.
Theꢀdefaultꢀalternativeꢀisꢀstaticꢀpayloadꢀlength.ꢀWithꢀstaticꢀpayloadꢀlengthꢀallꢀpacketsꢀbetweenꢀaꢀ
transmitterꢀandꢀaꢀreceiverꢀhaveꢀtheꢀsameꢀlength.ꢀTheꢀstaticꢀpayloadꢀlengthꢀisꢀsetꢀbyꢀtheꢀRX_PW_Pnꢀ
registers.ꢀTheꢀpayloadꢀlengthꢀonꢀtheꢀtransmitterꢀsideꢀisꢀsetꢀbyꢀtheꢀnumberꢀofꢀbytesꢀclockedꢀintoꢀtheꢀ
TX_FIFOꢀandꢀmustꢀequalꢀtoꢀtheꢀvalueꢀinꢀtheꢀRX_PW_Pnꢀregisterꢀonꢀtheꢀreceiverꢀside.ꢀEachꢀpipeꢀhasꢀ
itsꢀownꢀpayloadꢀlength.
TheꢀDynamicꢀPayloadꢀLength,ꢀDPL,ꢀisꢀanꢀalternativeꢀtoꢀtheꢀstaticꢀpayloadꢀlength.ꢀTheꢀDPLꢀenablesꢀ
theꢀtransmitterꢀtoꢀsendꢀpacketsꢀwithꢀvariableꢀpayloadꢀlengthsꢀtoꢀtheꢀreceiver.ꢀThisꢀmeansꢀthatꢀforꢀaꢀ
systemꢀwithꢀdifferentꢀpayloadꢀlengthsꢀitꢀisꢀnotꢀnecessaryꢀtoꢀscaleꢀtheꢀpacketꢀlengthꢀtoꢀtheꢀlongestꢀ
payload.
WithꢀtheꢀDPLꢀfeatureꢀtheꢀtransceiverꢀcanꢀdecodeꢀtheꢀpayloadꢀlengthꢀofꢀtheꢀreceivedꢀpacketꢀ
automaticallyꢀinsteadꢀofꢀusingꢀtheꢀRX_PW_Pnꢀregisters.ꢀTheꢀMCUꢀcanꢀreadꢀtheꢀlengthꢀofꢀtheꢀ
receivedꢀpayloadꢀusingꢀtheꢀcommand:ꢀR_RX_PL_WID.ꢀInꢀorderꢀtoꢀenableꢀtheꢀDPLꢀfunction,ꢀtheꢀ
EN_DPLꢀbitꢀinꢀtheꢀFEATUREꢀregisterꢀmustꢀbeꢀset.ꢀInꢀtheꢀRXꢀmodeꢀtheꢀDYNPDꢀregisterꢀhasꢀtoꢀbeꢀ
properlyꢀconfigured.ꢀAꢀPTXꢀdeviceꢀmustꢀsetꢀtheꢀDPL_P0ꢀbitꢀinꢀtheꢀDYNPDꢀregisterꢀtoꢀtransmitꢀtoꢀaꢀ
PRXꢀwithꢀtheꢀDPLꢀfunctionꢀbeingꢀenabled.
Rev. 1.40
ꢁ01
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
CRC
TheꢀCRCꢀisꢀtheꢀerrorꢀdetectionꢀmechanismꢀinꢀtheꢀpacket.ꢀTheꢀnumberꢀofꢀbytesꢀinꢀtheꢀCRCꢀisꢀsetꢀ
byꢀtheꢀCRCOꢀbitꢀinꢀtheꢀCONFIGꢀregister.ꢀItꢀmayꢀbeꢀeitherꢀ1ꢀorꢀ2ꢀbytesꢀandꢀisꢀcalculatedꢀoverꢀtheꢀ
address,ꢀPacketꢀControlꢀFieldꢀandꢀPayload.ꢀTheꢀpolynomialꢀforꢀa1-byteꢀCRCꢀisꢀX8ꢀ+ꢀX2ꢀ+ꢀXꢀ+ꢀ1ꢀwithꢀ
anꢀinitialꢀvalueꢀofꢀ0xFFH.ꢀTheꢀpolynomialꢀforꢀaꢀ2-byteꢀCRCꢀisꢀX16ꢀ+ꢀX12ꢀ+ꢀX5ꢀ+ꢀ1ꢀwithꢀanꢀinitialꢀ
valueꢀofꢀ0xFFFFH.ꢀNoꢀpacketꢀisꢀacceptedꢀbyꢀtheꢀreceiverꢀsideꢀifꢀtheꢀCRCꢀfails.
Packet Handling
Theꢀtransceiverꢀcircuitryꢀusesꢀburstꢀmodeꢀforꢀpayloadꢀtransmissionꢀandꢀreception.
TheꢀtransmitterꢀfetchesꢀtheꢀpayloadꢀfromꢀtheꢀTXꢀFIFO,ꢀautomaticallyꢀassemblesꢀitꢀintoꢀaꢀpacketꢀ
andꢀtransmitsꢀtheꢀpacketꢀinꢀaꢀveryꢀshortꢀburstꢀperiodꢀwithꢀaꢀ1Mbpsꢀorꢀ2Mbpsꢀairꢀdataꢀrate.ꢀAfterꢀaꢀ
transmission,ꢀifꢀtheꢀPTXꢀpacketꢀhasꢀtheꢀNO_ACKꢀflagꢀset,ꢀtheꢀtransceiverꢀsetsꢀtheꢀTX_DSꢀbitꢀandꢀ
givesꢀanꢀactiveꢀlowꢀinterruptꢀpulseꢀonꢀtheꢀIRQꢀlineꢀsentꢀtoꢀtheꢀMCU.ꢀIfꢀtheꢀPTXꢀisꢀanꢀACKꢀpacket,ꢀ
theꢀPTXꢀneedsꢀtoꢀreceiveꢀanꢀACKꢀfromꢀtheꢀPRXꢀandꢀthenꢀassertꢀtheꢀTX_DSꢀIRQ.
Theꢀreceiverꢀautomaticallyꢀvalidatesꢀandꢀdisassemblesꢀtheꢀreceivedꢀpacket.ꢀIfꢀthereꢀisꢀaꢀvalidꢀpacketꢀ
withinꢀtheꢀnewꢀpayload,ꢀitꢀwillꢀwriteꢀtheꢀpayloadꢀintoꢀtheꢀRXꢀFIFO,ꢀsetꢀtheꢀRX_DRꢀbitꢀandꢀgiveꢀanꢀ
activeꢀlowꢀinterruptꢀpulseꢀonꢀtheꢀIRQꢀlineꢀsentꢀtoꢀtheꢀMCU.
WhenꢀtheꢀautoꢀacknowledgeꢀfunctionꢀisꢀenabledꢀbyꢀsettingꢀtheꢀEN_AAꢀbitꢀtoꢀ1,ꢀtheꢀPTXꢀdeviceꢀwillꢀ
automaticallyꢀwaitꢀforꢀanꢀacknowledgeꢀpacketꢀafterꢀtransmissionꢀandꢀre-transmitꢀtheꢀoriginalꢀpacketꢀ
afterꢀtheꢀARDꢀdelayꢀuntilꢀanꢀacknowledgeꢀpacketꢀisꢀreceivedꢀorꢀtheꢀnumberꢀofꢀre-transmissionꢀ
exceedsꢀaꢀthresholdꢀdefinedꢀbyꢀtheꢀARCꢀfield.ꢀIfꢀtheꢀnumberꢀofꢀre-transmissionsꢀexceedsꢀaꢀthresholdꢀ
definedꢀbyꢀtheꢀARCꢀfield,ꢀtheꢀtransceiverꢀwillꢀsetꢀtheꢀMAX_RTꢀbitꢀandꢀgiveꢀanꢀactiveꢀlowꢀinterruptꢀ
pulseꢀonꢀtheꢀIRQꢀlineꢀsentꢀtoꢀtheꢀMCU.ꢀTwoꢀpacketꢀlossꢀcounters,ꢀARC_CNTꢀandꢀPLOS_CNT,ꢀ
areꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀaꢀpacketꢀisꢀlost.ꢀTheꢀARC_CNTꢀcounterꢀcountsꢀtheꢀnumberꢀofꢀ
retransmissionsꢀforꢀtheꢀcurrentꢀtransaction.ꢀTheꢀPLOS_CNTꢀcounterꢀcountsꢀtheꢀtotalꢀnumberꢀofꢀ
retransmissionsꢀsinceꢀtheꢀlastꢀchannelꢀchange.ꢀTheꢀARC_CNTꢀcounterꢀisꢀresetꢀbyꢀinitiatingꢀaꢀnewꢀ
transactionꢀwhileꢀtheꢀPLOS_CNTꢀcounterꢀisꢀresetꢀbyꢀwritingꢀaꢀvalueꢀtoꢀtheꢀRF_CHꢀregisterꢀtoꢀ
changeꢀaꢀRFꢀchannel.ꢀItꢀisꢀpossibleꢀtoꢀuseꢀtheꢀinformationꢀinꢀtheꢀOBSERVE_TXꢀregisterꢀtoꢀmakeꢀanꢀ
overallꢀassessmentꢀofꢀtheꢀchannelꢀquality.
TheꢀPTXꢀdeviceꢀwillꢀretransmitꢀifꢀitsꢀRXꢀFIFOꢀisꢀfullꢀbutꢀtheꢀreceivedꢀACKꢀframeꢀhasꢀaꢀpayload.ꢀ
AsꢀanꢀalternativeꢀforꢀtheꢀPTXꢀdeviceꢀtoꢀautoꢀretransmitꢀitꢀisꢀpossibleꢀtoꢀmanuallyꢀsetꢀtheꢀtransceiverꢀ
toꢀretransmitꢀaꢀpacketꢀaꢀnumberꢀofꢀtimes.ꢀThisꢀisꢀdoneꢀusingꢀtheꢀREUSE_TX_PLꢀcommand.ꢀWhenꢀ
theꢀautoꢀacknowledgeꢀfunctionꢀisꢀenabled,ꢀtheꢀPRXꢀdeviceꢀwillꢀautomaticallyꢀcheckꢀtheꢀNO_ACKꢀ
fieldꢀinꢀtheꢀreceivedꢀpacket,ꢀandꢀifꢀtheꢀNO_ACKꢀbitꢀisꢀ0,ꢀitꢀwillꢀautomaticallyꢀsendꢀanꢀacknowledgeꢀ
packetꢀtoꢀtheꢀPTXꢀdevice.ꢀIfꢀtheꢀEN_ACK_PAYꢀbitꢀisꢀset,ꢀtheꢀacknowledgeꢀpacketꢀcanꢀalsoꢀbeꢀ
regardedꢀasꢀaꢀpendingꢀpayloadꢀinꢀtheꢀTXꢀFIFO.
Rev. 1.40
ꢁ0ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Data and Control Interface
TX/RX FIFO
TheꢀdataꢀFIFOsꢀareꢀusedꢀtoꢀstoreꢀtheꢀpayloadꢀthatꢀisꢀtoꢀbeꢀtransmittedꢀinꢀtheꢀTXꢀFIFOꢀorꢀisꢀreceivedꢀ
inꢀtheꢀRXꢀFIFOꢀandꢀreadyꢀtoꢀbeꢀclockedꢀout.ꢀTheꢀFIFOꢀisꢀaccessibleꢀinꢀbothꢀtheꢀPTXꢀmodeꢀandꢀ
PRXꢀmodes.ꢀThereꢀisꢀaꢀthreeꢀlevelꢀ32ꢀbyteꢀFIFOꢀforꢀbothꢀtheꢀTXꢀandꢀRX,ꢀsupportingꢀbothꢀtheꢀ
acknowledgeꢀmodeꢀorꢀnoꢀacknowledgeꢀmodeꢀwithꢀupꢀtoꢀsixꢀdataꢀpipes.
•ꢀ TXꢀthreeꢀlevels,ꢀ32ꢀbytesꢀFIFO
•ꢀ RXꢀthreeꢀlevels,ꢀ32ꢀbytesꢀFIFO
BothꢀtheꢀTXꢀandꢀRXꢀFIFOsꢀhaveꢀaꢀcontrollerꢀandꢀareꢀaccessibleꢀthroughꢀtheꢀSPIꢀinterfaceꢀusingꢀ
dedicatedꢀSPIꢀcommands.ꢀAꢀTXꢀFIFOꢀinꢀPRXꢀcanꢀstoreꢀtheꢀpayloadꢀforꢀACKꢀpacketsꢀforꢀthreeꢀ
differentꢀPTXꢀdevices.ꢀIfꢀtheꢀTXꢀFIFOꢀcontainsꢀmoreꢀthanꢀoneꢀpayloadꢀforꢀaꢀpipe,ꢀtheꢀdifferentꢀ
payloadsꢀareꢀhandledꢀusingꢀtheꢀfirst-inꢀfirst-outꢀprinciple.ꢀTheꢀTXꢀFIFOꢀinꢀaꢀPRXꢀdeviceꢀisꢀblockedꢀ
ifꢀallꢀpendingꢀpayloadsꢀareꢀaddressedꢀtoꢀpipesꢀwhereꢀtheꢀlinkꢀtoꢀtheꢀPTXꢀdeviceꢀisꢀlost.ꢀInꢀthisꢀcase,ꢀ
theꢀMCUꢀcanꢀflushꢀtheꢀTXꢀFIFOꢀusingꢀtheꢀFLUSH_TXꢀcommand.
TheꢀRXꢀFIFOꢀinꢀtheꢀPRXꢀdeviceꢀmayꢀcontainꢀaꢀpayloadꢀfromꢀupꢀtoꢀthreeꢀdifferentꢀPTXꢀdevices.ꢀAꢀ
TXꢀFIFOꢀinꢀtheꢀPTXꢀdevicesꢀcanꢀhaveꢀupꢀtoꢀthreeꢀpayloadsꢀstored.ꢀTheꢀTXꢀFIFOꢀcanꢀbeꢀwrittenꢀtoꢀ
byꢀthreeꢀcommands,ꢀW_TX_PAYLOADꢀandꢀW_TX_PAYLOAD_NO_ACKꢀinꢀtheꢀPTXꢀmodeꢀandꢀ
W_ACK_PAYLOADꢀinꢀtheꢀPRXꢀmode.ꢀAllꢀthreeꢀcommandsꢀgiveꢀaccessꢀtoꢀtheꢀTX_PLDꢀregister.ꢀ
TheꢀRXꢀFIFOꢀcanꢀbeꢀreadꢀbyꢀtheꢀcommandꢀR_RX_PAYLOADꢀinꢀbothꢀPTXꢀandꢀPRXꢀmodes.ꢀThisꢀ
commandꢀgivesꢀaccessꢀtoꢀtheꢀRX_PLDꢀregister.ꢀTheꢀpayloadꢀinꢀtheꢀTXꢀFIFOꢀinꢀaꢀPTXꢀdeviceꢀisꢀ
NOTꢀremovedꢀifꢀtheꢀMAX_RTꢀIRQꢀisꢀasserted.
InꢀtheꢀFIFO_STATUSꢀregisterꢀitꢀisꢀpossibleꢀtoꢀknowꢀwhetherꢀtheꢀTXꢀandꢀRXꢀFIFOꢀareꢀfullꢀorꢀempty.ꢀ
TheꢀTX_REUSEꢀbitꢀisꢀalsoꢀavailableꢀinꢀtheꢀFIFO_STATUSꢀregister.ꢀTheꢀTX_REUSEꢀbitꢀisꢀsetꢀ
byꢀtheꢀSPIꢀcommand,ꢀREUSE_TX_PL,ꢀandꢀisꢀresetꢀbyꢀtheꢀSPIꢀcommand,ꢀW_TX_PAYLOADꢀorꢀ
FLUSHꢀTX.
Interrupt
InꢀtheꢀRFꢀtransceiverꢀcircuitryꢀthereꢀisꢀanꢀactiveꢀlowꢀinterruptꢀline,ꢀIRQ,ꢀwhichꢀisꢀactivatedꢀwhenꢀtheꢀ
TX_DSꢀIRQ,ꢀRX_DRꢀIRQꢀorꢀMAX_RTꢀIRQꢀbitꢀisꢀsetꢀtoꢀhighꢀbyꢀtheꢀstateꢀmachineꢀinꢀtheꢀSTATUSꢀ
register.ꢀTheꢀIRQꢀlineꢀisꢀinternallyꢀconnectedꢀtoꢀtheꢀMCUꢀexternalꢀinterruptꢀinput.ꢀTheꢀdetailedꢀ
MCUꢀexternalꢀinterruptꢀconfigurationsꢀareꢀdescribedꢀinꢀtheꢀprecedingꢀsectionꢀinꢀthisꢀdatasheet.ꢀ
TheꢀIRQꢀlineꢀisꢀresetꢀwhenꢀtheꢀMCUꢀwritesꢀaꢀ‘1’ꢀintoꢀtheꢀIRQꢀsourceꢀbitꢀinꢀtheꢀSTATUSꢀregister.ꢀ
TheꢀIRQꢀmaskꢀcontrolꢀbitꢀinꢀtheꢀCONFIGꢀregisterꢀisꢀusedꢀtoꢀselectꢀwhichꢀIRQꢀsourceꢀisꢀallowedꢀtoꢀ
assertꢀtheꢀIRQꢀline.ꢀByꢀsettingꢀoneꢀofꢀtheꢀMASKꢀbitsꢀhigh,ꢀtheꢀcorrespondingꢀIRQꢀsourceꢀwillꢀbeꢀ
disabled.ꢀByꢀdefaultꢀallꢀIRQꢀsourcesꢀareꢀenabled.ꢀTheꢀ3-bitꢀpipeꢀinformationꢀinꢀtheꢀSTATUSꢀregisterꢀ
isꢀupdatedꢀwhenꢀtheꢀIRQꢀlineꢀchangesꢀstateꢀfromꢀhighꢀtoꢀlow.ꢀIfꢀtheꢀSTATUSꢀregisterꢀisꢀreadꢀduringꢀ
aꢀhighꢀtoꢀlowꢀtransitionꢀofꢀanꢀIRQꢀline,ꢀtheꢀpipeꢀinformationꢀisꢀnotꢀavailable.
Rev. 1.40
ꢁ03
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SPI Interface
TheꢀSPIꢀcommandsꢀareꢀshownꢀinꢀtheꢀfollowingꢀtable.ꢀEveryꢀnewꢀcommandꢀmustꢀbeꢀstartedꢀbyꢀaꢀhighꢀ
toꢀlowꢀtransitionꢀonꢀtheꢀCSNꢀline.ꢀInꢀparallelꢀtoꢀtheꢀSPIꢀcommandꢀbyteꢀappliedꢀonꢀtheꢀMOSIꢀline,ꢀtheꢀ
STATUSꢀregisterꢀbit,ꢀSn,ꢀisꢀseriallyꢀshiftedꢀoutꢀonꢀtheꢀMISOꢀline.ꢀTheꢀRFꢀTransceiverꢀSPIꢀinterfaceꢀ
isꢀinternallyꢀconnectedꢀtoꢀtheꢀMCUꢀSPIAꢀinterface.ꢀTheꢀdetailedꢀMCUꢀSPIAꢀinterfaceꢀoperationsꢀareꢀ
describedꢀinꢀtheꢀcorrespondingꢀSPIAꢀinterfaceꢀsectionꢀinꢀthisꢀdatasheet.
TheꢀserialꢀshiftingꢀSPIꢀcommandsꢀareꢀinꢀtheꢀfollowingꢀformat:
•ꢀ Commandꢀbyte:ꢀoneꢀbyteꢀcommandꢀwordꢀfromꢀMSBꢀtoꢀLSB
•ꢀ Dataꢀreadꢀoperation:ꢀTheꢀdataꢀbyteꢀisꢀshiftedꢀoutꢀfromꢀtheꢀleastꢀsignificantꢀbyteꢀtoꢀtheꢀmostꢀ
significantꢀbyteꢀandꢀMSBꢀfirstꢀinꢀeachꢀbyteꢀforꢀallꢀregistersꢀinꢀallꢀregisterꢀbanks.
•ꢀ Dataꢀwriteꢀoperation:ꢀTheꢀdataꢀbyteꢀisꢀshiftedꢀinꢀfromꢀtheꢀmostꢀsignificantꢀbyteꢀtoꢀtheꢀleastꢀ
significantꢀbyteꢀandꢀMSBꢀinꢀeachꢀbyteꢀfirstꢀforꢀregisterꢀ0ꢀtoꢀregisterꢀ8ꢀinꢀregisterꢀbankꢀ1.ꢀForꢀ
otherꢀregistersꢀinꢀallꢀbanksꢀtheꢀdataꢀbyteꢀisꢀshiftedꢀinꢀfromꢀtheꢀleastꢀsignificantꢀbyteꢀtoꢀtheꢀmostꢀ
significantꢀbyte.
Command Data bytes
Command name
Operation
byte (Cn)
(Dn)
Read command and status registers
AAAAA=5-bit Register �ap Address
R_REGISTER
W_REGISTER
000AAAAA
1 to 5
Write command and status registers
AAAAA=5-bit Register �ap Address
Executable in power down or standbꢀ modes onlꢀ
001AAAAA
0110 0001
1 to 5
Read RX-paꢀload: 1~3ꢁ bꢀtesꢂ used in the RX mode
A read operation alwaꢀs starts at bꢀte 0
LSB byte first The RX Paꢀload is implemented in register bank 0 and is deleted
1 to 3ꢁ
R_RX_PAYLOAD
from the FIFO after it is read.
Write TX-paꢀload: 1~3ꢁ bꢀtes
1 to 3ꢁ
A write operation alwaꢀs starts at bꢀte 0
W_TX_PAYLOAD 1010 0000
LSB byte first The TX Paꢀload is implemented in register bank 0 and is used in
the TX mode
FLUSH_TX
FLUSH_RX
1110 0001
1110 0010
0
0
Flush TX FIFOꢂ used in TX mode
Flush RX FIFOꢂ used in RX mode.
Should not be executed during transmission of acknowledgeꢂ that
isꢂ an acknowledge package will not be completed.
Used for a PTX device
Reuse last transmitted paꢀload
Packets are repeatedlꢀ retransmitted as long as CE is high.
The TX paꢀload reuse is active until W_TX_PAYLOAD or FLUSH
TX is executed.
REUSE_TX_PL
1110 0011
0
The TX paꢀload reuse must not be activated or deactivated during
package transmission.
Rev. 1.40
ꢁ04
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Command Data bytes
Command name
Operation
byte (Cn)
(Dn)
This write command followed bꢀ data 0xꢃ3 activates the following
features:
• R_RX_PL_WID
• W_ACK_PAYLOAD
• W_TX_PAYLOAD_NOACK
A new ACTIVATE command with the same data deactivates them
again. This is executable in power down or standbꢀ modes onlꢀ.
The features registers named as R_RX_PL_WIDꢂ W_ACK_
PAYLOADꢂ and W_TX_PAYLOAD_NOACK are initiallꢀ in a
deactivated state; a write operation has no effectꢂ a read operation
onlꢀ results in zeros on �ISO. To activate these registersꢂ use the
ACTIVATE command followed bꢀ data 0xꢃ3. Then theꢀ can be
accessed just like anꢀ other registers. Using the same command
and data will deactivate the registers again.
ACTIVATE
0101 0000
1
This write command followed bꢀ data 0x53 toggles the register
bank and the current register bank number can be read out from
the STATUS register bit ꢃ.
Read RX-paꢀload width for the top
R_RX_PAYLOAD in the RX FIFO
R_RX_PL_WID
0110 0000
1010 1PPP
Write ACK Paꢀload: 1~3ꢁ bꢀtesꢂ used in the RX mode
Write Paꢀload to be transmitted together with ACK packet on PIPE
“PPP” where the “PPP” ranges from 000 to 101. �aximum three
ACK packet paꢀloads can be pending. Paꢀloads with the same
PPP are handled using first-in- first-out principle. A write operation
to the ACK paꢀload implemented in the register bank 0 alwaꢀs
starts at bꢀte 0.
W_ACK_
PAYLOAD
1 to 3ꢁ
LSB byte first
W_TX_PAYLOAD_
NOACK
1 to 3ꢁ
Used in TX mode and implemented in the register bank 0
1011 0000
1111 1111
LSB byte first Disables AUTOACK on this specific packet.
NOP
0
No Operation. �ight be used to read the STATUS register.
Rev. 1.40
ꢁ05
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
CSN
……
……
……
……
SCK
C7 C6 C5 C4 C3 C2 C1 C0
S7 S6 S5 S4 S3 S2 S1 S0
MOSI
MISO
D7
D6 ……… D0 D15 ……… D8 D23 ……… D16 D31 ………
Note:ꢀTheꢀdataꢀbyteꢀonꢀtheꢀMISOꢀlineꢀmayꢀbeꢀ1ꢀbyte,ꢀ4ꢀbytes,ꢀ11ꢀbytesꢀorꢀ32ꢀbytesꢀdependingꢀuponꢀwhichꢀregisterꢀ
isꢀaccessed.
SPI read operation – All registers in Bank 0 & Bank1
CSN
……
……
……
……
SCK
C7 C6 C5 C4 C3 C2 C1 C0
S7 S6 S5 S4 S3 S2 S1 S0
D7
D6 ……… D0 D15 ……… D8 D23 ……… D16 D31 ………
MOSI
MISO
Note:ꢀTheꢀdataꢀbyteꢀonꢀtheꢀMISOꢀlineꢀmayꢀbeꢀ1ꢀbyte,ꢀ4ꢀbytes,ꢀ11ꢀbytesꢀorꢀ32ꢀbytesꢀdependingꢀuponꢀwhichꢀregisterꢀ
isꢀaccessed.
SPI write operation – All registers in Bank 0 & Register 9~14 in Bank1
CSN
SCK
MOSI
MISO
C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8
S7 S6 S5 S4 S3 S2 S1 S0
D7
D6 D5 D4 D3 D2 D1 D0
SPI write operation – Register 0~8 in Bank1
Rev. 1.40
ꢁ06
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RF Transceiver Register Map
Thereꢀareꢀtwoꢀregisterꢀbanks,ꢀwhichꢀcanꢀbeꢀtoggledꢀbyꢀanꢀSPIꢀ“ACTIVATE”ꢀcommandꢀfollowedꢀ
withꢀ0x53ꢀdataꢀbyteꢀandꢀtheꢀbankꢀstatusꢀcanꢀbeꢀreadꢀfromꢀtheꢀSTATUSꢀregisterꢀbitꢀ7ꢀinꢀtheꢀRegisterꢀ
Bank0.
Register Bank 0
Itꢀisꢀrecommendedꢀthatꢀnoꢀaccessꢀisꢀexecutedꢀonꢀreservedꢀorꢀnonꢀdefinedꢀregisters.ꢀOtherwise,ꢀthisꢀ
mayꢀresultꢀinꢀunpredictableꢀconditions.
•ꢀ Address 00H – CONFIG Register
ThisꢀregisterꢀisꢀusedꢀtoꢀconfigureꢀtheꢀprimaryꢀsettingꢀofꢀtheꢀRFꢀTransceiver.
Bit
Name
R/W
7
—
6
5
4
3
2
1
0
�ASK_RX_DR �ASK_TX_DS �ASK_�AX_RT EN_CRC CRCO PWR_UP PRI�_RX
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6
Reservedꢀbit,ꢀonlyꢀdataꢀ“0”ꢀallowed.
MASK_RX_DR:ꢀRX_DRꢀMaskꢀinterruptꢀcontrol
0:ꢀRX_DRꢀinterruptꢀisꢀreflectedꢀasꢀanꢀactiveꢀlowꢀinterruptꢀpulseꢀonꢀtheꢀIRQꢀline
1:ꢀRX_DRꢀinterruptꢀisꢀnotꢀreflectedꢀonꢀtheꢀIRQꢀline
Bitꢀ5
Bitꢀ4
Bitꢀ3
MASK_TX_DS:ꢀTX_DSꢀMaskꢀinterruptꢀcontrol
0:ꢀTX_DSꢀinterruptꢀisꢀreflectedꢀasꢀanꢀactiveꢀlowꢀinterruptꢀpulseꢀonꢀtheꢀIRQꢀline
1:ꢀTX_DSꢀinterruptꢀisꢀnotꢀreflectedꢀonꢀtheꢀIRQꢀline
MASK_MAX_RT:ꢀMAX_RTꢀMaskꢀinterruptꢀcontrol
0:ꢀMAX_RTꢀinterruptꢀisꢀreflectedꢀasꢀanꢀactiveꢀlowꢀinterruptꢀpulseꢀonꢀtheꢀIRQꢀline
1:ꢀMAX_RTꢀinterruptꢀisꢀnotꢀreflectedꢀonꢀtheꢀIRQꢀline
EN_CRC:ꢀCRCꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀwillꢀbeꢀforcedꢀtoꢀhighꢀifꢀoneꢀofꢀtheꢀbitsꢀinꢀtheꢀEN_AAꢀregisterꢀisꢀhigh.
Bitꢀ2
Bitꢀ1
Bitꢀ0
CRCO:ꢀCRCꢀencodingꢀscheme
0:ꢀ1ꢀbyte
1:ꢀ2ꢀbytes
PWR_UP:ꢀRFꢀTransceiverꢀpowerꢀcontrol
0:ꢀPowerꢀdown
1:ꢀPowerꢀup
PRIM_RX:ꢀRX/TXꢀmodeꢀselection
0:ꢀPrimaryꢀTransmitꢀ–ꢀPTX
1:ꢀPrimaryꢀReceiveꢀ–ꢀPRX
Rev. 1.40
ꢁ0ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 01H – EN_AA Register
Thisꢀregisterꢀisꢀusedꢀtoꢀenableꢀtheꢀ“AutoꢀAcknowledgement”ꢀfunctionꢀofꢀtheꢀindividualꢀdataꢀpipe.
Bit
Name
R/W
7
—
6
—
5
4
3
2
1
0
ENAA_P5 ENAA_P4 ENAA_P3 ENAA_Pꢁ ENAA_P1 ENAA_P0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
ENAA_P5:ꢀDataꢀPipeꢀ5ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
ENAA_P4:ꢀDataꢀPipeꢀ4ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ENAA_P3:ꢀDataꢀPipeꢀ3ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ENAA_P2:ꢀDataꢀPipeꢀ2ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ENAA_P1:ꢀDataꢀPipeꢀ1ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ENAA_P0:ꢀDataꢀPipeꢀ0ꢀAutoꢀAcknowledgementꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.40
ꢁ08
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 02H – EN_RXADDR Register
ThisꢀregisterꢀisꢀusedꢀtoꢀenableꢀtheꢀRXꢀdataꢀpipeꢀaddress.
Bit
Name
R/W
7
—
6
—
5
ERX_P5
R/W
0
4
ERX_P4
R/W
0
3
ERX_P3
R/W
0
2
ERX_Pꢁ
R/W
0
1
ERX_P1
R/W
1
0
ERX_P0
R/W
1
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
ERX_P5:ꢀDataꢀPipeꢀ5ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
ERX_P4:ꢀDataꢀPipeꢀ4ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ERX_P3:ꢀDataꢀPipeꢀ3ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ERX_P2:ꢀDataꢀPipeꢀ2ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ERX_P1:ꢀDataꢀPipeꢀ1ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
ERX_P0:ꢀDataꢀPipeꢀ0ꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
•ꢀ Address 03H – SETUP_AW Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀaddressꢀfieldꢀwidth.
Bit
Name
R/W
7
—
6
—
5
—
4
—
3
—
2
—
1
0
AW1
R/W
1
AW0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“000000”ꢀallowed.
AW1~AW0:ꢀDataꢀpipeꢀAddressꢀFieldꢀWidth
00:ꢀIllegal,ꢀcanꢀnotꢀbeꢀused.
01:ꢀ3ꢀbytes
10:ꢀ4ꢀbytes
11:ꢀ5ꢀbytes
Theꢀfieldꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀaddressꢀfieldꢀwidthꢀwhichꢀisꢀtheꢀsameꢀforꢀallꢀ
dataꢀpipes.
Rev. 1.40
ꢁ09
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 04H – SETUP_RETR Register
Thisꢀregisterꢀisꢀusedꢀtoꢀsetꢀtheꢀnumberꢀandꢀdelayꢀofꢀtheꢀautomaticꢀretransmission.
Bit
Name
R/W
7
ARD3
R/W
0
6
ARDꢁ
R/W
0
5
ARD1
R/W
0
4
ARD0
R/W
0
3
ARC3
R/W
0
2
ARCꢁ
R/W
0
1
ARC1
R/W
1
0
ARC0
R/W
1
POR
Bitꢀ7~4
ARD3~ARD0:ꢀAutomaticꢀRetransmissionꢀDelayꢀselection
0000:ꢀ(1×250)ꢀμs
0001:ꢀ(2×250)ꢀμs
0010:ꢀ(3×250)ꢀμs
:
1110:ꢀ(15×250)ꢀμs
1111:ꢀ(16×250)ꢀμs
TheꢀAutomaticꢀRetransmissionꢀDelayꢀisꢀdefinedꢀasꢀtheꢀtimeꢀfromꢀtheꢀendꢀofꢀtheꢀcurrentꢀ
transmissionꢀtoꢀtheꢀstartꢀofꢀtheꢀnextꢀtransmission.
Bitꢀ3~0
ARC3~ARC0:ꢀAutomaticꢀRetransmissionꢀNumber
0000:ꢀNoꢀretransmissionꢀwhenꢀautomaticꢀacknowledgementꢀfailed.
0001:ꢀ1ꢀretransmissionꢀwhenꢀautomaticꢀacknowledgementꢀfailed.
0010:ꢀ2ꢀretransmissionsꢀwhenꢀautomaticꢀacknowledgementꢀfailed.
:
1110:ꢀ14ꢀretransmissionsꢀwhenꢀautomaticꢀacknowledgementꢀfailed.
1111:ꢀ15ꢀretransmissionsꢀwhenꢀautomaticꢀacknowledgementꢀfailed.
•ꢀ Address 05H – RF_CH Register
ThisꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀRFꢀchannel.
Bit
Name
R/W
7
—
6
5
4
3
2
1
0
RF_CH6 RF_CH5 RF_CH4 RF_CH3 RF_CHꢁ RF_CH1 RF_CH0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“0”ꢀallowed.
RF_CH6~RF_CH0:ꢀRFꢀChannelꢀselection
0000000~1111111:ꢀRFꢀchannelꢀ0~RFꢀchannelꢀ127
Rev. 1.40
ꢁ10
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 06H – RF_SETUP Register
ThisꢀregisterꢀisꢀusedꢀtoꢀconfigureꢀtheꢀRFꢀchannel.
Bit
Name
R/W
7
—
6
—
5
4
3
2
1
0
RF_DR_LOW PLL_LOCK RF_DR_HIGH RF_PWR1 RF_PWR0 LNA_HCURR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RF_DR_LOW:ꢀAirꢀDataꢀRateꢀselectꢀbit
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀairꢀdataꢀrateꢀtogetherꢀwithꢀtheꢀRF_DR_HIGHꢀbit.ꢀReferꢀtoꢀ
RF_DR_HIGHꢀbitꢀdefinitionꢀforꢀmoreꢀdetails.
Bitꢀ4
Bitꢀ3
PLL_LOCK:ꢀPLLꢀSignalꢀLockꢀcontrol
0:ꢀNoꢀeffect
1:ꢀPLLꢀsignalꢀisꢀlocked
ThisꢀbitꢀisꢀusedꢀtoꢀlockꢀtheꢀPLLꢀsignalꢀandꢀonlyꢀavailableꢀinꢀtheꢀtestꢀmode.
RF_DR_HIGH:ꢀAirꢀDataꢀRateꢀselectꢀbit
[RF_DR_LOW,ꢀRF_DR_HIGH]=AirꢀDataꢀRate
00:ꢀ1Mbps
01:ꢀ2Mbps
10:ꢀ250Kbps
11:ꢀ2Mbps
Bitꢀ2~1
RF_PWR1~RF_PWR0:ꢀRFꢀTXꢀOutputꢀPowerꢀselection
00:ꢀ-26dBm
01:ꢀ-14dBm
10:ꢀ-6dBm
11:ꢀ-1dBm
RF_PWR [1:0]
Optimisation
00
01
10
11
Register 4 [ꢁꢃ:ꢁ5]
000
001
010
011
100
101
-40
-30
-ꢁ6
-ꢁꢁ
-ꢁ0
-1ꢃ
-ꢁ4
-1ꢃ
-14
-10
-ꢃ
-16
-9
-6
-3
-ꢁ
0
-9
-3
-1
1
ꢁ
-5
3
Note:ꢀTheꢀOptimisationꢀRegisterꢀ4ꢀisꢀlocatedꢀatꢀaddressꢀ04HꢀinꢀtheꢀRFꢀBankꢀ1.
Bitꢀ0
LNA_HCURR:ꢀLNAꢀGainꢀselection
0:ꢀLowꢀgain
1:ꢀHighꢀgain
Rev. 1.40
ꢁ11
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 07H – STATUS Register
ThisꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀstatusꢀduringꢀtheꢀRFꢀdataꢀtransfer.ꢀWhenꢀtheꢀSPIꢀcommandꢀisꢀ
committedꢀtoꢀtheꢀRFꢀTransceiverꢀonꢀtheꢀMOSIꢀline,ꢀtheꢀcontentꢀofꢀtheꢀSTATUSꢀregisterꢀwillꢀbeꢀ
seriallyꢀshiftedꢀoutꢀfromꢀtheꢀRFꢀTransceiverꢀonꢀtheꢀMISOꢀline.
Bit
7
6
5
4
3
2
1
0
Name RBANK RX_DR TX_DS �AX_RT RX_P_NOꢁ RX_P_NO1 RX_P_NO0 TX_FULL
R/W
R
0
R/W
0
R/W
0
R/W
0
R
1
R
1
R
1
R
0
POR
Bitꢀ7
RBANK:ꢀRegisterꢀBankꢀStatus
0:ꢀRegisterꢀbankꢀ0
1:ꢀRegisterꢀbankꢀ1
Bitꢀ6
Bitꢀ5
RX_DR:ꢀRXꢀFIFOꢀDataꢀReceivedꢀStatus
0:ꢀNoꢀdataꢀisꢀreceivedꢀinꢀRXꢀFIFO
1:ꢀNewꢀdataꢀhasꢀbeenꢀreceivedꢀinꢀRXꢀFIFO
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀhardwareꢀandꢀclearedꢀtoꢀ0ꢀbyꢀwritingꢀaꢀ“1”ꢀintoꢀit.ꢀWhenꢀaꢀnewꢀ
dataꢀpacketꢀisꢀreceivedꢀinꢀtheꢀRXꢀFIFO,ꢀthisꢀbitꢀwillꢀbeꢀasserted.
TX_DS:ꢀTXꢀFIFOꢀDataꢀSentꢀStatus
0:ꢀNoꢀdataꢀisꢀtransmittedꢀfromꢀTXꢀFIFO
1:ꢀNewꢀdataꢀhasꢀbeenꢀtransmittedꢀfromꢀTXꢀFIFO
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀhardwareꢀandꢀclearedꢀtoꢀ0ꢀbyꢀwritingꢀaꢀ“1”ꢀintoꢀit.ꢀWhenꢀaꢀnewꢀ
dataꢀpacketꢀisꢀtransmittedꢀfromꢀtheꢀTXꢀFIFO,ꢀthisꢀbitꢀwillꢀbeꢀasserted.ꢀIfꢀtheꢀAUTO_
ACKꢀfunctionꢀisꢀenabled,ꢀthisꢀbitꢀwillꢀbeꢀsetꢀtoꢀ1ꢀafterꢀtheꢀACKꢀisꢀreceived.
Bitꢀ4
MAX_RT:ꢀMaximumꢀTXꢀretransmissionꢀStatus
0:ꢀTXꢀre-transmissionꢀnumberꢀdoesꢀnotꢀreachꢀtoꢀtheꢀmaximumꢀretransmissionꢀ
number.
1:ꢀTXꢀre-transmissionꢀnumberꢀhasꢀreachedꢀtoꢀtheꢀmaximumꢀretransmissionꢀnumber.
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀhardwareꢀandꢀclearedꢀtoꢀ0ꢀbyꢀwritingꢀaꢀ“1”ꢀintoꢀit.ꢀWhenꢀtheꢀTXꢀ
re-transmissionꢀnumberꢀhasꢀreachedꢀtoꢀtheꢀmaximumꢀretransmissionꢀnumber,ꢀthisꢀbitꢀ
willꢀbeꢀasserted.ꢀIfꢀtheꢀMAX_RTꢀbitꢀisꢀsetꢀtoꢀ1,ꢀitꢀmustꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀapplicationꢀ
programꢀtoꢀenableꢀfurtherꢀdataꢀcommunication.
Bitꢀ3~1
Bitꢀ0
RX_P_NO2~RX_P_NO0:ꢀDataꢀpipeꢀnumberꢀinꢀRXꢀFIFO
000~101:ꢀDataꢀpipeꢀ0~Dataꢀpipeꢀ5.
110:ꢀNotꢀused
111:ꢀRXꢀFIFOꢀempty
ThisꢀfieldꢀisꢀusedꢀtoꢀindicateꢀtheꢀdataꢀpipeꢀnumberꢀforꢀtheꢀavailableꢀpayloadꢀinꢀtheꢀRXꢀ
FIFO.ꢀWhenꢀthisꢀfieldꢀisꢀ“111”,ꢀitꢀmeansꢀthatꢀtheꢀRXꢀFIFOꢀisꢀempty.
TX_FULL:ꢀTXꢀFIFOꢀfullꢀflag
0:ꢀTXꢀFIFOꢀisꢀnotꢀfull
1:ꢀTXꢀFIFOꢀisꢀfull
Thisꢀbitꢀisꢀsetꢀandꢀclearedꢀbyꢀhardware.ꢀWhenꢀtheꢀTXꢀFIFOꢀisꢀfull,ꢀthisꢀbitꢀwillꢀbeꢀ
asserted.ꢀIfꢀthisꢀbitꢀisꢀ0,ꢀitꢀmeansꢀthatꢀtheꢀTXꢀFIFOꢀisꢀnotꢀfullꢀyetꢀandꢀstillꢀhasꢀavailableꢀ
locationsꢀtoꢀbeꢀused.
Rev. 1.40
ꢁ1ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 08H – OBSERVE_TX Register
Thisꢀregisterꢀincludesꢀtwoꢀread-onlyꢀcountersꢀandꢀisꢀusedꢀtoꢀindicateꢀtheꢀstatusꢀduringꢀtheꢀTXꢀdataꢀ
transmission.
Bit
7
6
5
4
3
2
1
0
Name PLOS_CNT3 PLOS_CNTꢁ PLOS_CNT1 PLOS_CNT0 ARC_CNT3 ARC_CNTꢁ ARC_CNT1 ARC_CNT0
R/W
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
POR
Bitꢀ7~4
Bitꢀ3~0
PLOS_CNT3~PLOS_CNT0:ꢀTXꢀlostꢀdataꢀpacketꢀnumber
0000~1111:ꢀ0ꢀTXꢀlostꢀdataꢀpacket~15ꢀTXꢀlostꢀdataꢀpackets
ThisꢀfieldꢀisꢀusedꢀtoꢀcountꢀtheꢀtotalꢀlostꢀdataꢀpacketsꢀduringꢀtheꢀTXꢀdataꢀtransmission.ꢀ
TheꢀPLOS_CNTꢀvalueꢀwillꢀbeꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀaꢀTXꢀdataꢀpacketꢀisꢀlostꢀ
andꢀretransmitted.ꢀWhenꢀtheꢀcounterꢀvalueꢀisꢀequalꢀtoꢀ“1111”,ꢀitꢀwillꢀstopꢀcountingꢀandꢀ
remainꢀtheꢀmaximumꢀvalueꢀofꢀ1111ꢀinsteadꢀofꢀcounterꢀoverflowꢀuntilꢀaꢀresetꢀconditionꢀ
occurs.ꢀThisꢀcounterꢀwillꢀbeꢀresetꢀbyꢀaꢀwriteꢀoperationꢀtoꢀtheꢀRF_CHꢀregister.
ARC_CNT3~ARC_CNT0:ꢀAutomaticꢀRetransmissionꢀnumber
ThisꢀfieldꢀisꢀusedꢀtoꢀcountꢀtheꢀretransmittedꢀdataꢀpacketsꢀduringꢀtheꢀTXꢀdataꢀ
transmission.ꢀTheꢀARC_CNTꢀvalueꢀwillꢀbeꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀaꢀTXꢀdataꢀ
packetꢀisꢀlostꢀandꢀretransmitted.ꢀThisꢀcounterꢀwillꢀbeꢀresetꢀwhenꢀaꢀnewꢀTXꢀdataꢀstartsꢀ
toꢀbeꢀtransmitted.
•ꢀ Address 09H – CD Register
Thisꢀregisterꢀisꢀusedꢀtoꢀindicateꢀtheꢀcarrierꢀdetectꢀstatus.
Bit
Name
R/W
7
6
5
4
3
2
1
0
CD
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
CD:ꢀCarrierꢀDetectꢀstatus
0:ꢀNoꢀcarrierꢀisꢀdetected
1:ꢀCarrierꢀhasꢀbeenꢀdetected
•ꢀ Address 0AH – RX_ADDR_P0 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ0ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P0
[39:3ꢁ]
RX_ADDR_P0
[31:ꢁ4]
RX_ADDR_P0
[ꢁ3:16]
RX_ADDR_P0
[15:8]
RX_ADDR_P0
[ꢃ:0]
Name
R/W
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
POR
Bitꢀ39~0
RX_ADDR_P0:ꢀDataꢀpipe0ꢀreceiveꢀaddress
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ0ꢀreceiveꢀaddress.ꢀTheꢀaddressꢀfieldꢀwidthꢀ
canꢀbeꢀupꢀtoꢀ5ꢀbytesꢀwhichꢀisꢀspecifiedꢀinꢀtheꢀSETUP_AWꢀregister.ꢀThisꢀaddressꢀfieldꢀ
configurationꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀfromꢀtheꢀleastꢀsignificantꢀbyteꢀtoꢀtheꢀmostꢀ
significantꢀbyte.
Rev. 1.40
ꢁ13
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 0BH – RX_ADDR_P1 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ1ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P1
[39:3ꢁ]
RX_ADDR_P1
[31:ꢁ4]
RX_ADDR_P1
[ꢁ3:16]
RX_ADDR_P1
[15:8]
RX_ADDR_P1
[ꢃ:0]
Name
R/W
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
POR
Bitꢀ39~0
RX_ADDR_P1:ꢀDataꢀpipe1ꢀreceiveꢀaddress
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ1ꢀreceiveꢀaddress.ꢀTheꢀaddressꢀfieldꢀwidthꢀ
canꢀbeꢀupꢀtoꢀ5ꢀbytesꢀwhichꢀisꢀspecifiedꢀinꢀtheꢀSETUP_AWꢀregister.ꢀThisꢀaddressꢀfieldꢀ
configurationꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀfromꢀtheꢀleastꢀsignificantꢀbyteꢀtoꢀtheꢀmostꢀ
significantꢀbyte.
•ꢀ Address 0CH – RX_ADDR_P2 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ2ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P1
[39:3ꢁ]
RX_ADDR_P1
[31:ꢁ4]
RX_ADDR_P1
[ꢁ3:16]
RX_ADDR_P1
[15:8]
RX_ADDR_Pꢁ
[ꢃ:0]
Name
R/W
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
C3
POR
Bitꢀ39~8
Bitꢀ7~0
RX_ADDR_P1 [39:8]:ꢀDataꢀpipe1ꢀreceiveꢀaddressꢀbitꢀ39~bitꢀ8
RX_ADDR_P2 [7:0]:ꢀDataꢀpipeꢀ2ꢀreceiveꢀaddressꢀbitꢀ7~bitꢀ0
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ2ꢀreceiveꢀaddress.ꢀNoteꢀthatꢀonlyꢀbitꢀ7~bitꢀ0ꢀofꢀ
theꢀaddressꢀfieldꢀcanꢀbeꢀconfiguredꢀandꢀotherꢀ32MSBsꢀfromꢀbitꢀ39ꢀtoꢀbitꢀ8ꢀmustꢀbeꢀtheꢀ
sameꢀasꢀtheꢀdataꢀpipeꢀ1ꢀaddress.
•ꢀ Address 0DH – RX_ADDR_P3 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ3ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P1
[39:3ꢁ]
RX_ADDR_P1
[31:ꢁ4]
RX_ADDR_P1
[ꢁ3:16]
RX_ADDR_P1
[15:8]
RX_ADDR_P3
[ꢃ:0]
Name
R/W
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
C4
POR
Bitꢀ39~8
Bitꢀ7~0
RX_ADDR_P1 [39:8]:ꢀDataꢀpipe1ꢀreceiveꢀaddressꢀbitꢀ39~bitꢀ8
RX_ADDR_P3 [7:0]: Dataꢀpipeꢀ3ꢀreceiveꢀaddressꢀbitꢀ7~bitꢀ0
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ3ꢀreceiveꢀaddress.ꢀNoteꢀthatꢀonlyꢀbitꢀ7~bitꢀ0ꢀofꢀ
theꢀaddressꢀfieldꢀcanꢀbeꢀconfiguredꢀandꢀotherꢀ32MSBsꢀfromꢀbitꢀ39ꢀtoꢀbitꢀ8ꢀmustꢀbeꢀtheꢀ
sameꢀasꢀtheꢀdataꢀpipeꢀ1ꢀaddress.
Rev. 1.40
ꢁ14
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 0EH – RX_ADDR_P4 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ4ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P1
[39:3ꢁ]
RX_ADDR_P1
[31:ꢁ4]
RX_ADDR_P1
[ꢁ3:16]
RX_ADDR_P1
[15:8]
RX_ADDR_P4
[ꢃ:0]
Name
R/W
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
C5
POR
Bitꢀ39~8
Bitꢀ7~0
RX_ADDR_P1 [39:8]:ꢀDataꢀpipe1ꢀreceiveꢀaddressꢀbitꢀ39~bitꢀ8
RX_ADDR_P4 [7:0]:ꢀDataꢀpipeꢀ4ꢀreceiveꢀaddressꢀbitꢀ7~bitꢀ0
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ4ꢀreceiveꢀaddress.ꢀNoteꢀthatꢀonlyꢀbitꢀ7~bitꢀ0ꢀofꢀ
theꢀaddressꢀfieldꢀcanꢀbeꢀconfiguredꢀandꢀotherꢀ32MSBsꢀfromꢀbitꢀ39ꢀtoꢀbitꢀ8ꢀmustꢀbeꢀtheꢀ
sameꢀasꢀtheꢀdataꢀpipeꢀ1ꢀaddress.
•ꢀ Address 0FH – RX_ADDR_P5 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ5ꢀRXꢀaddress.
Byte
4
3
2
1
0
RX_ADDR_P1
[39:3ꢁ]
RX_ADDR_P1
[31:ꢁ4]
RX_ADDR_P1
[ꢁ3:16]
RX_ADDR_P1
[15:8]
RX_ADDR_P5
[ꢃ:0]
Name
R/W
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
Cꢁ
R/W
C6
POR
Bitꢀ39~8
Bitꢀ7~0
RX_ADDR_P1 [39:8]:ꢀDataꢀpipe1ꢀreceiveꢀaddressꢀbitꢀ39~bitꢀ8
RX_ADDR_P5 [7:0]:ꢀDataꢀpipeꢀ5ꢀreceiveꢀaddressꢀbitꢀ7~bitꢀ0
Thisꢀfieldꢀisꢀusedꢀtoꢀdefineꢀtheꢀdataꢀpipeꢀ5ꢀreceiveꢀaddress.ꢀNoteꢀthatꢀonlyꢀbitꢀ7~bitꢀ0ꢀofꢀ
theꢀaddressꢀfieldꢀcanꢀbeꢀconfiguredꢀandꢀotherꢀ32MSBsꢀfromꢀbitꢀ39ꢀtoꢀbitꢀ8ꢀmustꢀbeꢀtheꢀ
sameꢀasꢀtheꢀdataꢀpipeꢀ1ꢀaddress.
•ꢀ Address 10H – TX_ADDR Register
ThisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀTXꢀaddress.
Byte
4
3
2
1
0
Name TX_ADDR [39:3ꢁ] TX_ADDR [31:ꢁ4] TX_ADDR [ꢁ3:16] TX_ADDR [15:8] TX_ADDR [ꢃ:0]
R/W
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
R/W
Eꢃ
POR
Bitꢀ39~0
TX_ADDR:ꢀTXꢀTransmitꢀaddress
ThisꢀfieldꢀisꢀonlyꢀusedꢀforꢀtheꢀPTXꢀdeviceꢀtoꢀdefineꢀtheꢀTXꢀtransmitꢀaddress.ꢀTheꢀ
addressꢀfieldꢀcanꢀbeꢀupꢀtoꢀ5ꢀbytesꢀwhichꢀisꢀspecifiedꢀinꢀtheꢀSETUP_AWꢀregister.ꢀThisꢀ
addressꢀfieldꢀconfigurationꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀfromꢀtheꢀleastꢀsignificantꢀ
byteꢀtoꢀtheꢀmostꢀsignificantꢀbyte.ꢀItꢀisꢀrecommendedꢀtoꢀspecifyꢀtheꢀsameꢀaddressꢀforꢀ
bothꢀRX_ADDR_P0ꢀandꢀTX_ADDRꢀaddressꢀfieldꢀtoꢀproperlyꢀhandleꢀtheꢀautomaticꢀ
acknowledgementꢀfunction.
Rev. 1.40
ꢁ15
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 11H – RX_PW_P0 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ0ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
P05
R/W
0
P04
R/W
0
P03
R/W
0
P0ꢁ
R/W
0
P01
R/W
0
P00
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P0 [5:0]:ꢀDataꢀPipeꢀ0ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused
•ꢀ Address 12H – RX_PW_P1 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ1ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
P15
R/W
0
P14
R/W
0
P13
R/W
0
P1ꢁ
R/W
0
P11
R/W
0
P10
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P1 [5:0]:ꢀDataꢀPipeꢀ1ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused
•ꢀ Address 13H – RX_PW_P2 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ2ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
Pꢁ5
R/W
0
Pꢁ4
R/W
0
Pꢁ3
R/W
0
Pꢁꢁ
R/W
0
Pꢁ1
R/W
0
Pꢁ0
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P2 [5:0]:ꢀDataꢀPipeꢀ2ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused
Rev. 1.40
ꢁ16
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 14H – RX_PW_P3 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ3ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
P35
R/W
0
P34
R/W
0
P33
R/W
0
P3ꢁ
R/W
0
P31
R/W
0
P30
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P3 [5:0]:ꢀDataꢀPipeꢀ3ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused.
•ꢀ Address 15H – RX_PW_P4 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ4ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
P45
R/W
0
P44
R/W
0
P43
R/W
0
P4ꢁ
R/W
0
P41
R/W
0
P40
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P4 [5:0]:ꢀDataꢀPipeꢀ4ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused.
•ꢀ Address 16H – RX_PW_P5 Register
Thisꢀregisterꢀisꢀusedꢀtoꢀspecifyꢀtheꢀdataꢀpipeꢀ5ꢀRXꢀpayloadꢀbyteꢀnumber.
Bit
7
6
5
4
3
2
1
0
RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_ RX_PW_
Name
—
—
P55
R/W
0
P54
R/W
0
P53
R/W
0
P5ꢁ
R/W
0
P51
R/W
0
P50
R/W
0
R/W
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~0
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
RX_PW_P5 [5:0]:ꢀDataꢀPipeꢀ5ꢀRXꢀpayloadꢀbyteꢀnumber
0:ꢀNotꢀused
1:ꢀ1ꢀbyte
2:ꢀ2ꢀbytes
:
32:ꢀ32ꢀbytes
Others:ꢀCanꢀnotꢀbeꢀused.
Rev. 1.40
ꢁ1ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 17H – FIFO_STATUS Register
ThisꢀregisterꢀisꢀusedꢀtoꢀindicateꢀtheꢀFIFOꢀstatusꢀduringꢀtheꢀdataꢀtransfer.
Bit
Name
R/W
7
—
6
5
4
3
—
2
—
1
0
TX_REUSE TX_FULL TX_E�PTY
RX_FULL RX_E�PTY
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R
1
POR
Bitꢀ7ꢀ
Reservedꢀbits,ꢀonlyꢀdataꢀ“0”ꢀallowed.
Bitꢀ6
TX_REUSE:ꢀLastꢀTransmittedꢀDataꢀPacketꢀReuseꢀstatus
0:ꢀLastꢀtransmittedꢀdataꢀpacketꢀisꢀnotꢀreused
1:ꢀLastꢀtransmittedꢀdataꢀpacketꢀisꢀreused
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀlastꢀTXꢀdataꢀpacketꢀisꢀrepeatedlyꢀtransmittedꢀ
orꢀnot.ꢀIfꢀtheꢀCEꢀlineꢀisꢀkeptꢀinꢀaꢀhighꢀstate,ꢀtheꢀlastꢀdataꢀpacketꢀwillꢀbeꢀrepeatedlyꢀ
retransmitted.ꢀThisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀSPIꢀcommand,ꢀREUSE_TX_PL,ꢀandꢀclearedꢀ
toꢀ0ꢀbyꢀtheꢀSPIꢀcommand,ꢀW_TX_PAYLOADꢀorꢀFLUSH_TX.
Bitꢀ5
Bitꢀ4
TX_FULL:ꢀTXꢀFIFOꢀFullꢀFlag
0:ꢀTXꢀFIFOꢀisꢀnotꢀfull
1:ꢀTXꢀFIFOꢀisꢀfull
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀTXꢀFIFOꢀisꢀfullꢀorꢀnot.
TX_EMPTY:ꢀTXꢀFIFOꢀEmptyꢀFlag
0:ꢀTXꢀFIFOꢀisꢀnotꢀempty
1:ꢀTXꢀFIFOꢀisꢀempty
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀTXꢀFIFOꢀisꢀemptyꢀorꢀnot.
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
Bitꢀ3~2ꢀ
Bitꢀ1
RX_FULL:ꢀRXꢀFIFOꢀFullꢀFlag
0:ꢀRXꢀFIFOꢀisꢀnotꢀfull
1:ꢀRXꢀFIFOꢀisꢀfull
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀRXꢀFIFOꢀisꢀfullꢀorꢀnot.
Bitꢀ0
RX_EMPTY:ꢀRXꢀFIFOꢀEmptyꢀFlag
0:ꢀRXꢀFIFOꢀisꢀnotꢀempty
1:ꢀRXꢀFIFOꢀisꢀempty
ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀRXꢀFIFOꢀisꢀemptyꢀorꢀnot.
Rev. 1.40
ꢁ18
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 1CH – DYNPD Register
Thisꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀtheꢀindividualꢀdataꢀpipeꢀdynamicꢀpayloadꢀlengthꢀfunction.
Bit
Name
R/W
7
—
6
—
5
4
3
2
1
0
DPL_P5 DPL_P4 DPL_P3 DPL_Pꢁ DPL_P1 DPL_P0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
Reservedꢀbits,ꢀonlyꢀdataꢀ“00”ꢀallowed.
DPL_P5:ꢀDataꢀPipeꢀ5ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe5ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P5ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
Bitꢀ4
Bitꢀ3
Bitꢀ2
Bitꢀ1
Bitꢀ0
DPL_P4:ꢀDataꢀPipeꢀ4ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe4ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P4ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
DPL_P3:ꢀDataꢀPipeꢀ3ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe3ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P3ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
DPL_P2:ꢀDataꢀPipeꢀ2ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe2ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P2ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
DPL_P1:ꢀDataꢀPipeꢀ1ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe1ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P1ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
DPL_P0:ꢀDataꢀPipeꢀ0ꢀDynamicꢀPayloadꢀLengthꢀfunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdataꢀpipe0ꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀItꢀisꢀonlyꢀ
availableꢀwhenꢀtheꢀEN_DPLꢀandꢀENAA_P0ꢀbitsꢀareꢀbothꢀsetꢀtoꢀ1.
Rev. 1.40
ꢁ19
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 1DH – FEATURE Register
ThisꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀseveralꢀmainꢀfeaturesꢀofꢀtheꢀRFꢀtransceiver.
Bit
Name
R/W
7
—
6
—
5
—
4
—
3
—
2
1
0
EN_DPL EN_ACK_PAY EN_DNY_ACK
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~3ꢀ
Bitꢀ2
Reservedꢀbits,ꢀonlyꢀdataꢀ“00000”ꢀallowed.
EN_DPL:ꢀRFꢀTransceiverꢀDynamicꢀPayloadꢀLengthꢀFunctionꢀcontrol
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀRFꢀTransceiverꢀdynamicꢀpayloadꢀlengthꢀfunction.ꢀIfꢀ
theꢀEN_DPLꢀbitꢀisꢀsetꢀtoꢀ1ꢀandꢀtheꢀcorrespondingꢀENAA_Pnꢀbitꢀisꢀalsoꢀsetꢀtoꢀ1,ꢀtheꢀ
dynamicꢀpayloadꢀlengthꢀfunctionꢀofꢀtheꢀrelevantꢀdataꢀpipeꢀnꢀwillꢀbeꢀavailable.
Bitꢀ1
Bitꢀ0
EN_ACK_PAY:ꢀRFꢀTransceiverꢀPayloadꢀwithꢀAcknowledgementꢀcontrol
0:ꢀDisable
1:ꢀEnable
EN_DNY_ACK:ꢀRFꢀTransceiverꢀ“W_TX_PAYLOAD_NOACK”ꢀCommandꢀcontrol
0:ꢀDisableꢀtheꢀcommand
1:ꢀEnableꢀtheꢀcommand
Register Bank 1
Itꢀisꢀrecommendedꢀthatꢀnoꢀaccessꢀisꢀexecutedꢀonꢀreservedꢀorꢀnonꢀdefinedꢀregisters.ꢀOtherwise,ꢀthisꢀ
mayꢀresultꢀinꢀunpredictableꢀconditions.
•ꢀ Address 00H – Optimisation Register 0
Bit
Name
R/W
31
30
…………
Optimisation_Value_0
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
ofꢀ0x858A_C01Cꢀintoꢀthisꢀregister.
•ꢀ Address 01H – Optimisation Register 1
Bit
Name
R/W
31
30
…………
Optimisation_Value_1
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
ofꢀ0x1103_C960ꢀintoꢀthisꢀregister.
•ꢀ Address 02H – Optimisation Register 2
Bit
Name
R/W
31
30
…………
Optimisation_Value_ꢁ
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
ofꢀ0x0000_0004ꢀintoꢀthisꢀregister.
Rev. 1.40
ꢁꢁ0
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 03H – Optimisation Register 3
Bit
Name
R/W
31
30
…………
Optimisation_Value_3
W
1
0
POR
0x0300_1ꢁ00
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
ofꢀ0x0000_0004ꢀintoꢀthisꢀregister.
•ꢀ Address 04H – Optimisation Register 4
Bit
Name
R/W
31
30
…………
Optimisation_Value_4
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
intoꢀthisꢀregisterꢀforꢀdifferentꢀoperatingꢀmodes.
•ꢀ Forꢀ1Mbpsꢀandꢀ2Mbps:ꢀ0x437D_563F
•ꢀ Forꢀ250kbps:ꢀ0x437D_663F
Forꢀsingleꢀcarrierꢀmode:
•ꢀ LowꢀPower:ꢀ0x437D_563F
•ꢀ NormalꢀPower:ꢀ0x417D_563F
•ꢀ Address 05H – Optimisation Register 5
Bit
Name
R/W
31
30
…………
Optimisation_Value_5
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
intoꢀthisꢀregisterꢀforꢀdifferentꢀdataꢀrates.
•ꢀ Forꢀ250kbpsꢀdataꢀrate:ꢀ0x7410_6C9F
•ꢀ Forꢀ1Mbpsꢀdataꢀrate:ꢀꢀ0x1412_6C9F
•ꢀ Forꢀ2Mbpsꢀdataꢀrate:ꢀꢀ0x7411_4C9F
•ꢀ Address 06H – Optimisation Register 6
Bit
Name
R/W
31
30
………
Optimisation Value 6
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀperformanceꢀofꢀtheꢀRFꢀTransceiverꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀ
ofꢀ0x0007_C022ꢀintoꢀthisꢀregister
Rev. 1.40
ꢁꢁ1
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
•ꢀ Address 07H – Status Register 1
Bit
Name
R/W
31
30
8
7
6
………
1
0
Reserved bits
RBANK
Reserved bits
W
0
R
0
W
0
POR
Thisꢀregisterꢀisꢀreservedꢀexceptꢀforꢀbitꢀ7,ꢀRBANK.ꢀItꢀisꢀrecommendedꢀtheꢀreservedꢀbitsꢀareꢀnotꢀ
accessedꢀtoꢀpreventꢀunpredictableꢀresults.
Bitꢀ7
RBANK:ꢀRegisterꢀBankꢀStatus
0:ꢀRegisterꢀbankꢀ0
1:ꢀRegisterꢀbankꢀ1
•ꢀ Address 08H – Chip ID Register
Bit
Name
R/W
31
30
…………
ID_Value
R
1
0
POR
0x0000_0000
Thisꢀregisterꢀisꢀaꢀread-onlyꢀregisterꢀandꢀisꢀusedꢀtoꢀstoreꢀtheꢀchipꢀIDꢀcode.
•ꢀ Address 0CH – Initialization Register
Bit
Name
R/W
31
30
…………
Initialisation_Value
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀinitialiseꢀtheꢀRFꢀTransceiverꢀPLLꢀLockꢀtimeꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀofꢀ
0x0573_1200ꢀintoꢀthisꢀregister.ꢀForꢀ120 sꢀmode,ꢀtheꢀvalueꢀisꢀ0x0073_1200.
m
•ꢀ Address 0DH – New_Feature Register
Bit
Name
R/W
31
30
…………
New_Feature_Value
W
1
0
POR
0x0000_0000
ThisꢀregisterꢀisꢀusedꢀtoꢀconfigureꢀtheꢀRFꢀTransceiverꢀfeaturesꢀbyꢀwritingꢀaꢀspecificꢀvalueꢀofꢀ
0x0080_B434ꢀintoꢀthisꢀregister.
•ꢀ Address 0EH – RAMP Register
Bit
Name
R/W
87
86
…………
1
0
RA�P_Value
W
POR
0xuu_uuuu_ uuuu_uuuu_ uuuu_uuuu
ThisꢀregisterꢀisꢀusedꢀtoꢀoptimiseꢀtheꢀRFꢀTransmitterꢀoutputꢀspectrumꢀrateꢀcurveꢀbyꢀwritingꢀaꢀspecificꢀ
valueꢀofꢀ0xCF_FFBD_F3CF_2080_8204_1041ꢀintoꢀthisꢀregister.
Rev. 1.40
ꢁꢁꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Configuration Options
ConfigurationꢀoptionsꢀreferꢀtoꢀcertainꢀoptionsꢀwithinꢀtheꢀMCUꢀthatꢀareꢀprogrammedꢀintoꢀtheꢀdevicesꢀ
duringꢀtheꢀprogrammingꢀprocess.ꢀDuringꢀtheꢀdevelopmentꢀprocess,ꢀtheseꢀoptionsꢀareꢀselectedꢀusingꢀ
theꢀHT-IDEꢀsoftwareꢀdevelopmentꢀtools.ꢀAsꢀtheseꢀoptionsꢀareꢀprogrammedꢀintoꢀtheꢀdevicesꢀusingꢀ
theꢀhardwareꢀprogrammingꢀtools,ꢀonceꢀtheyꢀareꢀselectedꢀtheyꢀcannotꢀbeꢀchangedꢀlaterꢀusingꢀtheꢀ
applicationꢀprogram.ꢀAllꢀoptionsꢀmustꢀbeꢀdefinedꢀforꢀproperꢀsystemꢀfunction,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀ
shownꢀinꢀtheꢀtable.
No.
Options
Oscillator Options
1
Supplementarꢀ Oscillator Selection – fSUB: LXT or LIRC
I/O Pin-Shared Options
ꢁ
3
Reset pin function: RES or I/O
VDDIO pin function: VDDIO or I/O
SIM/SPIA Interface Options
4
5
6
ꢃ
SI� Function: Enable or Disable
SPIA Function: Enable or Disable
SPI/SPIA – CSEN bit: Enable or Disable
SPI/SPIA – WCOL bit: Enable or Disable
IꢁC Debounce Time Selection: No debounceꢂ ꢁ sꢀstem clock debounce or 4 sꢀstem clock
debounce
8
Rev. 1.40
ꢁꢁ3
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Application Circuits
0R
3.3V
3.3V
VDDIO
VSSRX2
VDD
4.7pF
0.1uF
8.2nH
VDDPA
VSS
RFP1
RFN1
5.6nH
0R
2pF
I/O
VDD3B
3.9nH
1.2pF
10W
2.2uF
OSC1
OSC2
10W
VDD3RXRF
CDVDD
3.3V
10nF
1uF
10nF
10pF
10pF
16MHz
BC66F8x0
Rev. 1.40
ꢁꢁ4
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Instruction Set
Introduction
Centralꢀtoꢀtheꢀsuccessfulꢀoperationꢀofꢀanyꢀmicrocontrollerꢀisꢀitsꢀinstructionꢀset,ꢀwhichꢀisꢀaꢀsetꢀofꢀ
programꢀinstructionꢀcodesꢀthatꢀdirectsꢀtheꢀmicrocontrollerꢀtoꢀperformꢀcertainꢀoperations.ꢀInꢀtheꢀcaseꢀ
ofꢀHoltekꢀmicrocontroller,ꢀaꢀcomprehensiveꢀandꢀflexibleꢀsetꢀofꢀoverꢀ60ꢀinstructionsꢀisꢀprovidedꢀtoꢀ
enableꢀprogrammersꢀtoꢀimplementꢀtheirꢀapplicationꢀwithꢀtheꢀminimumꢀofꢀprogrammingꢀoverheads.ꢀ
Forꢀeasierꢀunderstandingꢀofꢀtheꢀvariousꢀinstructionꢀcodes,ꢀtheyꢀhaveꢀbeenꢀsubdividedꢀintoꢀseveralꢀ
functionalꢀgroupings.
Instruction Timing
Mostꢀinstructionsꢀareꢀimplementedꢀwithinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranch,ꢀ
call,ꢀorꢀtableꢀreadꢀinstructionsꢀwhereꢀtwoꢀinstructionꢀcyclesꢀareꢀrequired.ꢀOneꢀinstructionꢀcycleꢀisꢀ
equalꢀtoꢀ4ꢀsystemꢀclockꢀcycles,ꢀthereforeꢀinꢀtheꢀcaseꢀofꢀanꢀ8MHzꢀsystemꢀoscillator,ꢀmostꢀinstructionsꢀ
wouldꢀbeꢀimplementedꢀwithinꢀ0.5μsꢀandꢀbranchꢀorꢀcallꢀinstructionsꢀwouldꢀbeꢀimplementedꢀwithinꢀ
1μs.ꢀAlthoughꢀinstructionsꢀwhichꢀrequireꢀoneꢀmoreꢀcycleꢀtoꢀimplementꢀareꢀgenerallyꢀlimitedꢀtoꢀ
theꢀJMP,ꢀCALL,ꢀRET,ꢀRETIꢀandꢀtableꢀreadꢀinstructions,ꢀitꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀanyꢀotherꢀ
instructionsꢀwhichꢀinvolveꢀmanipulationꢀofꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCLꢀwillꢀalsoꢀtakeꢀ
oneꢀmoreꢀcycleꢀtoꢀimplement.ꢀAsꢀinstructionsꢀwhichꢀchangeꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀimplyꢀaꢀ
directꢀjumpꢀtoꢀthatꢀnewꢀaddress,ꢀoneꢀmoreꢀcycleꢀwillꢀbeꢀrequired.ꢀExamplesꢀofꢀsuchꢀinstructionsꢀ
wouldꢀbeꢀ“CLRꢀPCL”ꢀorꢀ“MOVꢀPCL,ꢀA”.ꢀForꢀtheꢀcaseꢀofꢀskipꢀinstructions,ꢀitꢀmustꢀbeꢀnotedꢀthatꢀifꢀ
theꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀoperationꢀthenꢀthisꢀwillꢀalsoꢀtakeꢀoneꢀmoreꢀcycle,ꢀifꢀnoꢀ
skipꢀisꢀinvolvedꢀthenꢀonlyꢀoneꢀcycleꢀisꢀrequired.
Moving and Transferring Data
Theꢀtransferꢀofꢀdataꢀwithinꢀtheꢀmicrocontrollerꢀprogramꢀisꢀoneꢀofꢀtheꢀmostꢀfrequentlyꢀusedꢀ
operations.ꢀMakingꢀuseꢀofꢀthreeꢀkindsꢀofꢀMOVꢀinstructions,ꢀdataꢀcanꢀbeꢀtransferredꢀfromꢀregistersꢀtoꢀ
theꢀAccumulatorꢀandꢀvice-versaꢀasꢀwellꢀasꢀbeingꢀableꢀtoꢀmoveꢀspecificꢀimmediateꢀdataꢀdirectlyꢀintoꢀ
theꢀAccumulator.ꢀOneꢀofꢀtheꢀmostꢀimportantꢀdataꢀtransferꢀapplicationsꢀisꢀtoꢀreceiveꢀdataꢀfromꢀtheꢀ
inputꢀportsꢀandꢀtransferꢀdataꢀtoꢀtheꢀoutputꢀports.
Arithmetic Operations
Theꢀabilityꢀtoꢀperformꢀcertainꢀarithmeticꢀoperationsꢀandꢀdataꢀmanipulationꢀisꢀaꢀnecessaryꢀfeatureꢀofꢀ
mostꢀmicrocontrollerꢀapplications.ꢀWithinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀsetꢀareꢀaꢀrangeꢀofꢀ
addꢀandꢀsubtractꢀinstructionꢀmnemonicsꢀtoꢀenableꢀtheꢀnecessaryꢀarithmeticꢀtoꢀbeꢀcarriedꢀout.ꢀCareꢀ
mustꢀbeꢀtakenꢀtoꢀensureꢀcorrectꢀhandlingꢀofꢀcarryꢀandꢀborrowꢀdataꢀwhenꢀresultsꢀexceedꢀ255ꢀforꢀ
additionꢀandꢀlessꢀthanꢀ0ꢀforꢀsubtraction.ꢀTheꢀincrementꢀandꢀdecrementꢀinstructionsꢀINC,ꢀINCA,ꢀDECꢀ
andꢀDECAꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀincreasingꢀorꢀdecreasingꢀbyꢀaꢀvalueꢀofꢀoneꢀofꢀtheꢀvaluesꢀinꢀtheꢀ
destinationꢀspecified.
Rev. 1.40
ꢁꢁ5
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Logical and Rotate Operation
TheꢀstandardꢀlogicalꢀoperationsꢀsuchꢀasꢀAND,ꢀOR,ꢀXORꢀandꢀCPLꢀallꢀhaveꢀtheirꢀownꢀinstructionꢀ
withinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀset.ꢀAsꢀwithꢀtheꢀcaseꢀofꢀmostꢀinstructionsꢀinvolvingꢀ
dataꢀmanipulation,ꢀdataꢀmustꢀpassꢀthroughꢀtheꢀAccumulatorꢀwhichꢀmayꢀinvolveꢀadditionalꢀ
programmingꢀsteps.ꢀInꢀallꢀlogicalꢀdataꢀoperations,ꢀtheꢀzeroꢀflagꢀmayꢀbeꢀsetꢀifꢀtheꢀresultꢀofꢀtheꢀ
operationꢀisꢀzero.ꢀAnotherꢀformꢀofꢀlogicalꢀdataꢀmanipulationꢀcomesꢀfromꢀtheꢀrotateꢀinstructionsꢀsuchꢀ
asꢀRR,ꢀRL,ꢀRRCꢀandꢀRLCꢀwhichꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀrotatingꢀoneꢀbitꢀrightꢀorꢀleft.ꢀDifferentꢀ
rotateꢀinstructionsꢀexistꢀdependingꢀonꢀprogramꢀrequirements.ꢀRotateꢀinstructionsꢀareꢀusefulꢀforꢀserialꢀ
portꢀprogrammingꢀapplicationsꢀwhereꢀdataꢀcanꢀbeꢀrotatedꢀfromꢀanꢀinternalꢀregisterꢀintoꢀtheꢀCarryꢀ
bitꢀfromꢀwhereꢀitꢀcanꢀbeꢀexaminedꢀandꢀtheꢀnecessaryꢀserialꢀbitꢀsetꢀhighꢀorꢀlow.ꢀAnotherꢀapplicationꢀ
whichꢀrotateꢀdataꢀoperationsꢀareꢀusedꢀisꢀtoꢀimplementꢀmultiplicationꢀandꢀdivisionꢀcalculations.
Branches and Control Transfer
ProgramꢀbranchingꢀtakesꢀtheꢀformꢀofꢀeitherꢀjumpsꢀtoꢀspecifiedꢀlocationsꢀusingꢀtheꢀJMPꢀinstructionꢀ
orꢀtoꢀaꢀsubroutineꢀusingꢀtheꢀCALLꢀinstruction.ꢀTheyꢀdifferꢀinꢀtheꢀsenseꢀthatꢀinꢀtheꢀcaseꢀofꢀaꢀ
subroutineꢀcall,ꢀtheꢀprogramꢀmustꢀreturnꢀtoꢀtheꢀinstructionꢀimmediatelyꢀwhenꢀtheꢀsubroutineꢀhasꢀ
beenꢀcarriedꢀout.ꢀThisꢀisꢀdoneꢀbyꢀplacingꢀaꢀreturnꢀinstructionꢀ“RET”ꢀinꢀtheꢀsubroutineꢀwhichꢀwillꢀ
causeꢀtheꢀprogramꢀtoꢀjumpꢀbackꢀtoꢀtheꢀaddressꢀrightꢀafterꢀtheꢀCALLꢀinstruction.ꢀInꢀtheꢀcaseꢀofꢀaꢀJMPꢀ
instruction,ꢀtheꢀprogramꢀsimplyꢀjumpsꢀtoꢀtheꢀdesiredꢀlocation.ꢀThereꢀisꢀnoꢀrequirementꢀtoꢀjumpꢀbackꢀ
toꢀtheꢀoriginalꢀjumpingꢀoffꢀpointꢀasꢀinꢀtheꢀcaseꢀofꢀtheꢀCALLꢀinstruction.ꢀOneꢀspecialꢀandꢀextremelyꢀ
usefulꢀsetꢀofꢀbranchꢀinstructionsꢀareꢀtheꢀconditionalꢀbranches.ꢀHereꢀaꢀdecisionꢀisꢀfirstꢀmadeꢀregardingꢀ
theꢀconditionꢀofꢀaꢀcertainꢀdataꢀmemoryꢀorꢀindividualꢀbits.ꢀDependingꢀuponꢀtheꢀconditions,ꢀtheꢀ
programꢀwillꢀcontinueꢀwithꢀtheꢀnextꢀinstructionꢀorꢀskipꢀoverꢀitꢀandꢀjumpꢀtoꢀtheꢀfollowingꢀinstruction.ꢀ
Theseꢀinstructionsꢀareꢀtheꢀkeyꢀtoꢀdecisionꢀmakingꢀandꢀbranchingꢀwithinꢀtheꢀprogramꢀperhapsꢀ
determinedꢀbyꢀtheꢀconditionꢀofꢀcertainꢀinputꢀswitchesꢀorꢀbyꢀtheꢀconditionꢀofꢀinternalꢀdataꢀbits.
Bit Operations
TheꢀabilityꢀtoꢀprovideꢀsingleꢀbitꢀoperationsꢀonꢀDataꢀMemoryꢀisꢀanꢀextremelyꢀflexibleꢀfeatureꢀofꢀallꢀ
Holtekꢀmicrocontrollers.ꢀThisꢀfeatureꢀisꢀespeciallyꢀusefulꢀforꢀoutputꢀportꢀbitꢀprogrammingꢀwhereꢀ
individualꢀbitsꢀorꢀportꢀpinsꢀcanꢀbeꢀdirectlyꢀsetꢀhighꢀorꢀlowꢀusingꢀeitherꢀtheꢀ“SETꢀ[m].i”ꢀorꢀ“CLRꢀ[m].i”ꢀ
instructionsꢀrespectively.ꢀTheꢀfeatureꢀremovesꢀtheꢀneedꢀforꢀprogrammersꢀtoꢀfirstꢀreadꢀtheꢀ8-bitꢀoutputꢀ
port,ꢀmanipulateꢀtheꢀinputꢀdataꢀtoꢀensureꢀthatꢀotherꢀbitsꢀareꢀnotꢀchangedꢀandꢀthenꢀoutputꢀtheꢀportꢀwithꢀ
theꢀcorrectꢀnewꢀdata.ꢀThisꢀread-modify-writeꢀprocessꢀisꢀtakenꢀcareꢀofꢀautomaticallyꢀwhenꢀtheseꢀbitꢀ
operationꢀinstructionsꢀareꢀused.
Table Read Operations
Dataꢀstorageꢀisꢀnormallyꢀimplementedꢀbyꢀusingꢀregisters.ꢀHowever,ꢀwhenꢀworkingꢀwithꢀlargeꢀ
amountsꢀofꢀfixedꢀdata,ꢀtheꢀvolumeꢀinvolvedꢀoftenꢀmakesꢀitꢀinconvenientꢀtoꢀstoreꢀtheꢀfixedꢀdataꢀinꢀ
theꢀDataꢀMemory.ꢀToꢀovercomeꢀthisꢀproblem,ꢀHoltekꢀmicrocontrollersꢀallowꢀanꢀareaꢀofꢀProgramꢀ
Memoryꢀtoꢀbeꢀsetupꢀasꢀaꢀtableꢀwhereꢀdataꢀcanꢀbeꢀdirectlyꢀstored.ꢀAꢀsetꢀofꢀeasyꢀtoꢀuseꢀinstructionsꢀ
providesꢀtheꢀmeansꢀbyꢀwhichꢀthisꢀfixedꢀdataꢀcanꢀbeꢀreferencedꢀandꢀretrievedꢀfromꢀtheꢀProgramꢀ
Memory.
Other Operations
Inꢀadditionꢀtoꢀtheꢀaboveꢀfunctionalꢀinstructions,ꢀaꢀrangeꢀofꢀotherꢀinstructionsꢀalsoꢀexistꢀsuchꢀasꢀ
theꢀ“HALT”ꢀinstructionꢀforꢀPower-downꢀoperationsꢀandꢀinstructionsꢀtoꢀcontrolꢀtheꢀoperationꢀofꢀ
theꢀWatchdogꢀTimerꢀforꢀreliableꢀprogramꢀoperationsꢀunderꢀextremeꢀelectricꢀorꢀelectromagneticꢀ
environments.ꢀForꢀtheirꢀrelevantꢀoperations,ꢀreferꢀtoꢀtheꢀfunctionalꢀrelatedꢀsections.
Rev. 1.40
ꢁꢁ6
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Instruction Set Summary
Theꢀfollowingꢀtableꢀdepictsꢀaꢀsummaryꢀofꢀtheꢀinstructionꢀsetꢀcategorisedꢀaccordingꢀtoꢀfunctionꢀandꢀ
canꢀbeꢀconsultedꢀasꢀaꢀbasicꢀinstructionꢀreferenceꢀusingꢀtheꢀfollowingꢀlistedꢀconventions.ꢀ
Table Conventions
x:ꢀBitsꢀimmediateꢀdataꢀ
m:ꢀDataꢀMemoryꢀaddressꢀ
A:ꢀAccumulatorꢀ
i:ꢀ0~7ꢀnumberꢀofꢀbitsꢀ
addr:ꢀProgramꢀmemoryꢀaddress
Mnemonic
Description
Cycles Flag Affected
Arithmetic
ADD Aꢂ[m]
ADD� Aꢂ[m]
ADD Aꢂx
Add Data �emorꢀ to ACC
Add ACC to Data �emorꢀ
Add immediate data to ACC
1
1Note
1
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
Zꢂ Cꢂ ACꢂ OV
C
ADC Aꢂ[m]
ADC� Aꢂ[m]
SUB Aꢂx
Add Data �emorꢀ to ACC with Carrꢀ
1
1Note
Add ACC to Data memorꢀ with Carrꢀ
Subtract immediate data from the ACC
1
SUB Aꢂ[m]
SUB� Aꢂ[m]
SBC Aꢂ[m]
SBC� Aꢂ[m]
DAA [m]
Subtract Data �emorꢀ from ACC
1
1Note
Subtract Data �emorꢀ from ACC with result in Data �emorꢀ
Subtract Data �emorꢀ from ACC with Carrꢀ
Subtract Data �emorꢀ from ACC with Carrꢀꢂ result in Data �emorꢀ
Decimal adjust ACC for Addition with result in Data �emorꢀ
1
1Note
1Note
Logic Operation
AND Aꢂ[m]
OR Aꢂ[m]
Logical AND Data �emorꢀ to ACC
Logical OR Data �emorꢀ to ACC
Logical XOR Data �emorꢀ to ACC
Logical AND ACC to Data �emorꢀ
Logical OR ACC to Data �emorꢀ
Logical XOR ACC to Data �emorꢀ
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data �emorꢀ
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
XOR Aꢂ[m]
AND� Aꢂ[m]
OR� Aꢂ[m]
XOR� Aꢂ[m]
AND Aꢂx
1
1Note
1Note
1Note
1
OR Aꢂx
1
XOR Aꢂx
1
1Note
CPL [m]
CPLA [m]
Complement Data �emorꢀ with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
Increment Data �emorꢀ with result in ACC
1
Z
Z
Z
Z
Increment Data �emorꢀ
1Note
Decrement Data �emorꢀ with result in ACC
Decrement Data �emorꢀ
1
1Note
RRA [m]
RR [m]
Rotate Data �emorꢀ right with result in ACC
Rotate Data �emorꢀ right
1
1Note
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data �emorꢀ right through Carrꢀ with result in ACC
Rotate Data �emorꢀ right through Carrꢀ
Rotate Data �emorꢀ left with result in ACC
Rotate Data �emorꢀ left
1Note
C
1
None
None
C
1Note
1
RLCA [m]
RLC [m]
Rotate Data �emorꢀ left through Carrꢀ with result in ACC
Rotate Data �emorꢀ left through Carrꢀ
1Note
C
Rev. 1.40
ꢁꢁꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Mnemonic
Data Move
Description
Cycles Flag Affected
�OV Aꢂ[m]
�OV [m]ꢂA
�OV Aꢂx
Bit Operation
CLR [m].i
SET [m].i
Branch
�ove Data �emorꢀ to ACC
�ove ACC to Data �emorꢀ
1
1Note
1
None
None
None
�ove immediate data to ACC
Clear bit of Data �emorꢀ
Set bit of Data �emorꢀ
1Note
1Note
None
None
J�P addr
SZ [m]
Jump unconditionallꢀ
ꢁ
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data �emorꢀ is zero
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
ꢁ
SZA [m]
Skip if Data �emorꢀ is zero with data movement to ACC
Skip if bit i of Data �emorꢀ is zero
Skip if bit i of Data �emorꢀ is not zero
Skip if increment Data �emorꢀ is zero
Skip if decrement Data �emorꢀ is zero
Skip if increment Data �emorꢀ is zero with result in ACC
Skip if decrement Data �emorꢀ is zero with result in ACC
Subroutine call
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
ꢁ
RET Aꢂx
Return from subroutine and load immediate data to ACC
Return from interrupt
ꢁ
RETI
ꢁ
Table Read
TABRD [m]
TABRDL [m]
Miscellaneous
NOP
Read table to TBLH and Data �emorꢀ
ꢁNote
ꢁNote
None
None
Read table (last page) to TBLH and Data �emorꢀ
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data �emorꢀ
SET [m]
Set Data �emorꢀ
None
CLR WDT
CLR WDT1
CLR WDTꢁ
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TOꢂ PDF
TOꢂ PDF
TOꢂ PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data �emorꢀ
Swap nibbles of Data �emorꢀ with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TOꢂ PDF
Note:ꢀ1.ꢀForꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀtwoꢀcyclesꢀareꢀrequired,ꢀifꢀnoꢀ
skipꢀtakesꢀplaceꢀonlyꢀoneꢀcycleꢀisꢀrequired.
2.ꢀAnyꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀalsoꢀrequireꢀ2ꢀcyclesꢀforꢀexecution.
3.ꢀForꢀtheꢀ“CLRꢀWDT1”ꢀandꢀ“CLRꢀWDT2”ꢀinstructionsꢀtheꢀTOꢀandꢀPDFꢀflagsꢀmayꢀbeꢀaffectedꢀbyꢀtheꢀ
executionꢀstatus.ꢀTheꢀTOꢀandꢀPDFꢀflagsꢀareꢀclearedꢀafterꢀbothꢀ“CLRꢀWDT1”ꢀandꢀ“CLRꢀWDT2”ꢀ
instructionsꢀareꢀconsecutivelyꢀexecuted.ꢀOtherwiseꢀtheꢀTOꢀandꢀPDFꢀflagsꢀremainꢀunchanged.
Rev. 1.40
ꢁꢁ8
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Instruction Definition
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry
ADC A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry
ADCM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACC
ADD A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
AddꢀimmediateꢀdataꢀtoꢀACC
ADD A,x
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀx
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemory
ADDM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC
AND A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀANDꢀimmediateꢀdataꢀtoꢀACC
AND A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitꢀwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory
ANDM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁꢁ9
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
Subroutineꢀcall
CALL addr
Descriptionꢀ
Unconditionallyꢀcallsꢀaꢀsubroutineꢀatꢀtheꢀspecifiedꢀaddress.ꢀTheꢀProgramꢀCounterꢀthenꢀ
incrementsꢀbyꢀ1ꢀtoꢀobtainꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀwhichꢀisꢀthenꢀpushedꢀontoꢀtheꢀ
stack.ꢀTheꢀspecifiedꢀaddressꢀisꢀthenꢀloadedꢀandꢀtheꢀprogramꢀcontinuesꢀexecutionꢀfromꢀthisꢀ
newꢀaddress.ꢀAsꢀthisꢀinstructionꢀrequiresꢀanꢀadditionalꢀoperation,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
Stackꢀ←ꢀProgramꢀCounterꢀ+ꢀ1ꢀ
ProgramꢀCounterꢀ←ꢀaddr
Affectedꢀflag(s)ꢀ
None
ꢀ
ClearꢀDataꢀMemory
CLR [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m]ꢀ←ꢀ00H
None
Affectedꢀflag(s)ꢀ
ClearꢀbitꢀofꢀDataꢀMemory
CLR [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m].iꢀ←ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
ClearꢀWatchdogꢀTimer
CLR WDT
Descriptionꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀ
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
Pre-clearꢀWatchdogꢀTimer
CLR WDT1
Descriptionꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀ
conjunctionꢀwithꢀCLRꢀWDT2ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT2ꢀtoꢀhaveꢀ
effect.ꢀRepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT2ꢀwillꢀ
haveꢀnoꢀeffect.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0ꢀ
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
Pre-clearꢀWatchdogꢀTimer
CLR WDT2
Descriptionꢀ
ꢀ
ꢀꢀ
ꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀconjunctionꢀ
withꢀCLRꢀWDT1ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT1ꢀtoꢀhaveꢀeffect.ꢀ
RepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT1ꢀwillꢀhaveꢀnoꢀ
effect.
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ComplementꢀDataꢀMemory
CPL [m]
Descriptionꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.
Operationꢀ
[m]ꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ30
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
CPLA [m]
Descriptionꢀ
ꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ
theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory
DAA [m]
Descriptionꢀ
ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ
resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ
orꢀifꢀACꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ
remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ
willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ
00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀflagꢀconditions.ꢀOnlyꢀtheꢀCꢀflagꢀ
mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ
100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ66H
ꢀ
ꢀ
ꢀ
Affectedꢀflag(s)ꢀ
C
ꢀ
DecrementꢀDataꢀMemory
DEC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
DECAꢀ[m]ꢀ
DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ
Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
Enterꢀpowerꢀdownꢀmode
HALT
Descriptionꢀ
ꢀ
ꢀ
Thisꢀinstructionꢀstopsꢀtheꢀprogramꢀexecutionꢀandꢀturnsꢀoffꢀtheꢀsystemꢀclock.ꢀTheꢀcontentsꢀofꢀꢀ
theꢀDataꢀMemoryꢀandꢀregistersꢀareꢀretained.ꢀTheꢀWDTꢀandꢀprescalerꢀareꢀcleared.ꢀTheꢀpowerꢀ
downꢀflagꢀPDFꢀisꢀsetꢀandꢀtheꢀWDTꢀtime-outꢀflagꢀTOꢀisꢀcleared.
Operationꢀ
ꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
IncrementꢀDataꢀMemoryꢀ
INC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
INCA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ
TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ31
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Jumpꢀunconditionally
JMP addr
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀreplacedꢀwithꢀtheꢀspecifiedꢀaddress.ꢀProgramꢀ
executionꢀthenꢀcontinuesꢀfromꢀthisꢀnewꢀaddress.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnewꢀaddressꢀisꢀloaded,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
Operationꢀ
ProgramꢀCounterꢀ←ꢀaddr
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀDataꢀMemoryꢀtoꢀACC
MOV A,[m]
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.
ACCꢀ←ꢀ[m]
None
Affectedꢀflag(s)ꢀ
MoveꢀimmediateꢀdataꢀtoꢀACC
MOV A,x
Descriptionꢀ
Operationꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀisꢀloadedꢀintoꢀtheꢀAccumulator.
ACCꢀ←ꢀx
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀACCꢀtoꢀDataꢀMemoryꢀ
MOV [m],A
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspecifiedꢀDataꢀMemory.
[m]ꢀ←ꢀACC
None
Affectedꢀflag(s)ꢀ
ꢀ
Noꢀoperation
NOP
Descriptionꢀ
Operationꢀ
Noꢀoperationꢀisꢀperformed.ꢀExecutionꢀcontinuesꢀwithꢀtheꢀnextꢀinstruction.
Noꢀoperation
None
Affectedꢀflag(s)ꢀ
LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC
OR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ
logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀimmediateꢀdataꢀtoꢀACC
OR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀACCꢀtoꢀDataꢀMemory
ORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
Returnꢀfromꢀsubroutine
RET
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstack.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀ
address.
Operationꢀ
ProgramꢀCounterꢀ←ꢀStack
None
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ3ꢁ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
ReturnꢀfromꢀsubroutineꢀandꢀloadꢀimmediateꢀdataꢀtoꢀACC
RET A,x
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀAccumulatorꢀloadedꢀwithꢀtheꢀspecifiedꢀ
immediateꢀdata.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀaddress.
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
ACCꢀ←ꢀx
Affectedꢀflag(s)ꢀ
None
ꢀ
Returnꢀfromꢀinterrupt
RETI
Descriptionꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀinterruptsꢀareꢀre-enabledꢀbyꢀsettingꢀtheꢀ
EMIꢀbit.ꢀEMIꢀisꢀtheꢀmasterꢀinterruptꢀglobalꢀenableꢀbit.ꢀIfꢀanꢀinterruptꢀwasꢀpendingꢀwhenꢀtheꢀꢀ
RETIꢀinstructionꢀisꢀexecuted,ꢀtheꢀpendingꢀInterruptꢀroutineꢀwillꢀbeꢀprocessedꢀbeforeꢀreturningꢀꢀ
toꢀtheꢀmainꢀprogram.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
EMIꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
None
ꢀ
RotateꢀDataꢀMemoryꢀleft
RL [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC
RLA [m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ
TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ
unchanged.
Operationꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry
RLC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RLCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ
Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
RotateꢀDataꢀMemoryꢀright
RR [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
Rev. 1.40
ꢁ33
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC
RRA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ
rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ
DataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry
RRC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RRCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ
theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry
SBC A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀꢀC
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory
SBCM A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0
SDZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
Rev. 1.40
ꢁ34
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SDZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ
theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SetꢀDataꢀMemory
SET [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m]ꢀ←ꢀFFH
None
Affectedꢀflag(s)ꢀ
SetꢀbitꢀofꢀDataꢀMemory
SET [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m].iꢀ←ꢀ1
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0
SIZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
Skipꢀifꢀ[m]=0ꢀ
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SIZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ
0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀnotꢀ0
SNZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].iꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACC
SUB A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ35
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory
SUBM A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
SubtractꢀimmediateꢀdataꢀfromꢀACC
SUB A,x
Descriptionꢀ
ꢀ
ꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀbyꢀtheꢀcodeꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀꢀ
flagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀx
OV,ꢀZ,ꢀAC,ꢀC
Affectedꢀflag(s)ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemory
SWAP [m]
Descriptionꢀ
Operationꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.
[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4
None
Affectedꢀflag(s)ꢀ
ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
SWAPA [m]
Descriptionꢀ
ꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ
resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ
ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀ0
SZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]=0
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC
SZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ
theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ
whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ
programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0
SZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ
theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].i=0
None
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ36
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
ꢀ
Readꢀtableꢀ(currentꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRD [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(currentꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀꢀ
movedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRDL [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ
toꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
ꢀ
LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC
XOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory
XORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀXORꢀimmediateꢀdataꢀtoꢀACC
XOR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀx
Z
Affectedꢀflag(s)ꢀ
Rev. 1.40
ꢁ3ꢃ
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Package Information
Noteꢀthatꢀtheꢀpackageꢀinformationꢀprovidedꢀhereꢀisꢀforꢀconsultationꢀpurposesꢀonly.ꢀAsꢀthisꢀ
informationꢀmayꢀbeꢀupdatedꢀatꢀregularꢀintervalsꢀusersꢀareꢀremindedꢀtoꢀconsultꢀtheꢀHoltekꢀwebsiteꢀforꢀ
theꢀlatestꢀversionꢀofꢀtheꢀPackage/CartonꢀInformation.
Additionalꢀsupplementaryꢀinformationꢀwithꢀregardꢀtoꢀpackagingꢀisꢀlistedꢀbelow.ꢀClickꢀonꢀtheꢀrelevantꢀ
sectionꢀtoꢀbeꢀtransferredꢀtoꢀtheꢀrelevantꢀwebsiteꢀpage.
•ꢀ FurtherꢀPackageꢀInformationꢀ(includeꢀOutlineꢀDimensions,ꢀProductꢀTapeꢀandꢀReelꢀSpecifications)
•ꢀ PackingꢀMeterialsꢀInformation
•ꢀ Cartonꢀinformation
Rev. 1.40
ꢁ38
�aꢀ ꢁ4ꢂ ꢁ01ꢃ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions
D
D
2
2
5
3
2
2
4
1
b
E
E
2
e
1
7
8
1
6
9
A
1
A
3
L
K
A
Dimensions in inch
Symbol
Min.
0.0�8
0.000
—
Nom.
0.030
Max.
A
A1
A3
b
0.031
0.00�
—
0.001
0.008 BSC
0.010
0.00ꢀ
0.193
0.193
—
0.01�
0.�01
0.�01
—
D
0.19ꢀ
E
0.19ꢀ
e
0.0�0 BSC
0.1�6
D�
E�
L
0.1��
0.1��
0.014
0.008
0.130
0.130
0.018
—
0.1�6
0.016
K
—
Dimensions in mm
Symbol
Min.
0.ꢀ00
0.000
—
Nom.
0.ꢀ50
0.0�0
0.�03 BSC
0.�50
5.000
5.000
0.50 BSC
3.�0
Max.
0.800
0.050
—
A
A1
A3
b
0.180
4.900
4.900
—
0.300
5.100
5.100
—
D
E
e
D�
E�
L
3.10
3.10
0.35
0.�0
3.30
3.30
0.45
—
3.�0
0.40
K
—
Rev. 1.40
�39
�aꢀ �4ꢂ �01ꢀ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SAW Type 40-pin (6mm×6mm for 0.75mm) QFN Outline Dimensions
D
D
2
3
1
4
0
3
0
1
b
E
E
e
2
1
1
0
2
0
1
1
A
1
L
K
A
3
A
Dimensions in inch
Nom.
Symbol
Min.
0.0�8
0.000
—
Max.
0.031
0.00�
—
A
A1
A3
b
0.030
0.001
0.008 BSC
0.010
0.00ꢀ
0.�3�
0.�3�
—
0.01�
0.�40
0.�40
—
D
0.�36
E
0.�36
e
0.0�0 BSC
0.1ꢀꢀ
D�
E�
L
0.1ꢀ3
0.1ꢀ3
0.014
0.008
0.181
0.181
0.018
—
0.1ꢀꢀ
0.016
K
—
Dimensions in mm
Nom.
Symbol
Min.
0.ꢀ00
0.000
—
Max.
0.800
0.050
—
A
A1
A3
b
0.ꢀ50
0.0�0
0.�03 BSC
0.�50
0.180
5.900
5.900
—
0.300
6.100
6.100
—
D
6.000
E
6.000
e
0.50 BSC
4.50
D�
E�
L
4.40
4.40
0.35
0.�0
4.60
4.60
0.45
—
4.50
0.40
K
—
Rev. 1.40
�40
ꢁ aꢂ �4ꢃ �01ꢀ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
SAW Type 46-pin (6.5mm×4.5mm) QFN Outline Dimensions
e
b
D
1
0
2
3
L
9
2
4
E
E
2
3
2
1
4
6
3
3
A
A
1
D
2
3
A
Dimensions in inch
Nom.
Symbol
Min.
0.031
0.000
—
Max.
A
A1
A3
b
0.033
0.035
0.001
0.00�
—
0.008 BSC
0.008
0.006
0.�54
0.1ꢀ5
—
0.010
0.�58
0.1ꢀ9
—
D
0.�56
E
0.1ꢀꢀ
e
0.016 BSC
0.�01
D�
E�
L
0.19ꢀ
0.118
0.01�
0.�05
0.1�6
0.0�0
0.1��
0.016
Dimensions in mm
Nom.
Symbol
Min.
0.800
0.000
—
Max.
0.900
0.040
—
A
A1
A3
b
0.850
0.0�0
0.�00 BSC
0.�00
0.150
6.450
4.450
—
0.�50
6.550
4.550
—
D
6.500
E
4.500
e
0.40 BSC
5.10
D�
E�
L
5.00
3.00
0.30
5.�0
3.�0
0.50
3.10
0.40
Rev. 1.40
�41
ꢁ aꢂ �4ꢃ �01ꢀ
BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Copꢂ right© �01ꢀ bꢂ HOLTEK SEꢁ ICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. Howeverꢃ Holtek assumes no responsibilitꢂ arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warrantꢂ or representation that
such applications will be suitable without further modificationꢃ nor recommends
the use of its products for application that maꢂ present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or sꢂ stems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.
Rev. 1.40
�4�
ꢁ aꢂ �4ꢃ �01ꢀ
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