HM62V16258CLTT-5 [HITACHI]
Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44;
| 型号： | HM62V16258CLTT-5 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V16258C Series
4 M SRAM (256-kword × 16-bit)
ADE-203-1100A (Z)
Preliminary
Rev. 0.1
Oct. 21, 1999
Description
The Hitachi HM62V16258C Series is 4-Mbit static RAM organized 262,144-word × 16-bit. HM62V16258C
Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS
process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in standard 44-pin plastic TSOPII.
Features
•
•
•
Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
Fast access time: 55 ns (max)
Power dissipation:
Active: TBD (typ)
Standby: 2.4 µW (typ)
•
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
•
•
•
Battery backup operation.
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
HM62V16258C Series
Ordering Information
Type No.
Access time
55 ns
Package
HM62V16258CLTT-5
400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB)
HM62V16258CLTT-5SL 55 ns
2
HM62V16258C Series
Pin Arrangement
44-pin TSOP
44
1
A5
A4
A3
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A6
3
A7
A2
4
OE
UB
LB
A1
5
A0
6
CS
7
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
A12
(Top view)
Pin Description
Pin name
Function
A0 to A17
Address input
I/O0 to I/O15
Data input/output
Chip select
CS
WE
OE
LB
Write enable
Output enable
Lower byte select
Upper byte select
Power supply
Ground
UB
VCC
VSS
NC
No connection
3
HM62V16258C Series
Block Diagram
TBD
4
HM62V16258C Series
Operation Table
CS
H
×
WE
×
OE
×
UB
×
LB
×
I/O0 to I/O7
High-Z
High-Z
Dout
I/O8 to I/O15
High-Z
High-Z
Dout
Operation
Standby
×
×
H
L
H
L
Standby
L
H
H
H
L
L
Read
L
L
H
L
L
Dout
High-Z
Dout
Lower byte read
Upper byte read
Write
L
L
H
L
High-Z
Din
L
×
L
Din
L
L
×
H
L
L
Din
High-Z
Din
Lower byte write
Upper byte write
Output disable
L
L
×
H
×
High-Z
High-Z
L
H
H
×
High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
VCC
VT
–0.5 to + 4.6
–0.5*1 to VCC + 0.3*2
V
V
PT
1.0
W
°C
°C
Storage temperature range
Storage temperature range under bias
Tstg
Tbias
–55 to +125
–20 to +85
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter
Symbol Min
Typ
Max
3.6
Unit
V
Note
Supply voltage
VCC
VSS
2.2
0
2.5/3.0
0
0
V
Input high voltage
Input low voltage
VCC = 2.2 V to 2.7 V VIH
VCC = 2.7 V to 3.6 V VIH
VCC = 2.2 V to 2.7 V VIL
VCC = 2.7 V to 3.6 V VIL
2.0
2.0
–0.2
–0.3
–20
—
VCC + 0.3
VCC + 0.3
0.4
V
—
V
—
V
1
1
—
0.6
V
Ambient temperature range
Ta
—
70
°C
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
5
HM62V16258C Series
DC Characteristics
Parameter
Symbol Min
Typ*1 Max
Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
1
1
µA
µA
Vin = VSS to VCC
|ILO|
CS = VIH or OE = VIH or
WE = VIL or, LB = UB =VIH, VI/O
VSS to VCC
=
Operating current
ICC
—
—
—
—
20
35
mA
mA
CS = VIL, Others = VIH/VIL, II/O = 0
mA
Average operating current
ICC1
Min. cycle, duty = 100%,
II/O = 0 mA, CS = VIL, Others =
VIH/VIL
ICC2
—
—
5
mA
Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS ≤ 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby current
Standby current
ISB
—
—
0.1
0.8
0.3
30
mA
CS = VIH
2
3
ISB1
*
µA
0 V ≤ Vin
CS ≥ VCC – 0.2 V
ISB1
*
—
0.8
—
5
µA
Output high VCC =2.2 V to 2.7 V VOH
voltage
2.0
—
V
IOH = –0.5 mA
VCC =2.7 V to 3.6 V VOH
VCC =2.2 V to 3.6 V VOH
2.4
—
—
V
V
V
IOH = –1 mA
IOH = –100 µA
IOL = 0.5 mA
VCC – 0.2—
—
Output low
voltage
VCC =2.2 V to 2.7 V VOL
—
—
0.4
VCC =2.7 V to 3.6 V VOL
VCC =2.2 V to 3.6 V VOL
—
—
—
—
0.4
0.2
V
V
IOL = 2 mA
IOL = 100 µA
Notes: 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L version.
3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
8
Unit
pF
Test conditions Note
Input capacitance
Input/output capacitance
Vin = 0 V
VI/O = 0 V
1
1
CI/O
—
—
10
pF
Note: 1. This parameter is sampled and not 100% tested.
6
HM62V16258C Series
AC Characteristics (Ta = –20 to +70°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
Input pulse levels: VIL = 0.4 V, VIH = 2.0 V (VCC = 2.2 V to 2.7 V)
VIL = 0.4 V, VIH = 2.2 V (VCC = 2.7 V to 3.6 V)
•
•
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
Output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
Input timing reference levels: 1.4 V (VCC = 2.7 V to 3.6 V)
Output timing reference levels: 2.0 V/0.8 V (VCC = 2.7 V to 3.6 V)
Output load: See figures (Including scope and jig)
VTM
1.4 V
R1
RL=500 Ω
Dout
Dout
R1 = 3070 Ω
30pF
R2
R2 = 3150 Ω
50pF
VTM = 2.3 V
Output load (A)
(VCC = 2.2 V to 2.7 V)
Output load (B)
(VCC = 2.7 V to 3.6 V)
7
HM62V16258C Series
Read Cycle
HM62V16258C
-5
Parameter
Symbol
tRC
Min
55
—
—
—
10
—
10
5
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
55
55
30
—
Chip select access time
Output enable to output valid
Output hold from address change
LB, UB access time
tACS
tOE
tOH
tBA
55
—
Chip select to output in low-Z
LB, UB enable to low-z
Output enable to output in low-Z
Chip deselect to output in high-Z
LB, UB disable to high-Z
Output disable to output in high-Z
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
2, 3
—
2, 3
5
—
2, 3
0
20
20
20
1, 2, 3
1, 2, 3
1, 2, 3
0
0
8
HM62V16258C Series
Write Cycle
HM62V16258C
-5
Min
55
50
50
40
50
0
Parameter
Symbol
tWC
Max
—
—
—
—
—
—
—
—
—
—
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip selection to end of write
Write pulse width
tAW
tCW
5
4
tWP
LB, UB valid to end of write
Address setup time
tBW
tAS
6
7
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in High-Z
Write to output in high-Z
tDW
25
0
tDH
tOW
5
2
tOHZ
tWHZ
0
1, 2
1, 2
0
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS, a low WE and a low LB or a low UB. A write begins
at the latest transition among CS going low, WE going low and LB going low or UB going low. A
write ends at the earliest transition among CS going high, WE going high and LB going high or UB
going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS going low to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS or WE going high to the end of write cycle.
9
HM62V16258C Series
Timing Waveform
Read Cycle
tRC
Address
Valid address
tAA
tACS
CS
2, 3
1, 2, 3
1, 2, 3
tCLZ
*
tCHZ
*
tBHZ
*
tBA
LB, UB
2, 3
tBLZ
*
1, 2, 3
tOHZ
*
tOE
OE
2, 3
tOLZ
*
tOH
High impedance
Dout
Valid data
10
HM62V16258C Series
Write Cycle (1) (WE Clock)
tWC
Valid address
Address
7
tWR
*
5
tCW
*
CS
tBW
LB, UB
tAW
4
tWP
*
6
WE
tAS*
tDW
Valid data
tDH
Din
1, 2
tWHZ
*
2
tOW
*
High impedance
Dout
11
HM62V16258C Series
Write Cycle (2) (CS Clock, OE = V )
IH
tWC
Valid address
tAW
Address
6
7
5
tAS
*
tWR*
tCW
*
CS
tBW
LB, UB
4
tWP
*
WE
tDW
Valid data
tDH
Din
High impedance
Dout
12
HM62V16258C Series
Write Cycle (3) (LB, UB Clock, OE = VIH)
tWC
Valid address
tAW
Address
5
7
tCW
*
tWR
*
CS
6
tBW
tAS
*
LB, UB
4
tWP
*
WE
tDW
Valid data
tDH
Din
High impedance
Dout
13
HM62V16258C Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ*4
Max
Unit
Test conditions*3
VCC for data retention
VDR
2.0
—
3.6
V
Vin ≥ 0V
(1) CS ≥ VCC – 0.2 V or
(2) LB = UB ≥ VCC – 0.2 V
CS ≤ 0.2 V
*1
Data retention current
ICCDR
—
0.8
20
µA
VCC = 3.0 V, Vin ≥ 0V
(1) CS ≥ VCC – 0.2 V or
(2) LB = UB ≥ VCC – 0.2 V
CS ≤ 0.2 V
*2
ICCDR
—
0
0.8
—
2
µA
Chip deselect to data
retention time
tCDR
—
ns
See retention waveform
*5
Operation recovery time
tR
tRC
—
—
ns
Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = 0 to +40°C.
2. This characteristic is guaranteed only for L-SL version, 2 µA max. at Ta = 0 to +40°C.
3. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data
retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If
LB, UB controls data retention mode, LB, UB must be LB = UB ≥ VCC – 0.2 V, CS must be CS ≤ 0.2
V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.
5. tRC = read cycle time.
14
HM62V16258C Series
Low VCC Data Retention Timing Waveform (1) (CS Controlled)
Data retention mode
tCDR
tR
VCC
2.2 V
VDR
2.0 V
CS
0 V
≥
CS VCC – 0.2 V
Low VCC Data Retention Timing Waveform (2) (LB, UB Controlled)
Data retention mode
tCDR
tR
VCC
2.2 V
VDR
2.0 V
LB, UB
0 V
≥
LB, UB VCC – 0.2 V
15
HM62V16258C Series
Package Dimensions
HM62V16258CLTT Series (TTP-44DB)
Unit: mm
18.41
18.81 Max
44
23
22
1
0.80
0.13
0.80
0.30 ± 0.10
0.25 ± 0.05
M
11.76 ± 0.20
1.005 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TTP-44DB
JEDEC
EIAJ
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.43 g
16
HM62V16258C Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
17
HM62V16258C Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
0.1
Aug. 10, 1999
Oct. 21, 1999
Initial issue
Y. Saitoh
K. Imato
Low VCC Data Retention Characteristics
Change of Timing Waveform(1) and (2)
18
相关型号：
HM62V16258CLTT-5SL
Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
HITACHI
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