HM628128ALP-5 [HITACHI]
131,072-word X 8-bit High Speed CMOS Static RAM; 131,072字×8位高速CMOS静态RAM
| 型号： | HM628128ALP-5 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 131,072-word X 8-bit High Speed CMOS Static RAM |
| 文件： | 总13页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADE-XXX-XXX
HM628128A Series
131,072-word × 8-bit High Speed CMOS Static RAM
Rev. X
January 1995
The Hitachi HM628128A is a CMOS static RAM
organized 128 kword × 8 bit. It realizes higher
density, higher performance and low power
consumption by employing 0.8 µm Hi-CMOS
process technology.
Features
• High speed
— Fast access time: 55/70/85/100 ns (max)
• Low power
— Active: 75 mW (typ)
It offers low power standby power dissipation;
therefore, it is suitable for battery back-up systems.
The device, packaged in a 525-mil SOP (460-mil
body SOP) or a 600-mil plastic DIP, or a 8 × 20
mm TSOP with thickness of 1.2 mm, is available
for high density mounting. TSOP package is
suitable for cards, and reverse type TSOP is also
provided.
— Standby: 10 µW (typ)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
2 chip selection for battery back up
HM628128A Series
Ordering Information
Access
time
Access
time
Type No.
Package
Type No.
Package
HM628128ALP–5
HM628128ALP–7
HM628128ALP–8
HM628128ALP–10
55 ns
70 ns
85 ns
100 ns
600-mil 32-pin
plastic DIP
(DP-32)
HM628128ALT–5
HM628128ALT–7
HM628128ALT–8
HM628128ALT–10
55 ns
70 ns
85 ns
100 ns
8 mm × 20 mm
32-pin TSOP
(normal type)
(TFP-32D)
HM628128ALP–5L
HM628128ALP–7L
HM628128ALP–8L
55 ns
70 ns
85 ns
HM628128ALT–5L
HM628128ALT–7L
HM628128ALT–8L
HM628128ALT–10L
55 ns
70 ns
85 ns
100 ns
HM628128ALP–10L 100 ns
HM628128ALP–5SL 55 ns
HM628128ALP–7SL 70 ns
HM628128ALP–8SL 85 ns
HM628128ALP–10SL 100 ns
HM628128ALT-5SL
HM628128ALT-7SL
HM628128ALT-8SL
55 ns
70 ns
85 ns
HM628128ALT-10SL 100 ns
HM628128ALFP–5
HM628128ALFP–7
HM628128ALFP–8
55 ns
70 ns
85 ns
525-mil 32-pin
plastic SOP
(FP-32D)
HM628128ALR–5
HM628128ALR–7
HM628128ALR–8
HM628128ALR–10
55 ns
70 ns
85 ns
100 ns
8 mm × 20 mm
32-pin TSOP
(reverse type)
(TFP-32DR)
HM628128ALFP–10 100 ns
HM628128ALFP–5L 55 ns
HM628128ALFP–7L 70 ns
HM628128ALFP–8L 85 ns
HM628128ALFP–10L 100 ns
HM628128ALR–5L
HM628128ALR–7L
HM628128ALR–8L
55 ns
70 ns
85 ns
HM628128ALR–10L 100 ns
HM628128ALFP–5SL 55 ns
HM628128ALFP–7SL 70 ns
HM628128ALFP–8SL 85 ns
HM628128ALFP–10SL100 ns
HM628128ALR-5SL 55 ns
HM628128ALR-7SL 70 ns
HM628128ALR-8SL 85 ns
HM628128ALR-10SL 100 ns
2
HM628128A Series
Pin Arrangement
HM628128ALP/ALFP Series
HM628128ALT Series
A4
A5
16
15
14
13
12
11
10
9
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CS2
WE
A13
A8
NC
A2
A6
A1
A0
2
A16
A7
3
A14
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
A10
OE
4
A12
5
A7
8
6
A6
7
7
A9
A5
6
5
8
A11
OE
A4
4
9
A3
3
A9
A11
2
10
A2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
1
11
A1
(Top View)
12
A0
13
I/O0
14
HM628128ALR Series
I/O1
15
I/O2
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
16
VSS
2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
3
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
4
(Top View)
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
(Top View)
Pin Description
Pin name
A0 – A16
I/O0 – I/O7
CS1
Function
Pin name
OE
Function
Address
Output enable
No connection
Power supply
Ground
Input/output
Chip select 1
Chip select 2
Write enable
NC
VCC
CS2
VSS
WE
3
HM628128A Series
Block Diagram
(MSB)
A13
V CC
V SS
A15
A6
•
•
•
•
•
A7
A12
A14
A16
A5
Memory Matrix
512 x 2,048
Row
Decoder
A4
(LSB)
I/O0
I/O7
•
•
•
•
Column I/O
Input
Data
Control
Column Decoder
(LSB)
(MSB)
A2 A3
A1
A8 A9 A11
A0
A10
•
•
CS2
CS1
Timing Pulse Generator
Read/Write Control
WE
OE
Function Table
CS1
H
X
CS2
X
OE
X
WE
X
Mode
VCC current
ISB, ISB1
I/O pin
High-Z
High-Z
High-Z
Dout
Ref. cycle
—
Standby
Standby
L
X
X
ISB, ISB1
—
L
H
H
L
H
H
L
Output disable ICC
—
L
H
Read
Write
Write
ICC
ICC
ICC
Read cycle
Write cycle (1)
Write cycle (2)
L
H
H
L
Din
L
H
L
Din
Note: X: H or L
4
HM628128A Series
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Supply voltage relative to VSS
–0.5 to +7.0
V
*1
Voltage on any pin relative to VSS
VT
–0.5 *2 to VCC + 0.3*3
1.0
V
Power dissipation
PT
W
°C
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
Storage temperature under bias
Note: 1. With respect to VSS
2. –3.0 V for pulse half-width ≤ 30 ns
3. Maximum voltage is 7.0V.
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
VSS
VIH
Min
4.5
Typ
5.0
0
Max
Unit
V
Supply voltage
5.5
0
0
V
Input voltage
2.2
—
—
—
—
VCC + 0.3
0.8
V
(HM628128A-7/8/10)
Input voltage
VIL
–0.3 *1
2.4
V
VIH
VCC + 0.3
0.8
V
(HM628128A-5)
VIL
–0.3 *1
V
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
5
HM628128A Series
DC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)
CC
SS
Parameter
Symbol
Min
—
Typ*1 Max
Unit
µA
Test conditions
Input leakage current
|ILI|
—
—
1.0
1.0
Vin = VSS to VCC
Output leakage current |ILO
|
—
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL,
VI/O = VSS to VCC
Operating power supply ICC
current: DC
—
—
—
—
15
45
50
15
30
70
80
25
mA
mA
mA
mA
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
II/O = 0 mA
Operating power supply ICC1
Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
current
(HM628128
A-7/8/10)
II/O = 0 mA
ICC1
(HM628128
A-5)
ICC2
Cycle time = 1 µs, duty = 100%,
I/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V
IH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
I
V
Standby power supply
current: DC
ISB
—
—
—
1
2
2
2
mA
µA
µA
(1) CS1 = VIH, CS2 = VIH or
(2) CS2 = VIL
Standby power supply
current (1): DC
ISB1
(L version)
100
50
0 V ≤ Vin ≤ VCC ,
(1) CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V or
(2) 0 V ≤ CS2 ≤ 0.2 V
ISB1
(L-L/L-SL
version)
Output voltage
VOL
VOH
—
—
—
0.4
—
V
V
IOL = 2.1 mA
2.4
IOH = –1.0 mA
Note: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading.
*1
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
8
Unit
pF
Test conditions
Vin = 0 V
Input capacitance
Input/output capacitance
CI/O
—
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM628128A Series
AC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, unless otherwise noted.)
CC
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V (HM628128A-7/8/10)
0 V to 3 V (HM628128A-5)
• Input rise and fall times: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate and CL (100 pF) (HM628128A-7/8/10)
1 TTL Gate and CL (30 pF) (HM628128A-5) (Including scope & jig)
Read Cycle
HM628128A
-5
-7
-8
-10
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Read cycle time
Address access time
Chip selection to
output valid
tRC
55
—
—
—
—
—
55
55
55
30
70
—
—
—
—
—
70
70
70
35
85
—
—
—
—
—
85
85
85
45
100
—
—
ns
tAA
100 ns
100 ns
100 ns
tCO1
tCO2
tOE
—
—
Output enable to
output valid
—
50
ns
Chip selection to
output in low-Z
tLZ1
tLZ2
tOLZ
5
5
5
—
—
—
10
10
5
—
—
—
10
10
5
—
—
—
10
10
5
—
—
—
ns
ns
ns
2, 3
2, 3
2, 3
Output enable to
output in low-Z
Chip deselection to
output in high-Z
tHZ1
tHZ2
tOHZ
0
0
0
20
20
20
0
0
0
25
25
25
0
0
0
30
30
30
0
0
0
35
35
35
ns
ns
ns
1, 2, 3
1, 2, 3
1, 2, 3
Output disable to
output in high-Z
Output hold from
address change
tOH
5
—
10
—
10
—
10
—
ns
7
HM628128A Series
*4
Read Timing Waveform
t RC
Address
CS1
Address Valid
tAA
tCO1
t LZ1
tHZ1
CS2
OE
tCO2
tLZ2
tHZ2
t OE
tOHZ
OLZ
t
tOH
Data Valid
High Impedance
Dout
Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
3. This parameter is sampled and not 100% tested.
4. WE is high for read cycle.
8
HM628128A Series
Write Cycle
HM628128A
-5
-7
-8
-10
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write cycle time
tWC
tCW
55
50
—
—
70
60
—
—
85
75
—
—
100
80
—
—
ns
ns
Chip selection to
end of write
Address setup time
tAS
0
—
—
0
—
—
0
—
—
0
—
—
ns
ns
Address valid to
end of write
tAW
50
60
75
80
Write pulse width
tWP
40
0
—
—
20
50
0
—
—
25
55
0
—
—
30
60
0
—
—
35
ns
ns
ns
Write recovery time
tWR
tWHZ
Write to output in
high-Z
0
0
0
0
10
10
Data to write time
overlap
tDW
tDH
tOW
25
0
—
—
—
30
0
—
—
—
35
0
—
—
—
40
0
—
—
—
ns
ns
ns
Data hold from
write time
Output active from
end of write
5
5
5
5
9
HM628128A Series
Write Timing Waveform (1) (OE Clock)
tWC
Address Valid
tAW
Address
OE
*2
tCW
CS1
CS2
*4
*6
tWR
*1
tWP
*3
tAS
WE
*5
tOHZ
High Impedance
Dout
Din
tDW
tDH
Data Valid
10
HM628128A Series
Write Timing Waveform (2) (OE low Fixed)
tWC
Address
Address Valid
*4
*2
tCW
tWR
CS1
CS2
*6
tAW
*1 *11
tWP
tOH
*3
WE
tAS
*5
tOW
High Impedance
tDW tDH
tWHZ
*8
*7
Dout
Din
*9
Data Valid
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the
latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the
earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS1 goes low simultaneously with WE going low or after the WE going low, the outputs
remain in a high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of next address.
9. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of opposite phase to the outputs must not be applied to them.
10. This parameter is sampled and not 100% tested.
11. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
11
HM628128A Series
data bus contention.
tWP ≥ tDW min + tWHZ max
Low V Data Retention Characteristics (Ta = 0 to +70°C)
CC
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*4
VCC for data retention
VDR
2.0
—
—
V
CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V
Vin>0 V
Data retention current
ICCDR
(L version)
—
—
—
1
1
1
50*1
30*2
15*3
µA
µA
µA
VCC = 3.0 V, Vin ≥ 0 V
CS1 ≥ VCC – 0.2V
CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V
ICCDR
(L-L version)
ICCDR
(L-SL
version)
Chip deselect to
data retention time
tCDR
0
5
—
—
—
—
ns
See retention waveform
Operation recovery time tR
ms
Low V Data Retention Timing Waveform (1) (CS1 Controlled)
CC
Data retention mode
tCDR
tR
VCC
4.5 V
2.2 V
VDR1
CS1
0 V
>
CS1 VCC – 0.2 V
Low V Data Retention Timing Waveform (2) (CS2 Controlled)
CC
tCDR
Data retention mode
tR
VCC
4.5 V
CS2
VDR2
0.4 V
0 V
<
<
0 V CS2 0.2 V
12
HM628128A Series
Notes: 1. 20 µA max at Ta = 0 to 40˚C (L-version).
2. 6 µA max at Ta = 0 to 40˚C (L-L-version).
3. 3 µA max at Ta = 0 to 40˚C (L-SL-version).
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
13
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