HM62256ALSP-15SL [HITACHI]
32,768-word x 8-bit High Speed CMOS Static RAM; 32,768字×8位高速CMOS静态RAM
| 型号： | HM62256ALSP-15SL |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 32,768-word x 8-bit High Speed CMOS Static RAM |
| 文件： | 总11页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Maintenance only
HM62256A Series
32,768-word × 8-bit High Speed CMOS Static RAM
The Hitachi HM62256A is a CMOS static RAM
Ordering Information
organized 32-kword × 8-bit. It realizes higher
performance and low power consumption by
employing 0.8 µm Hi-CMOS process technology.
The device, packaged in a 8 × 14 mm TSOP with
thickness of 1.2 mm, 450-mil SOP (foot print pitch
width), 600-mil plastic DIP, or 300-mil plastic DIP,
is available for high density mounting. TSOP
package is suitable for cards, and reverse type
TSOP is also provided. It offers low power
standby power dissipation; therefore, it is suitable
for battery back up system.
Type No.
Access time Package
——————————————————————–
HM62256AP-8
HM62256AP-10
HM62256AP-12
HM62256AP-15
85 ns
600-mil
28-pin
plastic DIP
(DP-28)
100 ns
120 ns
150 ns
————————————————–
HM62256ALP-8
HM62256ALP-10
HM62256ALP-12
HM62256ALP-15
85 ns
100 ns
120 ns
150 ns
————————————————–
HM62256ALP-8SL
HM62256ALP-10SL
HM62256ALP-12SL
HM62256ALP-15SL
85 ns
Features
100 ns
120 ns
150 ns
• High speed: Fast Access time 85/100/120/150 ns
(max)
• Low Power
——————————————————————–
HM62256ASP-8
HM62256ASP-10
HM62256ASP-12
HM62256ASP-15
85 ns
300-mil
28-pin
plastic DIP
(DP-28NA)
Standby: 5 µW (typ) (L/L-SL version)
Operation: 40 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state
output
100 ns
120 ns
150 ns
————————————————–
HM62256ALSP-8
HM62256ALSP-10
HM62256ALSP-12
HM62256ALSP-15
————————————————–
HM62256ALSP-8SL 85 ns
HM62256ALSP-10SL 100 ns
HM62256ALSP-12SL 120 ns
HM62256ALSP-15SL 150 ns
85 ns
100 ns
120 ns
150 ns
• Directly TTL compatible: All inputs and outputs
• Capability of battery back up operation
——————————————————————–
HM62256AFP-8T
HM62256AFP-10T
HM62256AFP-12T
HM62256AFP-15T
85 ns
450-mil
28-pin
plastic SOP
(FP-28DA)
100 ns
120 ns
150 ns
————————————————–
HM62256ALFP-8T
HM62256ALFP-10T
HM62256ALFP-12T
HM62256ALFP-15T
85 ns
100 ns
120 ns
150 ns
————————————————–
HM62256ALFP-8SLT 85 ns
HM62256ALFP-10SLT 100 ns
HM62256ALFP-12SLT 120 ns
HM62256ALFP-15SLT 150 ns
——————————————————————–
Note: This device is not available for new application.
1
HM62256A Series
HM62256A Series
TSOP Series
Type No.
Access time Package
Type No.
Access time Package
——————————————————————–
——————————————————————–
HM62256ALT-8
HM62256ALT-10
HM62256ALT-12
HM62256ALT-15
85 ns
8 mm × 14 mm
32-pin TSOP
(normal type)
(TFP-32DA)
HM62256ALR-8
HM62256ALR-10
HM62256ALR-12
HM62256ALR-15
85 ns
8 mm × 14 mm
32-pin TSOP
(reverse type)
(TFP-32DAR)
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
———————————————–
HM62256ALT-8SL 85 ns
HM62256ALT-10SL 100 ns
HM62256ALT-12SL 120 ns
HM62256ALT-15SL 150 ns
———————————————–
HM62256ALR-8SL 85 ns
HM62256ALR-10SL 100 ns
HM62256ALR-12SL 120 ns
HM62256ALR-15SL 150 ns
——————————————————————–
——————————————————————–
Pin Arrangement
HM62256AP/AFP/ASP Series
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
2
3
A6
4
A5
5
A9
A4
6
A11
OE
A3
7
A2
8
A10
CS
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
V
SS
(Top view)
HM62256AR Series
HM62256AT Series
OE
A11
NC
A9
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CS
NC
A3
A4
NC
A5
A6
A7
A12
A14
VCC
WE
A13
A8
16
15
14
13
12
11
10
9
8
7
6
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A2
A1
NC
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
NC
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A8
A13
WE
VCC
A14
A12
A7
A6
A5
NC
A4
A3
9
10
11
12
13
14
15
16
A9
4
3
2
1
NC
A1
A2
NC
A11
OE
CS
A10
(Top view)
(Top view)
2
HM62256A Series
HM62256A Series
Pin Description
Symbol
Function
Symbol
Function
——————————————————————–
——————————————————————–
OE Output enable
——————————————————————–
NC No connection
——————————————————————–
Power supply
——————————————————————–
Ground
A0 – A14
——————————————————————–
I/O0 – I/O7 Input/output
——————————————————————–
CS Chip select
——————————————————————–
Write enable
Address
V
CC
WE
V
SS
——————————————————————–
——————————————————————–
Block Diagram
V CC
V SS
A5
A4
•
A3
•
•
•
•
•
•
•
•
•
Memory Matrix
A11
Row
Decoder
×
512 512
A9
A8
A12
A7
A6
I/O0
•
•
•
•
Column I/O
•
•
•
•
•
•
Input
Data
Control
Column Decoder
•
•
•
•
•
•
•
•
•
I/O7
A1 A2 A10 A13 A14
A0
•
•
Timing Pulse Generator
Read/Write Control
CS
WE
OE
3
HM62256A Series
HM62256A Series
Function Table
WE
———————————————————————————————————————————————–
Not selected , I High-Z
———————————————————————————————————————————————–
Output disable High-Z
———————————————————————————————————————————————–
Read Dout Read cycle (1)–(3)
———————————————————————————————————————————————–
Write Din Write cycle (1)
———————————————————————————————————————————————–
Write Din Write cycle (2)
CS
OE
Mode
V
current
I/O pin
Ref. cycle
CC
X
H
X
I
—
SB SB1
H
L
H
I
—
CC
H
L
L
I
CC
L
L
H
I
CC
L
L
L
I
CC
———————————————————————————————————————————————–
Note: X: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
———————————————————————————————————————————————–
*1
Voltage on any pin relative to V
V
–0.5 to +7.0
V
SS
T
———————————————————————————————————————————————–
Power dissipation 1.0
———————————————————————————————————————————————–
Operating temperature Topr 0 to +70 °C
———————————————————————————————————————————————–
Storage temperature Tstg –55 to +125 °C
———————————————————————————————————————————————–
Storage temperature under bias Tbias –10 to +85 °C
———————————————————————————————————————————————–
P
W
T
Note: 1. V min = –3.0 V for pulse half-width ≤ 50 ns
T
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
———————————————————————————————————————————————–
Supply voltage 4.5 5.0 5.5
———————————————————————————————–
Symbol
Min
Typ
Max
Unit
V
V
CC
V
0
0
0
V
SS
———————————————————————————————————————————————–
Input high (logic 1) voltage 2.2 6.0
V
—
V
IH
———————————————————————————————————————————————–
*1
Input low (logic 0) voltage
V
–0.5
—
0.8
V
IL
———————————————————————————————————————————————–
Note: 1. V min = –3.0 V for pulse half-width ≤ 50 ns
IL
4
HM62256A Series
HM62256A Series
DC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)
CC
SS
*1
Parameter
Symbol Min
Typ
Max
Unit Test conditions
———————————————————————————————————————————————–
Input leakage current |I | µA Vin = V to V
———————————————————————————————————————————————–
Output leakage current |I µA CS = V or OE = V or WE = V ,
—
—
1
LI
SS
CC
|
—
—
1
LO
IH
IH
IL
V
= V to V
I/O
SS CC
———————————————————————————————————————————————–
Operating V
current
I
—
6
15
mA
CS = V , others = V /V
CC
CC
IL
IH IL
Iout = 0 mA
——————————————————————————————————————————
HM62256A-8
HM62256A-10
HM62256A-12
HM62256A-15
I
—
—
—
—
33
30
27
24
50
50
45
40
mA
min cycle, duty = 100%, I = 0 mA
CC1
I/O
CS = V , others = V /V
IL
IH IL
——————————————————————————————————————————
15 mA Cycle time = 1µs, I = 0 mA
I
—
5
CC2
I/O
CS = V , V = V , V = 0
IL IH
CC IL
———————————————————————————————————————————————–
Standby V current 0.3 mA CS = V
———————————————————————————————————
0.01 mA Vin ≥ 0 V
—————————————— CS ≥ V
I
—
2
CC
SB
IH
I
—
1
SB1
– 0.2 V
CC
*2
*2
—
0.3
100
µA
——————————————
*3
*3
—
0.3
———————————————————————————————————————————————–
Output low voltage 0.4 = 2.1 mA
———————————————————————————————————————————————–
Output high voltage 2.4 = –1.0 mA
———————————————————————————————————————————————–
Notes: 1. Typical values are at V = 5.0 V, Ta = +25°C and not guaranteed.
50
µA
V
—
—
V
I
OL
OL
V
—
—
V
I
OH
OH
CC
2. This characteristics is guaranteed only for L-version.
3. This characteristics is guaranteed only for L-SL version.
*1
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
———————————————————————————————————————————————–
Input capacitance Cin pF Vin = 0 V
———————————————————————————————————————————————–
Input/output capacitance pF = 0 V
Symbol
Min
Typ
Max
Unit
Test conditions
—
—
6
C
—
—
8
V
I/O
I/O
———————————————————————————————————————————————–
Note: 1. This parameter is sampled and not 100% tested.
5
HM62256A Series
HM62256A Series
AC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, unless otherwise noted.)
CC
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V
• Input rise and fall times: 5 ns
• Input and output timing refernce levels: 1.5 V
• Output load: 1 TTL Gate + C (100 pF)
(Including scope & jig)
L
Read Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
—————– —————– —————– —————–
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit
Note
———————————————————————————————————————————————–
Read cycle time 85 100 120 150 ns
———————————————————————————————————————————————–
Address access time 85 100 120 150 ns
———————————————————————————————————————————————–
t
—
—
—
—
RC
t
—
—
—
—
AA
Chip select
access time
t
—
85
—
100
—
120
—
150
ns
ACS
———————————————————————————————————————————————–
Output enable to
output valid
t
—
45
—
50
—
60
—
70
ns
OE
———————————————————————————————————————————————–
Chip selection to
output in low-Z
t
10
—
10
—
10
—
10
—
ns
2
CLZ
———————————————————————————————————————————————–
Output enable to
output in low-Z
t
5
—
5
—
5
—
5
—
ns
2
OLZ
———————————————————————————————————————————————–
Chip deselection to
output in high-Z
t
0
30
0
35
0
40
0
50
ns
1, 2
CHZ
———————————————————————————————————————————————–
Output disable to
output in high-Z
t
0
30
0
35
0
40
0
50
ns
1, 2
OHZ
———————————————————————————————————————————————–
Output hold from
address change
t
5
—
10
—
10
—
10
—
ns
OH
———————————————————————————————————————————————–
6
HM62256A Series
HM62256A Series
*3
Read Timing Waveform (1)
t RC
Address
CS
tAA
tACS
*2
tCLZ
tOE
tOH
*2
OLZ
t
OE
*1 *2
tOHZ
*1 *2
tCHZ
Dout
Valid Data
*3 *4 *6
Read Timing Waveform (2)
tRC
Address
Dout
tOH
tAA
tOH
Valid Data
7
HM62256A Series
HM62256A Series
*3 *5 *6
Read Timing Waveform (3)
CS
tACS
*1,*2
tCHZ
*2
tCLZ
Dout
Valid Data
Notes: 1.
t
and t
are defined as the time at which the outputs achieve the open circuit
OHZ
CHZ
conditions and are not referenced to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. WE is high for read cycle.
4. Device is continuously selected, CS = V .
IL
5. Address Valid prior to or coincident with CS transition Low.
6. OE = V .
IL
Write Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
—————– —————– —————– —————–
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit
Note
———————————————————————————————————————————————–
Write cycle time 85 100 120 150 ns
———————————————————————————————————————————————–
t
—
—
—
—
WC
Chip selection to
end of write
t
75
—
80
—
85
—
100
—
ns
2
CW
———————————————————————————————————————————————–
Address setup time ns
———————————————————————————————————————————————–
t
0
—
0
—
0
—
0
—
3
AS
Address valid to
end of write
t
75
—
80
—
85
—
100
—
ns
AW
———————————————————————————————————————————————–
Write pulse width 55 60 70 90 ns
———————————————————————————————————————————————–
Write recovery time ns
———————————————————————————————————————————————–
WE to output in high-Z 30 35 40 50 ns 10
———————————————————————————————————————————————–
t
—
—
—
—
1
WP
t
0
—
0
—
0
—
0
—
4
WR
t
0
0
0
0
WHZ
Data to write time
overlap
t
40
—
40
—
50
—
60
—
ns
DW
———————————————————————————————————————————————–
Data hold from
write time
t
0
—
0
—
0
—
0
—
ns
DH
———————————————————————————————————————————————–
Output active from
end of write
t
5
—
5
—
5
—
5
—
ns
10
OW
———————————————————————————————————————————————–
Output disable to
output in high-Z
t
0
30
0
35
0
40
0
50
ns
10, 11
OHZ
———————————————————————————————————————————————–
8
HM62256A Series
HM62256A Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
*4
tAW
tWR
OE
CS
*2
tCW
*6
*1
*3
tWP
tAS
WE
*5 *10
tOHZ
Dout
Din
tDW
tDH
Valid Data
9
HM62256A Series
HM62256A Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
*4
*2
tCW
tWR
CS
*6
tAW
*1
tWP
tOH
*3
tAS
WE
*10
*5 *10
tOW
tWHZ
*8
*7
Dout
Din
tDW
tDH
*9
Valid Data
Notes: 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS
going high or WE going high. t
write.
is measured from the beginning of write to the end of
WP
2.
3.
4.
t
t
t
is measured from CS going low to the end of write.
CW
AS
is measured from the address valid to the beginning of write.
is measured from the earlier of WE or CS going high to the end of write cycle.
WR
5. During this period, I/O pins are in the output state so that the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output remain in a high impedance state.
7. Dout is the same phase of the write data of this write cycle.
8. Dout is the read data of next address.
9. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals
of the opposite phase to the output must not be applied to them.
10. This parameter is sampled and not 100% tested.
11. t
and t
are defined as the time at which the outputs achieve the open circuit
OHZ
WHZ
conditions and are not referenced to output voltage levels.
10
HM62256A Series
HM62256A Series
Low V
Data Retention Characteristics (Ta = 0 to +70°C)
CC
This characteristics is guaranteed only for L/L-SL version.
*1
Parameter
———————————————————————————————————————————————–
for data retention – 0.2 V, Vin ≥ 0 V
Symbol Min
Typ
Max
Unit Test conditions
V
V
2
—
—
V
CS ≥ V
CC
CC
DR
———————————————————————————————————————————————–
*2
Data retention current
I
—
0.2
30
µA
V
= 3.0 V, Vin ≥ 0 V
CCDR
CC
——————————————–
*3
—
0.2
10
µA
CS ≥ V
– 0.2 V
CC
———————————————————————————————————————————————–
Chip deselect to data retention time t ns See retention waveform
0
—
—
CDR
——————————————————————————————————––
*4
Operation recovery time
t
t
—
—
ns
R
RC
———————————————————————————————————————————————–
Low V
Data Retention Timing Waveform
CC
Data retention mode
VCC
4.5 V
tR
tCDR
2.2 V
VDR
CS
0 V
≥
CS VCC – 0.2 V
Notes:
1
Typical values are at V
= 3.0 V, Ta = +25°C and not guaranteed.
CC
2. 20 µA max at Ta = 0 to +40°C. (only for L-version)
3. 3 µA max at Ta = 0 to +40°C. (only for L-SL version)
4.
t
= read cycle time.
RC
5. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data
retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.
11
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