HM514400BLZ-6 [HITACHI]
Fast Page DRAM, 1MX4, 60ns, CMOS, PZIP20, 0.400 INCH, PLASTIC, ZIP-20;
| 型号： | HM514400BLZ-6 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 1MX4, 60ns, CMOS, PZIP20, 0.400 INCH, PLASTIC, ZIP-20 动态存储器 内存集成电路 |
| 文件： | 总27页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADE-203-269A (Z)
HM514400B/BL Series
HM514400C/CL Series
1,048,576-word × 4-bit Dynamic Random Access Memory
Rev. 1.0
Nov. 29, 1994
The Hitachi HM514400B/BL, HM514400C/CL
are CMOS dynamic RAM organized 1,048,576-
word × 4-bit. HM514400B/BL, HM514400C/CL
have realized higher density, higher performance
and various functions by employing 0.8 µm CMOS
process technology and some new CMOS circuit
design technologies. The HM514400B/BL,
HM514400C/CL offer Fast Page Mode as a high
speed access mode. Multiplexed address input
permits the HM514400B/BL, HM514400C/CL to
be packaged in standard 300-mil 26-pin plastic
SOJ, standard 400-mil 20-pin plastic ZIP and 26-
pin plastic TSOP II.
• Test function
• Battery back up operation
— HM514400BL Series (L-version)
— HM514400CL Series (L-version)
Features
• Single 5 V (±10%)
• High speed
— Access time
60 ns/70 ns/80 ns (max)
• Low power dissipation
— Active mode
605 mW/550 mW/495 mW (max)
— Standby mode 11 mW (max)
0.55 mW (max) (L-version)
• Fast page mode capability
• 1024 refresh cycles : 16 ms
1024 refresh cycles : 128 ms (L-version)
• 3 variations of refresh
— RAS-only refresh
— CAS-before-RAS refresh
— Hidden refresh
HM514400B/BL, HM514400C/CL Series
Ordering Information
Access
time
Access
time
Type No.
Package
Type No.
Package
HM514400BS-6
HM514400BS-7
HM514400BS-8
60 ns
70 ns
80 ns
300-mil 26-pin
plastic SOJ
(CP-26/20D)
HM514400CZ-6
HM514400CZ-7
HM514400CZ-8
60 ns
70 ns
80 ns
400-mil 20-pin
plastic ZIP
(ZP-20)
HM514400BLS-6
HM514400BLS-7
HM514400BLS-8
60 ns
70 ns
80 ns
HM514400CLZ-6
HM514400CLZ-7
HM514400CLZ-8
60 ns
70 ns
80 ns
HM514400CS-6
HM514400CS-7
HM514400CS-8
60 ns
70 ns
80 ns
HM514400BTT-6
HM514400BTT-7
HM514400BTT-8
60 ns
70 ns
80 ns
26-pin
plastic TSOPII
(TTP-26/20D)
HM514400CLS-6
HM514400CLS-7
HM514400CLS-8
60 ns
70 ns
80 ns
HM514400BLTT-6
HM514400BLTT-7
HM514400BLTT-8
60 ns
70 ns
80 ns
HM514400BZ-6
HM514400BZ-7
HM514400BZ-8
60 ns
70 ns
80 ns
400-mil 20-pin
plastic ZIP
(ZP-20)
HM514400CTT-6
HM514400CTT-7
HM514400CTT-8
60 ns
70 ns
80 ns
HM514400BLZ-6
HM514400BLZ-7
HM514400BLZ-8
60 ns
70 ns
80 ns
HM514400CLTT-6
HM514400CLTT-7
HM514400CLTT-8
60 ns
70 ns
80 ns
2
HM514400B/BL, HM514400C/CL Series
Pin Arrangement
HM514400BS/BLS Series
HM514400CS/CLS Series
HM514400BZ/BLZ Series
HM514400CZ/CLZ Series
1
3
5
7
9
OE
I/O1 1
I/O2 2
WE 3
RAS 4
A9 5
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
CAS 2
I/O4 4
I/O1 6
I/O3
VSS
I/O2
RAS
WE
8
A9 10
A1 12
A3 14
A4 16
A6 18
A8 20
11 A0
13 A2
15 VCC
17 A5
19 A7
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
(Top view)
(Bottom view)
HM514400BTT/BLTT Series
HM514400CTT/CLTT Series
I/O1
I/O2
WE
RAS
A9
26 VSS
1
2
3
4
5
25 I/O4
24 I/O3
23 CAS
22 OE
A0
A1
A2
A3
VCC
18 A8
17 A7
16 A6
15 A5
14 A4
9
10
11
12
13
(Top view)
3
HM514400B/BL, HM514400C/CL Series
Pin Description
Pin name
A0 to A9
A0 to A9
I/O1 to I/O4
RAS
Function
Address input
Refresh address input
Data-in/Data-out
Row address strobe
Column address strobe
Read/Write enable
Output enable
CAS
WE
OE
VCC
Power (+5 V)
VSS
Ground
4
HM514400B/BL, HM514400C/CL Series
Block Diagram
CAS
WE
OE
RAS
RAS Control
Circuit
CAS Control
Circuit
WE Control
Circuit
OE Control
Circuit
I/O1
I/O2
I/O3
I/O4
I/O1 Buffer
I/O2 Buffer
I/O3 Buffer
I/O4 Buffer
Row
Driver
Row
Driver
Row
Driver
Row
Driver Driver
Row
Row
Driver
Row
Driver
Row
Driver
Row Decoder & Peripheral Circuit
Row
Row
Row
Row
Row
Row
Row
Row
Driver
Driver Driver
Driver
Driver
Driver Driver
Driver
Column Address Buffer
Row Address Buffer
Address A0–A9
5
HM514400B/BL, HM514400C/CL Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
Iout
V
mA
W
PT
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VSS
Min
0
Typ
0
Max
0
Unit
V
Note
Supply voltage
VCC
VIH
4.5
2.4
–1.0
5.0
—
5.5
6.5
0.8
V
1
1
1
Input high voltage
Input low voltage
V
VIL
—
V
Note: 1. All voltage referred to VSS
.
6
HM514400B/BL, HM514400C/CL Series
DC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)
CC
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Test conditions
SS
Parameter
Notes
Operating current
ICC1
—
110 —
100 —
90 mA RAS, CAS cycling
1, 2
tRC = min
Standby current
ICC2
—
2
1
—
—
2
1
—
—
2
1
mA TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
mA CMOS interface
RAS, CAS
≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
100 —
110 —
100 —
100 —
100 µA CMOS interface
RAS, CAS =VIH
4
WE, OE, Address and
Din = VIH or VIL
Dout = High-Z
RAS-only
refresh current
ICC3
ICC5
ICC6
ICC7
ICC10
—
—
—
—
—
90 mA tRC = min
2
1
Standby current
5
—
5
—
5
mA RAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS
refresh current
110 —
110 —
200 —
100 —
100 —
200 —
90 mA tRC = min
90 mA tPC = min
200 µA tRC = 125 µs
Fast page mode
current
1, 3
4
Battery back up
current
tRAS ≤ 1 µs
(Standby with
CBR refresh)
(L-version)
WE = VIH, CAS = VIL
OE, Address and
Din = VIH or VIL
Dout = High-Z
Input leakage current ILI
–10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V
Output leakage
current
ILO
–10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –5 mA
Low Iout = 4.2 mA
0
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VCC – 0.2 V ≤ VIH ≤ 6.5 V and 0 V ≤ VIL ≤ 0.2 V.
7
HM514400B/BL, HM514400C/CL Series
Capacitance (Ta = 25°C, V = 5 V ± 10%)
CC
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
5
7
7
1
CI2
—
pF
1
Output capacitance
(Data-in, Data-out)
CI/O
—
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
*1, *14, *15, *16
AC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)
CC
SS
Test Conditions
• Input rise and fall times : 5 ns
• Input timing reference levels : 0.8 V, 2.4 V
• Output load : 2 TTL gate + C (100 pF) (Including scope and jig)
L
8
HM514400B/BL, HM514400C/CL Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Random read or write cycle time
RAS precharge time
tRC
110
40
60
15
0
—
—
130
50
—
—
150
60
—
—
ns
ns
tRP
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tODD
tDZO
tDZC
tT
10000 70
10000 20
10000 80
10000 20
10000 ns
10000 ns
19
20
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
—
—
—
50
16
128
0
—
—
—
—
50
35
—
—
—
—
—
—
50
16
128
0
—
—
—
—
60
40
—
—
—
—
—
—
50
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
10
0
10
0
10
0
15
20
15
15
60
10
15
0
15
20
15
20
70
10
20
0
15
20
15
20
80
10
20
0
8
9
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS setup time from Din
Transition time (rise and fall)
Refresh period
0
0
0
3
3
3
7
tREF
tREF
—
—
—
—
—
—
Refresh period (L-version)
128 ms
9
HM514400B/BL, HM514400C/CL Series
Read Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Access time from RAS
Access time from CAS
tRAC
tCAC
—
—
60
15
—
—
70
20
—
—
80
20
ns
ns
2, 3, 17
3, 4, 13,
17
Access time from address
tAA
—
30
—
35
—
40
ns
3, 5, 13,
17
Access time from OE
tOAC
tRCS
tRCH
tRRH
tRAL
—
0
15
—
—
—
—
15
15
—
—
—
0
20
—
—
—
—
20
20
—
—
—
0
20
—
—
—
—
20
20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 17
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Output buffer turn-off time
Output buffer turn-off time to OE
CAS to Din delay time
0
0
0
18
18
0
0
0
30
0
35
0
40
0
tOFF1
tOFF2
tCDD
tOEP
6
6
0
0
0
15
15
20
20
20
20
OE pulse width
Write Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
10
15
10
15
15
0
15
10
20
20
0
15
10
20
20
0
tRWL
tCWL
tDS
11
11
Data-in hold time
tDH
15
15
15
10
HM514400B/BL, HM514400C/CL Series
Read-Modify-Write Cycle
HM514400B/BL, HM514400C/CL
-6
-7
-8
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
tRWC
tRWD
tCWD
tAWD
tOEH
150
80
35
50
15
—
—
—
—
—
180
95
45
60
20
—
—
—
—
—
200
105
45
—
—
—
—
—
ns
ns
ns
ns
ns
10
10
10
65
20
Refresh Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
CAS setup time (CBR refresh cycle) tCSR
10
10
10
10
—
—
—
—
10
10
10
10
—
—
—
—
10
10
10
10
—
—
—
—
ns
ns
ns
ns
CAS hold time (CBR refresh cycle)
RAS precharge to CAS hold time
tCHR
tRPC
CAS precharge time in normal mode tCPN
Fast Page Mode Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Fast page mode cycle time
tPC
40
10
—
—
—
45
10
—
—
—
50
10
—
—
—
—
ns
ns
Fast page mode CAS precharge time tCP
—
—
Fast page mode RAS pulse width
Access time from CAS precharge
tRASC
100000
35
100000
40
100000ns
12
tACP
45
ns
3, 13,
17
RAS hold time from CAS precharge
tRHCP
35
—
40
—
45
—
ns
11
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read-Modify-Write Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Fast page mode read-modify-write
cycle time
tPCM
80
—
95
—
100
—
ns
Fast page mode read-modify-write
cycle CAS precharge to WE delay
time
tCPW
55
—
65
—
70
—
ns
10
Test Mode Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
Parameter
Test mode WE setup time
Test mode WE hold time
tWS
tWH
0
—
—
0
—
—
0
—
—
ns
ns
10
10
10
Counter Test Cycle
HM514400B/BL, HM514400C/CL
-6 -7 -8
Symbol Min Max Min Max Min Max Unit Notes
tCPT 40 40 40 ns
Parameter
CAS precharge time in counter test
cycle
—
—
—
12
HM514400B/BL, HM514400C/CL Series
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified
as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time
is controlled exclusively by tCAC
.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified
as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time
is controlled exclusively by tAA
.
10. tWCS, tRWD, tCWD, tCPW and tAWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tCPW ≥ tCPW (min) and tAWD ≥ tAWD (min), the cycle is a
read-modify-write and the data output will contain data read from the selected cell; if neither of
the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or read-modify-write cycle.
12. tRASC defines RAS pulse width in fast page mode cycles.
13. Access time is determined by the longest among tAA, tCAC and tACP
.
14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter
is used, a minimum of eight CAS-before-RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
16. Test mode operation specified in this data sheet is 2-bit test function controlled by control
address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is high level. When the state of test bits do not accord, the condition
of the output data is low level. In order to end this test mode operation, perform a RAS-only
refresh cycle or a CAS-before-RAS refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2 ns to 5 ns
for the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
18. Either tRCH or tRRH must be satisfied
19. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.
20. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
13
HM514400B/BL, HM514400C/CL Series
*21
Timing Waveforms
Read Cycle
t
t
RC
RAS
RAS
CAS
t
RP
t
CRP
t
T
t
RSH
t
RCD
t
t
CAS
CSH
t
t
RAD
RAL
t
t
CAH
ASR
t
RAH
t
ASC
Row
Column
Address
t
RCS
t
RCH
t
RRH
WE
Dout
Din
t
CAC
t
OFF1
t
AA
Dout
t
RAC
t
OFF2
t
t
DZC
OAC
t
CDD
High-Z
t
t
ODD
DZO
t
OEP
OE
Notes: 21.
H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
Invalid Dout
14
HM514400B/BL, HM514400C/CL Series
Early Write Cycle
t
t
RC
RAS
RAS
CAS
t
RP
t
t
t
RSH
CAS
T
t
CRP
t
RCD
t
CSH
t
t
t
t
CAH
RAH
ASR
ASC
Row
Address
Column
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
*
t
t
(min)
WCS
WCS
**
: H or L
OE
15
HM514400B/BL, HM514400C/CL Series
Delayed Write Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
RCD
RSH
t
t
CAS
T
CAS
t
t
ASC
CWL
t
t
ASR
RAH
t
RWL
t
CAH
Row
Address
Column
t
t
RCS
WP
WE
Din
t
DS
t
DH
High-Z
Din
t
DZC
t
ODD
t
OEH
t
DZO
Dout
OE
Invalid Dout*
t
OFF2
*
*
Invalid Dout comes out, when OE is low level.
16
HM514400B/BL, HM514400C/CL Series
Read-Modify-Write Cycle
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
CAS
t
RAD
t
ASR
t
t
t
ASC
CAH
RAH
Address
Column
t
Row
t
CWL
CWD
t
RCS
t
t
RWL
AWD
t
WP
WE
t
AA
t
RWD
t
CAC
t
t
DH
t
DS
RAC
t
DZC
High-Z
Din
Din
Dout
Dout
t
OAC
t
t
OEH
OFF2
ODD
t
t
DZO
t
OEP
OE
17
HM514400B/BL, HM514400C/CL Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
(Read)
(Refresh)
(Refresh)
RAS
CAS
t
T
t
CRP
t
t
CHR
RSH
t
CAS
t
RCD
t
ASC
t
t
ASR
RAL
t
RAD
t
CAH
t
RAH
Address
Row
Column
t
RCH
RRH
t
t
RCS
t
CAC
WE
t
AA
t
OFF1
t
RAC
Dout
Dout
t
DZC
t
OFF2
t
CDD
High-Z
Din
OE
t
t
ODD
t
DZO
OAC
18
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read Cycle
t
RASC
t
t
RP
RHCP
RAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CP
CAS
CAS
t
t
RAL
ASR
t
RAD
t
t
t
t
t
CAH
ASC
t
RAH
CAH
CAH
t
ASC
ASC
Address
Row
Column
Column
Column
t
t
RCS
t
RRH
RCS
t
t
t
t
RCH
RCH
CDD
RCS
t
RCH
WE
Din
t
t
t
DZC
DZC
DZC
t
t
CDD
CDD
High-Z
High-Z
High-Z
t
t
ODD
CAC
t
CAC
t
t
CAC
ODD
t
t
AA
AA
t
AA
t
OFF1
t
t
t
t
ACP
ACP
RAC
DZO
t
t
OFF1
DZO
OFF1
t
Dout
Dout
OE
Dout
Dout
t
OAC
t
OAC
t
t
t
ODD
DZO
t
OFF2
t
OFF2
t
OFF2
t
t
OEP
OEP
OEP
t
OAC
19
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Early Write Cycle
t
t
RP
RASC
RAS
CAS
t
T
t
RSH
t
t
t
PC
CSH
RCD
t
t
t
t
t
t
CRP
CAS
CAS
CP
CAS
CP
t
t
t
t
t
t
t
ASC
t
CAH
ASR
ASC
CAH
ASC
CAH
RAH
Address
Row
Column
Column
Column
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
t
WCS
WE
t
t
DH
DH
t
t
t
t
DH
DS
DS
DS
Din
Din
Din
Din
High-Z
Dout
:
OE
H or L
*
20
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Delayed Write Cycle
t
t
t
RASC
RP
RAS
t
T
t
t
t
RSH
CSH
t
PC
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
Address
WE
t
t
ASC
ASR
t
CAH
t
ASC
t
t
CAH
RAH
t
ASC
t
CAH
Row
Column
Column
Column
t
t
t
t
CWL
CWL
CWL
t
t
t
RCS
WP
WP
t
WP
RWL
t
t
t
DH
RCS
DH
t
t
DH
RCS
t
DS
t
t
DS
DS
Din
Din
Din
Din
t
OEH
High-Z
Dout
t
ODD
OE
21
HM514400B/BL, HM514400C/CL Series
Fast Page Mode Read-Modify-Write Cycle
t
t
RP
RASC
RAS
CAS
t
t
RCD
PCM
t
T
t
CRP
t
t
CP
CP
t
t
t
CAS
CAS
CAS
t
RAD
t
t
RAH
ACP
t
t
CAH
t
t
CAH
CAH
t
ASR
t
ASC
ASC
t
ASC
Column
Column
t
CPW
Row
Column
Address
t
t
CWL
RWL
WP
t
t
CWL
t
AWD
AWD
t
CWL
t
t
t
AWD
CWD
CWD
t
t
RCS
RCS
t
t
t
t
WP
RCS
CWD
t
t
CPW
RWD
t
WP
WE
t
t
ACP
DS
t
t
DS
DS
t
CAC
t
t
DZC
t
CAC
DZC
t
t
t
DH
t
DH
DH
DZC
High-Z
High-Z
AA
High-Z
Din
t
Din
Din
t
Din
t
AA
t
t
CAC
t
t
DZO
RAC
t
AA
t
OAC
t
t
t
OAC
OAC
OEH
OEH
OEH
Dout
Dout
OFF2
Dout
OFF2
Dout
t
t
t
OFF2
t
t
DZO
DZO
OE
t
t
ODD
t
ODD
ODD
t
OEP
t
OEP
t
OEP
22
HM514400B/BL, HM514400C/CL Series
Test Mode Cycle
*,**
Set Cycle**
Test Mode Cycle
Reset Cycle Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
Test Mode Set Cycle
WE-and-CAS-Before RAS-Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CPN
CPN @
WS
WH
WE
Address
Dout
t
OFF1
High-Z
23
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
t
T
t
RPC
t
CRP
t
t
t
t
t
CPN
CPN
RPC
CSR
CHR
CAS
WE
t
t
WH
WS
Address
t
OFF1
High-Z
Dout
24
HM514400B/BL, HM514400C/CL Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
CRP
t
t
RPC
CRP
CAS
t
t
RAH
ASR
Address
Row
High-Z
Dout
*
Refresh address : A0 – A9 (AX0 – AX9)
: H or L
WE
**
25
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Counter Check Cycle (Read)
t
t
RP
RAS
RAS
CAS
t
T
t
t
t
t
RSH
CSR
CHR
CPT
t
CRP
t
CAS
t
t
CAH
ASC
Address
Column
t
RCH
t
RRH
t
t
t
RCS
WS
WH
WE
Din
t
t
CDD
DZC
High-Z
t
CAC
t
AA
t
OFF1
Dout
Dout
t
OFF2
t
OAC
t
DZO
t
ODD
t
OEP
OE
26
HM514400B/BL, HM514400C/CL Series
CAS-Before-RAS Refresh Counter Check Cycle (Write)
t
RAS
t
RP
RAS
CAS
t
T
t
CRP
t
t
t
t
RSH
CSR
CHR
CPT
t
CAS
t
t
ASC
CAH
Address
Column
WCH
t
t
t
WCS
t
WS
WH
WE
t
t
DH
DS
Din
Dout
OE
Din
High-Z
27
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