HM5116100S-6 [HITACHI]
16M FP DRAM (16-Mword x 1-bit) 4k Refresh; 16M的FP DRAM（ 16 Mword ×1位） 4K的刷新
| 型号： | HM5116100S-6 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 16M FP DRAM (16-Mword x 1-bit) 4k Refresh |
| 文件： | 总24页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5116100 Series
16 M FP DRAM (16-Mword × 1-bit)
4 k Refresh
ADE-203-646E (Z)
Rev. 5.0
Nov. 1997
Description
The Hitachi HM5116100 is a CMOS dynamic RAM organized 16,777,216-word × 1-bit. It employs the
most advanced 0.5µm CMOS technology for high performance and low power. The HM5116100 offers
Fast Page Mode as a high speed access mode. It is packaged in 26-pin plastic SOJ.
Features
•
•
•
Single 5 V (±10%)
Access time: 60 ns/70 ns (max)
Power dissipation
Active mode: 440 mW/385 mW (max)
Standby mode 11 mW (max)
Fast page mode capability
Refresh cycles
•
•
4096 refresh cycles : 64 ms
3 variations of refresh
RAS-only refresh
•
CAS-before-RAS refresh
Hidden refresh
•
Test function
16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM5116100S-6
HM5116100S-7
60 ns
70 ns
300-mil 26-pin plastic SOJ (CP-26/24DB)
HM5116100 Series
Pin Arrangement
HM5116100S Series
VCC
Din
1
2
3
4
5
6
26
25
24
23
22
21
VSS
Dout
NC
NC
WE
CAS
NC
RAS
A11
A9
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
10
11
12
13
VCC
(Top view)
Pin Description
Pin name
Function
Address input
A0 to A11
•
•
Row/Refresh A0 to A11
Column A0 to A11
Din
Data input
Dout
RAS
CAS
WE
VCC
Data output
Row address strobe
Column address strobe
Read/write enable
Power supply
VSS
Ground
NC
No connection
2
HM5116100 Series
Block Diagram
RAS
CAS
WE
Timing and control
A0
Column decoder
A1
Column
address
buffers
•
•
•
to
Din
buffer
Din
A11
16M array
•
•
•
Row
address
buffers
Dout
buffer
Dout
3
HM5116100 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
6.5
0.8
Unit
Note
Supply voltage
V
V
V
1
1
1
Input high voltage
Input low voltage
VIH
2.4
VIL
–1.0
—
Note: 1. All voltage referred to VSS
4
HM5116100 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM5116100
-6
-7
Parameter
Symbol Min
Max Min Max Unit
Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
80
2
—
—
70
2
mA
mA
tRC = min
Standby current
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
80
5
—
—
70
5
mA
mA
tRC = min
RAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh current
Fast page mode current*1, *3
Input leakage current
ICC6
ICC7
ILI
—
80
70
10
10
—
—
70
60
mA
mA
µA
tRC = min
—
tPC = min
–10
–10
–10 10
–10 10
0 V ≤ Vin ≤ 7 V
Output leakage current
ILO
µA
0 V ≤ Vout ≤ 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –5 mA
Low Iout = 4.2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address, Data-in)
Input capacitance (Clocks)
Output capacitance (Data-out)
5
7
7
1
CI2
—
pF
1
CO
—
pF
1, 2
Notes: 1. Capacitance measured with Booton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
5
HM5116100 Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *2, *16
Test Conditions
•
•
•
Input rise and fall time : 5 ns
Input timing reference levels : 0.8 V, 2.4 V
Output load : 2 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5116100
-6
-7
Parameter
Symbol
tRC
Min
110
40
10
60
15
0
Max
—
Min
130
50
Max
—
Unit
ns
Notes
Random read or write cycle time
RAS precharge time
tRP
—
—
ns
CAS precharge time
tCP
—
10
—
ns
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
10000 70
10000 18
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
50
0
—
—
—
—
52
35
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
10
20
15
15
60
5
15
20
15
18
70
5
3
4
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
3
3
5
6
HM5116100 Series
Read Cycle
HM5116100
-6
-7
Min
—
—
—
0
Parameter
Symbol
tRAC
tCAC
tAA
Min
—
—
—
0
Max
Max
70
18
35
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access time from RAS
60
15
30
—
—
—
—
—
—
—
15
6, 7, 17
Access time from CAS
7, 8, 15, 17
7, 9, 15, 17
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
tRCS
tRCH
tRRH
tRAL
0
0
—
10
10
0
0
—
30
30
0
35
35
0
—
tCAL
—
tCLZ
—
Output data hold time
tOH
3
3
—
Output buffer turn-off time
tOFF
—
—
15
11
Write Cycle
HM5116100
-6
-7
Parameter
Symbol
tWCS
tWCH
tWP
Min
0
Max
Min
0
Max
—
Unit
ns
Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
—
—
—
—
—
—
—
12
10
10
15
15
0
15
10
18
18
0
—
ns
—
ns
tRWL
tCWL
tDS
—
ns
—
ns
—
ns
13
13
Data-in hold time
tDH
10
15
—
ns
7
HM5116100 Series
Read-Modify-Write Cycle
HM5116100
-6
-7
Parameter
Symbol
tRWC
Min
130
60
Max
Min
153
70
Max
—
Unit
ns
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
—
—
—
—
tRWD
—
ns
12
12
12
tCWD
15
18
—
ns
tAWD
30
35
—
ns
Refresh Cycle
HM5116100
-6
-7
Min
5
Parameter
Symbol
tCSR
Min
5
Max
Max
—
Unit
ns
Notes
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
—
—
—
—
—
tCHR
10
0
10
0
—
ns
tWRP
—
ns
tWRH
10
5
10
5
—
ns
tRPC
—
ns
Fast Page Mode Cycle
HM5116100
-6
-7
Parameter
Symbol
tPC
Min
40
—
Max
Min
45
Max
Unit
Notes
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
—
—
ns
tRASP
tCPA
100000 —
100000 ns
14
—
35
—
—
40
—
ns
ns
7, 15, 17
tCPRH
35
40
8
HM5116100 Series
Fast Page Mode Read-Modify-Write Cycle
HM5116100
-6
-7
Parameter
Symbol
Min
Max
Min
68
Max
Unit
Notes
Fast page mode read-modify-write cycle tPRWC
time
60
—
—
ns
WE delay time from CAS precharge
tCPW
35
—
40
—
ns
12
Test Mode Cycle *16
HM5116100
-6
-7
Parameter
Symbol
tWTS
Min
0
Max
Min
0
Max
—
Unit
ns
Notes
Test mode WE setup time
Test mode WE hold time
—
—
tWTH
10
10
—
ns
Refresh Cycle
Parameter
Symbol
Max
Unit
Note
Refresh period
tREF
64
ms
4096 cycles
9
HM5116100 Series
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. Assume that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
9. Assume that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
10. Either tRCH or tRRH must be satisfied for a read cycles.
11. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
12. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
14. tRASP defines RAS pulse width in fast page mode cycles.
15. Access time is determined by the longest among tAA, tCAC and tCPA
.
16. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and
CA11 for the 16M × 1 are don’t care during test mode. Test mode is set by performing a WE-
and-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in
parallel at Din and read out from Dout.
If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then
the device has passed. If they are not equal, data output pin is a low state, then the device has
failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-
before-RAS refresh cycle or RAS-only refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
18. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
10
HM5116100 Series
Timing Waveforms*18
Read Cycle
t
RC
t
t
RP
RAS
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
RAD
RAL
CAL
t
t
t
t
CAH
ASR
RAH
ASC
Address
Column
Row
t
RRH
t
RCH
t
RCS
WE
t
t
t
OH
OFF
CAC
t
AA
t
RAC
t
CLZ
Dout
Dout
11
HM5116100 Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
12
HM5116100 Series
Delayed Write Cycle
t
RC
t
t
RAS
RP
RAS
CAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
t
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
CWL
RWL
t
RCS
WP
WE
t
t
DH
DS
Din
Din
t
t
OFF
CLZ
Dout
Invalid Dout
13
HM5116100 Series
Read-Modify-Write Cycle
t
t
RWC
RAS
t
RP
RAS
t
t
CRP
T
t
t
CAS
RCD
CAS
Address
WE
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
t
t
t
t
RCS
CWD
CWL
RWL
t
t
AWD
RWD
t
WP
t
t
DH
DS
Din
Din
t
CAC
t
t
OH
OFF
t
AA
t
RAC
t
CLZ
Dout
Dout
14
HM5116100 Series
RAS-Only Refresh Cycle
t
RC
t
t
RAS
RP
RAS
t
T
t
t
t
CRP
CRP
RPC
CAS
t
t
RAH
ASR
Address
Row
t
OFF
High-Z
Dout
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
RAS
CAS
t
t
t
T
t
t
t
CRP
RPC
CP
RPC
CP
t
t
t
t
CHR
CSR
CHR
CSR
t
t
t
t
WRH
WRP
WRH
WRP
WE
Address
t
OFF
High-Z
Dout
15
HM5116100 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
RP
t
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
Address
WE
t
t
RAD
RAL
CAH
t
t
t
ASR
RAH
t
ASC
Row
Column
t
WRP
t
t
WRH
WRP
t
t
WRH
RCS
t
RRH
t
CAC
t
OH
t
AA
t
OFF
t
RAC
t
CLZ
Dout
Dout
16
HM5116100 Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
t
T
t
t
t
t
CSH
RCD
PC
RSH
CAS
t
t
t
t
t
t
CRP
CAS
CP
CAS
CP
CAS
t
t
t
RAL
CAL
CAH
t
t
t
t
t
RAD
RAH
CAL
CAH
CAL
CAH
t
t
t
t
t
ASC
ASR
ASC
ASC
Address
Row
Column 1
Column 2
Column N
t
t
RCS
t
RCS
t
RCH
RRH
t
t
RCH
t
RCS
RCH
WE
t
t
t
CPA
t
CAC
CLZ
CPA
t
t
t
AA
AA
AA
t
t
t
t
t
t
t
t
t
t
t
CAC
CLZ
OH
OFF
OH
CAC
CLZ
OH
RAC
OFF
OFF
Dout
Dout 1
Dout 2
Dout N
17
HM5116100 Series
Fast Page Mode Early Write Cycle
t
t
RASP
RP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
Address
WE
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
ROW
Column 1
Column 2
Column N
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
18
HM5116100 Series
Fast Page Mode Delayed Write Cycle
t
t
RP
RASP
RAS
t
T
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
Address
WE
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
Row
Column 1
t
Column 2
t
Column N
t
RWL
t
CWL
CWL
CWL
t
t
t
t
t
t
WP
RCS
WP
RCS
WP
RCS
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din
Din 1
Din 2
Din N
t
t
t
t
t
t
OFF
CLZ
OFF
CLZ
OFF
CLZ
Dout
Invalid Dout
Invalid Dout
Invalid Dout
19
HM5116100 Series
Fast Page Mode Read-Modify-Write Cycle
t
t
RP
RASP
RAS
t
T
t
PRWC
t
t
RSH
t
t
t
t
t
CP
t
CRP
RCD
CAS
CP
CAS
CAS
CAS
Address
WE
t
t
t
t
CAH
RAD
CAH
CAH
t
t
t
t
t
RAH ASC
ASC
ASR
ASC
Row
Column 1
Column 2
Column N
t
t
t
RCS
t
RCS
RWL
t
t
RCS
t
t
CWL
t
CWL
t
CWL
t
AWD
t
t
AWD
AWD
RWD
t
WP
WP
WP
t
t
CWD
CWD
t
t
t
CPW
CWD
CPW
t
t
t
DS
DS
DS
t
t
t
DH
DH
DH
Din
Din 1
Din 2
Din N
t
t
t
CAC
CAC
CAC
t
t
t
t
AA
CPA
CPA
t
t
AA
t
AA
RAC
t
t
t
OH
OH
OH
t
OFF
t
t
OFF
OFF
t
t
CLZ
CLZ
CLZ
Dout
Dout 1
Dout 2
Dout N
20
HM5116100 Series
Test Mode Cycle*16
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din: H or L
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CP
CP
WTS
WTH
WE
Address
Dout
t
OFF
High-Z
21
HM5116100 Series
Package Dimensions
HM5116100S Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
21 19
26
1
14
13
6
8
0.74
1.30 Max
+ 0.19
– 0.18
1.27
0.10
6.79
0.43 ± 0.10
0.41 ± 0.08
2.54
Hitachi Code
JEDEC
EIAJ
CP-26/24DB
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.8 g
22
HM5116100 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
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other reasons during operation of the user’s unit according to this document.
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performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
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Semiconductor & IC Div.
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Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
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Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
23
HM5116100 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
Y. Kasama M. Mishima
Y. Kasama Y. Matsuno
Y. Kasama Y. Matsuno
1.0
2.0
3.0
Oct. 14, 1996
Initial issue
Dec. 10, 1996
Feb. 27, 1997
Addition of HM5116100-5 Series
AC Characteristics
t
RRH min: 5/5/5 ns to 0/0/0 ns
4.0
5.0
Jun. 24, 1997
Nov. 1997
Deletion of HM5116100-5 Series
Change of Subtitle
Y. Kasama Y. Matsuno
24
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