HD74HCT74AT-EL [HITACHI]
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, TTP-14D;
| 型号： | HD74HCT74AT-EL |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, TTP-14D 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74HCT74A
Dual D–type Positive Edge–triggered Flip Flops
with Clear and Preset
ADE-205-290 (Z)
1st. Edition
June 1999
Description
The HD74HCT74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin
package. The logic level present at the data input is transferred to the output during the positive going
transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level
at the appropriate input.
Features
•
•
VCC = 4.5 to 5.5 V operation
Input terminal has protection diode
Function Table
Inputs
Outputs
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
Q
L
H
L
H
X
L
H *1
H
H *1
L
L
X
H
H
H
H
↑
H
L
H
↑
L
H
H
L
X
Q0
Q0
H : High level
L : Low level
X : Immaterial
↑ : Low to high transition
Q0 : Level to Q before the indicated steady state input conditions were established.
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if
preset and clear go high simultaneously.
HD74HCT74A
Pin Arrangement
14
13
12
11
10
VCC
1
2
3
4
5
6
7
1CLR
1D
2CLR
2D
1CLK
1PRE
1Q
2CLK
2PRE
9 2Q
1Q
GND
8
2Q
(Top view)
Absolute Maximum Ratings
Item
Symbol
VCC
Ratings
Unit
V
Supply voltage
–0.5 to 7.0
±20
Input diode peak current
Output diode peak current
Output current
IIK
mA
mA
mA
mA
°C
IOK
±20
IO
±25
VCC, GND current / pin
Storage temperature
ICC or IGND
Tstg
±50
–65 to 150
2
HD74HCT74A
Recommended Operating Conditions
Item
Symbol
VCC
VIH
Min
4.5
2.0
0
Typ
5.0
—
—
—
—
–4
4
Max
5.5
—
Unit
V
Supply voltage
Input voltage
V
VIL
0.8
VCC
VCC
—
VI
0
Output voltage
Output current
VO
0
V
IOH
—
—
—
–40
mA
IOL
—
Input rise / fall time
tr, tf
Ta
—
—
500
85
ns
Operating temperature
°C
3
HD74HCT74A
Logic Diagram
PRE
C
CLK
C
C
Q
TG
C
C
C
C
TG
TG
TG
D
Q
C
C
C
CLR
Electrical Characteristics
Item
Symbol VCC (V) Ta = 25°C
Ta = –40 to 85°C Unit Test Conditions
Min
4.40
3.98
—
Typ
Max Min
Max
—
Output voltage
VOH
VOL
II
4.5
4.5
4.5
4.5
5.5
5.5
—
—
4.40
3.84
—
V
IO = –20 µA
IO = –4 mA
IO = 20 µA
IO = 4 mA
—
—
—
—
0.10
0.26
±100
4.0
0.10
0.33
—
—
—
Input current
—
±0.1
—
—
±1000 nA VI = VCC or GND
Quiescent supply ICC
voltage
—
—
40
µA VI = VCC or GND,
IO = 0
4
HD74HCT74A
Switching Characteristics (CL = 50 pF)
Item
Symbol VCC (V) Ta = 25°C
Ta = –40 to 85°C Unit Input
Max Min FROM
Output
TO
Min
27
30
—
—
—
—
—
—
10
9
Typ
Max
—
—
35
32
28
25
19
16
—
—
—
—
—
—
—
—
10
—
Maximum clock
frequency
fmax
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
—
78
92
14
12
14
13
7
—
—
28
25
22
20
15
13
—
—
—
—
—
—
—
—
10
—
22
24
—
—
—
—
—
—
13
12
5
MHz
Propagation
delay time
tPLH
tPHL
ns PRE,
CLR
Q, Q
Q, Q
CLK
Output rise / fall
time
tr / tf
ns
Each
6
output
Setup time
tsu
—
—
—
—
—
—
—
—
3
ns
D
5
PRE, CLR
5
5
inactive
Hold time
th
0
0
ns
ns
0
0
Pulse width
tw
15
14
—
—
19
17
—
—
Input capacitance CI
pF
pF
Power dissipation CPD
capacitance
—
35
5
HD74HCT74A
Test Circuit
1) fmax , tPLH ,tPHL (CLK → Q, Q)
VCC
VCC
Input
Input
PR
Pulse Generator
Output Q
D
Q
Zout = 50 Ω
CL
Pulse Generator
Output Q
CLK
CLR
Q
Zout = 50 Ω
CL
2) tPLH ,tPHL (CLR or PR → Q, Q)
Input
VCC
Pulse Generator
Zout = 50 Ω
PR
D
Q
Output Q
CL
CLK
CLR
Q
Output Q
Input
CL
Pulse Generator
Zout = 50 Ω
Notes: 1. CL includes probe and jig capacitance.
2. Test is put into the each flip flops.
6
HD74HCT74A
• Waveform
tf
tr
3 V
0 V
90 %
1.3 V 1.3 V
10 % 10 %
90 %
Input CLR
tw
tf
tr
3 V
90 %
1.3 V
10 %
90 %
1.3 V
10 %
Input PR
0 V
tw (H) tw (L)
tw
tr
tf
3 V
0 V
90 % 90 %
1.3 V 1.3 V 1.3 V
10 %
1.3 V
1.3 V
Input CLK
10 %
tsu (H)
90 %
th (H) tsu (L) th (L)
3 V
0 V
90 %
1.3 V
10 %
1.3 V
1.3 V
1.3 V
Input D
10 %
tr
tf
tPHL
tPLH
tPHL
tPLH
VOH
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Output Q
VOL
tPLH
tPHL
tPLH
tPHL
VOH
Output
Q
1.3 V
1.3 V
VOL
Note: 1. Input waveform : PRR = 1 MHz, duty cycle 50%, tr = 6 ns, tf = 6 ns
7
HD74HCT74A
Package Dimensions
Unit : mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
FP-14DA
—
EIAJ
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.23 g
8
HD74HCT74A
5.00
5.30 Max
14
8
1
7
0.65
1.0
+0.08
–0.07
0.22
0.13 M
0.20 ± 0.06
6.40 ± 0.20
0.83 Max
0° – 8°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-14D
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.05 g
9
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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