HD6413001VF [HITACHI]
Microcontroller, 32-Bit, H8/300H CPU, 8MHz, CMOS, PQFP80, QFP-80;
| 型号： | HD6413001VF |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Microcontroller, 32-Bit, H8/300H CPU, 8MHz, CMOS, PQFP80, QFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总491页 (文件大小：1606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OMC942723178
H8/3001
Hardware Manual
Preface
The H8/3001 is a high-performance microcontroller that integrates system supporting functions
together with an H8/300H CPU core.
This manual describes the H8/3001 CPU architecture, supporting functions, electrical
characteristics, and package dimensions. For details of the instruction set, refer to the H8/300H
Programming Manual (ADE-602-053).
Contents
Section 1
Overview .....................................................................................................
1
1
4
5
5
6
9
1.1
1.2
1.3
Overview ........................................................................................................................
Block Diagram................................................................................................................
Pin Description ...............................................................................................................
1.3.1
1.3.2
Pin Arrangement.............................................................................................
Pin Functions ..................................................................................................
1.4
Pin Functions ..................................................................................................................
Section 2
CPU............................................................................................................... 13
2.1
Overview ........................................................................................................................ 13
2.1.1
2.1.2
Features........................................................................................................... 13
Differences from H8/300 CPU ....................................................................... 14
2.2
2.3
2.4
CPU Operating Modes.................................................................................................... 15
Address Space................................................................................................................. 16
Register Configuration.................................................................................................... 17
2.4.1
2.4.2
2.4.3
2.4.4
Overview......................................................................................................... 17
General Registers............................................................................................ 18
Control Registers ............................................................................................ 19
Initial CPU Register Values............................................................................ 20
2.5
2.6
Data Formats................................................................................................................... 21
2.5.1
2.5.2
General Register Data Formats....................................................................... 21
Memory Data Formats.................................................................................... 22
Instruction Set................................................................................................................. 24
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
Instruction Set Overview................................................................................ 24
Instructions and Addressing Modes................................................................ 25
Tables of Instructions Classified by Function ................................................ 26
Basic Instruction Formats............................................................................... 36
Notes on Use of Bit Manipulation Instructions.............................................. 37
2.7
2.8
Addressing Modes and Effective Address Calculation .................................................. 37
2.7.1
2.7.2
Addressing Modes .......................................................................................... 37
Effective Address Calculation ........................................................................ 40
Processing States ............................................................................................................ 44
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
Overview......................................................................................................... 44
Program Execution State ................................................................................ 45
Exception-Handling State............................................................................... 45
Exception-Handling Sequences...................................................................... 47
Bus-Released State ......................................................................................... 48
Reset State ...................................................................................................... 48
Power-Down State.......................................................................................... 48
2.9
Basic Operational Timing............................................................................................... 49
2.9.1
2.9.2
2.9.3
2.9.4
Overview......................................................................................................... 49
On-Chip Memory Access Timing................................................................... 49
On-Chip Supporting Module Access Timing ................................................. 51
Access to External Address Space.................................................................. 52
Section 3
MCU Operating Modes........................................................................... 53
3.1
Overview ........................................................................................................................ 53
3.1.1
3.1.2
Operating Mode Selection.............................................................................. 53
Register Configuration.................................................................................... 54
3.2
3.3
3.4
Mode Control Register (MDCR).................................................................................... 55
System Control Register (SYSCR)................................................................................. 56
Operating Mode Descriptions......................................................................................... 58
3.4.1
3.4.2
3.4.3
3.4.4
Mode 1............................................................................................................ 58
Mode 2............................................................................................................ 58
Mode 3............................................................................................................ 58
Mode 4............................................................................................................ 58
3.5
3.6
Pin Functions in Each Operating Mode.......................................................................... 59
Memory Map in Each Operating Mode.......................................................................... 59
Section 4
Exception Handling.................................................................................. 61
4.1
Overview ........................................................................................................................ 61
4.1.1
4.1.2
4.1.3
Reset
4.2.1
4.2.2
4.2.3
Exception Handling Types and Priority.......................................................... 61
Exception Handling Operation ....................................................................... 61
Exception Vector Table................................................................................... 62
........................................................................................................................ 63
Overview......................................................................................................... 63
Reset Sequence............................................................................................... 63
Interrupts after Reset....................................................................................... 65
4.2
4.3
4.4
4.5
4.6
Interrupts ........................................................................................................................ 66
Trap Instruction............................................................................................................... 67
Stack Status after Exception Handling ........................................................................... 67
Notes on Stack Usage..................................................................................................... 68
Section 5
Interrupt Controller................................................................................... 69
5.1
Overview ........................................................................................................................ 69
5.1.1
5.1.2
5.1.3
5.1.4
Features........................................................................................................... 69
Block Diagram................................................................................................ 70
Pin Configuration............................................................................................ 71
Register Configuration.................................................................................... 71
5.2
Register Descriptions...................................................................................................... 72
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
System Control Register (SYSCR)................................................................. 72
Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 73
IRQ Status Register (ISR) .............................................................................. 79
IRQ Enable Register (IER)............................................................................. 80
IRQ Sense Control Register (ISCR)............................................................... 81
5.3
5.4
5.5
Interrupt Sources............................................................................................................. 82
5.3.1
5.3.2
5.3.3
External Interrupts .......................................................................................... 82
Internal Interrupts ........................................................................................... 83
Interrupt Vector Table..................................................................................... 83
Interrupt Operation ......................................................................................................... 86
5.4.1
5.4.2
5.4.3
Interrupt Handling Process ............................................................................. 86
Interrupt Sequence.......................................................................................... 91
Interrupt Response Time................................................................................. 92
Usage Notes.................................................................................................................... 93
5.5.1
5.5.2
5.5.3
Contention between Interrupt and Interrupt-Disabling Instruction ................ 93
Instructions that Inhibit Interrupts .................................................................. 94
Interrupts during EEPMOV Instruction Execution ........................................ 94
Section 6
Bus Controller............................................................................................ 95
6.1
Overview ........................................................................................................................ 95
6.1.1
6.1.2
6.1.3
6.1.4
Features........................................................................................................... 95
Block Diagram................................................................................................ 96
Input/Output Pins............................................................................................ 97
Register Configuration.................................................................................... 97
6.2
Register Descriptions...................................................................................................... 98
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Bus Width Control Register (ABWCR) ......................................................... 98
Access State Control Register (ASTCR)........................................................ 99
Wait Control Register (WCR)......................................................................... 100
Wait State Controller Enable Register (WCER)............................................. 101
Bus Release Control Register (BRCR)........................................................... 102
6.3
6.4
Operation ........................................................................................................................ 103
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Area Division.................................................................................................. 103
Data Bus.......................................................................................................... 105
Bus Control Signal Timing............................................................................. 106
Wait Modes..................................................................................................... 114
Bus Arbiter Operation..................................................................................... 120
Usage Notes.................................................................................................................... 123
6.4.1
6.4.2
ABWCR, ASTCR, and WCER Write Timing................................................ 123
BREQ Input Timing........................................................................................ 123
Section 7
I/O Ports....................................................................................................... 125
7.1
Overview ........................................................................................................................ 125
7.2
Port 4
7.2.1
7.2.2
7.2.3
7.2.4
Port 6
7.3.1
7.3.2
7.3.3
Port 7
7.4.1
7.4.2
Port 8
7.5.1
7.5.2
7.5.3
Port 9
7.6.1
7.6.2
7.6.3
Port A
7.7.1
7.7.2
7.7.3
Port B
7.8.1
7.8.2
7.8.3
........................................................................................................................ 127
Overview......................................................................................................... 127
Register Descriptions...................................................................................... 128
Pin Functions in Each Mode........................................................................... 130
Input Pull-Up Transistors................................................................................ 131
........................................................................................................................ 132
Overview......................................................................................................... 132
Register Descriptions...................................................................................... 132
Pin Functions .................................................................................................. 134
........................................................................................................................ 134
Overview......................................................................................................... 134
Register Description ....................................................................................... 135
........................................................................................................................ 136
Overview......................................................................................................... 136
Register Descriptions...................................................................................... 136
Pin Functions .................................................................................................. 138
........................................................................................................................ 139
Overview......................................................................................................... 139
Register Descriptions...................................................................................... 139
Pin Functions .................................................................................................. 141
........................................................................................................................ 142
Overview......................................................................................................... 142
Register Descriptions...................................................................................... 143
Pin Functions .................................................................................................. 145
........................................................................................................................ 152
Overview......................................................................................................... 152
Register Descriptions...................................................................................... 152
Pin Functions .................................................................................................. 154
7.3
7.4
7.5
7.6
7.7
7.8
Section 8
16-Bit Integrated Timer Unit (ITU)..................................................... 159
8.1
Overview ........................................................................................................................ 159
8.1.1
8.1.2
8.1.3
8.1.4
Features........................................................................................................... 159
Block Diagrams .............................................................................................. 162
Input/Output Pins............................................................................................ 166
Register Configuration.................................................................................... 167
8.2
Register Descriptions...................................................................................................... 170
8.2.1
8.2.2
8.2.3
Timer Start Register (TSTR) .......................................................................... 170
Timer Synchro Register (TSNC) .................................................................... 171
Timer Mode Register (TMDR)....................................................................... 173
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
Timer Function Control Register (TFCR) ...................................................... 176
Timer Output Master Enable Register (TOER).............................................. 178
Timer Counters (TCNT) ................................................................................. 180
General Registers (GRA, GRB) ..................................................................... 181
Buffer Registers (BRA, BRB) ........................................................................ 182
Timer Control Registers (TCR) ...................................................................... 183
Timer I/O Control Register (TIOR)................................................................ 185
Timer Status Register (TSR)........................................................................... 187
Timer Interrupt Enable Register (TIER)......................................................... 190
8.3
8.4
CPU Interface ................................................................................................................. 192
8.3.1
8.3.2
16-Bit Accessible Registers............................................................................ 192
8-Bit Accessible Registers.............................................................................. 194
Operation ........................................................................................................................ 196
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
Overview......................................................................................................... 196
Basic Functions............................................................................................... 196
Synchronization.............................................................................................. 206
PWM Mode .................................................................................................... 208
Phase Counting Mode..................................................................................... 212
Buffering......................................................................................................... 214
ITU Output Timing......................................................................................... 220
8.5
8.6
Interrupts ........................................................................................................................ 221
8.5.1
8.5.2
8.5.3
Setting of Status Flags .................................................................................... 221
Clearing of Status Flags.................................................................................. 223
Interrupt Sources............................................................................................. 224
Usage Notes.................................................................................................................... 225
Section 9
Programmable Timing Pattern Controller......................................... 241
9.1
Overview ........................................................................................................................ 241
9.1.1
9.1.2
9.1.3
9.1.4
Features........................................................................................................... 241
Block Diagram................................................................................................ 242
TPC Pins......................................................................................................... 243
Registers ......................................................................................................... 244
9.2
Register Descriptions...................................................................................................... 245
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
Port A Data Direction Register (PADDR)...................................................... 245
Port A Data Register (PADR)......................................................................... 245
Port B Data Direction Register (PBDDR)...................................................... 246
Port B Data Register (PBDR)......................................................................... 246
Next Data Register A (NDRA)....................................................................... 247
Next Data Register B (NDRB) ....................................................................... 249
Next Data Enable Register A (NDERA) ........................................................ 251
Next Data Enable Register B (NDERB)......................................................... 252
9.2.9
9.2.10
TPC Output Control Register (TPCR)............................................................ 253
TPC Output Mode Register (TPMR).............................................................. 256
9.3
9.4
Operation ........................................................................................................................ 258
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Overview......................................................................................................... 258
Output Timing................................................................................................. 259
Normal TPC Output........................................................................................ 260
Non-Overlapping TPC Output........................................................................ 262
TPC Output Triggering by Input Capture....................................................... 264
Usage Notes.................................................................................................................... 265
9.4.1
9.4.2
Operation of TPC Output Pins........................................................................ 265
Note on Non-Overlapping Output .................................................................. 265
Section 10
Serial Communication Interface........................................................... 267
10.1 Overview ........................................................................................................................ 267
10.1.1
10.1.2
10.1.3
10.1.4
Features........................................................................................................... 267
Block Diagram................................................................................................ 269
Input/Output Pins............................................................................................ 270
Register Configuration.................................................................................... 270
10.2 Register Descriptions...................................................................................................... 271
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
Receive Shift Register (RSR)......................................................................... 271
Receive Data Register (RDR)......................................................................... 271
Transmit Shift Register (TSR)........................................................................ 272
Transmit Data Register (TDR) ....................................................................... 272
Serial Mode Register (SMR) .......................................................................... 273
Serial Control Register (SCR) ........................................................................ 277
Serial Status Register (SSR)........................................................................... 281
Bit Rate Register (BRR)................................................................................. 285
10.3 Operation ........................................................................................................................ 294
10.3.1
10.3.2
10.3.3
10.3.4
Overview......................................................................................................... 294
Operation in Asynchronous Mode.................................................................. 296
Multiprocessor Communication ..................................................................... 305
Synchronous Operation .................................................................................. 312
10.4 SCI Interrupts.................................................................................................................. 321
10.5 Usage Notes.................................................................................................................... 322
Section 11
A/D Converter............................................................................................ 327
11.1 Overview ........................................................................................................................ 327
11.1.1
11.1.2
11.1.3
11.1.4
Features........................................................................................................... 327
Block Diagram................................................................................................ 328
Input Pins........................................................................................................ 329
Register Configuration.................................................................................... 329
11.2 Register Descriptions...................................................................................................... 330
11.2.1
11.2.2
11.2.3
A/D Data Registers A to D (ADDRA to ADDRD)........................................ 330
A/D Control/Status Register (ADCSR).......................................................... 331
A/D Control Register (ADCR)....................................................................... 334
11.3 CPU Interface ................................................................................................................. 335
11.4 Operation ........................................................................................................................ 336
11.4.1
11.4.2
11.4.3
Single Mode (SCAN = 0) ............................................................................... 336
Scan Mode (SCAN = 1).................................................................................. 338
Input Sampling and A/D Conversion Time .................................................... 340
11.5 Interrupts ........................................................................................................................ 341
11.6 Usage Notes.................................................................................................................... 341
Section 12
RAM ............................................................................................................. 343
12.1 Overview ........................................................................................................................ 343
12.1.1
12.1.2
Block Diagram................................................................................................ 343
Register Configuration.................................................................................... 344
12.2 System Control Register (SYSCR)................................................................................. 345
12.3 Operation ........................................................................................................................ 346
Section 13
Clock Pulse Generator............................................................................. 347
13.1 Overview ........................................................................................................................ 347
13.1.1 Block Diagram................................................................................................ 347
13.2 Oscillator Circuit ............................................................................................................ 348
13.2.1
13.2.2
Connecting a Crystal Resonator ..................................................................... 348
External Clock Input....................................................................................... 350
13.3 Duty Adjustment Circuit................................................................................................. 352
13.4 Prescalers........................................................................................................................ 352
Section 14
Power-Down State.................................................................................... 353
14.1 Overview ........................................................................................................................ 353
14.2 Register Configuration.................................................................................................... 354
14.2.1
System Control Register (SYSCR)................................................................. 354
14.3 Sleep Mode..................................................................................................................... 356
14.3.1
14.3.2
Transition to Sleep Mode................................................................................ 356
Exit from Sleep Mode..................................................................................... 356
14.4 Software Standby Mode ................................................................................................. 357
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
Transition to Software Standby Mode............................................................ 357
Exit from Software Standby Mode................................................................. 357
Selection of Waiting Time for Exit from Software Standby Mode ................ 358
Sample Application of Software Standby Mode ............................................ 359
Note................................................................................................................. 359
14.5 Hardware Standby Mode................................................................................................ 360
14.5.1
14.5.2
14.5.3
Transition to Hardware Standby Mode........................................................... 360
Exit from Hardware Standby Mode................................................................ 360
Timing for Hardware Standby Mode.............................................................. 360
Section 15
Electrical Characteristics........................................................................ 361
15.1 Absolute Maximum Ratings........................................................................................... 361
15.2 Electrical Characteristics ................................................................................................ 362
15.2.1
15.2.2
15.2.3
DC Characteristics.......................................................................................... 362
AC Characteristics.......................................................................................... 370
A/D Conversion Characteristics ..................................................................... 376
15.3 Operational Timing......................................................................................................... 377
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
Bus Timing ..................................................................................................... 377
Control Signal Timing .................................................................................... 381
Clock Timing .................................................................................................. 383
TPC and I/O Port Timing................................................................................ 383
ITU Timing..................................................................................................... 384
SCI Input/Output Timing................................................................................ 385
Appendix A Instruction Set............................................................................................ 387
A.1
A.2
A.3
Instruction List................................................................................................................ 387
Operation Code Map....................................................................................................... 402
Number of States Required for Execution...................................................................... 405
Appendix B Register Field ............................................................................................. 414
B.1
Register Addresses and Bit Names................................................................................. 414
B.2
Register Descriptions...................................................................................................... 422
Appendix C I/O Port Block Diagrams........................................................................ 467
C.1
C.2
C.3
C.4
C.5
C.6
C.7
Port 4 Block Diagram..................................................................................................... 467
Port 6 Block Diagrams.................................................................................................... 468
Port 7 Block Diagram..................................................................................................... 471
Port 8 Block Diagrams.................................................................................................... 472
Port 9 Block Diagrams.................................................................................................... 474
Port A Block Diagrams................................................................................................... 477
Port B Block Diagrams................................................................................................... 480
Appendix D Pin States ..................................................................................................... 481
D.1
Port States in Each Mode................................................................................................ 481
D.2
Pin States at Reset........................................................................................................... 483
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode.............................................................. 486
Appendix F Package Dimensions................................................................................ 487
Appendix G Register Index............................................................................................ 489
Section 1 Overview
1.1 Overview
The H8/3001 is a microcontroller (MCU) that integrates system supporting functions together
with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include RAM, a 16-bit integrated timer-pulse unit (ITU),
a programmable timing pattern controller (TPC), a serial communication interface (SCI), an A/D
converter, I/O ports, and other facilities. Four MCU operating modes offer a choice of data bus
width and address space size.
Table 1-1 summarizes the H8/3001 features.
Table 1-1 Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
Two CPU operating modes
• Normal mode (64-kbyte address space, not available in the H8/3001)
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
1
Table 1-1 Features (cont)
Feature
Description
Memory
RAM: 512 bytes
Interrupt
controller
• Four external interrupt pins: NMI, IRQ0, IRQ1, and IRQ4
• 20 internal interrupts
• Three selectable interrupt priority levels
Bus controller
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
16-bit integrated • Five 16-bit timer channels, capable of processing up to 10 pulse outputs or 10
timer unit (ITU)
pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
Programmable
timing pattern
controller (TPC)
• Maximum 12-bit pulse output, using ITU as time base
• Up to three 4-bit pulse output groups (or one 12-bit group, one 8-bit group,
and one 4-bit group)
• Non-overlap mode available
Serial
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
communication
interface (SCI),
1 channel
A/D converter
I/O ports
• Resolution: 10 bits
• Four channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• 28 input/output pins
• 4 input-only pins
2
Table 1-1 Features (cont)
Feature
Description
Operating modes Four MCU operating modes
Address
Space
Address
Pins
Initial Bus Max. Bus
Mode
Width
Width
16 bits
16 bits
16 bits
16 bits
Mode 1
Mode 2
Mode 3
Mode 4
1 Mbyte
1 Mbyte
A0 to A19
A0 to A19
8 bits
16 bits
8 bits
16 Mbyte A0 to A23
16 Mbyte A0 to A23
16 bits
• Sleep mode
• Software standby mode
• Hardware standby mode
Power-down
state
Other features
Product lineup
• On-chip clock oscillator
Model
Package
Power Supply Voltage
5 V ± 10%
HD6413001F
HD6413001VF
80-pin QFP
(FP-80A)
2.7 V to 5.5 V
5 V ± 10%
HD6413001TF
HD6413001VTF
80-pin TQFP
(TFP-80C)
2.7 V to 5.5 V
3
1.2 Block Diagram
Data bus
Port 4
MD
MD
MD
2
1
0
EXTAL
XTAL
ø
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
19
18
17
16
15
14
13
12
11
10
9
Clock
osc.
H8/300H CPU
STBY
RES
NMI
AS
Interrupt controller
RD
HWR
LWR
RAM
512 bytes
P6 /BACK
2
8
P6 /BREQ
1
7
P6 /WAIT
0
6
5
4
3
P8 /IRQ
1
1
0
16-bit
integrated
timer-pulse unit
(ITU)
2
P8 /IRQ
0
1
Serial communication
interface
0
×
(SCI) 2 channels
P9 /SCK/IRQ
4
4
Programmable
timing pattern
controller (TPC)
A/D converter
P9 /RxD
2
P9 /TxD
0
Port B
Port A
Port 7
Figure 1-1 Block Diagram of H8/3001
4
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the H8/3001.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
P9 /TxD
0
1
MD
MD
MD
2
1
0
P9 /RxD
2
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P9 /SCK/IRQ
3
4
4
V
4
LWR
HWR
RD
SS
P4 /D
0
5
0
1
2
3
4
5
6
7
8
9
P4 /D
1
6
P4 /D
2
7
AS
P4 /D
3
8
V
CC
P4 /D
4
9
XTAL
P4 /D
5
10
11
12
13
14
15
16
17
18
19
20
EXTAL
Top view
P4 /D
6
V
SS
P4 /D
7
NMI
RES
STBY
ø
D
D
D
10
11
12
13
14
15
D
D
D
D
D
P6 /BACK
2
P6 /BREQ
1
P6 /WAIT
0
A
19
A
18
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 1-2 Pin Arrangement (FP-80A, TFP-80C Top View)
5
1.3.2 Pin Functions
Pin Assignments in Each Mode: Table 1-2 lists the pin assignments in each mode.
Table 1-2 H8/3001 Pin Assignments in Each Mode
Pin Name
Pin
No. Mode 1
Mode 2
P90/TxD
P92/RxD
P94/SCK/IRQ4
VSS
Mode 3
Mode 4
P90/TxD
P92/RxD
P94/SCK/IRQ4
VSS
1
2
3
4
5
6
7
8
9
P90/TxD
P92/RxD
P94/SCK/IRQ4
VSS
P90/TxD
P92/RxD
P94/SCK/IRQ4
VSS
*1
*1
P40/D0
P40*2/D0
P41*2/D1
P42*2/D2
P43*2/D3
P44*2/D4
P45*2/D5
P46*2/D6
P47*2/D7
D8
P40/D0
P40*2/D0
P41*2/D1
P42*2/D2
P43*2/D3
P44*2/D4
P45*2/D5
P46*2/D6
P47*2/D7
D8
*1
*1
P41/D1
P41/D1
*1
*1
P42/D2
P42/D2
*1
*1
P43/D3
P43/D3
*1
*1
P44/D4
P44/D4
*1
*1
10 P45/D5
11 P46/D6
12 P47/D7
13 D8
P45/D5
*1
*1
*1
P46/D6
*1
P47/D7
D8
14 D9
D9
D9
D9
15 D10
16 D11
17 D12
18 D13
19 D14
20 D15
21 VCC
22 A0
D10
D10
D11
D12
D13
D14
D15
VCC
A0
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
VCC
VCC
A0
A0
23 A1
A1
A1
A1
24 A2
A2
A2
A2
25 A3
A3
A3
A3
26 A4
A4
A4
A4
27 A5
A5
A5
A5
6
Table 1-2 H8/3001 Pin Assignments in Each Mode (cont)
Pin Name
Pin
No. Mode 1
Mode 2
A6
Mode 3
A6
Mode 4
A6
28 A6
29 A7
A7
A7
A7
30 VSS
31 A8
VSS
VSS
VSS
A8
A8
A8
32 A9
A9
A9
A9
33 A10
A10
A10
A10
34 A11
A11
A11
A11
35 A12
A12
A12
A12
36 A13
A13
A13
A13
37 A14
A14
A14
A14
38 A15
A15
A15
A15
39 A16
A16
A16
A16
40 A17
A17
A17
A17
41 A18
A18
A18
A18
42 A19
A19
A19
A19
43 P60/WAIT
44 P61/BREQ
45 P62/BACK
P60/WAIT
P61/BREQ
P62/BACK
ø
P60/WAIT
P61/BREQ
P62/BACK
ø
P60/WAIT
P61/BREQ
P62/BACK
ø
46
ø
47 STBY
48 RES
49 NMI
50 VSS
STBY
RES
NMI
VSS
STBY
RES
NMI
VSS
STBY
RES
NMI
VSS
51 EXTAL
52 XTAL
53 VCC
54 AS
EXTAL
XTAL
VCC
EXTAL
XTAL
VCC
EXTAL
XTAL
VCC
AS
AS
AS
55 RD
RD
RD
RD
56 HWR
57 LWR
HWR
LWR
HWR
LWR
HWR
LWR
7
Table 1-2 H8/3001 Pin Assignments in Each Mode (cont)
Pin Name
Pin
No. Mode 1
Mode 2
MD0
Mode 3
MD0
Mode 4
MD0
58 MD0
59 MD1
MD1
MD1
MD1
60 MD2
MD2
MD2
MD2
61 AVCC
AVCC
AVCC
AVCC
62 P70/AN0
63 P71/AN1
64 P72/AN2
65 P73/AN3
66 AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
AVSS
67 P80/IRQ0
68 P81/IRQ1
69 PA0/TP0/TCLKA
70 PA1/TP1/TCKLKB
P80/IRQ0
P81/IRQ1
PA0/TP0/TCLKA
PA1/TP1/TCKLKB
P80/IRQ0
P81/IRQ1
PA0/TP0/TCLKA
PA1/TP1/TCKLKB
P80/IRQ0
P81/IRQ1
PA0/TP0/TCLKA
PA1/TP1/TCKLKB
71 PA2/TP2/TIOCA0/
TCLKC
PA2/TP2/TIOCA0/
TCLKC
PA2/TP2/TIOCA0/
TCLKC
PA2/TP2/TIOCA0/
TCLKC
72 PA3/TP3/TIOCB0/
TCLKD
PA3/TP3/TIOCB0/
TCLKD
PA3/TP3/TIOCB0/
TCLKD
PA3/TP3/TIOCB0/
TCLKD
73 PA4/TP4/TIOCA1
74 PA5/TP5/TIOCB1
75 PA6/TP6/TIOCA2
76 PA7/TP7/TIOCB2
77 PB0/TP8/TIOCA3
78 PB1/TP9/TIOCB3
79 PB2/TP10/TIOCA4
80 PB3/TP11/TIOCB4
PA4/TP4/TIOCA1
PA5/TP5/TIOCB1
PA6/TP6/TIOCA2
PA7/TP7/TIOCB2
PB0/TP8/TIOCA3
PB1/TP9/TIOCB3
PB2/TP10/TIOCA4
PB3/TP11/TIOCB4
A23
A23
A22
A22
A21
A21
A20
A20
PB0/TP8/TIOCA3
PB1/TP9/TIOCB3
PB2/TP10/TIOCA4
PB3/TP11/TIOCB4
PB0/TP8/TIOCA3
PB1/TP9/TIOCB3
PB2/TP10/TIOCA4
PB3/TP11/TIOCB4
Notes: 1. In modes 1 and 3 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a reset, but
they can be changed by software.
2. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a reset, but they
can be changed by software.
8
1.4 Pin Functions
Table 1-3 summarizes the pin functions.
Table 1-3 Pin Functions
Pin No.
Type
Symbol
QFP-112
I/O
Name and Function
Power
VCC
21, 53
Input
Power: For connection to the power supply
(+5 V). Connect all VCC pins to the +5-V system
power supply.
VSS
4, 30, 50
52
Input
Input
Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
Clock
XTAL
For connection to a crystal resonator.
For examples of crystal resonator and external
clock input, see section 13, Clock Pulse
Gangerator.
EXTAL
51
Input
For connection to a crystal resonator or input of
an external clock signal. For examples of
crystal resonator and external clock input, see
section 13, Clock Pulse Generator.
ø
46
Output System clock: Supplies the system clock to
external devices
Operating
MD2 to MD0 60 to 58
Input
Mode 2 to mode 0: For setting the operating
mode control
mode, as follows
MD2
0
MD1
0
MD0
0
Operating Mode
—
0
0
1
Mode 1
Mode 2
Mode 3
Mode 4
—
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
—
1
1
1
—
9
Table 1-3 Pin Functions (cont)
Pin No.
Type
Symbol
QFP-112
I/O
Name and Function
System control RES
48
Input
Reset input: When driven low, this pin resets
the H8/3001
STBY
BREQ
BACK
47
44
45
Input
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode
Bus request: Used by an external bus master
to request the bus right from the H8/3001
Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
Interrupts
NMI
49
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ4, IRQ1, 3, 68, 67
IRQ0
Input
Interrupt request 4, 1, 0: Maskable interrupt
request pins
Address bus
A23 to A0
73 to 76,
42 to 31,
29 to 22
Output Address bus: Outputs address signals
Data bus
D15 to D0
20 to 5
Input/ Data bus: Bidirectional data bus
output
Bus control
AS
54
Output Address strobe: Goes low to indicate valid
address output on the address bus
RD
55
Output Read: Goes low to indicate reading from the
external address space
HWR
56
Output High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D15 to D8).
LWR
57
43
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D7 to D0).
WAIT
Input
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
10
Table 1-3 Pin Functions (cont)
Pin No.
QFP-112
Type
Symbol
I/O
Name and Function
16-bit
integrated
timer unit (ITU)
TCLKD to 72 to 69
TCLKA
Input
Clock input A to D: External clock inputs
TIOCA4 to 79, 77, 75, Input/ Input capture/output compare A4 to A0:
TIOCA0
73, 71
output GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to 80, 78, 76, Input/ Input capture/output compare B4 to B0:
TIOCB0
74, 72
output GRB4 to GRB0 output compare or input
capture, or PWM output
Programmable TP11 to
timing pattern TP0
controller (TPC)
80 to 69
Output TPC output 11 to 0: Pulse output
Serial com-
munication
interface (SCI)
TxD
RxD
SCK
1
2
3
Output Transmit data: SCI data output
Input
Receive data: SCI data input
Input/ Serial clock: SCI clock input/output
output
A/D
converter
AN3 to AN0 65 to 62
Input
Input
Analog 3 to 0: Analog input pins
AVCC
61
Power supply pin for the A/D converter.
Connect to the system power supply (+5 V)
when not using the A/D converter.
AVSS
66
Input
Ground pin for the A/D converter. Connect to
system ground (0 V) when not using the A/D
converter.
I/O ports
P47 to P40 12 to 5
P62 to P60 45 to 43
P73 to P70 65 to 62
Input/ Port 4: Eight input/output pins. The
output direction of each pin can be selected in the port
4 data direction register (P4DDR).
Input/ Port 6: Three input/output pins. The direction
output of each pin can be selected in the port 6 data
direction register (P6DDR).
Input
Input
Port 7: Four input pins
P81
P80
68
67
Port 8: Two input/output pins. The direction of
each pin can be selected in the port 8 data
direction register (P8DDR).
Input/
output
11
Table 1-3 Pin Functions (cont)
Pin No.
Type
Symbol
QFP-112
I/O
Name and Function
I/O ports
P94, P92,
P90
3 to 1
Input/ Port 9: Three input/output pins. The direction
output of each pin can be selected in the port 9 data
direction register (P9DDR).
PA7 to PA0 76 to 69
PB3 to PB0 80 to 77
Input/ Port A: Eight input/output pins. The direction of
output each pin can be selected in the port A data
direction register (PADDR).
Input/ Port B: Four input/output pins. The direction of
output each pin can be selected in the port B data
direction register (PBDDR).
12
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
•
•
•
Upward compatibility with H8/300 CPU
Can execute H8/300 series object programs without alteration
General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
Sixty-two basic instructions
— 8/16/32-bit arithmetic and logic instructions
— Multiply and divide instructions
— Powerful bit-manipulation instructions
•
Eight addressing modes
— Register direct [Rn]
— Register indirect [@ERn]
— Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
— Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
— Absolute address [@aa:8, @aa:16, or @aa:24]
— Immediate [#xx:8, #xx:16, or #xx:32]
— Program-counter relative [@(d:8, PC) or @(d:16, PC)]
— Memory indirect [@@aa:8]
•
16-Mbyte linear address space
13
•
High-speed operation
— All frequently-used instructions execute in two to four states
— Maximum clock frequency:
16 MHz
— 8/16/32-bit register-register add/subtract: 125 ns
— 8 × 8-bit register-register multiply:
— 16 ÷ 8-bit register-register divide:
— 16 × 16-bit register-register multiply:
— 32 ÷ 16-bit register-register divide:
875 ns
875 ns
1.375 µs
1.375 µs
•
•
Two CPU operating modes
— Normal mode (not available in H8/3001)
— Advanced mode
Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
•
More general registers
Eight 16-bit registers have been added.
Expanded address space
•
— Advanced mode supports a maximum 16-Mbyte address space.
— Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
•
•
Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
Enhanced instructions
— Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
— Signed multiply/divide instructions and other instructions have been added.
14
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1.
The H8/3001 uses only advanced mode.
Maximum 64 kbytes, program
and data areas combined
Normal mode*
CPU operating modes
Maximum 16 Mbytes, program
Advanced mode
and data areas combined
Note: *Normal mode is not available in the H8/3001.
Figure 2-1 CPU Operating Modes
15
2.3 Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3001 has two operating
modes (MCU modes), one providing a 1-Mbyte address space, the other supporting the full
16 Mbytes.
Figure 2-2 shows the H8/3001’s address ranges. For further details see section 3.6, Memory Map
in Each Operating Mode.
The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'00000
H'FFFFF
H'000000
H'FFFFFF
a. 1-Mbyte mode
b. 16-Mbyte mode
Figure 2-2 Memory Map
16
2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers:
general registers and control registers.
General Registers (ERn)
15
0 7
0 7
0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend
SP: Stack pointer
PC: Program counter
CCR: Condition code register
I:
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
UI:
H:
U:
N:
Z:
V:
C:
Overflow flag
Carry flag
Figure 2-3 CPU Registers
17
2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2-4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers
(extended registers)
E0 to E7
ER registers
ER0 to ER7
RH registers
R0H to R7H
R registers
R0 to R7
RL registers
R0L to R7L
Figure 2-4 Usage of General Registers
18
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2-5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
19
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
•
•
•
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
20
2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2-6 and 2-7 show the data formats in general registers.
General
Data Type
Register
Data Format
7
0
1-bit data
RnH
7 6 5 4 3 2 1 0
Don’t care
7
0
Don’t care
7 6 5 4 3 2 1 0
1-bit data
RnL
RnH
RnL
RnH
RnL
4 3
7
0
Upper digit Lower digit
4-bit BCD data
4-bit BCD data
Byte data
Don’t care
4 3
7
0
Upper digit Lower digit
Don’t care
7
0
Don’t care
MSB
LSB
7
0
Don’t care
Byte data
MSB
LSB
Figure 2-6 General Register Data Formats (1)
21
General
Data Type
Register Data Format
15
0
Word data
Rn
MSB
LSB
15
0
Word data
En
MSB
31
LSB
16 15
0
Longword data ERn
MSB
LSB
Legend
ERn: General register
En:
Rn:
General register E
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2-7 General Register Data Formats (2)
2.5.2 Memory Data Formats
Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, no address error occurs but
the least significant bit of the address is regarded as 0, so the access starts at the preceding
address. This also applies to instruction fetches.
22
Data Type
Address
Data Format
7
7
0
0
1-bit data
Byte data
Word data
Address
Address
6
5
4
3
2
1
MSB
MSB
LSB
Address 2m
LSB
Address 2m + 1
Address 2n
MSB
Longword data
Address 2n + 1
Address 2n + 2
Address 2n + 3
LSB
Figure 2-8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
23
2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified in table 2-1.
Table 2-1 Instruction Classification
Function
Instruction
Types
3
Data transfer
MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*2
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU
18
Logic operations
Shift operations
Bit manipulation
AND, OR, XOR, NOT
4
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc*3, JMP, BSR, JSR, RTS
5
9
1
System control
Block data transfer
Total 62 types
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
EEPMOV
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. They are not available in the H8/3001.
3. Bcc is a generic branching instruction.
24
2.6.2 Instructions and Addressing Modes
Table 2-2 indicates the instructions available in the H8/300H CPU.
Table 2-2 Instructions and Addressing Modes
Addressing Modes
@
@
@
@
(d:16, (d:24, @ERn+/ @
@
@
(d:8, (d:16, @@
Function Instruction
#xx Rn
BWL BWL BWL
@ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 PC)
PC)
aa:8 Implied
MOV
BWL BWL BWL
B
BWL BWL
—
—
—
—
—
—
—
—
Data
transfer
POP, PUSH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
WL
—
MOVFPE,
MOVTPE
—
ADD, CMP
SUB
BWL BWL
WL BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Arithmetic
operations
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
B
B
—
—
—
—
L
BWL
B
DIVXU,
MULXS,
MULXU,
DIVXS
BW
NEG
—
—
BWL
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
AND, OR,
Logic
operations XOR
BWL BWL
NOT
—
—
—
—
—
—
—
—
—
B
BWL
BWL
B
—
—
B
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
B
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
o
—
—
—
o
—
—
—
o
—
—
—
—
o
—
—
—
—
—
o
Shift instructions
Bit manipulation
Branch
Bcc, BSR
—
—
o
—
—
—
—
—
—
—
—
—
JMP, JSR
RTS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
TRAPA
RTE
—
o
System
control
—
o
SLEEP
LDC
—
o
B
—
—
—
STC
—
B
B
ANDC, ORC,
XORC
—
NOP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
o
Block data transfer
BW
Legend
B: Byte
W: Word
L: Longword
25
2.6.3 Tables of Instructions Classified by Function
Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd
Rs
Rn
ERn
(EAd)
(EAs)
CCR
N
General register (destination)*
General register (source)*
General register*
General register (32-bit register or address register)
Destination operand
Source operand
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Program counter
Z
V
C
PC
SP
#IMM
disp
+
Stack pointer
Immediate data
Displacement
Addition
–
Subtraction
×
Multiplication
÷
Division
AND logical
OR logical
Exclusive OR logical
Move
→
¬
NOT (logical complement)
3-, 8-, 16-, or 24-bit length
:3/:8/:16/:24
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
26
Table 2-3 Data Transfer Instructions
Instruction Size* Function
MOV
B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
MOVTPE
POP
B
(EAs) → Rd
Cannot be used in the H8/3001.
Rs → (EAs)
B
Cannot be used in the H8/3001.
@SP+ → Rn
W/L
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W
Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
27
Table 2-4 Arithmetic Operation Instructions
Instruction Size* Function
ADD,
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from data in a general register. Use the SUBX or ADD
instruction.)
ADDX,
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general
registers, or on immediate data and data in a general register.
INC,
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only.)
ADDS,
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Rd decimal adjust → Rd
DAA,
DAS
B
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
MULXU
MULXS
B/W
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
28
Table 2-4 Arithmetic Operation Instructions (cont)
Instruction Size* Function
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
CMP
NEG
EXTS
B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
W/L
W/L
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
29
Table 2-5 Logic Operation Instructions
Instruction Size* Function
AND
B/W/L Rd Rs → Rd, Rd #IMM → Rd
Performs a logical AND operation on a general register and another general
register or immediate data.
OR
B/W/L Rd Rs → Rd, Rd #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR
NOT
B/W/L Rd Rs → Rd, Rd #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
B/W/L ¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2-6 Shift Instructions
Instruction Size* Function
SHAL,
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry bit.
SHLL,
SHLR
ROTL,
ROTR
ROTXL,
ROTXR
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
30
Table 2-7 Bit Manipulation Instructions
Instruction Size* Function
BSET
BCLR
BNOT
BTST
B
B
B
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower 3 bits of a general register.
BAND
B
B
C
(<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
C
[¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
31
Table 2-7 Bit Manipulation Instructions (cont)
Instruction Size* Function
BOR
B
C
(<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C
[¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR
BIXOR
B
B
C
(<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
C
[¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
32
Table 2-8 Branching Instructions
Instruction Size
Function
Bcc
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
BRA (BT)
BRN (BF)
BHI
Description
Always (true)
Never (false)
High
Condition
Always
Never
C
C
Z = 0
Z = 1
BLS
Low or same
Carry clear (high or same)
Carry set (low)
Not equal
Bcc (BHS)
BCS (BLO)
BNE
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ
Equal
BVC
Overflow clear
Overflow set
Plus
BVS
BPL
BMI
Minus
BGE
Greater or equal
Less than
N
N
Z
Z
V = 0
BLT
V = 1
BGT
Greater than
Less or equal
(N V) = 0
(N V) = 1
BLE
JMP
BSR
JSR
RTS
—
—
—
—
Branches unconditionally to a specified address
Branches to a subroutine at a specified address
Branches to a subroutine at a specified address
Returns from a subroutine
33
Table 2-9 System Control Instructions
Instruction Size* Function
TRAPA
RTE
—
Starts trap-instruction exception handling
Returns from an exception-handling routine
Causes a transition to the power-down state
(EAs) → CCR
—
SLEEP
LDC
—
B/W
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC
ORC
B
CCR #IMM → CCR
Logically ANDs the condition code register with immediate data.
CCR #IMM → CCR
B
Logically ORs the condition code register with immediate data.
CCR #IMM → CCR
XORC
NOP
B
Logically exclusive-ORs the condition code register with immediate data.
PC + 2 → PC
—
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
34
Table 2-10 Block Transfer Instruction
Instruction Size
EEPMOV.B
Function
—
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until
R4L = 0
else next;
EEPMOV.W —
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until
R4 = 0
else next;
Transfers a data block according to parameters set in general registers R4L
or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5:
ER6:
Starting source address
Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
35
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2-9 shows examples of instruction formats.
Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op rn rm
MOV.B @(d:16, Rn), Rm
EA (disp)
Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:8
Figure 2-9 Instruction Formats
36
2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag
ahead of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2-11 Addressing Modes
No.
1
Addressing Mode
Symbol
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16, ERn)/@d:24, ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
6
7
8
Absolute address
Immediate
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8, PC)/@(d:16, PC)
@@aa:8
Program-counter relative
Memory indirect
37
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
•
Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
•
Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the
resulting register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2-12 indicates the accessible
address ranges.
38
Table 2-12 Absolute Address Access Ranges
Absolute
Address
1-Mbyte Modes
16-Mbyte Modes
8 bits (@aa:8)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
16 bits (@aa:16)
24 bits (@aa:24)
H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-
extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The
first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10.
The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is
0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector
area. For further details see section 5, Interrupt Controller.
39
Reserved
Specified by @aa:8
Branch address
Figure 2-10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2-13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
40
Table 2-13 Effective Address Calculation
Addressing Mode and
No. Instruction Format
Effective Address Calculation
Effective Address
1
Register direct (Rn)
op rm rn
Operand is general
register contents
31
0
0
23
23
0
0
2
Register indirect (@ERn)
General register contents
op
r
3
4
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
31
General register contents
op
r
disp
Sign extension
disp
Register indirect with post-increment
or pre-decrement
31
0
0
23
23
0
0
Register indirect with post-increment
@ERn+
General register contents
1, 2, or 4
op
r
31
Register indirect with pre-decrement
@–ERn
General register contents
1, 2, or 4
op
r
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Table 2-13 Effective Address Calculation (cont)
Addressing Mode and
No. Instruction Format
Effective Address Calculation
Effective Address
23
8 7
0
0
0
5
Absolute address
@aa:8
H'FFFF
op
abs
23 16 15
Sign
@aa:16
extension
op
abs
23
@aa:24
op
abs
6
7
Immediate
#xx:8, #xx:16, or #xx:32
Operand is immediate data
op
IMM
Program-counter relative
@(d:8, PC) or @(d:16, PC)
23
0
PC contents
23
0
Sign
extension
disp
op
disp
Table 2-13 Effective Address Calculation (cont)
Addressing Mode and
No. Instruction Format
Effective Address Calculation
Effective Address
8
Memory indirect
@@aa:8
op
abs
23
8 7
0
0
abs
H'0000
31
23
0
Memory contents
Legend
r, rm, rn: Register field
op:
Operation field
Displacement
Immediate data
Absolute address
disp:
IMM:
abs:
2.8 Processing States
2.8.1 Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing
states. Figure 2-13 indicates the state transitions.
Processing states
Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
Bus-released state
The external bus has been released in response to a bus request
signal from a bus master other than the CPU
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Power-down state
Sleep mode
The CPU is halted to conserve power
Software standby mode
Hardware standby mode
Figure 2-11 Processing States
44
2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2-14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts immediately
when RES changes from low to high
Interrupt
End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Trap instruction
When TRAPA instruction Exception handling starts when a trap
is executed (TRAPA) instruction is executed
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2-12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
45
Reset
External interrupts
Exception
sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2-12 Classification of Exception Sources
End of bus release
Bus request
Program execution state
End of bus
SLEEP
release
instruction
Bus
with SSBY = 0
request
Exception
Bus-released state
Sleep mode
End of
exception
handling
SLEEP instruction
with SSBY = 1
Interrupt
NMI, IRQ0, IRQ 1,
or IRQ4 interrupt
Exception-handling state
Software standby mode
RES = 1
STBY= 1, RES = 0
Reset state*1
Hardware standby mode*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2-13 State Transitions
46
2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2-14 shows the stack after the exception-handling sequence.
CCR
PC
SP–4
SP–3
SP (ER7)
SP+1
SP–2
SP+2
SP–1
SP+3
Stack area
SP (ER7)
SP+4
Even
address
Before exception
handling starts
After exception
handling ends
Pushed on stack
Legend
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2-14 Stack Structure after Exception Handling
47
2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus master other than the CPU is the external bus master. While the bus is released, the CPU
halts except for internal operations. Interrupt requests are not accepted. For details see section
6.3.7, Bus Arbiter Operation
2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The
I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
2.8.7 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 14, Power-Down State.
48
2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2-15 shows the on-chip memory access cycle. Figure 2-16 indicates the pin
states.
Bus cycle
T1 state
T2 state
ø
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Write data
Internal write signal
Internal data bus
(write access)
Figure 2-15 On-Chip Memory Access Cycle
49
T1
T2
ø
Address bus
Address
AS, RD, HWR, LWR
High
High impedance
D15 to D0
Figure 2-16 Pin States during On-Chip Memory Access
50
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2-17 shows the on-chip supporting module
access timing. Figure 2-18 indicates the pin states.
Bus cycle
T1 state
T2 state
T3 state
ø
Address
Address bus
Internal read signal
Internal data bus
Read
access
Read data
Internal write signal
Internal data bus
Write
access
Write data
Figure 2-17 Access Cycle for On-Chip Supporting Modules
51
T1
T2
T3
ø
Address bus
Address
AS, RD, HWR, LWR
High
High impedance
D15 to D0
Figure 2-18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
52
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3001 has four operating modes (modes 1 to 4) that are selected by the mode pins (MD to
2
MD ) as indicated in table 3-1. The input at these pins determines the size of the address space
0
and the initial bus mode.
Table 3-1 Operating Mode Selection
Mode Pins
Description
Operating Mode MD2 MD1 MD0 Address Space
Initial Bus Mode*1
On-Chip RAM
—
—
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
—
Mode 1
Mode 2
Mode 3
Mode 4
—
1 Mbyte
1 Mbyte
16 Mbytes
16 Mbytes
—
8 bits
16 bits
8 bits
16 bits
—
Enabled*2
Enabled*2
Enabled*2
Enabled*2
—
—
—
—
—
—
—
—
—
Notes: 1. In all modes, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings
made in the area bus width control register (ABWCR). For details see section 6, Bus
Controller.
2. If the RAM enable bit (RAME) in the system control register (SYSCR) is cleared to 0,
these addresses become external addresses.
For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is
either 8 or 16 bits wide depending on the settings in the area bus width control register (ABWCR).
If 8-bit access is selected for all areas, the external data bus is 8 bits wide. For details see
section 6, Bus Controller.
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a
maximum address space of 16 Mbytes.
The H8/3001 can only be used in modes 1 to 4. The inputs at the mode pins must select one of
these four modes. The inputs at the mode pins must not be changed during operation.
53
3.1.2 Register Configuration
The H8/3001 has a mode control register (MDCR) that indicates the inputs at the mode pins
(MD to MD ), and a system control register (SYSCR). Table 3-2 summarizes these registers.
2
0
Table 3-2 Registers
Address*
H'FFF1
Name
Abbreviation
MDCR
R/W
R
Initial Value
Undetermined
H'0B
Mode control register
System control register
H'FFF2
SYSCR
R/W
Note: * The lower 16 bits of the address are indicated.
54
3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3001.
Bit
7
—
1
6
—
1
5
—
0
4
—
0
3
—
0
2
MDS2
—*
1
MDS1
—*
0
MDS0
—*
Initial value
Read/Write
—
—
—
—
—
R
R
R
Reserved bits
Reserved bits
Mode select 2 to 0
Bits indicating the current
operating mode
Note: * Determined by pins MD2 to MD0.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD to MD (the current operating mode). MDS2 to MDS0 correspond to MD to MD . MDS2
2
0
2
0
to MDS0 are read-only bits. The mode pin (MD to MD ) levels are latched when MDCR is read.
2
0
55
3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3001.
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
UE
1
2
NMIEG
0
1
—
1
0
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use UI bit in CCR 6
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 14, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY
Description
0
1
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
56
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
least 8 ms at the system clock rate. For further information about waiting time selection, see
section 14.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
0
1
1
0
0
1
1
0
1
0
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Illegal setting
(Initial value)
1
0
1
—
—
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as an interrupt mask bit
UI bit in CCR is used as a user bit
1
(Initial value)
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0
1
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
1
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
57
3.4 Operating Mode Descriptions
3.4.1 Mode 1
Address pins A to A are enabled, permitting access to a maximum 1-Mbyte address space. The
19
0
initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Address pins A to A are enabled, permitting access to a maximum 1-Mbyte address space. The
19
0
initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated
for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Address pins A to A are enabled, permitting access to a maximum 16-Mbyte address space.
23
0
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.4 Mode 4
Address pins A to A are enabled, permitting access to a maximum 16-Mbyte address space.
23
0
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are
designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
58
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 4 and A vary depending on the operating mode. Table 3-3 indicates
their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port
Mode 1
Mode 2
Mode 3
Mode 4
Port 4
P47 to P40*
D7 to D0*
P47 to P40*
D7 to D0*
Port A PA7/TP7/TIOCB2 PA7/TP7/TIOCB2
PA6/TP6/TIOCA2 PA6/TP6/TIOCA2
PA5/TP5/TIOCB1 PA5/TP5/TIOCB1
PA4/TP4/TIOCA1 PA4/TP4/TIOCA1
A20
A21
A22
A23
A20
A21
A22
A23
Note: * Initial state. The bus mode can be switched by settings in ABWCR.
These pins function as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
3.6 Memory Map in Each Operating Mode
Figure 3-1 shows a memory map for modes 1 to 4. The address space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address
locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1
and 2) and 16-Mbyte modes (modes 3 and 4). The address range specifiable by the CPU in its 8-
and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
59
Modes 1 and 2 (1-Mbyte modes)
Vector table
Modes 3 and 4 (16-Mbyte modes)
Vector table
H'00000
H'07FFF
H'000000
H'007FFFF
16-bit
16-bit
absolute
addresses
absolute
addresses
Area 0
Area 1
Area 2
Area 0
Area 1
H'1FFFF
H'20000
H'3FFFF
H'40000
H'1FFFFF
H'200000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'3FFFFF
H'400000
External address space
Area 3
Area 4
Area 5
Area 6
Area 7
Area 2
H'5FFFFF
H'600000
External address
Area 3
space
H'DFFFF
H'E0000
H'7FFFFF
H'800000
Area 4
Area 5
Area 6
Area 7
H'9FFFFF
H'A00000
H'F8000
H'FFD0F
H'FFD10
H'BFFFFF
H'C00000
On-chip RAM*
16-bit
absolute
addresses
H'FFF00
H'FFF0F
H'FFF10
H'DFFFFF
H'E00000
External address
space
8-bit
absolute
addresses
H'FFF1B
H'FFF1C
On-chip registers
H'FF8000
F'FFFFF
H'FFFD0F
H'FFFD10
On-chip RAM*
16-bit
absolute
addresses
H'FFFF00
H'FFFF0F
H'FFFF10
External address
8-bit
space
absolute
H'FFFF1B
H'FFFF1C
addresses
On-chip registers
H'FFFFFF
Note: * External addresses can be accessed by clearing the RAME bit to 0 in the system control register (SYSCR).
Figure 3-1 Memory Map in Each Operating Mode
60
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES pin
Interrupt
Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
Low
Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
61
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vectors are assigned to
different exception sources. Table 4-2 lists the exception sources and their vector addresses.
• Reset
External interrupts: NMI, IRQ0, IRQ1, and IRQ4
Exception
• Interrupts
sources
Internal interrupts: 20 interrupts from on-chip
supporting modules
• Trap instruction
Figure 4-1 Exception Sources
Table 4-2 Exception Vector Table
Exception Source
Reset
Vector Number
Vector Address*1
H'0000 to H'0003
H'0004 to H'0007
H'0008 to H'000B
H'000C to H'000F
H'0010 to H'0013
H'0014 to H'0017
H'0018 to H'001B
H'001C to H'001F
H'0020 to H'0023
H'0024 to H'0027
H'0028 to H'002B
H'002C to H'002F
H'0030 to H'0033
H'0034 to H'0037
H'0038 to H'003B
H'003C to H'003F
H'0040 to H'0043
H'0044 to H'0047
H'0048 to H'004B
H'004C to H'004F
0
Reserved for system use
1
2
3
4
5
6
External interrupt (NMI)
7
Trap instruction (4 sources)
8
9
10
11
12
13
14
15
16
17
18
19
External interrupt IRQ0
External interrupt IRQ1
External interrupt Reserved for system use
External interrupt Reserved for system use
External interrupt Reserved for system use
External interrupt Reserved for system use
External interrupt Reserved for system use
External interrupt Reserved for system use
Internal interrupts*2
20
to
H'0050 to H'0053
to
60
H'00F0 to H'00F3
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
62
4.2 Reset
4.2.1 Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
H8/3001 enters the reset state. A reset initializes the internal state of the CPU and the registers of
the on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
4.2.2 Reset Sequence
The H8/3001 enters the reset state when the RES pin goes low.
To ensure that the H8/3001 is reset, hold the RES pin low for at least 20 ms at power-up. To reset
the H8/3001 during operation, hold the RES pin low for at least 10 system clock (ø) cycles. See
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the H8/3001 starts reset
exception handling as follows.
•
•
The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
The contents of the reset vector address (H'0000 to H'0003) are read, and program execution
starts from the address indicated in the vector address.
Figure 4-2 shows the reset sequence in modes 1 and 3. Figure 4-3 shows the reset sequence in
modes 2 and 4.
63
Internal
processing
Vector fetch
Prefetch of
first program
instruction
ø
RES
Address
bus
(1)
(3)
(5)
(7)
(9)
RD
High
HWR, LWR
(2)
(4)
(6)
(8)
(10)
D15 to D8
(1), (3), (5), (7) Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003
(2), (4), (6), (8) Start address (contents of reset vector)
(9)
Start address
(10)
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Internal
Vector fetch
processing
Prefetch of first
program instruction
ø
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
High
(2)
(4)
(6)
D15 to D0
(1), (3) Address of reset vector: (1) = H'00000, (3) = H'00002
(2), (4) Start address (contents of reset vector)
(5)
(6)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4-3 Reset Sequence (Modes 2 and 4)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
65
4.3 Interrupts
Interrupt exception handling can be requested by four external sources (NMI, IRQ , IRQ , and
0
1
IRQ ) and 20 internal sources in the on-chip supporting modules. Figure 4-4 classifies the
4
interrupt sources and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the 16-bit integrated timer unit
(ITU), serial communication interface (SCI), and A/D converter. Each interrupt source has a
separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
NMI (1)
External interrupts
IRQ0, IRQ1, IRQ4 (3)
Interrupts
ITU (15)
Internal interrupts
SCI (4)
A/D converter (1)
Note: Numbers in parentheses are the number of interrupt sources.
Figure 4-4 Interrupt Sources and Number of Interrupts
66
4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
PC
SP
Note: In modes 1 and 2 only 20 PC bits are valid; the upper 4 bits are ignored.
Figure 4-5 Stack after Completion of Exception Handling
67
4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3001 regards the lowest address bit as 0. The
stack should always be accessed by word access or longword access, and the value of the stack
pointer (SP, ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what
happens when the SP value is odd.
CCR
PC
SP
RIL
PC
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
SP
H'FFFEFF
SP
TRAPA instruction executed
MOV. B RIL, @-ER7
SP set to H'FFFEFF
Data saved above SP
CCR contents lost
Legend
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: The diagram illustrates modes 3 and 4.
Figure 4-6 Operation when SP Value is Odd
68
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
•
Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
•
•
Three-level masking by the I and UI bits in the CPU condition code register (CCR)
Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
•
Four external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ , IRQ , and IRQ sensing of the falling edge or level sensing can
0
1
4
be selected independently.
69
5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the interrupt controller.
CPU
ISCR
IER
IPRA, IPRB
NMI
input
IRQ input
section ISR
IRQ input
IMIA0
Interrupt
request
Priority
IMIEA0
decision logic
.
.
.
.
.
.
.
Vector
number
.
.
.
ADI
ADIE
I
CCR
UI
Interrupt controller
UE
SYSCR
Legend
I:
Interrupt mask bit
IRQ enable register
Interrupt priority register A
Interrupt priority register B
IRQ sense control register
IRQ status register
IER:
IPRA:
IPRB:
ISCR:
ISR:
SYSCR: System control register
UE:
UI:
User bit enable
User bit/interrupt mask bit
Figure 5-1 Interrupt Controller Block Diagram
70
5.1.3 Pin Configuration
Table 5-1 lists the interrupt pins.
Table 5-1 Interrupt Pins
Name
Abbreviation I/O
NMI Input
Function
Nonmaskable interrupt
Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt request 0, 1, 4 IRQ0, IRQ1,
IRQ4
Input
Maskable interrupts, falling edge or
level sensing selectable
5.1.4 Register Configuration
Table 5-2 lists the registers of the interrupt controller.
Table 5-2 Interrupt Controller Registers
Address*1
H'FFF2
H'FFF4
H'FFF5
H'FFF6
H'FFF8
H'FFF9
Name
Abbreviation
SYSCR
ISCR
R/W
R/W
R/W
R/W
Initial Value
H'0B
System control register
IRQ sense control register
IRQ enable register
IRQ status register
H'00
IER
H'00
ISR
R/(W)*2 H'00
Interrupt priority register A
Interrupt priority register B
IPRA
R/W
R/W
H'00
H'00
IPRB
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
71
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
UE
1
2
NMIEG
0
1
—
0
RAME
1
Initial value
Read/Write
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Reserved bit
NMI edge select
Selects the NMI input edge
Standby timer
select 2 to 0
Software standby
User bit enable
Selects whether to use CCR bit 6
as a user bit or interrupt mask bit
72
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as interrupt mask bit
UI bit in CCR is used as user bit
1
(Initial value)
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0
1
Interrupt is requested at falling edge of NMI input
Interrupt is requested at rising edge of NMI input
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
73
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
IPRA7
0
6
IPRA6
0
5
—
4
IPRA4
0
3
—
2
IPRA2
0
1
0
IPRA1 IPRA0
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Reserved bit
Priority level A4
Selects the priority level of IRQ4
interrupt requests
Reserved bit
Priority level A6
Selects the priority level of IRQ1 interrupt requests
Priority level A7
Selects the priority level of IRQ0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
74
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests.
0
Bit 7
IPRA7 Description
0
1
IRQ0 interrupt requests have priority level 0 (low priority)
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
1
Bit 6
IPRA6 Description
0
1
IRQ1 interrupt requests have priority level 0 (low priority)
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ interrupt requests.
4
Bit 4
IPRA4 Description
0
1
IRQ4 interrupt requests have priority level 0 (low priority)
IRQ4 interrupt requests have priority level 1 (high priority)
(Initial value)
75
Bit 3—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Bit 2
IPRA2 Description
0
1
ITU channel 0 interrupt requests have priority level 0 (low priority)
ITU channel 0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Bit 1
IPRA1 Description
0
1
ITU channel 1 interrupt requests have priority level 0 (low priority)
ITU channel 1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Bit 0
IPRA0 Description
0
1
ITU channel 2 interrupt requests have priority level 0 (low priority)
ITU channel 2 interrupt requests have priority level 1 (high priority)
(Initial value)
76
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
IPRB7
0
6
IPRB6
0
5
—
4
—
3
IPRB3
0
2
—
1
IPRB1
0
0
—
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Priority level B1
Selects the priority level
of A/D converter
interrupt request
Reserved bit
Priority level B3
Selects the priority level of SCI
interrupt requests
Reserved bit
Priority level B6
Selects the priority level of ITU channel 4 interrupt requests
Priority level B7
Selects the priority level of ITU channel 3 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
77
Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests.
Bit 7
IPRB7 Description
0
1
ITU channel 3 interrupt requests have priority level 0 (low priority)
ITU channel 3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Bit 6
IPRB6 Description
0
1
ITU channel 4 interrupt requests have priority level 0 (low priority)
ITU channel 4 interrupt requests have priority level 1 (high priority)
(Initial value)
Bits 5 and 4—Reserved: These bits can be written and read, but they do not affect interrupt
priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI interrupt requests.
Bit 3
IPRB3 Description
0
1
SCI interrupt requests have priority level 0 (low priority)
SCI interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 2—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.
Bit 1
IPRB1 Description
0
1
A/D converter interrupt requests have priority level 0 (low priority)
A/D converter interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
78
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ , IRQ , and IRQ
0
4
1
interrupt requests.
Bit
7
—
0
6
—
0
5
—
0
4
3
—
0
2
1
0
IRQ4F
0
—
0
IRQ1F IRQ0F
Initial value
Read/Write
0
0
—
—
—
R/(W)*
—
—
R/(W)* R/(W)*
Reserved bit
IRQ4, IRQ1, IRQ0 flags
These bits indicate IRQ4, IRQ1,
and IRQ0 interrupt request status
Reserved bits
Note: * Only 0 can be written, to clear flags.
Bits 7 to 5, 3, 2—Reserved: Read-only bits, always read as 0.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 4, 1, 0—IRQ , IRQ , IRQ Flags (IRQ4F, IRQ1F, IRQ0F): These bits indicate the status
4
1
0
of IRQ , IRQ , and IRQ interrupt requests.
4
1
0
Bit n
IRQnF
Description
0
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 4, 1, 0
79
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ , IRQ , IRQ interrupt
4
1
0
requests.
Bit
7
—
6
—
5
—
4
IRQ4E
0
3
—
2
—
1
0
IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
IRQ4, IRQ1, IRQ0 enable
These bits enable or disable IRQ4, IRQ1,
and IRQ0 interrupts
Reserved bits
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5, 3, 2—Reserved: Although reserved, these bits can be written and read.
Bits 4, 1, 0—IRQ , IRQ , IRQ Enable (IRQ4E, IRQ1E, IRQ0E): These bits enable or disable
4
1
0
IRQ , IRQ , and IRQ interrupts.
4
1
0
Bit n
IRQnE
Description
0
1
IRQn interrupts are disabled
IRQn interrupts are enabled
(Initial value)
Note: n = 4, 1, 0
80
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ , IRQ , IRQ .
4
1
0
Bit
7
—
6
—
5
—
4
IRQ4SC
0
3
—
2
—
1
0
IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ4, IRQ1, IRQ0 sense control
These bits select level sensing or falling-edge
sensing for IRQ4, IRQ1, and IRQ0
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5, 3, 2—Reserved: Although reserved, these bits can be written and read.
Bits 4, 1, 0—IRQ , IRQ , IRQ Sense Control (IRQ4SC, IRQ1SC, IRQ0SC): These bits
4
1
0
selects whether interrupts IRQ , IRQ , IRQ are requested by level sensing of pins IRQ , IRQ ,
4
1
0
4
1
IRQ ,or by falling-edge sensing.
0
Bit n
IRQnSC
Description
0
Interrupts are requested when IRQn input is low
(Initial value)
1
Interrupts are requested by falling-edge input at IRQn
Note: n = 4, 1, 0
81
5.3 Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ , IRQ , IRQ ) and 20 internal
0
1
4
interrupts.
5.3.1 External Interrupts
There are four external interrupts: NMI, IRQ , IRQ , and IRQ . Of these, NMI, IRQ , and IRQ
1
0
1
4
0
can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ , IRQ , and IRQ Interrupts: These interrupts are requested by input signals at pins IRQ ,
0
1
4
0
IRQ , and IRQ . These interrupts have the following features.
1
4
•
•
•
ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ , IRQ , and IRQ , or by the falling edge.
0
1
4
IER settings can enable or disable the IRQ , IRQ , IRQ , interrupts. Interrupt priority levels
0
1
4
can be assigned by four bits in IPRA (IPRA7, IPRA6, and IPRA4).
The status of IRQ , IRQ , and IRQ interrupt requests is indicated in ISR. The ISR flags can
0
1
4
be cleared to 0 by software.
Figure 5-2 shows a block diagram of interrupts IRQ , IRQ , and IRQ .
0
1
4
IRQnSC
IRQnE
IRQnF
IRQn interrupt
request
Edge/level
sense circuit
S
R
Q
IRQn input
Clear signal
Note: n = 0, 1, 4
Figure 5-2 Block Diagram of Interrupts IRQ , IRQ , and IRQ
0
1
4
82
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF).
ø
IRQn
input pin
IRQnF
Note: n = 0, 1, 4
Figure 5-3 Timing of Setting of IRQnF
Interrupts IRQ , IRQ , and IRQ , have vector numbers 12, 13, and 16. These interrupts are
0
1
4
detected regardless of whether the corresponding pin is set for input or output. When using a pin
for external interrupt input, clear its DDR bit to 0. When using the IRQ interrupt, do not use the
4
IRQ pin for SCI input or output.
4
5.3.2 Internal Interrupts
Twenty internal interrupts are requested from the on-chip supporting modules.
•
Each on-chip supporting module has status flags for indicating interrupt status, and enable
bits for enabling or disabling interrupts.
•
Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3 Interrupt Vector Table
Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5-3.
83
Table 5-3 Interrupt Sources, Vector Addresses, and Priority
Vector
Interrupt Source
NMI
Origin
Number Vector Address* IPR
Priority
External pins
7
H'001C to H'001F
—
High
IRQ0
12
13
14
15
16
17
18
19
20
21
22
23
24
H'0030 to H'0033 IPRA7
H'0034 to H0037 IPRA6
IRQ1
Reserved
—
H'0038 to H'003B
H'003C to H'003F
H'0040 to H'0043
H'0044 to H'0047
H'0048 to H'004B
H'004C to H'004F
H'0050 to H'0053
H'0054 to H'0057
H'0058 to H'005B
H'005C to H'005F
—
IRQ4
External pin
—
Reserved
—
IMIA0 (compare match/input ITU channel 0
capture A0)
H'0060 to H'0063 IPRA2
IMIB0 (compare match/input
capture B0)
25
H'0064 to H'0067
OVI0 (overflow 0)
26
27
28
H'0068 to H'006B
Reserved
—
H'006C to H'006F
IMIA1 (compare match/input ITU channel 1
capture A1)
H'0070 to H'0073 IPRA1
IMIB1 (compare match/input
capture B1)
29
H'0074 to H'0077
OVI1 (overflow 1)
30
31
32
H'0078 to H'007B
Reserved
—
H'007C to H'007F
IMIA2 (compare match/input ITU channel 2
capture A2)
H'0080 to H'0083 IPRA0
IMIB2 (compare match/input
capture B2)
33
H'0084 to H'0087
OVI2 (overflow 2)
34
35
H'0088 to H'008B
H'008C to H'008F
Reserved
—
Low
Note: * Lower 16 bits of the address.
84
Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont)
Vector
Interrupt Source
Origin
Number Vector Address* IPR
Priority
IMIA3 (compare match/input ITU channel 3
capture A3)
36
H'0090 to H'0093 IPRB7 High
IMIB3 (compare match/input
capture B3)
37
H'0094 to H'0097
OVI3 (overflow 3)
38
39
40
H'0098 to H'009B
Reserved
—
H'009C to H'009F
IMIA4 (compare match/input ITU channel 4
capture A4)
H'00A0 to H'00A3 IPRB6
IMIB4 (compare match/input
capture B4)
41
H'00A4 to H'00A7
OVI4 (overflow 4)
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
H'00A8 to H'00AB
H'00AC to H'00AF
Reserved
Reserved
—
—
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
—
ERI (receive error)
RXI (receive data full)
TXI (transmit data empty)
TEI (transmit end)
Reserved
SCI
—
H'00D0 to H'00D3 IPRB3
H'00D4 to H'00D7
H'00D8 to H'00DB
H'00DC to H'00DF
H'00E0 to H'00E3
H'00E4 to H'00E7
H'00E8 to H'00EB
H'00EC to H'00EF
—
ADI (A/D end)
A/D
H'00F0 to H'00F3 IPRB1 Low
Note: * Lower 16 bits of the address.
85
5.4 Interrupt Operation
5.4.1 Interrupt Handling Process
The H8/3001 handles interrupts differently depending on the setting of the UE bit. When UE = 1,
interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I, and
UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ
interrupts and interrupts from the on-chip supporting modules have their own enable bits.
Interrupt requests are ignored when the enable bits are cleared to 0.
Table 5-4 UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
CCR
UI
UE
I
Description
1
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
—
—
No interrupts are accepted except NMI.
0
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
1
NMI and interrupts with priority level 1 are accepted.
No interrupts are accepted except NMI.
UE = 1: Interrupts IRQ , IRQ , and IRQ and interrupts from the on-chip supporting modules can
0
1
4
all be masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority.
Figure 5-4 is a flowchart showing how interrupts are accepted when UE = 1.
86
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
No
No
IRQ0
Yes
IRQ0
Yes
No
No
IRQ1
Yes
IRQ1
Yes
ADI
Yes
ADI
Yes
No
I = 0
Yes
Save PC and CCR
←
I
1
Read vector address
Branch to interrupt
service routine
Figure 5-4 Process Up to Interrupt Acceptance when UE = 1
87
•
•
If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests
pending. If two or more interrupts with the same IPR setting are requested simultaneously, the
interrupt controller follows the priority order shown in table 5-3.
•
The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt
request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are
held pending.
•
•
When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from
the interrupt service routine.
•
•
Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ ,
0
IRQ , and IRQ interrupts and interrupts from the on-chip supporting modules.
1
4
•
Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
•
Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1,
and are unmasked when either the I bit or the UI bit is cleared to 0.
For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'10, and IPRB is set to H'00 (giving IRQ interrupt request priority over other interrupts),
4
interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ > IRQ >IRQ …).
4
0
1
b. If I = 1 and UI = 0, only NMI and IRQ are unmasked.
4
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
88
Figure 5-5 shows the transitions among the above states.
←
I
0
a. All interrupts are
unmasked
b. Only NMI, and IRQ4
are unmasked
←
←
0
I
1, UI
Exception handling,
←
←
1
or I 1, UI
←
←
0
I
0
UI
Exception handling,
←
or UI
1
c. All interrupts are
masked except NMI
Figure 5-5 Interrupt Masking State Transitions (Example)
Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0.
•
•
If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests
pending. If two or more interrupts with the same IPR setting are requested simultaneously, the
interrupt controller follows the priority order shown in table 5-3.
•
The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt
request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set
to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted;
interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to
1, only NMI is accepted; all other interrupt requests are held pending.
•
•
When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from
the interrupt service routine.
•
•
The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
89
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
No
No
IRQ0
Yes
IRQ0
Yes
No
No
IRQ1
Yes
IRQ1
Yes
ADI
Yes
ADI
Yes
No
No
I = 0
I = 0
Yes
Yes
Yes
No
UI = 0
Save PC and CCR
←
←
1
I
1, UI
Read vector address
Branch to interrupt
service routine
Figure 5-6 Process Up to Interrupt Acceptance when UE = 0
90
Interrupt accepted
Prefetch of
interrupt
service routine
Interrupt level
decision and wait
for end of instruction prefetch
Instruction Internal
processing
Internal
Stack
Vector fetch
processing instruction
ø
Interrupt
request
signal
(1)
(3)
(5)
(7)
(9)
(11)
(13)
A19 to A0
RD
HWR, LWR
High
(4)
(2)
(6)
(8)
(10)
(12)
(14)
D15 to D0
(1)
Instruction prefetch address (not executed;
return address, same as PC contents)
(6), (8)
(9), (11) Vector address
PC and CCR saved to stack
(2), (4) Instruction code (not executed)
(10), (12) Starting address of interrupt service routine (contents of
vector address)
(3)
(5)
(7)
Instruction prefetch address (not executed)
SP – 2
SP – 4
(13)
(14)
Starting address of interrupt service routine; (13) = (10), (12)
First instruction of interrupt service routine
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
5.4.3 Interrupt Response Time
Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until
the first instruction of the interrupt service routine is executed.
Table 5-5 Interrupt Response Time
External Memory
8-Bit Bus
2 States 3 States
16-Bit Bus
2 States 3 States
On-Chip
Memory
No. Item
1
2
Interrupt priority decision
2*1
2*1
2*1
2*1
2*1
Maximum number of states
until end of current instruction
1 to 23
1 to 27
1 to 31*4
1 to 23
1 to 25*4
3
Saving PC and CCR to stack
Vector fetch
4
8
12*4
12*4
12*4
4
4
6*4
4
4
8
4
6*4
5
Instruction prefetch*2
Internal processing*3
4
8
4
6*4
6
4
4
4
4
Total
19 to 41
31 to 57
43 to 73
19 to 41
25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
92
5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU.
TIER write cycle by CPU
IMIA exception handling
ø
Internal
address bus
TIER address
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
93
5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs,
after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the
CPU is currently executing one of these interrupt-inhibiting instructions, however, when the
instruction is completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
94
Section 6 Bus Controller
6.1 Overview
The H8/3001 has an on-chip bus controller that divides the address space into eight areas and can
assign different bus specifications to each. This enables different types of memory to be connected
easily.
A bus arbitration function of the bus controller can release the bus to an external device.
6.1.1 Features
Features of the bus controller are listed below.
•
•
•
Independent settings for address areas 0 to 7
— 128-kbyte areas in 1-Mbyte modes; 2-Mbyte areas in 16-Mbyte modes.
— Areas can be designated for 8-bit or 16-bit access.
— Areas can be designated for two-state or three-state access.
Four wait modes
— Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be
selected.
— Zero to three wait states can be inserted automatically.
Bus arbitration function
— A built-in bus arbiter grants the bus right to the CPU or an external bus master.
95
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
ABWCR
Internal
address bus
ASTCR
Area
decoder
WCER
Internal signals
Bus mode control signal
Bus control
circuit
Bus size control signal
Access state control signal
Wait request signal
Wait-state
controller
WAIT
WCR
BRCR
Internal signals
CPU bus request signal
Bus arbiter
CPU bus acknowledge signal
BACK
BREQ
Legend
ABWCR: Bus width control register
ASTCR: Access state control register
WCER: Wait state controller enable register
WCR:
Wait control register
BRCR: Bus release control register
Figure 6-1 Block Diagram of Bus Controller
96
6.1.3 Input/Output Pins
Table 6-1 summarizes the bus controller’s input/output pins.
Table 6-1 Bus Controller Pins
Name
Abbreviation I/O
Function
Address strobe
AS
Output Strobe signal indicating valid address output on the
address bus
Read
RD
Output Strobe signal indicating reading from the external
address space
High write
HWR
Output Strobe signal indicating writing to the external
address space, with valid data on the upper data
bus (D15 to D8)
Low write
LWR
Output Strobe signal indicating writing to the external
address space, with valid data on the lower data
bus (D7 to D0)
Wait
WAIT
BREQ
BACK
Input
Wait request signal for access to external three-
state-access areas
Bus request
Bus acknowledge
Input
Request signal for releasing the bus to an external
device
Output Acknowledge signal indicating the bus is released
to an external device
6.1.4 Register Configuration
Table 6-2 summarizes the bus controller’s registers.
Table 6-2 Bus Controller Registers
Initial Value
Abbrevi
ation
Address* Name
R/W Modes 1 & 3 Modes 2 & 4
H'FFEC
H'FFED
H'FFEE
H'FFEF
H'FFF3
Bus width control register
Access state control register
Wait control register
ABWCR R/W H'FF
H'00
H'FF
H'F3
H'FF
H'FE
ASTCR
WCR
R/W H'FF
R/W H'F3
R/W H'FF
R/W H'FE
Wait state controller enable register
Bus release control register
WCER
BRCR
Note: * Lower 16 bits of the address.
97
6.2 Register Descriptions
6.2.1 Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit
7
ABW7
1
6
ABW6
1
5
ABW5
1
4
ABW4
1
3
ABW3
1
2
ABW2
1
1
ABW1
1
0
ABW0
1
Modes 1, 3
Modes 2, 4
Initial
value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits selecting bus width for each area
When ABWCR contains H'FF (selecting 8-bit access for all areas), the H8/3001 operates in 8-bit
bus mode: the upper data bus (D to D ) is valid, and port 4 is an input/output port. When at least
15
8
one bit is cleared to 0 in ABWCR, the H8/3003 operates in 16-bit bus mode with a 16-bit data bus
(D to D ). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby
15
0
mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.
ABWCR is not initialized in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access to the corresponding address areas.
Bits 7 to 0
ABW7 to ABW0
Description
0
1
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and
registers is fixed and does not depend on ABWCR settings.
98
6.2.2 Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
7
AST7
1
6
AST6
1
5
AST5
1
4
AST4
1
3
AST3
1
2
AST2
1
1
AST1
1
0
AST0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
Description
0
1
Areas 7 to 0 are accessed in two states
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
99
6.2.3 Wait Control Register (WCR)
WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller
(WSC) and specifies the number of wait states.
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
WC1
1
0
WC0
1
WMS1 WMS0
Initial value
Read/Write
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Wait count 1/0
These bits select the
number of wait states
inserted
Wait mode select 1/0
These bits select the wait mode
WCR is initialized to H'F3 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3
Bit 2
WMS1 WMS0 Description
0
1
0
1
0
1
Programmable wait mode
No wait states inserted by wait-state controller
Pin wait mode 1
(Initial value)
Pin auto-wait mode
100
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external three-state-access areas.
Bit 1
WC1
Bit 0
WC0
Description
0
0
1
0
1
No wait states inserted by wait-state controller
1 state inserted
1
2 states inserted
3 states inserted
(Initial value)
6.2.4 Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that enables or disables wait-state control of external
three-state-access areas by the wait-state controller.
Bit
7
WCE7
1
6
5
4
3
2
WCE2
1
1
0
WCE6 WCE5
WCE4 WCE3
WCE1 WCE0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wait state controller enable 7 to 0
These bits enable or disable wait-state control
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0
WCE7 to WCE0 Description
0
1
Wait-state control disabled (pin wait mode 0)
Wait-state control enabled
(Initial value)
101
6.2.5 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables or disables release of the bus to an
external device.
Bit
7
—
6
—
5
—
4
3
2
1
0
BRLE
0
—
1
—
1
—
1
—
1
Initial valeu
1
1
1
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
Modes 1, 2
Read/
Write
R/W
R/W
R/W
Modes 3, 4
Bus release enable
Enables or disables
release of the bus to
an external device
Reserved bits
Reserved bits
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5—Reserved: In modes 1 and 2, these are read-only bits that always read 1. In modes 3
and 4, they can be written and read.
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
Description
0
The bus cannot be released to an external device; BREQ and BACK
can be used as input/output pins
(Initial value)
1
The bus can be released to an external device
102
6.3 Operation
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general view of the
memory map.
H'00000
H'000000
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
H'1FFFF
H'20000
H'1FFFFF
H'200000
H'3FFFF
H'40000
H'3FFFFF
H'400000
H'5FFFF
H'60000
H'5FFFFF
H'600000
H'7FFFF
H'80000
H'7FFFFF
H'800000
H'9FFFF
H'A0000
H'9FFFFF
H'A00000
H'BFFFF
H'C0000
H'BFFFFF
H'C00000
H'DFFFF
H'E0000
H'DFFFFF
H'E00000
Area 7 (128 kbytes)
On-chip RAM*1,*2
Area 7 (2 Mbytes)
On-chip RAM*1,*2
External address space*3
On-chip registers*1
External address space*3
On-chip registers*1
H'FFFFF
H'FFFFFF
a. 1-Mbyte modes (modes 1 and 2)
b. 16-Mbyte modes (modes 3 and 4)
Notes: 1. The on-chip RAM and on-chip registers have a fixed bus width and are accessed in a fixed
number of states.
2. When the RAME bit is cleared to 0 in SYSCR, this area conforms to the specifications of area 7.
3. The 12-byte external address space conforms to the specifications of area 7.
Figure 6-2 Access Area Map for Modes 1 to 4
103
The bus specifications for each area can be selected in ABWCR, ASTCR, WCER, and WCR as
shown in table 6-3.
Table 6-3 Bus Specifications
ABWCR ASTCR WCER
WCR
Bus Specifications
Access
States Wait Mode
Bus
WMS1 WMS0 Width
ABWn
ASTn
WCEn
0
0
1
—
0
—
—
0
—
—
0
16
16
16
16
16
16
8
2
3
3
3
3
3
2
3
3
3
3
3
Disabled
Pin wait mode 0
Programmable wait mode
Disabled
1
1
1
0
Pin wait mode 1
Pin auto-wait mode
Disabled
1
1
0
1
—
0
—
—
0
—
—
0
8
Pin wait mode 0
Programmable wait mode
Disabled
1
8
1
8
1
0
8
Pin wait mode 1
Pin auto-wait mode
1
8
Note: n = 0 to 7
104
6.3.2 Data Bus
The H8/3001 allows either 8-bit access or 16-bit access to be designated for each of areas 0 to 7.
An 8-bit-access area uses the upper data bus (D to D ). A 16-bit-access area uses both the upper
15
8
data bus (D to D ) and lower data bus (D to D ).
15
8
7
0
In read access the RD signal applies without distinction to both the upper and lower data bus. In
write access the HWR signal applies to the upper data bus, and the LWR signal applies to the
lower data bus.
Table 6-4 indicates how the two parts of the data bus are used under different access conditions.
Table 6-4 Access Conditions and Data Bus Usage
Access Read/
Valid
Upper Data Bus
(D15 to D8)
Lower Data Bus
(D7 to D0)
Area
Size
Write Address Strobe
8-bit-access
area
—
Read
Write
—
—
RD
Valid
Invalid
HWR
RD
Undetermined data
Invalid
16-bit-access
area
Byte
Read Even
Odd
Valid
Invalid
Valid
Valid
Write
Even
Odd
—
HWR
LWR
RD
Undetermined data
Undetermined data Valid
Word
Read
Write
Valid
Valid
Valid
—
HWR, LWR Valid
Note: Undetermined data means that unpredictable data is output.
Invalid means that the bus is in the input state and the input is ignored.
105
6.3.3 Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper address bus (D to D ) is used to access these areas. The LWR
15
8
pin is always high. Wait states can be inserted.
Bus cycle
T2
T1
T3
ø
Address bus
External address
AS
RD
Read
D15 to D8
Valid
access
D7 to D0
HWR
Invalid
High
LWR
Write
access
D15 to D8
D7 to D0
Valid
Undetermined data
Figure 6-3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
106
8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper address bus (D to D ) is used to access these areas. The LWR
15
8
pin is always high. Wait states cannot be inserted.
Bus cycle
T1
T2
ø
Address bus
External address
AS
RD
Read
access
D15 to D8
Valid
Invalid
D7 to D0
HWR
LWR
High
Write
access
D15 to D8
D7 to D0
Valid
Undetermined data
Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
107
16-Bit, Three-State-Access Areas: Figures 6-5 to 6-7 show the timing of bus control signals for a
16-bit, three-state-access area. In these areas, the upper address bus (D to D ) is used to access
15
8
even addresses and the lower address bus (D to D ) is used to access odd addresses. Wait states
7
0
can be inserted.
Bus cycle
T2
T1
T3
ø
Address bus
Even external address
AS
RD
Read
access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
access
D15 to D8
D7 to D0
Valid
Undetermined data
Figure 6-5 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
108
Bus cycle
T2
T1
T3
ø
Address bus
Odd external address
AS
RD
Read
access
D15 to D8
Invalid
Valid
D7 to D0
HWR
High
LWR
Write
access
D15 to D8
D7 to D0
Undetermined data
Valid
Figure 6-6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
109
Bus cycle
T2
T1
T3
ø
Address bus
External address
AS
RD
Read
access
D15 to D8
Valid
Valid
D7 to D0
HWR
LWR
Write
access
D15 to D8
D7 to D0
Valid
Valid
Figure 6-7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
110
16-Bit, Two-State-Access Areas: Figures 6-8 to 6-10 show the timing of bus control signals for a
16-bit, two-state-access area. In these areas, the upper address bus (D to D ) is used to access
15
8
even addresses and the lower address bus (D to D ) is used to access odd addresses. Wait states
7
0
cannot be inserted.
Bus cycle
T1
T2
ø
Address bus
Even external address in area n
AS
RD
Read
access
D15 to D8
Valid
Invalid
D7 to D0
HWR
LWR
High
Write
access
D15 to D8
D7 to D0
Valid
Undetermined data
Figure 6-8 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
111
Bus cycle
T1
T2
ø
Address bus
Odd external address in area n
AS
RD
Read
access
D15 to D8
Invalid
Valid
D7 to D0
HWR
High
LWR
Write
access
D15 to D8
D7 to D0
Undetermined data
Valid
Figure 6-9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
112
Bus cycle
T1
T2
ø
Address bus
External address in area n
AS
RD
Read
access
D15 to D8
Valid
Valid
D7 to D0
HWR
LWR
Write
access
D15 to D8
D7 to D0
Valid
Valid
Figure 6-10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access)
113
6.3.4 Wait Modes
Four wait modes can be selected for each area as shown in table 6-5.
Table 6-5 Wait Mode Selection
ASTCR
WCER
WCR
ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode
0
1
—
0
—
—
0
—
—
0
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
No wait states
Pin wait mode 0
Programmable wait mode
No wait states
1
1
1
0
Pin wait mode 1
Pin auto-wait mode
1
Note: n = 7 to 0
The AST and WCE bits can be set independently for each area. Bits WMS1 and WMS0 apply to
n
n
all areas. All areas for which WSC control is enabled operate in the same wait mode.
114
Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT
pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall
of the system clock (ø) in the T state, a wait state (T ) is inserted. If the WAIT pin remains low,
2
W
wait states continue to be inserted until the WAIT signal goes high. Figure 6-11 shows the timing.
Inserted by WAIT signal
T
1
T2
TW
TW
T3
ø
*
*
*
WAIT pin
Address bus
External address
AS
RD
Read
Read data
access
Data bus
HWR, LWR
Data bus
Write
access
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-11 Pin Wait Mode 0
115
Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states
(T ) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system
W
clock (ø) in the last of these wait states, an additional wait state is inserted. If the WAIT pin
remains low, wait states continue to be inserted until the WAIT signal goes high.
Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
If the wait count is 0, this mode operates in the same way as pin wait mode 0.
Figure 6-12 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional
wait state is inserted by WAIT input.
Inserted by Inserted by
wait count
WAIT signal
T
1
T2
TW
TW
T3
ø
*
*
WAIT pin
Address bus
External address
AS
RD
Read
access
Read data
Data bus
HWR, LWR
Data bus
Write
access
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-12 Pin Wait Mode 1
116
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T ) selected by bits
W
WC1 and WC0 are inserted.
In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T state,
2
the number of wait states (T ) selected by bits WC1 and WC0 are inserted. No additional wait
W
states are inserted even if the WAIT pin remains low.
Figure 6-13 shows the timing when the wait count is 1.
T
1
T2
T3
T1
T2
TW
T3
ø
*
*
WAIT
Address bus
AS
External address
External address
RD, RS
Read
access
Read data
Read data
Data bus
HWR, LWR
Write
access
Data bus
Write data
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-13 Pin Auto-Wait Mode
117
Programmable Wait Mode: The number of wait states (T ) selected by bits WC1 and WC0 are
W
inserted in all accesses to external three-state-access areas. Figure 6-14 shows the timing when the
wait count is 1 (WC1 = 0, WC0 = 1).
T
1
T2
TW
T3
ø
External address
Address bus
AS
RD
Read
access
Read data
Data bus
HWR, LWR
Write
access
Write data
Data bus
Figure 6-14 Programmable Wait Mode
118
Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and
WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can
select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.
Figure 6-15 shows an example of wait mode settings.
3-state-access area,
Area 0
programmable wait mode
3-state-access area,
programmable wait mode
Area 1
3-state-access area,
Area 2
pin wait mode 0
3-state-access area,
Area 3
pin wait mode 0
2-state-access area,
no wait states inserted
Area 4
2-state-access area,
Area 5
no wait states inserted
2-state-access area,
Area 6
no wait states inserted
2-state-access area,
Area 7
no wait states inserted
Bit:
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
ASTCR H'0F:
WCER H'33:
WCR H'F3:
0
0
1
1
0
0
0
0
1
1
1
1
—
—
—
—
Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR.
Figure 6-15 Wait Mode Settings (Example)
119
6.3.5 Bus Arbiter Operation
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There
are two bus masters: the CPU and an external bus master. When a bus master has the bus right it
can carry out read or write access. Each bus master uses a bus request signal to request the bus
right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant
the bus to a bus master, which can then operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master if the bus request signal is active. When two or
more bus masters request the bus, the highest-priority bus master receives an acknowledge signal.
The bus master that receives an acknowledge signal can continue to use the bus until the
acknowledge signal is deactivated.
The bus master priority order is:
(High)
External bus master > CPU
(Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
CPU: The CPU is the lowest-priority bus master. If an external bus master requests the bus while
the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it.
The bus right is transferred at the following times:
•
•
•
The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
If another bus master requests the bus while the CPU is performing internal operations, such
as executing a multiply or divide instruction, the bus right is transferred immediately. The
CPU continues its internal operations.
If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
120
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter by driving the BREQ signal low. Once the external bus master gets the bus, it keeps
the bus right until the BREQ signal goes high. While the bus is released to an external bus master,
the H8/3001 holds the address bus and data bus control signals (AS, RD, HWR, and LWR) in the
high-impedance state, and holds the BACK pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (ø). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK signal is driven high to end
the bus-release cycle.
121
Figure 6-16 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
CPU cycles
T1
External bus released
CPU cycles
T0
T2
ø
High-impedance
High-impedance
High-impedance
High-impedance
Address
Address
Data bus
(D15 to D0 )
AS , RD
HWR , LWR
BREQ
High
BACK
Minimum 2 cycles
1
2
3
4
5
6
1
2
3
Low BREQ signal is sampled at rise of T0 state.
BACK signal goes low at end of CPU read cycle, releasing bus right to external bus master.
BREQ
pin continues to be sampled while bus is released to external bus master.
4, 5 HighBREQ signal is sampled twice consecutively.
BREQ
6
signal goes high, ending bus-release cycle.
Figure 6-16 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
122
6.4 Usage Notes
6.4.1 ABWCR, ASTCR, and WCER Write Timing
Data written to ABWCR, ASTCR, or WCER takes effect starting from the next bus cycle. Figure
6-17 shows the timing when an instruction fetched from area 0 changes area 0 from three-state
access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
ø
ASTCR address
Address
3-state access to area 0
2-state access
to area 0
Figure 6-17 ASTCR Write Timing
6.4.2 BREQ Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes low, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
If BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
123
124
Section 7 I/O Ports
7.1 Overview
The H8/3001 has six input/output ports (ports 4, 6, 8, 9, A, and B) and one input port
(port 7). Table 7-1 summarizes the port functions. The pins in each port are multiplexed as shown
in table 7-1.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for storing output data. In addition to its DDR and DR, port 4 has an input pull-up control
register (PCR) for switching input pull-up transistors on and off.
Ports 4, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive
one TTL load and a 30-pF capacitive load. Ports 4, 6, 8, 9, A, and B can drive a Darlington pair.
Port 5 can drive LEDs (with 10-mA current sink). Ports P8 , P8 , PA to PA , and PB to PB
0
1
0
7
0
3
have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
125
Table 7-1 Port Functions
Port
Description
Pins
Mode 1 Mode 2 Mode 3 Mode 4
Port 4 8-bit I/O port
Input pull-up
P47 to P40/D7 to D0
Data bus (D7 to D0) and 8-bit generic
input/output
8-bit bus mode: generic input/output
16-bit bus mode: data bus
Port 6 3-bit I/O port
Port 7 4-bit input port
P62/BACK
P61/BREQ
P60/WAIT
Bus control signal input/output (BACK,
BREQ, WAIT) and 3-bit generic
input/output
P73 to P70/AN3 to AN0
Analog input (AN3 to AN0) to A/D
converter, and 4-bit generic input
Port 8 2-bit I/O port
Schmitt inputs
P81/IRQ1
IRQ1 input and generic input
Do not set DDR to 1
P80/IRQ0
IRQ0 input and generic input/output
Port 9 3-bit I/O port
P94/SCK/IRQ4
P92/RxD
P90/TxD
Input and output (SCK, RxD, TxD)
for serial communication interface
(SCI), IRQ4 input, and 3-bit generic
input/output
Port A 8-bit I/O port
Schmitt inputs
PA7/TP7/TIOCB2/A20
PA6/TP6/TIOCA2/A21
PA5/TP5/TIOCB1/A22
PA4/TP4/TIOCA1/A23
PA3/TP3/TIOCB0/TCLKD
PA2/TP2/TIOCA0/TCLKC
PA1/TP1/TCLKB
Output (TP7 to TP0) Address output pin
from programmable
timing pattern
controller (TPC),
input and output (TCLKD, TCLKC,
TCLKB, TCLKA, TIOCB2, TIOCA2,
TIOCB1, TIOCA1, TIOCB0, TIOCA0) for
16-bit integrated timer unit (ITU), and
8-bit generic input/output
PA0/TP0/TCLKA
Port B 4-bit I/O port
Can drive LEDs
Schmitt inputs
PB3/TP11/TIOCB4
PB2/TP10/TIOCA4
PB1/TP9/TIOCB3
PB0/TP8/TIOCB3
Output (TP11 to TP8) from TPC,
ITU input and output (TIOCB4, TIOCA4,
TIOCB3, TIOCA3), and 4-bit generic
input/output
126
7.2 Port 4
7.2.1 Overview
Port 4 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin
functions differ between the 8-bit and 16-bit bus modes.
When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas,
the H8/3001 operates in 8-bit bus mode and port 4 is a generic input/output port. When at least
one of areas 0 to 7 is designated as a 16-bit-access area, the H8/3001 operates in 16-bit bus mode
and port 4 becomes the lower data bus.
Port 4 has software-programmable built-in pull-up transistors.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 4 pins
8-bit bus mode*1
16-bit bus mode*2
P47/D7
P46/D6
P45/D5
P44/D4
P43/D3
P42/D2
P41/D1
P40/D0
P47 (input/output)
P46 (input/output)
P45 (input/output)
P44 (input/output)
P43 (input/output)
P42 (input/output)
P41 (input/output)
P40 (input/output)
D7 (input/output)
D6 (input/output)
D5 (input/output)
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Port 4
Notes: 1. Initial state in modes 1 and 3.
2. Initial state in modes 2 and 4.
Figure 7-1 Port 4 Pin Configuration
127
7.2.2 Register Descriptions
Table 7-2 summarizes the registers of port 4.
Table 7-2 Port 4 Registers
Address*
H'FFC5
H'FFC7
H'FFDA
Name
Abbreviation
P4DDR
R/W
W
Initial Value
H'00
Port 4 data direction register
Port 4 data register
P4DR
R/W
R/W
H'00
Port 4 input pull-up control register
P4PCR
H'00
Note: * Lower 16 bits of the address.
Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select
input or output for each pin in port 4.
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 4 data direction 7 to 0
These bits select input or output for port 4 pins
8-Bit Bus Mode: When all areas are designated as 8-bit-access areas, selecting 8-bit bus mode,
port 4 functions as a generic input/output port. A pin in port 4 becomes an output pin if the
corresponding P4DDR bit is set to 1, and an input pin if this bit is cleared to 0.
16-Bit Bus Mode: When at least one area is designated as a 16-bit-access area, selecting 16-bit
bus mode, port 4 functions as the lower data bus.
P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a
generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
128
Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores data for
pins P4 to P4 .
7
0
Bit
7
P47
0
6
P46
0
5
P45
0
4
P44
0
3
P43
0
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 data 7 to 0
These bits store data for port 4 pins
When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P4DDR is cleared to 0, if
port 4 is read the corresponding pin level is read. This applies in both 8-bit and 16-bit bus modes.
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 4 Input Pull-Up Control Register (P4PCR): P4PCR is an 8-bit readable/writable register
that controls the MOS input pull-up transistors in port 4.
Bit
7
6
5
4
3
2
1
0
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 input pull-up control 7 to 0
These bits control input pull-up transistors built into port 4
In 8-bit bus mode, when a P4DDR bit is cleared to 0 (selecting generic input), if the
corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on.
P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
129
7.2.3 Pin Functions in Each Mode
The functions of port 4 differ as described below depending on whether 8-bit or 16-bit bus mode
is selected by ABWCR settings.
8-Bit Bus Mode: Input or output can be selected separately for each pin in port 4. A pin becomes
an output pin if the corresponding P4DDR bit is set to 1 and an input pin if this bit is cleared to 0.
The initial state is 8-bit bus mode in modes 1 and 3. Figure 7-2 shows the pin functions in 8-bit
bus mode.
P47 (input/output)
P46 (input/output)
P45 (input/output)
P44 (input/output)
Port 4
P43 (input/output)
P42 (input/output)
P41 (input/output)
P40 (input/output)
Figure 7-2 Pin Functions in 8-Bit Bus Mode (Port 4)
16-Bit Bus Mode: The input/output settings in P4DDR are ignored. Port 4 automatically becomes
a bidirectional data bus. The initial state is 16-bit bus mode in modes 2 and 4. Figure 7-3 shows
the pin functions in 16-bit bus mode.
130
D7 (input/output)
D6 (input/output)
D5 (input/output)
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Port 4
Figure 7-3 Pin Functions in 16-Bit Bus Mode (Port 4)
7.2.4 Input Pull-Up Transistors
Port 4 has built-in MOS input pull-up transistors that can be controlled by software. These input
pull-up transistors can be used in 8-bit bus mode. They can be turned on and off individually.
In 8-bit bus mode, when a P4PCR bit is set to 1 and the corresponding P4DDR bit is cleared to 0,
the input pull-up transistor is turned on.
The input pull-up transistors are turned off by a reset and in hardware standby mode. In software
standby mode they retain their previous state.
Table 7-3 summarizes the states of the input pull-ups in the 8-bit and 16-bit bus modes.
Table 7-3 Input Pull-Up Transistor States (Port 4)
Hardware
Software
Mode
Reset
Standby Mode
Standby Mode
Other Modes
On/off
8-bit bus mode
16-bit bus mode
Legend
Off
Off
On/off
Off
Off
Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
131
7.3 Port 6
7.3.1 Overview
Port 6 is a 3-bit input/output port that is also used for input and output of bus control signals
(BACK, BREQ, and WAIT). Port 6 has the same set of pin functions in all operating modes.
Figure 7-4 shows the pin configuration of port 6.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 6 pins
P62 (input/output)/BACK (output)
Port 6
P61 (input/output)/BREQ (input)
P60 (input/output)/WAIT (input)
Figure 7-4 Port 6 Pin Configuration
7.3.2 Register Descriptions
Table 7-4 summarizes the registers of port 6.
Table 7-4 Port 6 Registers
Address*
H'FFC9
Name
Abbreviation
P6DDR
R/W
W
Initial Value
H'80
Port 6 data direction register
Port 6 data register
H'FFCB
P6DR
R/W
H'80
Note: * Lower 16 bits of the address.
132
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bit
7
—
1
6
—
0
5
—
0
4
—
0
3
—
0
2
1
0
P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
—
W
W
W
W
W
W
W
Reserved bits
Port 6 data direction 2 to 0
These bits select input or
output for port 6 pins
A pin in port 6 becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin
if this bit is cleared to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a P6DDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores data for
pins P6 to P6 .
2
0
Bit
7
—
1
6
—
5
—
4
—
3
—
2
1
0
P62
0
P61
0
P60
0
Initial value
Read/Write
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 6 data 2 to 0
These bits store data
for port 6 pins
When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is
returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin
level is read. In this case bit 7 reads 1 and bits 6 to 3 have undetermined values. Bits 7 to 3 are
reserved. Bits 6 to 3 can be written and read, but they do not have corresponding pins. Bit 7
cannot be modified and always reads 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
133
7.3.3 Pin Functions
The port 6 pins are also used for BACK output and BREQ and WAIT input. Table 7-5 describes
the selection of pin functions.
Table 7-5 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P62/BACK
Bit BRLE in BRCR and bit P62DDR select the pin function as follows
BRLE
0
1
—
P62DDR
Pin function
0
1
P62 input
P62 output
BACK output
P61/BREQ
P60/WAIT
Bit BRLE in BRCR and bit P61DDR select the pin function as follows
BRLE
0
1
—
P61DDR
Pin function
0
1
P61 input
P61 output
BREQ input
Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the
pin function as follows
WCER
All 1s
Not all 1s
WMS1
0
1
—
P60DDR
Pin function
0
1
0*
0*
P60 input
P60 output
WAIT input
Note: * Do not set bit P60DDR to 1.
7.4 Port 7
7.4.1 Overview
Port 7 is a 4-bit input port that is also used for analog input to the A/D converter. Port 7 has the
same set of pin functions in all operating modes. Figure 7-5 shows the pin configuration of port 7.
134
Port 7 pins
P73 (input)/AN3 (input)
P72 (input)/AN2 (input)
P71 (input)/AN1 (input)
P70 (input)/AN0 (input)
Port 7
Figure 7-5 Port 7 Pin Configuration
7.4.2 Register Description
Table 7-6 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction
register.
Table 7-6 Port 7 Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFCE
Port 7 data register
P7DR
R
Undetermined
Note: * Lower 16 bits of the address.
Port 7 Data Register (P7DR)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
P73
—*
R
P72
—*
R
P71
—*
R
P70
—*
R
Initial value
Read/Write
R
R
R
R
Note: * Determined by pins P73 to P70.
When port 7 is read, the pin levels are always read.
135
7.5 Port 8
7.5.1 Overview
Port 8 is a 2-bit input/output port that is also used for IRQ and IRQ input. Port 8 has the same
1
0
set of pin functions in all operating modes. Figure 7-6 shows the pin configuration of port 8.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair. Port 8 has Schmitt-trigger inputs.
Port 8 pins
P81 (input)/IRQ1 (input)
Port 8
P80 (input/output)/IRQ0 (input)
Figure 7-6 Port 8 Pin Configuration
7.5.2 Register Descriptions
Table 7-7 summarizes the registers of port 8.
Table 7-7 Port 8 Registers
Address*
H'FFCD
H'FFCF
Name
Abbreviation
P8DDR
R/W
W
Initial Value
H'F0
Port 8 data direction register
Port 8 data register
P8DR
R/W
H'E0
Note: * Lower 16 bits of the address.
136
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
0
P81DDR P80DDR
Initial value
Read/Write
0
0
—
—
—
W
W
W
W
W
Reserved bits
Port 8 data direction 1 and 0
These bits select input or
output for port 8 pins
When P8 DDR is set to 1, P8 becomes a generic output pin, and when it is cleared to 0, P8
0
0
0
becomes an input pin. Do not set P8 DDR to 1.
1
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a P8DDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores data for
pins P8 and P8 .
1
0
Bit
7
—
1
6
—
1
5
—
1
4
—
3
—
2
—
1
0
P81
0
P80
0
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 1 and 0
These bits store data
for port 8 pins
When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is
returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin
level is read.
Bits 7 to 2 are reserved. Bits 7 to 5 cannot be modified and always read 1. Bits 4 to 2 can be
written and read, but they do not have corresponding pins.
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
137
7.5.3 Pin Functions
The port 8 pins are also used for IRQ and IRQ input. Table 7-8 describes the selection of pin
1
0
functions.
Table 7-8 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P81/IRQ1
Bit P81DDR selects the pin function as follows
P81DDR
0
1
Pin function
P81 input
IRQ1 input
—
P80/IRQ0
Bit RFSHE P80DDR select the pin function as follows
P80DDR
0
1
Pin function
P80 input
P80 output
IRQ0 input
138
7.6 Port 9
7.6.1 Overview
Port 9 is a 3-bit input/output port that is also used for input and output (TxD, RxD, SCK) by serial
communication interface (SCI), and for IRQ input. Port 9 has the same set of pin functions in all
4
operating modes. Figure 7-7 shows the pin configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 9 pins
P94 (input/output)/SCK (input/output)IRQ4 (input)
Port 9
P92 (input/output)/RxD (input)
P90 (input/output)/TxD (output)
Figure 7-7 Port 9 Pin Configuration
7.6.2 Register Descriptions
Table 7-9 summarizes the registers of port 9.
Table 7-9 Port 9 Registers
Address*
H'FFD0
Name
Abbreviation
P9DDR
R/W
W
Initial Value
H'C0
Port 9 data direction register
Port 9 data register
H'FFD2
P9DR
R/W
H'C0
Note: * Lower 16 bits of the address.
139
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bit
7
—
1
6
—
1
5
—
0
4
3
—
0
2
1
—
0
0
P94DDR
P92DDR
P90DDR
Initial value
Read/Write
0
0
0
—
—
W
W
W
W
W
W
Reserved bits
Port 9 data direction 4, 2, and 0
These bits select input or
output for port 9 pins
A pin in port 9 becomes an output pin if the corresponding P9DDR bit is set to 1, and an input pin
if this bit is cleared to 0.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a P9DDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores data for
pins P9 , P9 , and P9 .
4
2
0
Bit
7
6
—
1
5
—
4
P94
0
3
—
2
1
—
0
—
1
P92
0
P90
0
Initial value
Read/Write
0
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 9 data 4, 2 and 0
These bits store data
for port 9 pins
When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned
directly. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
Bits 7 and 6 are reserved. They cannot be modified and are always read as 1. Bits 5, 3, and 1 are
also reserved. They can be written and read, but they do not have corresponding pins.
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
140
7.6.3 Pin Functions
The port 9 pins are also used for SCI input and output (TxD, RxD, SCK), and for IRQ input.
4
Table 7-10 describes the selection of pin functions.
Table 7-10 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P94/SCK/IRQ4
Bit C/A in SMR of SCI, bits CKE0 and CKE1 in SCR of SCI0, and bit P94DDR
select the pin function as follows
CKE1
0
1
C/A
0
1
—
—
CKE0
0
1
—
—
—
P94DDR
Pin function
0
1
—
P94
P94
SCK output
SCK output
SCK input
input output
IRQ4 input
Bit RE in SCR of SCI and bit P92DDR select the pin function as follows
P92/RxD
P90/TxD
RE
0
1
—
P92DDR
Pin function
0
1
P92 input
P92 output
RxD input
Bit TE in SCR of SCI and bit P90DDR select the pin function as follows
TE
0
1
—
P90DDR
Pin function
0
1
P90 input
P90 output
TxD output
141
7.7 Port A
7.7.1 Overview
Port A is an 8-bit input/output port that is also used for address output (A to A ), output (TP to
23
20
7
TP ) from the programmable timing pattern controller (TPC), and input and output (TIOCB ,
0
2
TIOCA , TIOCB , TIOCA , TIOCB , TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-
2
1
1
0
0
bit integrated timer unit (ITU). Pin functions differ depending on the operating mode. Figure 7-8
shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
Modes 1 and 2
Port A pins
PA7 (input/output)/TP7 (output)/TIOCB2 (input/output)
PA6 (input/output)/TP6 (output)/TIOCA2 (input/output)
PA5 (input/output)/TP5 (output)/TIOCB1 (input/output)
PA4 (input/output)/TP4 (output)/TIOCA1 (input/output)
PA3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input)
PA2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input)
PA1 (input/output)/TP1 (output)/TCLKB (input)
Port A
PA0 (input/output)/TP0 (output)/TCLKA (input)
Modes 3 and 4
Port A pins
A20 (output)
A
A
A
21 (output)
22 (output)
23 (output)
Port A
PA3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input)
PA2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input)
PA1 (input/output)/TP1 (output)/TCLKB (input)
PA0 (input/output)/TP0 (output)/TCLKA (input)
Figure 7-8 Port A Pin Configuration
142
7.7.2 Register Descriptions
Table 7-11 summarizes the registers of port A.
Table 7-11 Port A Registers
Address*
Name
Abbreviation R/W Initial Value
H'FFD1
Port A data direction register
PADDR
W
Modes 1, 2
Modes 3, 4
H'00
H'80
H'FFD3
Port A data register
PADR
R/W H'00
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
Read/Write
Initial value
0
W
1
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
Modes
1, 2
Modes
3, 4
Read/Write —
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3 and 4, PA DDR is fixed at 1 and PA functions as an
7
7
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1 and 2. It is
initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby
mode it retains its previous setting, so if a PADDR bit is set to 1, the corresponding pin maintains
its output state in software standby mode.
143
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for
pins PA to PA .
7
0
Bit
7
6
5
4
3
2
1
0
PA7
0
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin
level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
144
7.7.3 Pin Functions
The port A pins are also used for address output (A to A ), TPC output (TP to TP ), ITU
23
20
7
0
input/output (TIOCB to TIOCB , TIOCA to TIOCA ), and input (TCLKD, TCLKC, TCLKB,
2
0
2
0
TCLKA). Table 7-12 describes the selection of pin functions.
Table 7-12 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA7/TP7/TIOCB2/ The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to
A20
IOB0 in TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the
pin function as follows
Modes 1 and 2
2 in table below
Modes 3 and 4
—
ITU channel
2 settings
1 in table
below
PA7DDR
NDER7
—
—
0
1
0
1
1
—
—
—
—
Pin function
TIOCB2 output
PA7
PA7
TP7
input output output
TIOCB2 input*
A20 output
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
ITU channel
2 settings
2
1
2
1
IOB2
0
IOB1
0
0
0
1
1
—
—
IOB0
—
145
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA6/TP6/TIOCA2/ The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to
A21
IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA6DDR in PADDR select the
pin function as follows
Modes 1 and 2
2 in table below
Modes 3 and 4
—
ITU channel
2 settings
1 in table
below
PA6DDR
NDER6
—
—
0
1
0
1
1
—
—
—
—
Pin function
TIOCA2 output
PA6
PA6
TP6
input output output
TIOCA2 input*
A21 output
Note: * TIOCA2 input when IOA2 = 1.
ITU channel
2 settings
PWM2
IOA2
2
1
2
1
0
1
0
0
1
1
—
—
—
IOA1
0
0
1
—
—
IOA0
—
146
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA5/TP5/TIOCB1/ The mode setting, ITU channel 1 settings (bit A22E in BRCR, bit PWM1 in
A22
TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit
PA5DDR in PADDR select the pin function as follows
Modes 1 and 2
2 in table below
Modes 3 and 4
ITU channel
1 settings
1 in table
below
—
PA5DDR
NDER5
—
0
1
0
1
1
—
—
—
—
—
Pin function
TIOCB1 output
PA5
PA5
TP5
input output output
TIOCB1 input*
A22 output
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
ITU channel
1 settings
2
1
2
1
IOB2
0
IOB1
0
0
0
1
1
—
—
IOB0
—
147
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA4/TP4/TIOCA1/ The mode setting, ITU channel 1 settings (bit A23E in BRCR, bit PWM1 in
A23
TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit
PA4DDR in PADDR select the pin function as follows
Modes 1 and 2
2 in table below
Modes 3 and 4
ITU channel
1 settings
1 in table
below
—
PA4DDR
NDER4
—
—
0
1
0
1
1
—
—
—
—
Pin function
TIOCA1 output
PA4
PA4
TP4
input output output
TIOCA1 input*
A23 output
Note: * TIOCA1 input when IOA2 = 1.
ITU channel
1 settings
PWM1
IOA2
2
1
2
1
0
1
0
0
1
1
—
—
—
IOA1
0
0
1
—
—
IOA0
—
148
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA3/TP3/TIOCB0/ ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0),
TCLKD
bits TPSC2 to TPSC0 in timer control registers 4 to 0 (TCR4 to TCR0), bit
NDER3 in NDERA, and bit PA3DDR in PADDR select the pin function as
follows
ITU channel
0 settings
PA3DDR
NDER3
1 in table below
2 in table below
—
—
0
1
0
1
1
—
Pin function
TIOCB0 output
PA3
PA3
TP3
input
output
output
TIOCB0 input*1
TCLKD input*2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of
TCR4 to TCR0.
ITU channel
0 settings
2
1
2
1
IOB2
0
IOB1
0
0
0
1
1
—
—
IOB0
—
149
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA2/TP2/TIOCA0/ ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0),
TCLKC
bits TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit
PA2DDR in PADDR select the pin function as follows
ITU channel
0 settings
PA2DDR
NDER2
1 in table below
2 in table below
—
—
0
1
0
1
1
—
Pin function
TIOCA0 output
PA2
PA2
TP2
input
TIOCA0 input*1 and TCLKC input*2
Notes: 1. TIOCA0 input when IOA2 = 1.
output
output
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of
TCR4 to TCR0.
ITU channel
0 settings
PWM0
IOA2
2
1
2
1
0
1
0
0
1
1
—
—
—
IOA1
0
0
1
—
—
IOA0
—
150
Table 7-12 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA1/TP1/TCLKB
Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function
as follows
PA1DDR
NDER1
0
—
1
1
1
0
Pin function
PA1 input
PA1 output
TCLKB input*
TP1 output
Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1,
TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
PA0/TP0/TCLKA
Bit NDER0 in NDERA and bit PA0DDR in PADDR select the pin function
as follows
PA0DDR
NDER0
0
—
1
1
1
0
Pin function
PA0 input
PA0 output
TCLKA input*
TP0 output
Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and
TPSC1 = 0 in any of TCR4 to TCR0.
151
7.8 Port B
7.8.1 Overview
Port B is a 4-bit input/output port that is also used for output (TP to TP ) from the
11
8
programmable timing pattern controller (TPC), and input/output (TIOCB , TIOCB , TIOCA ,
4
3
4
TIOCA ) by the 16-bit integrated timer unit (ITU). Port B has the same set of pin functions in all
3
operating modes. Figure 7-9 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port B has Schmitt-trigger inputs.
Port B pins
PB3 (input/output)/TP11 (output)/TIOCB4 (input/output)
PB2 (input/output)/TP10 (output)/TIOCA4 (input/output)
Port B
PB1 (input/output)/TP9 (output)/TIOCB3 (input/output)
PB0 (input/output)/TP8 (output)/TIOCA3 (input/output)
Figure 7-9 Port B Pin Configuration
7.8.2 Register Descriptions
Table 7-13 summarizes the registers of port B.
Table 7-13 Port B Registers
Address*
H'FFD4
Name
Abbreviation
PBDDR
R/W
W
Initial Value
H'00
Port B data direction register
Port B data register
H'FFD6
PBDR
R/W
H'00
Note: * Lower 16 bits of the address.
152
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B.
Bit
7
—
0
6
—
0
5
—
0
4
—
0
3
2
1
0
PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
Read/Write
0
0
0
0
W
W
W
W
W
W
W
W
Reserved bits
Port B data direction 3 to 0
These bits select input or output
for port B pins
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input
pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a PBDDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for
pins PB to PB .
3
0
Bit
7
—
6
—
5
—
4
—
3
2
1
0
PB3
0
PB2
0
PB1
0
PB0
0
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port B data 3 to 0
These bits store data
for port B pins
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin
level is read. Bits 7 to 4 are reserved and can be written and read. When a bit is read with its
corresponding DDR bit set to 1, the DR value is read directly. If the DDR bit is 0, it always reads
as 1.
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
153
7.8.3 Pin Functions
The port B pins are also used for TPC output (TP to TP ) and ITU input/output (TIOCB ,
11
8
4
TIOCB , TIOCA , TIOCA ). Table 7-14 describes the selection of pin functions.
3
4
3
Table 7-14 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB3/TP11/TIOCB4 ITU channel 4 settings (bit PWM4 in TMDR, bit EB4 in TOER, and bits IOB2 to
IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB3DDR in PBDDR select the
pin function as follows
ITU channel
4 settings
1 in table below
2 in table below
PB3DDR
—
—
0
1
0
1
1
NDER11
—
Pin function
TIOCB4 output
PB3
PB3
TP11
input
output
output
TIOCB4 input*
Note: * TIOCB4 input when PWM4 = 0 and IOB2 = 1.
ITU channel
4 settings
2
2
1
2
EB4
0
1
IOB2
—
—
—
0
0
0
0
0
1
0
1
1
IOB1
—
—
IOB0
—
154
Table 7-14 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB2/TP10/TIOCA4 ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in
TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit
PB2DDR in PBDDR select the pin function as follows
ITU channel
4 settings
1 in table below
2 in table below
PB2DDR
—
—
0
1
0
1
1
NDER10
—
Pin function
TIOCA4 output
PB2
PB2
TP10
input
output
output
TIOCA4 input*
Note: * TIOCA4 input when PWM4 = 0 and IOA2 = 1.
ITU channel
4 settings
2
2
1
2
1
EA4
0
1
PWM4
IOA2
—
—
—
—
0
1
0
0
0
0
0
1
0
1
1
—
—
—
IOA1
—
—
IOA0
—
155
Table 7-14 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB1/TP9/TIOCB3 ITU channel 3 settings (bit PWM3 in TMDR, bit EB3 in TOER, and bits IOB2 to
IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB1DDR in PBDDR select the
pin function as follows
ITU channel
3 settings
PB1DDR
NDER9
1 in table below
2 in table below
—
—
0
1
0
1
1
—
Pin function
TIOCB3 output
PB1
PB1
TP9
input
output
output
TIOCB3 input*
Note: * TIOCB3 input when PWM3 = 0 and IOB2 = 1.
ITU channel
3 settings
2
2
1
2
EB3
0
1
IOB2
—
—
—
0
0
0
0
0
1
0
1
1
IOB1
—
—
IOB0
—
156
Table 7-14 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB0/TP8/TIOCA3 ITU channel 3 settings (bit EA3 in TOER, bit PWM3 in TMDR, and bits IOA2 to
IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select the
pin function as follows
ITU channel
3 settings
PB0DDR
NDER8
1 in table below
2 in table below
—
—
0
1
0
1
1
—
Pin function
TIOCA3 output
PB0
PB0
TP8
input
output
output
TIOCA3 input*
Note: * TIOCA3 input when PWM3 = 0 and IOA2 = 1.
ITU channel
3 settings
2
2
1
2
1
EA3
0
1
PWM3
IOA2
—
—
—
—
0
1
0
0
0
0
0
1
0
1
1
—
—
—
IOA1
—
—
IOA0
—
157
158
Section 8 16-Bit Integrated Timer Unit (ITU)
8.1 Overview
The H8/3001 has a built-in 16-bit integrated timer unit (ITU) with five 16-bit timer channels.
8.1.1 Features
ITU features are listed below.
•
•
Capability to process up to 10 pulse outputs or 10 pulse inputs
Ten general registers (GRs, two per channel) with independently-assignable output compare
or input capture functions
•
•
Selection of eight counter clock sources for each channel:
Internal clocks: ø, ø/2, ø/4, ø/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
Five operating modes selectable in all channels:
— Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
— Input capture function
Rising edge, falling edge, or both edges (selectable)
— Counter clearing function
Counters can be cleared by compare match or input capture
— Synchronization
Two or more timer counters (TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
159
— PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
five-phase PWM output is possible
•
•
Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
One additional mode selectable in channels 3 and 4
— Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
•
•
•
High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
Output triggering of programmable pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output
triggers.
160
Table 8-1 summarizes the ITU functions.
Table 8-1 ITU Functions
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Clock sources
Internal clocks: ø, ø/2, ø/4, ø/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
General registers
(output compare/input
capture registers)
Buffer registers
Input/output pins
—
—
—
BRA3, BRB3
BRA4, BRB4
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Counter clearing function GRA0/GRB0
GRA1/GRB1
compare
GRA2/GRB2
compare
GRA3/GRB3
compare
GRA4/GRB4
compare
compare
match or
match or
match or
match or
match or
input capture
input capture
input capture
input capture
input capture
Compare
match output
0
oo
oo
oo
oo
oo
oo
—
oo
oo
—
oo
oo
oo
—
—
o
1
o
Toggle
oo
o
Input capture function
Synchronization
PWM mode
o
o
Phase counting mode
Buffering
o—
—
—
—
oo
Interrupt sources
Three sources Three sources Three sources Three sources Three sources
• Compare
match/input
capture A0
• Compare
match/input
capture A1
• Compare
match/input
capture A2
• Compare
match/input
capture A3
• Compare
match/input
capture A4
• Compare
match/input
capture B0
• Compare
match/input
capture B1
• Compare
match/input
capture B2
• Compare
match/input
capture B3
• Compare
match/input
capture B4
• Overflow
• Overflow
• Overflow
• Overflow
• Overflow
Legend
o: Available
—: Not available
161
8.1.2 Block Diagrams
ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU.
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TCLKA to TCLKD
Clock selector
Control logic
ø, ø/2, ø/4, ø/8
Counter control and
pulse I/O control unit
TIOCA0 to TIOCA4
TIOCB0 to TIOCB4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
Figure 8-1 ITU Block Diagram (Overall)
162
Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have
the structure shown in figure 8-2.
TCLKA to TCLKD
ø, ø/2, ø/4, ø/8
TIOCA0
TIOCB0
Clock selector
Comparator
IMIA0
IMIB0
OVI0
Control logic
Module data bus
Legend
TCNT:
Timer counter (16 bits)
GRA, GRB: General registers A and B (input capture/output compare registers) (16 bits × 2)
TCR:
TIOR:
TIER:
TSR:
Timer control register (8 bits)
Timer I/O control register (8 bits)
Timer interrupt enable register (8 bits)
Timer status register (8 bits)
Figure 8-2 Block Diagram of Channels 0 and 1 (for Channel 0)
163
Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel
that provides only 0 output and 1 output.
TCLKA to TCLKD
ø, ø/2, ø/4, ø/8
TIOCA2
TIOCB2
Clock selector
Comparator
IMIA2
IMIB2
OVI2
Control logic
Module data bus
Legend
TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
TCR2:
TIOR2:
TIER2:
TSR2:
Timer control register 2 (8 bits)
Timer I/O control register 2 (8 bits)
Timer interrupt enable register 2 (8 bits)
Timer status register 2 (8 bits)
Figure 8-3 Block Diagram of Channel 2
164
Block Diagrams of Channels 3 and 4: ITU channels 3 and 4 have identical functions. Figure 8-4
is a block diagram of channel 3. A block diagram of channel 4 is similar.
TIOCA3
TIOCB3
TCLKA to
TCLKD
ø, ø/2,
Clock selector
Comparator
ø/4, ø/8
IMIA3
IMIB3
OVI3
Control logic
Module data bus
Legend
TCNT:
GRA, GRB:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers)
Figure 8-4 Block Diagram of Channel 3
165
8.1.3 Input/Output Pins
Table 8-2 summarizes the ITU pins.
Table 8-2 ITU Pins
Abbre-
viation
Input/
Output Function
Channel Name
Common Clock input A
TCLKA
Input
Input
External clock A input pin
(phase-A input pin in phase counting mode)
Clock input B
TCLKB
External clock B input pin
(phase-B input pin in phase counting mode)
Clock input C
Clock input D
TCLKC
TCLKD
Input
Input
External clock C input pin
External clock D input pin
0
1
2
3
4
Input capture/output TIOCA0 Input/
compare A0 output
GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB0 Input/
compare B0 output
GRB0 output compare or input capture pin
Input capture/output TIOCA1 Input/
compare A1 output
GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB1 Input/
compare B1 output
GRB1 output compare or input capture pin
Input capture/output TIOCA2 Input/
compare A2 output
GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB2 Input/
compare B2 output
GRB2 output compare or input capture pin
Input capture/output TIOCA3 Input/
compare A3 output
GRA3 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB3 Input/
compare B3 output
GRB3 output compare or input capture pin
Input capture/output TIOCA4 Input/
compare A4 output
GRA4 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB4 Input/
compare B4 output
GRB4 output compare or input capture pin
166
8.1.4 Register Configuration
Table 8-3 summarizes the ITU registers.
Table 8-3 ITU Registers
Abbre-
viation
Initial
Value
Channel
Address*1 Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*2
Common H'FF60
H'FF61
Timer start register
TSTR
TSNC
TMDR
TFCR
TOER
TCR0
TIOR0
TIER0
TSR0
H'E0
H'E0
H'80
H'C0
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
Timer synchro register
H'FF62
Timer mode register
H'FF63
Timer function control register
Timer output master enable register
Timer control register 0
Timer I/O control register 0
Timer interrupt enable register 0
Timer status register 0
H'FF90
0
H'FF64
H'FF65
H'FF66
H'FF67
H'FF68
H'FF69
H'FF6A
H'FF6B
H'FF6C
H'FF6D
H'FF6E
H'FF6F
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF75
H'FF76
H'FF77
Timer counter 0 (high)
TCNT0H R/W
TCNT0L R/W
Timer counter 0 (low)
General register A0 (high)
General register A0 (low)
General register B0 (high)
General register B0 (low)
Timer control register 1
Timer I/O control register 1
Timer interrupt enable register 1
Timer status register 1
GRA0H
GRA0L
GRB0H
GRB0L
TCR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*2
1
TIOR1
TIER1
TSR1
Timer counter 1 (high)
TCNT1H R/W
TCNT1L R/W
Timer counter 1 (low)
General register A1 (high)
General register A1 (low)
General register B1 (high)
General register B1 (low)
GRA1H
GRA1L
GRB1H
GRB1L
R/W
R/W
R/W
R/W
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
167
Table 8-3 ITU Registers (cont)
Abbre-
viation
Initial
Value
Channel
Address*1 Name
Timer control register 2
R/W
2
H'FF78
H'FF79
H'FF7A
H'FF7B
H'FF7C
H'FF7D
H'FF7E
H'FF7F
H'FF80
H'FF81
H'FF82
H'FF83
H'FF84
H'FF85
H'FF86
H'FF87
H'FF88
H'FF89
H'FF8A
H'FF8B
H'FF8C
H'FF8D
H'FF8E
H'FF8F
TCR2
TIOR2
TIER2
TSR2
R/W
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
Timer I/O control register 2
Timer interrupt enable register 2
Timer status register 2
R/W
R/W
R/(W)*2
Timer counter 2 (high)
TCNT2H R/W
TCNT2L R/W
Timer counter 2 (low)
General register A2 (high)
General register A2 (low)
General register B2 (high)
General register B2 (low)
Timer control register 3
Timer I/O control register 3
Timer interrupt enable register 3
Timer status register 3
GRA2H
GRA2L
GRB2H
GRB2L
TCR3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*2
3
TIOR3
TIER3
TSR3
Timer counter 3 (high)
TCNT3H R/W
TCNT3L R/W
Timer counter 3 (low)
General register A3 (high)
General register A3 (low)
General register B3 (high)
General register B3 (low)
Buffer register A3 (high)
Buffer register A3 (low)
Buffer register B3 (high)
Buffer register B3 (low)
GRA3H
GRA3L
GRB3H
GRB3L
BRA3H
BRA3L
BRB3H
BRB3L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
168
Table 8-3 ITU Registers (cont)
Abbre-
viation
Initial
Value
Channel
Address*1 Name
Timer control register 4
R/W
4
H'FF92
H'FF93
H'FF94
H'FF95
H'FF96
H'FF97
H'FF98
H'FF99
H'FF9A
H'FF9B
H'FF9C
H'FF9D
H'FF9E
H'FF9F
TCR4
TIOR4
TIER4
TSR4
R/W
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
Timer I/O control register 4
Timer interrupt enable register 4
Timer status register 4
R/W
R/W
R/(W)*2
Timer counter 4 (high)
TCNT4H R/W
TCNT4L R/W
Timer counter 4 (low)
General register A4 (high)
General register A4 (low)
General register B4 (high)
General register B4 (low)
Buffer register A4 (high)
Buffer register A4 (low)
Buffer register B4 (high)
Buffer register B4 (low)
GRA4H
GRA4L
GRB4H
GRB4L
BRA4H
BRA4L
BRB4H
BRB4L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
169
8.2 Register Descriptions
8.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in
channels 0 to 4.
Bit
7
—
1
6
—
1
5
—
1
4
STR4
0
3
STR3
0
2
STR2
0
1
STR1
0
0
STR0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Counter start 4 to 0
These bits start and
stop TCNT4 to TCNT0
TSTR is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4).
Bit 4
STR4
Description
0
1
TCNT4 is halted
TCNT4 is counting
(Initial value)
(Initial value)
(Initial value)
Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3).
Bit 3
STR3
Description
0
1
TCNT3 is halted
TCNT3 is counting
Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2).
Bit 2
STR2
Description
0
1
TCNT2 is halted
TCNT2 is counting
170
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1).
Bit 1
STR1
Description
0
1
TCNT1 is halted
TCNT1 is counting
(Initial value)
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0).
Bit 0
STR0
Description
0
1
TCNT0 is halted
TCNT0 is counting
(Initial value)
8.2.2 Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
0
SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Initial value
Read/Write
0
0
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Timer sync 4 to 0
These bits synchronize
channels 4 to 0
TSNC is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or
synchronously.
Bit 4
SYNC4 Description
0
Channel 4’s timer counter (TCNT4) operates independently
TCNT4 is preset and cleared independently of other channels
(Initial value)
1
Channel 4 operates synchronously
TCNT4 can be synchronously preset and cleared
171
Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or
synchronously.
Bit 3
SYNC3 Description
0
Channel 3’s timer counter (TCNT3) operates independently
TCNT3 is preset and cleared independently of other channels
(Initial value)
1
Channel 3 operates synchronously
TCNT3 can be synchronously preset and cleared
Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2 Description
0
Channel 2’s timer counter (TCNT2) operates independently
TCNT2 is preset and cleared independently of other channels
(Initial value)
1
Channel 2 operates synchronously
TCNT2 can be synchronously preset and cleared
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1 Description
0
Channel 1’s timer counter (TCNT1) operates independently
TCNT1 is preset and cleared independently of other channels
(Initial value)
1
Channel 1 operates synchronously
TCNT1 can be synchronously preset and cleared
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0 Description
0
Channel 0’s timer counter (TCNT0) operates independently
TCNT0 is preset and cleared independently of other channels
(Initial value)
1
Channel 0 operates synchronously
TCNT0 can be synchronously preset and cleared
172
8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
7
—
1
6
5
FDIR
0
4
3
2
1
0
MDF
0
PWM4 PWM3 PWM2
PWM1 PWM0
Initial value
Read/Write
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
Description
0
1
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
173
When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an
up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts
both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
TCLKA pin
Down-Counting
Up-Counting
Low
High
Low
Low
High
TCLKB pin
High
High
Low
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in
timer control register 2 (TCR2). Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare
match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer
interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase
counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the overflow flag (OVF) in
timer status register 2 (TSR2). The FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
Description
0
1
OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
OVF is set to 1 in TSR2 when TCNT2 overflows
(Initial value)
Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.
Bit 4
PWM4 Description
0
1
Channel 4 operates normally
(Initial value)
Channel 4 operates in PWM mode
When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The
output goes to 1 at compare match with general register A4 (GRA4), and to 0 at compare match
with general register B4 (GRB4).
174
Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode.
Bit 3
PWM3 Description
0
1
Channel 3 operates normally
(Initial value)
Channel 3 operates in PWM mode
When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The
output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match
with general register B3 (GRB3).
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2 Description
0
1
Channel 2 operates normally
(Initial value)
Channel 2 operates in PWM mode
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with general register A2 (GRA2), and to 0 at compare match
with general register B2 (GRB2).
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1 Description
0
1
Channel 1 operates normally
(Initial value)
Channel 1 operates in PWM mode
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with general register A1 (GRA1), and to 0 at compare match
with general register B1 (GRB1).
175
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0 Description
0
1
Channel 0 operates normally
(Initial value)
Channel 0 operates in PWM mode
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match
with general register B0 (GRB0).
8.2.4 Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects buffering for channels 3 and 4.
Bit
7
—
1
6
—
1
5
—
4
—
3
BFB4
0
2
BFA4
0
1
BFB3
0
0
BFA3
0
Initial value
Read/Write
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Reserved bits
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
176
Bits 5 and 4—Reserved: These bits can be written and read, but do not set them to 1.
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 3
BFB4
Description
0
1
GRB4 operates normally
GRB4 is buffered by BRB4
(Initial value)
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2
BFA4
Description
0
1
GRA4 operates normally
GRA4 is buffered by BRA4
(Initial value)
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3
Description
0
1
GRB3 operates normally
GRB3 is buffered by BRB3
(Initial value)
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3
Description
0
1
GRA3 operates normally
GRA3 is buffered by BRA3
(Initial value)
177
8.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
7
—
1
6
—
1
5
—
4
—
3
2
1
0
EB3
1
EB4
1
EA4
1
EA3
1
Initial value
Read/Write
1
1
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Reserved bits
Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4
These bits enable or disable output settings for pins
TIOCA3, TIOCB3 , TIOCA4, and TIOCB4
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 and 4—Reserved: Although reserved, these bits can be written and read.
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3.
Bit 3
EB3
Description
0
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates as
a generic input/output pin).
1
TIOCB3 is enabled for output according to TIOR3 and TFCR settings
(Initial value)
178
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2
EB4
Description
0
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as
a generic input/output pin).
1
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
(Initial value)
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1
EA4
Description
0
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4
operates as a generic input/output pin).
1
TIOCA4 is enabled for output according to TIOR4, TMDR, and
TFCR settings
(Initial value)
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0
EA3
Description
0
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3
operates as a generic input/output pin).
1
TIOCA3 is enabled for output according to TIOR3, TMDR, and
TFCR settings
(Initial value)
179
8.2.6 Timer Counters (TCNT)
TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel.
Channel
Abbreviation
TCNT0
Function
0
1
2
Up-counter
TCNT1
TCNT2
Phase counting mode: up/down-counter
Other modes: up-counter
3
4
TCNT3
TCNT4
Up/down-counter
Bit
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Initial value
Read/Write
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The
clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR).
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and
an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters.
TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or
by input capture to GRA or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in
the timer status register (TSR) of the corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in
TSR of the corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
180
8.2.7 General Registers (GRA, GRB)
The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel
Abbreviation
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
GRA4, GRB4
Function
0
1
2
3
4
Output compare/input capture register
Output compare/input capture register; can be buffered by buffer
registers BRA and BRB
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in the timer I/O
control register (TIOR).
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The
valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
181
8.2.8 Buffer Registers (BRA, BRB)
The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3
and 4.
Channel
Abbreviation
BRA3, BRB3
BRA4, BRB4
Function
3
4
Used for buffering
• When the corresponding GRA or GRB functions as an output
compare register, BRA or BRB can function as an output compare
buffer register: the BRA or BRB value is automatically transferred
to GRA or GRB at compare match
• When the corresponding GRA or GRB functions as an input
capture register, BRA or BRB can function as an input capture
buffer register: the GRA or GRB value is automatically transferred
to BRA or BRB at input capture
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as an
output compare register, the buffer register functions as an output compare buffer register. When
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
182
8.2.9 Timer Control Registers (TCR)
TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel
Abbreviation
TCR0
Function
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to
TPSC0 in TCR2 are ignored.
0
1
2
3
4
TCR1
TCR2
TCR3
TCR4
Bit
7
6
5
4
3
2
1
0
—
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
1
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Reserved bit
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
183
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6
Bit 5
CCLR1 CCLR0 Description
0
1
0
1
0
1
TCNT is not cleared
(Initial value)
TCNT is cleared by GRA compare match or input capture*1
TCNT is cleared by GRB compare match or input capture*1
Synchronous clear: TCNT is cleared in synchronization with other
synchronized timers*2
Notes: 1. TCNT is cleared by compare match when the general register functions as a compare
match register, and by input capture when the general register functions as an input
capture register.
2. Selected in the timer synchro register (TSNC).
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4
Bit 3
CKEG1 CKEG0 Description
0
1
0
Count rising edges
Count falling edges
Count both edges
(Initial value)
1
—
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
184
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
Bit 1
Bit 0
TPSC2 TPSC1 TPSC0 Function
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: ø
(Initial value)
Internal clock: ø/2
Internal clock: ø/4
Internal clock: ø/8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer
counts the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.
8.2.10 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel
Abbreviation
TIOR0
Function
0
1
2
3
4
TIOR controls the general registers. Some functions differ in PWM
mode.
TIOR1
TIOR2
TIOR3
TIOR4
185
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
IOA2
0
1
IOA1
0
0
IOA0
0
Initial value
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
Function
0
1
0
0
1
0
1
GRB is an output
compare register
No output at compare match
(Initial value)
0 output at GRB compare match*1
1 output at GRB compare match*1
1
Output toggles at GRB compare match
(1 output in channel 2)*1, *2
0
1
0
1
0
1
GRB is an input
capture register
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
186
Bit 3—Reserved: Read-only bit, always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
Function
0
1
0
0
1
0
1
GRA is an output
compare register
No output at compare match
(Initial value)
0 output at GRA compare match*1
1 output at GRA compare match*1
1
Output toggles at GRA compare match
(1 output in channel 2)*1, *2
0
1
0
1
0
1
GRA is an input
capture register
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
8.2.11 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
Abbreviation
TSR0
Function
0
1
2
3
4
Indicates input capture, compare match, and overflow status
TSR1
TSR2
TSR3
TSR4
187
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVF
0
1
IMFB
0
0
IMFA
0
Initial value
Read/Write
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written, to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Note: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow can
only occur when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
188
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1
IMFB
Description
0
[Clearing condition]
(Initial value)
Read IMFB when IMFB = 1, then write 0 in IMFB
1
[Setting conditions]
TCNT = GRB when GRB functions as a compare match register.
TCNT value is transferred to GRB by an input capture signal, when GRB functions as
an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0
IMFA
Description
0
[Clearing condition]
(Initial value)
Read IMFA when IMFA = 1, then write 0 in IMFA.
1
[Setting conditions]
TCNT = GRA when GRA functions as a compare match register.
TCNT value is transferred to GRA by an input capture signal, when GRA functions
as an input capture register.
189
8.2.12 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
Abbreviation
TIER0
Function
0
1
2
3
4
Enables or disables interrupt requests.
TIER1
TIER2
TIER3
TIER4
Bit
7
6
—
1
5
—
1
4
—
1
3
—
1
2
OVIE
0
1
IMIEB
0
0
IMIEA
0
—
Initial value
Read/Write
1
—
—
—
—
—
R/W
R/W
R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
190
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
overflow flag (OVF) in TSR when OVF is set to 1.
Bit 2
OVIE
Description
0
1
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
(Initial value)
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1
IMIEB
Description
0
1
IMIB interrupt requested by IMFB is disabled
IMIB interrupt requested by IMFB is enabled
(Initial value)
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0
IMIEA
Description
0
1
IMIA interrupt requested by IMFA is disabled
IMIA interrupt requested by IMFA is enabled
(Initial value)
191
8.3 CPU Interface
8.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 8-5 and 8-6 show examples of word access to a timer counter (TCNT). Figures 8-7, 8-8,
8-9, and 8-10 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
H
L
H
L
Module
data bus
CPU
Bus interface
TCNTH
TCNTL
Figure 8-5 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
H
L
H
L
Module
data bus
CPU
Bus interface
TCNTH
TCNTL
Figure 8-6 Access to Timer Counter (CPU Reads TCNT, Word)
192
On-chip data bus
H
L
H
L
Module
data bus
CPU
CPU
CPU
Bus interface
TCNTH
TCNTL
Figure 8-7 Access to Timer Counter (CPU Writes to TCNT, Upper Byte)
On-chip data bus
H
L
H
L
Module
data bus
Bus interface
TCNTH
TCNTL
Figure 8-8 Access to Timer Counter (CPU Writes to TCNT, Lower Byte)
On-chip data bus
H
L
H
L
Module
data bus
Bus interface
TCNTH
TCNTL
Figure 8-9 Access to Timer Counter (CPU Reads TCNT, Upper Byte)
193
On-chip data bus
H
L
H
L
Module
data bus
CPU
Bus interface
TCNTH
TCNTL
Figure 8-10 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
8.3.2 8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 8-11 and 8-12 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
L
H
L
Module
data bus
CPU
Bus interface
TCR
Figure 8-11 TCR Access (CPU Writes to TCR)
194
On-chip data bus
H
L
H
L
Module
data bus
CPU
Bus interface
TCR
Figure 8-12 TCR Access (CPU Reads TCR)
195
8.4 Operation
8.4.1 Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or external event counter.
General registers A and B can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-
counter.
Buffering
•
If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
If the general register is an input capture register
•
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
8.4.2 Basic Functions
Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register
(TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can
be free-running or periodic.
•
Sample setup procedure for counter
Figure 8-13 shows a sample procedure for setting up a counter.
196
Counter setup
Select counter clock
1
No
Type of counting?
Yes
Free-running counting
Periodic counting
Select counter clear source
2
3
Select output compare
register function
Set period
4
5
Start counter
Start counter
5
Periodic counter
Free-running counter
Figure 8-13 Counter Setup Procedure (Example)
1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the
external clock signal.
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA
compare match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
197
•
Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A
free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When
the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer
status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable
register, a CPU interrupt is requested. After the overflow, the counter continues counting up
from H'0000. Figure 8-14 illustrates free-running counting.
TCNT value
H'FFFF
H'0000
Time
STR0 to
STR4 bit
OVF
Figure 8-14 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare
match, and set the count period in GRA or GRB. After these settings, the counter starts
counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the
count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is
cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU
interrupt is requested at this time. After the compare match, TCNT continues counting up
from H'0000. Figure 8-15 illustrates periodic counting.
198
TCNT value
Counter cleared by general
register compare match
GR
H'0000
STR bit
IMF
Time
Figure 8-15 Periodic Counter Operation
•
Count timing
— Internal clock source
Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock
sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Figure 8-16 shows the timing.
ø
Internal
clock
TCNT input
TCNT
N – 1
N
N + 1
Figure 8-16 Count Timing for Internal Clock Sources
199
— External clock source
Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD),
and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge,
falling edge, or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected.
Shorter pulses will not be counted correctly.
Figure 8-17 shows the timing when both edges are detected.
ø
External
clock input
TCNT input
TCNT
N – 1
N
N + 1
Figure 8-17 Count Timing for External Clock Sources (when Both Edges are Detected)
200
Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B
can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the
output can only go to 0 or go to 1.
•
Sample setup procedure for waveform output by compare match
Figure 8-18 shows a sample procedure for setting up waveform output by compare match.
Output setup
1. Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
0 until the first compare match occurs.
Select waveform
output mode
1
2
3
Set output timing
2. Set a value in GRA or GRB to designate the
compare match timing.
Start counter
3. Set the STR bit to 1 in TSTR to start the timer
counter.
Waveform output
Figure 8-18 Setup Procedure for Waveform Output by Compare Match (Example)
•
Examples of waveform output
Figure 8-19 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
201
TCNT value
H'FFFF
GRB
GRA
H'0000
Time
TIOCB
TIOCA
No change
No change
No change
No change
1 output
0 output
Figure 8-19 0 and 1 Output (Examples)
Figure 8-20 shows examples of toggle output. TCNT operates as a periodic counter, cleared
by compare match B. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
TIOCB
Time
Toggle
output
Toggle
output
TIOCA
Figure 8-20 Toggle Output (Example)
202
•
Output compare timing
The compare match signal is generated in the last state in which TCNT and the general
register match (when TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the output
compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8-21 shows the output compare timing.
ø
TCNT input
clock
TCNT
GR
N
N
N + 1
Compare
match signal
TIOCA,
TIOCB
Figure 8-21 Output Compare Timing
Input Capture Function: The TCNT value can be captured into a general register when a
transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take
place on the rising edge, falling edge, or both edges. The input capture function can be used to
measure pulse width or period.
•
Sample setup procedure for input capture
Figure 8-22 shows a sample procedure for setting up input capture.
203
Input selection
1. Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
port data direction bit to 0 before making these
TIOR settings.
Select input-capture input
1
2
Start counter
Input capture
2. Set the STR bit to 1 in TSTR to start the timer
counter.
Figure 8-22 Setup Procedure for Input Capture (Example)
Examples of input capture
•
Figure 8-23 illustrates input capture when the falling edge of TIOCB and both edges of
TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB.
TCNT value
Counter cleared by TIOCB
input (falling edge)
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 8-23 Input Capture (Example)
204
•
Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 8-24 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
ø
Input-capture input
Internal input
capture signal
TCNT
GR
N
N
Figure 8-24 Input Capture Signal Timing
205
8.4.3 Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or
more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 4).
Sample Setup Procedure for Synchronization: Figure 8-25 shows a sample procedure for
setting up synchronization.
Setup for synchronization
1
Select synchronization
Synchronous preset
Synchronous clear
Clearing
synchronized to this
channel?
No
2
Write to TCNT
Yes
3
Select counter clear source
Start counter
4
5
Select counter clear source
Start counter
Counter clear
5
Synchronous preset
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in TCNT in one of the synchronized channels, the same value is
simultaneously written in TCNT in the other channels (synchronized preset).
3. Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 8-25 Setup Procedure for Synchronization (Example)
206
Example of Synchronization: Figure 8-26 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0,
TIOCA1, and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode.
Value of TCNT0 to TCNT2
Cleared by compare match with GRB0
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
Time
TIOCA0
TIOCA1
TIOCA2
Figure 8-26 Synchronization (Example)
207
8.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all channels (0 to 4).
Table 8-4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Table 8-4 PWM Output Pins and Registers
Channel
Output Pin
TIOCA0
TIOCA1
TIOCA2
TIOCA3
TIOCA4
1 Output
GRA0
GRA1
GRA2
GRA3
GRA4
0 Output
GRB0
GRB1
GRB2
GRB3
GRB4
0
1
2
3
4
208
Sample Setup Procedure for PWM Mode: Figure 8-27 shows a sample procedure for setting up
PWM mode.
PWM mode
1. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in TCR to
select the desired edge(s) of the
external clock signal.
2. Set bits CCLR1 and CCLR0 in TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
Select counter clock
Select counter clear source
Set GRA
1
2
3
4
5
6
Set GRB
Select PWM mode
Start counter
PWM mode
Figure 8-27 Setup Procedure for PWM Mode (Example)
209
Examples of PWM Mode: Figure 8-28 shows examples of operation in PWM mode. The PWM
waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and
to 0 at compare match with GRB.
In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
H'0000
TIOCA
Time
a. Counter cleared by GRA
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCA
b. Counter cleared by GRB
Figure 8-28 PWM Mode (Example 1)
210
Figure 8-29 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
TIOCA
Time
Write to GRA
a. 0% duty cycle
Write to GRA
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
H'0000
Time
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle
Figure 8-29 PWM Mode (Example 2)
211
8.4.5 Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in
TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare
functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 8-30 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
Select flag setting condition
1
1. Set the MDF bit in TMDR to 1 to select
phase counting mode.
2. Select the flag setting condition with
the FDIR bit in TMDR.
3. Set the STR2 bit to 1 in TSTR to start
the timer counter.
2
3
Start counter
Phase counting mode
Figure 8-30 Setup Procedure for Phase Counting Mode (Example)
212
Example of Phase Counting Mode: Figure 8-31 shows an example of operations in phase
counting mode. Table 8-5 lists the up-counting and down-counting conditions for TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted.
The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap
must also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 8-32.
TCNT2 value
Counting up
Counting down
Time
TCLKB
TCLKA
Figure 8-31 Operation in Phase Counting Mode (Example)
Table 8-5 Up/Down Counting Conditions
Counting Direction
TCLKB
Up-Counting
High
Down-Counting
Low
High
Low
Low
TCLKA
Low
High
High
Phase
Phase
difference
difference
Pulse width
Pulse width
TCLKA
TCLKB
Phase difference and overlap: at least 1.5 states
Pulse width: at least 2.5 states
Overlap
Overlap
Figure 8-32 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
213
8.4.6 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register. Buffering is available only in channels 3 and 4. Buffering
operations under the conditions mentioned above are described next.
•
General register used for output compare
The buffer register value is transferred to the general register at compare match. See
figure 8-33.
Compare match signal
BR
GR
Comparator
TCNT
Figure 8-33 Compare Match Buffering
General register used for input capture
•
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 8-34.
Input capture signal
BR
GR
TCNT
Figure 8-34 Input Capture Buffering
214
Sample Buffering Setup Procedure: Figure 8-35 shows a sample buffering setup procedure.
Buffering
Select general register functions
Set buffer bits
1
2
3
1. Set TIOR to select the output compare or input
capture function of the general registers.
2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
to select buffering of the required general registers.
3. Set the STR bits to 1 in TSTR to start the timer
counters.
Start counters
Buffered operation
Figure 8-35 Buffering Setup Procedure (Example)
215
Examples of Buffering: Figure 8-36 shows an example in which GRA is set to function as an
output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by
GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B.
Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is
simultaneously transferred to GRA. This operation is repeated each time compare match A occurs.
Figure 8-37 shows the transfer timing.
TCNT value
GRB
Counter cleared by compare match B
H'0250
H'0200
H'0100
H'0000
Time
BRA
H'0200
H'0250
H'0100
H'0200
H'0200
H'0200
GRA
H'0100
Toggle
output
TIOCB
TIOCA
Toggle
output
Compare match A
Figure 8-36 Register Buffering (Example 1: Buffering of Output Compare Register)
216
ø
n
n + 1
TCNT
Compare
match signal
Buffer transfer
signal
N
BR
GR
n
N
Figure 8-37 Compare Match and Buffer Transfer Timing (Example)
217
Figure 8-38 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 8-39 shows the transfer timing.
TCNT value
Counter cleared by
input capture B
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TOICA
GRA
BRA
H'0005
H'0160
H'0005
H'0160
GRB
H'0180
Input capture A
Figure 8-38 Register Buffering (Example 2: Buffering of Input Capture Register)
218
ø
TIOC pin
Input capture
signal
TCNT
GR
n
n + 1
N
n
N + 1
M
m
n
N
n
M
BR
M
Figure 8-39 Input Capture and Buffer Transfer Timing (Example)
219
8.4.7 ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is
disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by
appropriate settings of the data register (DR) and data direction register (DDR) of the
corresponding input/output port. Figure 8-40 illustrates the timing of the enabling and disabling of
ITU output by TOER.
T1
T2
T3
ø
Address
TOER
TOER address
Timer output
ITU output
I/O port
ITU output pin
Generic input/output
Figure 8-40 Timing of Disabling of ITU Output by Writing to TOER (Example)
220
8.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when TCNT is updated from
the matching count to the next count). Therefore, when TCNT matches a general register, the
compare match signal is not generated until the next timer clock input. Figure 8-41 shows the
timing of the setting of IMFA and IMFB.
ø
TCNT input
clock
N
N + 1
TCNT
GR
N
Compare
match signal
IMF
IMI
Figure 8-41 Timing of Setting of IMFA and IMFB by Compare Match
221
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The TCNT contents are simultaneously transferred to the corresponding
general register. Figure 8-42 shows the timing.
ø
Input capture
signal
IMF
N
TCNT
GR
N
IMI
Figure 8-42 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8-43 shows the timing.
222
ø
TCNT
H'FFFF
H'0000
Overflow
signal
OVF
OVI
Figure 8-43 Timing of Setting of OVF
8.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8-44 shows the timing.
TSR write cycle
T1
T2
T3
ø
Address
IMF, OVF
TSR address
Figure 8-44 Timing of Clearing of Status Flags
223
8.5.3 Interrupt Sources
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Table 8-6 lists the interrupt sources.
Table 8-6 ITU Interrupt Sources
Interrupt
Channel
Source
IMIA0
IMIB0
OVI0
Description
Priority*
0
Compare match/input capture A0
Compare match/input capture B0
Overflow 0
High
1
2
3
4
IMIA1
IMIB1
OVI1
Compare match/input capture A1
Compare match/input capture B1
Overflow 1
IMIA2
IMIB2
OVI2
Compare match/input capture A2
Compare match/input capture B2
Overflow 2
IMIA3
IMIB3
OVI3
Compare match/input capture A3
Compare match/input capture B3
Overflow 3
IMIA4
IMIB4
OVI4
Compare match/input capture A4
Compare match/input capture B4
Overflow 4
Low
Note: *The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA and IPRB.
224
8.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a
3
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 8-45.
TCNT write cycle
T1
T2
T3
ø
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 8-45 Contention between TCNT Write and Clear
225
Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T
state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See
figure 8-46.
3
TCNT word write cycle
T1
T2
T3
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
TCNT write data
Figure 8-46 Contention between TCNT Word Write and Increment
226
Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T
2
or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The
3
TCNT byte that was not written retains its previous value. See figure 8-47, which shows an
increment pulse occurring in the T state of a byte write to TCNTH.
2
TCNTH byte write cycle
T1
T2
T3
ø
TCNTH address
Address
Internal write signal
TCNT input clock
TCNTH
N
M
X
TCNTH write data
X + 1
TCNTL
X
Figure 8-47 Contention between TCNT Byte Write and Increment
227
Contention between General Register Write and Compare Match: If a compare match occurs
in the T state of a general register write cycle, writing takes priority and the compare match
3
signal is inhibited. See figure 8-48.
General register write cycle
T1
T2
T3
ø
Address
GR address
Internal write signal
TCNT
N
N
N + 1
GR
M
General register write data
Compare match signal
Inhibited
Figure 8-48 Contention between General Register Write and Compare Match
228
Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T
state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is
set to 1.The same holds for underflow. See figure 8-49.
3
TCNT write cycle
T1
T2
T3
ø
Address
TCNT address
Internal write signal
TCNT input clock
Overflow signal
TCNT
H'FFFF
TCNT write data
M
OVF
Figure 8-49 Contention between TCNT Write and Overflow
229
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T state of a general register read cycle, the value before input capture is read.
3
See figure 8-50.
General register read cycle
T1
T2
T3
ø
GR address
Address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 8-50 Contention between General Register Read and Input Capture
230
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8-51.
ø
Input capture signal
Counter clear signal
TCNT input clock
N
H'0000
N
TCNT
GR
Figure 8-51 Contention between Counter Clearing by Input Capture and
Counter Increment
231
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T state of a general register write cycle, input capture takes priority and the write to
3
the general register is not performed. See figure 8-52.
General register write cycle
T1
T2
T3
ø
Address
GR address
Internal write signal
Input capture signal
TCNT
M
GR
M
Figure 8-52 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
ø
f =
(N + 1)
(f: counter frequency. ø: system clock frequency. N: value set in general register.)
232
Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T state of a write cycle, input
3
capture takes priority and the write to the buffer register is not performed.
See figure 8-53.
Buffer register write cycle
T1
T2
T3
ø
Address
BR address
Internal write signal
Input capture signal
GR
BR
N
X
N
TCNT value
M
Figure 8-53 Contention between Buffer Register Write and Input Capture
233
Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by
byte write access, all 16 bits of all synchronized counters assume the same value as the counter
that was addressed.
(Example) When channels 2 and 3 are synchronized
• Byte write to channel 2 or byte write to channel 3
Write A to upper byte
of channel 2
TCNT2
TCNT3
W
Y
X
Z
TCNT2
TCNT3
A
A
X
X
Upper byte Lower byte
Upper byte Lower byte
Write A to lower byte
of channel 3
TCNT2
TCNT3
Y
Y
A
A
Upper byte Lower byte
• Word write to channel 2 or word write to channel 3
TCNT2
TCNT3
W
Y
X
Z
TCNT2
TCNT3
A
A
B
B
Write AB word to
channel 2 or 3
Upper byte Lower byte
Upper byte Lower byte
234
ITU Operating Modes
Table 8-7 (a) ITU Operating Modes (Channel 0)
Register Settings
TOER
TSNC
TMDR
FDIR
TFCR
TIOR0
IOB
TCR0
Clock
Synchro-
nization
Master
Clear
Select
Operating Mode
Synchronous preset
PWM mode
MDF
—
PWM
Buffering
Enable
IOA
o
Select
SYNC0 = 1
—
—
—
o
—
—
—
—
o
o
o
o
o
o
o
o
o
—
PWM0 = 1
PWM0 = 0
—
—
o*
o
Output compare A
—
—
IOA2 = 0
Other bits
unrestricted
Output compare B
Input capture A
Input capture B
o
o
o
o
o
—
—
—
—
—
—
—
—
—
—
—
—
o
—
—
—
—
—
—
—
—
—
—
—
—
o
IOB2 = 0
Other bits
unrestricted
o
o
o
o
o
o
o
o
o
PWM0 = 0
IOA2 = 1
Other bits
unrestricted
o
PWM0 = 0
o
o
o
o
IOB2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
o
o
o
o
o
o
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
CCLR1 = 1
CCLR0 = 0
Synchronous SYNC0 = 1
clear
CCLR1 = 1
CCLR0 = 1
Legend: o Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Table 8-7 (b) ITU Operating Modes (Channel 1)
Register Settings
TOER
TSNC
TMDR
FDIR
TFCR
TIOR1
IOB
TCR1
Clock
Synchro-
nization
Master
Clear
Select
Operating Mode
Synchronous preset
PWM mode
MDF
—
PWM
Buffering
Enable
IOA
o
Select
SYNC1 = 1
—
—
—
o
—
—
—
—
o
o
o
o
o
o
o
o
o
*1
o
o
—
PWM1 = 1
PWM1 = 0
—
—
Output compare A
—
—
IOA2 = 0
Other bits
unrestricted
Output compare B
Input capture A
Input capture B
o
o
o
o
o
—
—
—
—
—
—
—
—
—
—
—
—
o
—
—
—
—
—
—
—
—
—
—
—
—
o
IOB2 = 0
Other bits
unrestricted
o
o
o
o
o
o
o
o
o
PWM1 = 0
IOA2 = 1
Other bits
unrestricted
o
PWM1 = 0
o
o
o
o
IOB2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
o
o
o
o
o
o
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
CCLR1 = 1
CCLR0 = 0
Synchronous SYNC1 = 1
clear
CCLR1 = 1
CCLR0 = 1
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.
Table 8-7 (c) ITU Operating Modes (Channel 2)
Register Settings
TOER
TSNC
TMDR
FDIR
TFCR
TIOR2
IOB
TCR2
Clock
Synchro-
nization
Master
Clear
Select
Operating Mode
Synchronous preset
PWM mode
MDF
PWM
Buffering
Enable
IOA
o
Select
SYNC2 = 1
o
o
o
—
—
—
o
—
—
—
—
o
o
o
o
o
o
o
o
o
PWM2 = 1
PWM2 = 0
—
—
o*
o
Output compare A
—
IOA2 = 0
Other bits
unrestricted
Output compare B
Input capture A
Input capture B
o
o
o
o
o
o
o
o
o
o
—
—
—
—
—
o
—
—
—
—
—
—
—
—
—
—
o
IOB2 = 0
Other bits
unrestricted
o
o
o
o
o
o
o
o
PWM2 = 0
IOA2 = 1
Other bits
unrestricted
o
PWM2 = 0
o
o
o
IOB2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
o
o
o
o
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
CCLR1 = 1
CCLR0 = 0
Synchronous SYNC2 = 1
clear
o
—
o
o
—
—
—
—
o
o
o
o
CCLR1 = 1
CCLR0 = 1
o
Phase counting mode
o
MDF = 1
o
o
—
Legend: o Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Table 8-7 (d) ITU Operating Modes (Channel 3)
Register Settings
TOER
TSNC
TMDR
FDIR
TFCR
TIOR3
IOB
TCR3
Clock
Synchro-
nization
Master
Clear
Select
Operating Mode
ynchronous preset
MDF
—
PWM
Buffering
Enable
IOA
o
Select
*1
S
SYNC3 = 1
—
—
—
o
o
o
o
o
o
o
o
o
o
o
o
o
o
*2
PWM mode
o
o
—
PWM3 = 1
PWM3 = 0
o
o
—
Output compare A
—
IOA2 = 0
Other bits
unrestricted
Output compare B
Input capture A
Input capture B
o
o
o
o
o
—
—
—
—
—
—
—
—
—
—
o
o
o
o
o
o
o
o
o
IOB2 = 0
Other bits
unrestricted
o
o
o
o
o
o
o
o
PWM3 = 0
EA3 ignored IOA2 = 1
Other bits
unrestricted
o
Other bits
unrestricted
PWM3 = 0
EA3 ignored
Other bits
unrestricted
o
o
o
IOA2 = 1
Other bits
unrestricted
*1
Counter
clearing
By compare
match/input
capture A
o
o
o
o
o
CCLR1 = 0
CCLR0 = 1
*1
By compare
match/input
capture B
o
CCLR1 = 1
CCLR0 = 0
*1
Synchronous SYNC3 = 1
clear
—
—
—
—
o
o
o
o
o
o
o
CCLR1 = 1
CCLR0 = 1
o
o
*1
Buffering
(BRA)
o
BFA3 = 1
Other bits
unrestricted
o
o
*1
Buffering
(BRB)
o
—
—
o
BFB3 = 1
Other bits
unrestricted
o
o
o
o
o
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Table 8-7 (e) ITU Operating Modes (Channel 4)
Register Settings
TOER
TSNC
TMDR
FDIR
TFCR
TIOR4
IOB
TCR4
Clock
Synchro-
nization
Master
Clear
Select
Operating Mode
ynchronous preset
MDF
—
PWM
Buffering
Enable
IOA
o
Select
*1
S
SYNC4 = 1
—
—
—
o
o
o
o
o
o
o
o
o
o
o
o
o
o
*2
PWM mode
o
o
—
PWM4 = 1
PWM4 = 0
o
o
—
Output compare A
—
IOA2 = 0
Other bits
unrestricted
Output compare B
Input capture A
Input capture B
o
o
o
o
o
—
—
—
—
—
—
—
—
—
—
o
o
o
o
o
o
o
o
o
IOB2 = 0
Other bits
unrestricted
o
o
o
o
o
o
o
o
PWM4 = 0
EA4 ignored IOA2 = 1
Other bits
unrestricted
o
Other bits
unrestricted
PWM4 = 0
EB4 ignored
Other bits
unrestricted
o
o
o
IOB2 = 1
Other bits
unrestricted
*1
Counter
clearing
By compare
match/input
capture A
o
o
o
o
o
CCLR1 = 0
CCLR0 = 1
*1
By compare
match/input
capture B
o
CCLR1 = 1
CCLR0 = 0
*1
Synchronous SYNC4 = 1
clear
—
—
—
—
o
o
o
o
o
o
o
CCLR1 = 1
CCLR0 = 1
o
o
*1
Buffering
(BRA)
o
BFA4 = 1
Other bits
unrestricted
o
o
*1
Buffering
(BRB)
o
—
—
o
BFB4 = 1
Other bits
unrestricted
o
o
o
o
o
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
240
Section 9 Programmable Timing Pattern Controller
9.1 Overview
The H8/3001 has a built-in programmable timing pattern controller (TPC) that provides pulse
outputs by using the 16-bit integrated timer unit (ITU) as a time base. The TPC pulse outputs are
divided into 4-bit groups (group 2 to group 0) that can operate simultaneously and independently.
9.1.1 Features
TPC features are listed below.
•
12-bit output data
Maximum 12-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
Three output groups
•
Output trigger signals can be selected in 4-bit groups to provide up to three different 4-bit
outputs.
•
•
Selectable output trigger signals
Output trigger signals can be selected for each group from the compare-match signals of four
ITU channels.
Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
241
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of the TPC.
ITU compare match signals
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
Control logic
Internal
data bus
PBDR
NDRB
NDRA
TP11
TP10
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Pulse output
pins, group 2
Pulse output
pins, group 1
PADR
Pulse output
pins, group 0
Legend
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register B
NDERA: Next data enable register A
PBDDR: Port B data direction register
PADDR: Port A data direction register
NDRB: Next data register B
NDRA: Next data register A
PBDR: Port B data register
PADR: Port A data register
Figure 9-1 TPC Block Diagram
242
9.1.3 TPC Pins
Table 9-1 summarizes the TPC output pins.
Table 9-1 TPC Pins
Name
Symbol
TP0
I/O
Function
TPC output 0
TPC output 1
TPC output 2
TPC output 3
TPC output 4
TPC output 5
TPC output 6
TPC output 7
TPC output 8
TPC output 9
TPC output 10
TPC output 11
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Group 0 pulse output
TP1
TP2
TP3
TP4
Group 1 pulse output
Group 2 pulse output
TP5
TP6
TP7
TP8
TP9
TP10
TP11
243
9.1.4 Registers
Table 9-2 summarizes the TPC registers.
Table 9-2 TPC Registers
Address*1
H'FFD1
H'FFD3
H'FFD4
H'FFD6
H'FFA0
H'FFA1
H'FFA2
H'FFA3
Name
Abbreviation
PADDR
PADR
R/W
Initial Value
Port A data direction register
Port A data register
W
H'00
R/(W)*2 H'00
H'00
R/(W)*2 H'00
Port B data direction register
Port B data register
PBDDR
PBDR
W
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Next data register A
TPMR
R/W
R/W
R/W
R/W
R/W
H'F0
H'FF
H'00
H'00
H'00
TPCR
NDERB
NDERA
NDRA
H'FFA5/
H'FFA7*3
H'FFA4
H'FFA6*4
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1.
4. When the output triggers of TPC output group 2 and output group 3 are identical, as set
in TPCR, the NDRB address becomes H'FFA4. When the output triggers differ, the
NDRB address for group 2 becomes H'FFA6. The H8/3001 does not have any pins that
correspond to TPC output group 3.
244
9.2 Register Descriptions
9.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP to TP . Bits corresponding to pins used for TPC output must
7
0
be set to 1. For further information about PADDR, see section 7.7, Port A.
9.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
7
PA7
0
6
PA6
0
5
PA5
0
4
PA4
0
3
PA3
0
2
PA2
0
1
PA1
0
0
PA0
0
Initial value
Read/Write
R/(W)*
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R/(W)* R/(W)*
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 7.7, Port A.
245
9.2.3 Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
—
0
6
—
0
5
—
0
4
—
0
3
2
1
0
PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
Read/Write
0
0
0
0
W
W
W
W
W
W
W
W
Reserved bits
Port B data direction 3 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP to TP . Bits corresponding to pins used for TPC output must
11
8
be set to 1. For further information about PBDDR, see section 7.8, Port B.
9.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for group 2 when these
TPC output groups are used.
Bit
7
—
6
—
0
5
—
0
4
—
0
3
PB3
0
2
PB2
0
1
PB1
0
0
PB0
0
Initial value
Read/Write
0
R/(W)*
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R/(W)* R/(W)*
Reserved bits
Port B data 3 to 0
These bits store output data
for TPC output group 2
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 7.8, Port B.
246
9.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in
7
0
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA5
Bit
7
NDR7
0
6
NDR6
0
5
NDR5
0
4
NDR4
0
3
NDR3
0
2
NDR2
0
1
NDR1
0
0
NDR0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 7 to 4
Next data 3 to 0
These bits store the data that
These bits store the data that
TPC output group 1 outputs next
TPC output group 0 outputs next
Address H'FFA7
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
247
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFA5
Bit
7
NDR7
0
6
NDR6
0
5
NDR5
0
4
NDR4
0
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 7 to 4
Reserved bits
These bits store the data that
TPC output group 1 outputs next
Address H'FFA7
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
NDR3
0
2
NDR2
0
1
NDR1
0
0
NDR0
0
Initial value
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Next data 3 to 0
These bits store the data that
TPC output group 0 outputs next
248
9.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the data that TPC output groups 3 and 2
(pins TP to TP ) output next. However, the H8/3001 does not have any pins that correspond to
11
8
TPC output group 3. During TPC output, when an ITU compare match event specified in TPCR
occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB
differs depending on whether TPC output groups 2 and 3 have the same output trigger or different
output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFA4. The upper four bits belong to group
3 and the lower four bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFA4
Bit
7
—
6
—
5
—
4
—
3
2
1
NDR9
0
0
NDR8
0
NDR11 NDR10
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Next data 11 to 8
These bits store the data that
TPC output group 2 outputs next
Address H'FFA6
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
249
Different Triggers for TPC Output Groups 2 and 3: If TPC output triggers 2 and 3 are
triggered by different compare match events, the address of the upper four bits of NDRB is
H'FFA4, and the address of the lower four bits (group 2) is H'FFA6. All bits of address H'FFA4
and bits 7 to 4 of address H'FFA6 are reserved bits. Bits 7 to 4 of H'FFA4 can be written and read,
while all other bits are read-only bits that always read 1.
Address H'FFA4
Bit
7
—
6
—
5
—
4
—
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
—
—
—
—
Reserved bits
Address H'FFA6
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
NDR9
0
0
NDR8
0
NDR11 NDR10
Initial value
Read/Write
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Next data 11 to 8
These bits store the next output
data for TPC output group 2
250
9.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP to TP ) on a bit-by-bit basis.
7
0
Bit
7
6
5
4
3
2
1
0
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected
in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP to TP ) on a bit-by-bit basis.
7
0
Bits 7 to 0
NDER7 to NDER0
Description
0
1
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
(Initial value)
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
251
9.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP to TP ) on a bit-by-bit basis.
15
8
Bit
7
—
6
—
5
—
4
—
3
2
1
0
NDER11 NDER10 NDER9 NDER8
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Next data enable 11 to 8
These bits enable or disable
TPC output group 2
If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to
the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Although reserved, these bits can be written and read.
Bits 3 to 0—Next Data Enable 11 to 8 (NDER11 to NDER8): These bits enable or disable TPC
output group 2 (TP to TP ) on a bit-by-bit basis.
15
8
Bits 7 to 0
NDER11 to NDER8
Description
0
TPC outputs TP11 to TP8 are disabled
(Initial value)
(NDR11 to NDR8 are not transferred to PB3 to PB0)
1
TPC outputs TP11 to TP8 are enabled
(NDR11 to NDR8 are transferred to PB3 to PB0)
252
9.2.9 TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3.
Note that the H8/3001
does not have any
pins corresponding
to group 3. (They are
used for setting the
address of NDRB.)
Group 2 compare
match select 1 and 0
These bits select
the compare match
Group 1 compare
match select 1 and 0
These bits select
event that triggers
TPC output group 2
(TP11 to TP8)
the compare match
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
event that triggers
TPC output group 1
(TP7 to TP )
4
(TP3 to TP )
0
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
253
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3. Note that the H8/3001 does not
have any pins corresponding to TPC output group 3. (They are used for setting the address of
NDRB.)
Bit 7
Bit 6
G3CMS1 G3CMS0 Description
0
1
0
1
0
1
TPC output group 3 is triggered by compare match in ITU channel 0
TPC output group 3 is triggered by compare match in ITU channel 1
TPC output group 3 is triggered by compare match in ITU channel 2
TPC output group 3 is triggered by compare match
in ITU channel 3
(Initial value)
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP to TP ).
11
8
Bit 5
Bit 4
G2CMS1 G2CMS0 Description
0
1
0
1
0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 0
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 1
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 2
TPC output group 2 (TP11 to TP8) is triggered by
compare match in ITU channel 3
(Initial value)
254
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP to TP ).
7
4
Bit 3
Bit 2
G1CMS1 G1CMS0 Description
0
1
0
1
0
1
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 0
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 1
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 2
TPC output group 1 (TP7 to TP4) is triggered by
compare match in ITU channel 3
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP to TP ).
3
0
Bit 1
Bit 0
G0CMS1 G0CMS0 Description
0
1
0
1
0
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 2
TPC output group 0 (TP3 to TP0) is triggered by
compare match in ITU channel 3
(Initial value)
255
9.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
2
1
0
G2NOV G1NOV G0NOV
Initial value
Read/Write
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP to TP8 )
11
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP4 )
7
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP0 )
3
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see
section 9.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
256
Bit 3—Reserved: Although reserved, this bit can be written and read.
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP to TP ).
11
8
Bit 2
G2NOV
Description
0
Normal TPC output in group 2 (output values change at
compare match A in the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP to TP ).
7
4
Bit 1
G1NOV
Description
0
Normal TPC output in group 1 (output values change at
compare match A in the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP to TP ).
3
0
Bit 0
G0NOV
Description
0
Normal TPC output in group 0 (output values change at
compare match A in the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
257
9.3 Operation
9.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 9-2 illustrates the TPC output operation. Table 9-3 summarizes the TPC operating
conditions.
DDR
Q
NDER
Q
Output trigger signal
C
Internal
data bus
Q
DR
D
Q
NDR
D
TPC output pin
Figure 9-2 TPC Output Operation
Table 9-3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
1
0
Generic input port
Generic output port
1
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
Sequential output of up to 12-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 9.3.4, Non-Overlapping TPC Output.
258
9.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when
the selected compare match event occurs. Figure 9-3 shows the timing of these operations for the
case of normal output in groups 2, triggered by compare match A.
ø
TCNT
GRA
N
N + 1
N
n
Compare
match A signal
NDRB
PBDR
m
m
n
n
TP8 to TP15
Figure 9-3 Timing of Transfer of Next Data Register Contents and Output (Example)
259
9.3.3 Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 9-4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
Select GR functions
Set GRA value
1
2
3
4
1. Set TIOR to make GRA an output compare
register (with output inhibited).
2. Set the TPC output trigger period.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
ITU setup
Select counting operation
Select interrupt request
Set initial output data
Select port output
5
6
7
8
6. Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. Select the ITU compare match event to be
used as the TPC output trigger in TPCR.
9. Set the next TPC output values in the NDR bits.
10. Set the STR bit to 1 in TSTR to start the
timer counter.
Port and
TPC setup
Enable TPC output
Select TPC output trigger
11. At each IMFA interrupt, set the next output
values in the NDR bits.
Set next TPC output data
Start counter
9
ITU setup
10
No
11
Compare match?
Yes
Set next TPC output data
Figure 9-4 Setup Procedure for Normal TPC Output (Example)
260
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an
example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
GRA
Compare match
TCNT
H'0000
NDRA
Time
80
C0
40
60
20
30
10
18
08
88
80
C0
40
PADR
TP7
00
80
C0
40
60
20
30
10
18
08
88
80
C0
TP6
TP5
TP4
TP3
•
•
•
•
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRA.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents
are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRA.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts.
Figure 9-5 Normal TPC Output Example (Five-Phase Pulse Output)
261
9.3.4 Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 9-6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
Select GR functions
Set GR values
1
2
3
4
1. Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
2. Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
9. In TPMR, select the groups that will operate
in non-overlap mode.
10. Set the next TPC output values in the NDR
bits.
ITU setup
Select counting operation
Select interrupt requests
Set initial output data
Set up TPC output
5
6
7
8
9
Enable TPC transfer
Port and
TPC setup
Select TPC transfer trigger
Select non-overlapping groups
11. Set the STR bit to 1 in TSTR to start the timer
counter.
12. At each IMFA interrupt, write the next output
value in the NDR bits.
Set next TPC output data
Start counter
10
11
ITU setup
No
Compare match A?
Yes
Set next TPC output data
12
Figure 9-6 Setup Procedure for Non-Overlapping TPC Output (Example)
262
Example of Non-Overlapping TPC Output (Example of Eight-Phase Complementary Non-
Overlapping Output): Figure 9-7 shows an example of the use of TPC output for eight-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
Time
NDRA
95
00
65
59
56
95
65
PADR
TP7
95
05
65
41 59
50
56
14 95
05 65
Non-overlap margin
TP6
TP5
TP4
TP3
TP2
TP1
TP0
• The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
• H'FF is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set
Bits G1NOV and G0NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
• Eight-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
Figure 9-7 Non-Overlapping TPC Output Example (Eight-Phase Complementary
Non-Overlapping Pulse Output)
263
9.3.5 TPC Output Triggering by Input Capture
TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions
as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by
the input capture signal. Figure 11-8 shows the timing.
ø
TIOC pin
Input capture
signal
N
NDR
DR
M
N
Figure 9-8 TPC Output Triggering by Input Capture (Example)
264
9.4 Usage Notes
9.4.1 Operation of TPC Output Pins
TP to TP are multiplexed with ITU, address output, and other pin functions. When ITU or
0
11
address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer
from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
9.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 9-9 illustrates the non-overlapping TPC output operation.
DDR
Q
NDER
Q
Compare match A
Compare match B
C
Internal
data bus
Q
DR
D
Q
NDR
D
TPC output pin
Figure 9-9 Non-Overlapping TPC Output
265
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR. The next data must be written before the next compare match B occurs.
Figure 9-10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output
0/1 output
0 output
0/1 output
Write to NDR
in this interval
Write to NDR
in this interval
Do not write
to NDR in this
interval
Do not write
to NDR in this
interval
Figure 9-10 Non-Overlapping Operation and NDR Write Timing
266
Section 10 Serial Communication Interface
10.1 Overview
The H8/3001 has one channel of serial communication interface (SCI). The SCI can communicate
in asynchronous mode or synchronous mode, and has a multiprocessor communication function
for serial communication among two or more processors.
10.1.1 Features
SCI features are listed below.
•
Selection of asynchronous or synchronous mode for serial communication
a. Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous serial
communication. It can also communicate with two or more other processors using the
multiprocessor communication function. There are twelve selectable serial data
communication formats.
— Data length:
7 or 8 bits
— Stop bit length:
— Parity bit:
— Multiprocessor bit:
1 or 2 bits
even, odd, or none
1 or 0
— Receive error detection: parity, overrun, and framing errors
— Break detection:
by reading the RxD level directly when a framing error occurs
b. Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function. There is one serial data
communication format.
— Data length:
8 bits
— Receive error detection: overrun errors
267
•
Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
•
•
Built-in baud rate generator with selectable bit rates
Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin.
•
Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are
requested independently.
268
10.1.2 Block Diagram
Figure 10-1 shows a block diagram of the SCI.
Internal
data bus
Module data bus
RDR
RSR
TDR
TSR
SSR
BRR
SCR
SMR
ø
Baud rate
generator
RxD
TxD
SCK
ø/4
Transmit/
receive control
ø/16
ø/64
Parity generate
Parity check
Clock
External clock
TEI
TXI
RXI
ERI
Legend
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 10-1 SCI Block Diagram
269
10.1.3 Input/Output Pins
The SCI has serial pins for each channel as listed in table 10-1.
Table 10-1 SCI Pins
Name
Abbreviation
SCK
I/O
Function
Serial clock pin
Receive data pin
Transmit data pin
Input/output
Input
SCI clock input/output
SCI receive data input
SCI transmit data output
RxD
TxD
Output
10.1.4 Register Configuration
The SCI has internal registers as listed in table 10-2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, and control the transmitter and receiver
sections.
Table 10-2 Registers
Address*1
H'FFB0
H'FFB1
H'FFB2
H'FFB3
H'FFB4
H'FFB5
Name
Abbreviation
SMR
R/W
R/W
R/W
R/W
R/W
R/(W)*2
R
Initial Value
H'00
Serial mode register
Bit rate register
BRR
H'FF
Serial control register
Transmit data register
Serial status register
Receive data register
SCR
H'00
TDR
H'FF
SSR
H'84
RDR
H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
270
10.2 Register Descriptions
10.2.1 Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When 1 byte has been received, it is automatically
transferred to RDR. The CPU cannot read or write RSR directly.
10.2.2 Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into
RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to
be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
271
10.2.3 Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next
transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR,
however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR
directly.
10.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
272
10.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock
source for the baud rate generator.
Bit
7
C/A
0
6
5
PE
0
4
O/E
0
3
STOP
0
2
MP
0
1
CKS1
0
0
CKS0
0
CHR
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 1/0
These bits select the
baud rate generator’s
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
273
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7
C/A
Description
0
Asynchronous mode
Synchronous mode
(Initial value)
1
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In
synchronous mode the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR
Description
8-bit data
0
1
(Initial value)
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode
the parity bit is neither added nor checked, regardless of the PE setting.
Bit 5
PE
Description
0
Parity bit not added or checked
Parity bit added and checked*
(Initial value)
1
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data according to the
even or odd parity mode selected by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
274
Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in
asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.
The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled
in asynchronous mode.
Bit 4
O/E
Description
Even parity*1
Odd parity*2
0
(Initial value)
1
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
Description
0
1
One stop bit*1
Two stop bits*2
(Initial value)
Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character.
2. Two stop bits (with value 1) are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the
next incoming character.
275
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 10.3.3,
Multiprocessor Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source of the on-chip
baud rate generator. Four clock sources are available: ø, ø/4, ø/16, and ø/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see
section 10.2.8, Bit Rate Register.
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
1
1
0
1
0
1
ø
(Initial value)
ø/4
ø/16
ø/64
276
10.2.6 Serial Control Register (SCR)
SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
MPIE
0
2
TEIE
0
1
CKE1
0
0
CKE0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit end interrupt enable
Enables or disables transmit-
end interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
277
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
Transmit-data-empty interrupt request (TXI) is enabled
(Initial value)
1
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt
(RXI) requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from
RSR to RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE
Description
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests
are disabled
(Initial value)
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,
PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5
TE
Description
0
Transmitting disabled*1
Transmitting enabled*2
(Initial value)
1
Notes: 1. The TDRE bit is locked at 1 in SSR.
2. In the enabled state, serial transmitting starts when the TDRE bit in SSR is cleared to 0
after writing of transmit data into TDR. Select the transmit format in SMR before setting
the TE bit to 1.
278
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
Description
0
Receiving disabled*1
Receiving enabled*2
(Initial value)
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
(Initial value)
The MPIE bit is cleared to 0.
MPB = 1 in received data.
1
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF,
FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit
set to 1 is received.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and
ORER flags to be set.
279
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
0
1
Transmit-end interrupt requests (TEI) are disabled*
Transmit-end interrupt requests (TEI) are enabled*
(Initial value)
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 10-9 in
section 10.3, Operation.
Bit 1
Bit 0
CKE1
CKE0
Description
0
0
Asynchronous mode
Internal clock, SCK pin available for generic
input/output *1
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Internal clock, SCK pin used for serial clock output *1
Internal clock, SCK pin used for clock output *2
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input *3
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input *3
External clock, SCK pin used for serial clock input
0
1
1
1
0
1
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
280
10.2.7 Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI
operating status.
Bit
7
6
RDRF
0
5
ORER
0
4
FER
0
3
PER
0
2
TEND
1
1
MPB
0
0
MPBT
0
TDRE
1
Initial value
Read/Write
R/(W)*
R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Multiprocessor
bit transfer
Value of multi-
processor bit to
be transmitted
Multiprocessor bit
Stores the received
multiprocessor bit value
Transmit end
Status flag indicating end of
transmission
Parity error
Status flag indicating detection of
a receive parity error
Framing error
Status flag indicating detection of a receive
framing error
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from TDR into
TSR and new data can be written in TDR
Note: * Only 0 can be written, to clear the flag.
281
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 7
TDRE
Description
0
TDR contains valid transmit data
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0.
1
TDR does not contain valid transmit data
[Setting conditions]
(Initial value)
The chip is reset or enters standby mode.
The TE bit in SCR is cleared to 0.
TDR contents are loaded into TSR, so new data can be written in TDR.
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
Description
0
RDR does not contain new receive data
[Clearing conditions]
(Initial value)
The chip is reset or enters standby mode.
Software reads RDRF while it is set to 1, then writes 0.
1
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR.
Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
282
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER
Description
0
Receiving is in progress or has ended normally
[Clearing conditions]
(Initial value)*1
The chip is reset or enters standby mode.
Software reads ORER while it is set to 1, then writes 0.
1
A receive overrun error occurred*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4
FER
Description
0
Receiving is in progress or has ended normally
[Clearing conditions]
(Initial value)*1
The chip is reset or enters standby mode.
Software reads FER while it is set to 1, then writes 0.
1
A receive framing error occurred*2
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
283
Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER
Description
0
Receiving is in progress or has ended normally*1
[Clearing conditions]
(Initial value)
The chip is reset or enters standby mode.
Software reads PER while it is set to 1, then writes 0.
1
A receive parity error occurred*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the even or
odd parity setting of O/E in SMR.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is
a read-only bit and cannot be written.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
1
End of transmission
(Initial value)
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit is cleared to 0 in SCR.
TDRE is 1 when the last bit of a serial character is transmitted.
284
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Bit 1
MPB
Description
0
1
Multiprocessor bit value in receive data is 0*
Multiprocessor bit value in receive data is 1
(Initial value)
Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting.
Bit 0
MPBT
Description
0
1
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
(Initial value)
10.2.8 Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode.
Table 10-3 shows examples of BRR settings in asynchronous mode. Table 10-4 shows examples
of BRR settings in synchronous mode.
285
Table 10-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
ø (MHz)
2
2.097152
Error
(%)
2.4576
Error
(%)
174 –0.26
3
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
1
0
0
0
0
0
0
0
—
N
110
141 0.03
103 0.16
207 0.16
103 0.16
148 –0.04
108 0.21
217 0.21
108 0.21
212 0.03
155 0.16
150
127
255
127
63
31
15
7
0
300
0
77
0.16
600
0
155 0.16
1200
2400
4800
9600
19200
31250
38400
51
25
12
6
0.16
0.16
0.16
–6.99
8.51
0
54
26
13
6
–0.70
1.14
0
77
38
19
9
0.16
0.16
–2.34
–2.34
–2.34
0
0
–2.48
–2.48
13.78
4.86
0
0
2
2
3
0
4
1
1
1
22.88
0
2
1
–18.62
1
–14.67
1
—
—
ø (MHz)
3.6864
4
4.9152
Error
5
Bit Rate
(bits/s)
Error
(%)
Error
(%)
Error
(%)
n
2
1
1
0
0
0
0
0
0
—
0
N
n
2
1
1
0
0
0
0
0
0
0
0
N
n
2
1
1
0
0
0
0
0
0
0
0
N
(%)
n
2
2
1
1
0
0
0
0
0
0
0
N
110
64
191
95
191
95
47
23
11
5
0.70
0
70
0.03
86
255
127
255
127
63
31
15
7
0.31
88
64
–0.25
0.16
150
207 0.16
103 0.16
207 0.16
103 0.16
0
300
0
0
129 0.16
64 0.16
129 0.16
600
0
0
1200
2400
4800
9600
19200
31250
38400
0
0
0
51
25
12
6
0.16
0.16
0.16
–6.99
0
0
64
32
15
7
0.16
–1.36
1.73
1.73
0
0
0
0
0
0
0
—
2
—
0
3
4
–1.70
0
4
2
8.51
3
3
1.73
286
Table 10-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont)
ø (MHz)
6
6.144
Error
(%)
108 0.08
7.3728
Error
(%)
130 –0.07
8
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
0
N
110
106 –0.44
77 0.16
155 0.16
77 0.16
155 0.16
141 0.03
103 0.16
207 0.16
103 0.16
207 0.16
103 0.16
150
79
159
79
159
79
39
19
9
0
95
191
95
191
95
47
23
11
6
0
300
0
0
600
0
0
1200
2400
4800
9600
19200
31250
38400
0
0
77
38
19
9
0.16
0.16
–2.34
–2.34
0
0
0
0
0
51
25
12
7
0.16
0.16
0.16
0
0
0
0
0
5
5
2.40
0
5.33
0
4
–2.34
4
5
6
–6.99
ø (MHz)
9.8304
10
12
12.288
Error
(%)
217 0.08
Bit Rate
(bits/s)
Error
(%)
Error
(%)
Error
(%)
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
2
2
1
1
0
0
0
0
0
0
N
n
2
2
2
1
1
0
0
0
0
0
0
N
n
2
2
2
1
1
0
0
0
0
0
0
N
110
174 –0.26
177 –0.25
129 0.16
212 0.03
155 0.16
150
127
255
127
255
127
63
0
159
79
159
79
159
79
39
19
11
0
300
0
64
129 0.16
64 0.16
129 0.16
0.16
77
155 0.16
77 0.16
155 0.16
0.16
0
600
0
0
1200
2400
4800
9600
19200
31250
38400
0
0
0
0
0
64
32
15
9
0.16
–1.36
1.73
0
77
38
19
11
9
0.16
0.16
–2.34
0
0
31
0
0
15
0
0
9
–1.70
0
2.40
0
7
7
1.73
–2.34
9
287
Table 10-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont)
ø (MHz)
14
14.7456
Error
16
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
2
2
2
1
1
0
0
0
0
0
0
N
n
3
2
2
1
1
0
0
0
0
0
0
N
(%)
n
3
2
2
1
1
0
0
0
0
0
0
N
110
248 –0.17
181 0.16
64
191
95
191
95
191
95
47
23
14
11
0.70
70
0.03
150
0
207 0.16
103 0.16
207 0.16
103 0.16
207 0.16
103 0.16
300
90
181 0.16
90 0.16
181 0.16
0.16
0
600
0
1200
2400
4800
9600
19200
31250
38400
0
0
90
45
22
13
10
0.16
–0.93
–0.93
0
0
0
51
25
15
12
0.16
0.16
0
0
–1.70
0
3.57
0.16
288
Table 10-4 Examples of Bit Rates and BRR Settings in Synchronous Mode
ø (MHz)
2
4
8
10
16
Bit Rate
(bits/s)
n
3
2
1
1
0
0
0
0
0
0
0
0
N
n
—
2
2
1
1
0
0
0
0
0
0
0
0
N
n
—
3
N
n
N
n
—
3
3
2
2
1
1
0
0
0
0
0
0
0
—
0
N
110
70
124
249
124
199
99
49
19
9
—
—
—
—
—
—
1
—
—
—
—
249
124
249
99
49
24
9
—
250
249
124
249
99
199
99
39
19
9
124
249
124
199
99
199
79
39
19
7
249
124
249
99
199
99
159
79
39
15
7
500
2
1 k
2
2.5 k
5 k
1
1
1
10 k
25 k
50 k
100 k
250 k
500 k
1 M
0
0
0
0
0
0
4
0
0
1
3
0
0
0*
1
0
3
0
4
0*
0
1
—
—
0
—
—
0*
3
2 M
0
0*
—
1
2.5 M
4 M
—
—
0*
Note: Settings with an error of 1% or less are recommended.
Legend
Blank: No setting available
—:
Setting possible, but error occurs
*:
Continuous transmit/receive not possible
The BRR setting is calculated as follows:
Asynchronous mode:
ø
N =
× 106 – 1
64 × 22n–1 × B
Synchronous mode:
ø
N =
× 106 – 1
8 × 22n–1 × B
B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
ø: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the table below.)
289
SMR Settings
n
0
1
2
3
Clock Source
CKS1
CKS0
ø
0
0
1
1
0
1
0
1
ø/4
ø/16
ø/64
The bit rate error in asynchronous mode is calculated as follows.
ø × 106
Error (%) =
–1 × 100
(N + 1) × B × 64 × 22n–1
290
Table 10-5 indicates the maximum bit rates in asynchronous mode for various system clock
frequencies. Tables 10-6 and 10-7 indicate the maximum bit rates with external clock input.
Table 10-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
ø (MHz)
2
Maximum Bit Rate (bits/s)
62500
n
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2.097152
2.4576
3
65536
76800
93750
3.6864
4
115200
125000
153600
156250
187500
192000
230400
250000
307200
312500
375000
384000
437500
460800
500000
4.9152
5
6
6.144
7.3728
8
9.8304
10
12
12.288
14
14.7456
16
291
Table 10-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
ø (MHz)
2
External Input Clock (MHz)
0.5000
Maximum Bit Rate (bits/s)
31250
2.097152
2.4576
3
0.5243
32768
0.6144
38400
0.7500
46875
3.6864
4
0.9216
57600
1.0000
62500
4.9152
5
1.2288
76800
1.2500
78125
6
1.5000
93750
6.144
7.3728
8
1.5360
96000
1.8432
115200
125000
153600
156250
187500
192000
218750
230400
250000
2.0000
9.8304
10
2.4576
2.5000
12
3.0000
12.288
14
3.0720
3.5000
14.7456
16
3.6864
4.0000
292
Table 10-7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
ø (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
333333.3
2
0.3333
0.6667
1.0000
1.3333
1.6667
2.0000
2.3333
2.6667
4
666666.7
6
1000000.0
8
1333333.3
10
12
14
16
1666666.7
2000000.0
2333333.3
2666666.7
293
10.3 Operation
10.3.1 Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a
synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous or synchronous mode and the
communication format are selected in SMR, as shown in table 10-8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 10-9.
Asynchronous Mode
•
•
Data length is selectable: 7 or 8 bits.
Parity and multiprocessor bits are selectable. So is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
•
•
In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
An internal or external clock can be selected as the SCI clock source.
— When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
— When an external clock is selected, the external clock input must have a frequency
16 times the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode
•
•
•
The communication format has a fixed 8-bit data length.
In receiving, it is possible to detect overrun errors.
An internal or external clock can be selected as the SCI clock source.
— When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a serial clock signal to external devices.
— When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
294
Table 10-8 SMR Settings and Serial Communication Formats
SCI Communication Format
SMR Settings
Multi-
processor Parity
Stop
Bit
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
Data
C/A CHR MP
PE
STOP Mode
Length
Bit
Bit
Length
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
—
0
0
0
0
0
0
0
0
1
1
1
1
—
0
0
1
0
1
0
1
0
1
0
1
0
1
—
Asynchronous 8-bit data Absent
mode
Absent
1 bit
0
2 bits
1
Present 1 bit
2 bits
1
0
7-bit data
Absent
1 bit
0
2 bits
1
Present 1 bit
2 bits
1
Asynchronous
mode (multi-
processor
—
—
—
—
—
8-bit data Present
7-bit data
Absent
1 bit
2 bits
1 bit
format)
2 bits
None
Synchronous
mode
8-bit data Absent
Table 10-9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings
SCI Transmit/Receive Clock
Bit 7 Bit 1 Bit 0
C/A CKE1 CKE0
Mode
Clock Source SCK Pin Function
0
0
0
0
0
1
Asynchronous mode Internal
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
External
Inputs a clock with frequency
16 times the bit rate
Synchronous mode
Internal
External
Outputs the serial clock
Inputs the serial clock
295
10.3.2 Operation in Asynchronous Mode
In asynchronous mode each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 10-2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
Idle (mark) state
1
(LSB)
(MSB)
1
Serial data
0
D0 D1 D2 D3 D4 D5 D6 D7 0/1
1
1
Start
bit
Parity Stop
bit bit
Transmit or receive data
7 bits or 8 bits
1 bit
1 bit or 1 bit or
no bit 2 bits
One unit of data (character or frame)
Figure 10-2 Data Format in Asynchronous Communication (Example: 8-Bit Data with
Parity and 2 Stop Bits)
296
Communication Formats: Table 10-10 shows the 12 communication formats that can be selected
in asynchronous mode. The format is selected by settings in SMR.
Table 10-10 Serial Communication Formats (Asynchronous Mode)
SMR Settings
Serial Communication Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
8-bit data
8-bit data
8-bit data
7-bit data
7-bit data
7-bit data
7-bit data
8 bit data
STOP
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
S
S
S
S
S
S
S
S
STOP STOP
P
P
STOP
1
STOP STOP
1
STOP
0
STOP STOP
0
P
P
STOP
1
STOP STOP
1
MPB STOP
—
—
—
—
S
S
S
8 bit data
7-bit data
7-bit data
MPB STOP STOP
MPB STOP
MPB STOP STOP
Legend
S:
Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
297
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 10-9.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 10-3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0
D0 D1 D2 D3 D4 D5 D6 D7 0/1
1 frame
1
1
Figure 10-3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and
RDR, which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
Figure 10-4 is a sample flowchart for initializing the SCI.
298
Start of initialization
1. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0. If clock output is selected in
asynchronous mode, clock output starts immediately after
the setting is made in SCR.
Clear TE and RE bits
to 0 in SCR
2. Select the communication format in SMR.
3. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
4. Wait for at least the interval required to transmit or receive
1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits as necessary. Setting the TE
or RE bit enables the SCI to use the TxD or RxD pin.
Set CKE1 and CKE0 bits
in SCR (leaving TE and
RE bits cleared to 0)
1
2
Select communication
format in SMR
3
Set value in BRR
Wait
No
1 bit interval
elapsed?
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
4
Transmitting or receiving
Figure 10-4 Sample Flowchart for SCI Initialization
299
Transmitting Serial Data (Asynchronous Mode): Figure 10-5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
1
1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
Initialize
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit data
in TDR and clear the TDRE flag to 0.
Start transmitting
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE
flag to 0.
2
Read TDRE flag in SSR
4. To output a break signal at the end of serial transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then clear the
TE bit to 0 in SCR.
No
TDRE = 1?
Yes
Write transmit data
in TDR and clear TDRE
flag to 0 in SSR
All data
transmitted?
No
3
Yes
Read TEND flag in SSR
No
No
TEND = 1?
Yes
Output break
signal?
4
Yes
Clear DR bit to 0,
set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 10-5 Sample Flowchart for Transmitting Serial Data
300
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
— Start bit:
One 0 bit is output.
— Transmit data:
7 or 8 bits are output, LSB first.
— Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. Formats in which neither a parity bit nor a
multiprocessor bit is output can also be selected.
— Stop bit:
— Mark state:
One or two 1 bits (stop bits) are output.
Output of 1 bits continues until the start bit of the next
transmit data.
•
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of
the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the
stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 10-6 shows an example of SCI transmit operation in asynchronous mode.
Start
bit
Parity Stop Start
bit bit bit
Parity Stop
bit bit
Data
Data
1
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle (mark)
state
TDRE
TEND
TXI
TXI interrupt handler
TXI
interrupt
request
writes data in TDR and
clears TDRE flag to 0
interrupt
request
TEI interrupt request
1 frame
Figure 10-6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and 1 Stop Bit)
301
Receiving Serial Data (Asynchronous Mode): Figure 10-7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
Initialize
1
2
1. SCI initialization: the receive data function of
the RxD pin is selected automatically.
2., 3. Receive error handling and break
detection: if a receive error occurs, read the
ORER, PER, and FER flags in SSR to identify
the error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if any
of the ORER, PER, and FER flags remains
set to 1. When a framing error occurs, the
RxD pin can be read to detect the break state.
4. SCI status check and receive data read: read
SSR, check that RDRF is set to 1, then read
receive data from RDR and clear the RDRF
flag to 0. Notification that the RDRF flag has
changed from 0 to 1 can also be given by the
RXI interrupt.
Start receiving
Read ORER, PER,
and FER flags in SSR
Yes
PER RER
ORER = 1?
3
No
Error handling
(continued on next page)
5. To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the stop bit of the current
frame is received.
Read RDRF flag in SSR
4
No
RDRF = 1?
Yes
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
No
Finished
receiving?
5
Yes
Clear RE bit to 0 in SCR
End
Figure 10-7 Sample Flowchart for Receiving Serial Data (1)
302
3
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit to 0 in SCR
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags to 0 in SSR
End
Figure 10-7 Sample Flowchart for Receiving Serial Data (2)
303
In receiving, the SCI operates as follows.
•
The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
•
•
Receive data is stored in RSR in order from LSB to MSB.
The parity bit and stop bit are received.
After receiving, the SCI makes the following checks:
— Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
— Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
bit is checked.
— Status check: The RDRF flag must be 0 so that receive data can be transferred from
RSR into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 10-11.
Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is
not set to 1. Be sure to clear the error flags.
•
When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 10-11 Receive Error Conditions
Receive Error
Abbreviation
Condition
Data Transfer
Overrun error
ORER
Receiving of next data ends
while RDRF flag is still set to
1 in SSR
Receive data not transferred
from RSR to RDR
Framing error
Parity error
FER
PER
Stop bit is 0
Receive data transferred
from RSR to RDR
Parity of receive data differs
from even/odd parity setting
in SMR
Receive data transferred
from RSR to RDR
304
Figure 10-8 shows an example of SCI receive operation in asynchronous mode.
Start
bit
Parity Stop Start
Parity Stop
bit bit
Data
Data
1
1
bit
bit
bit
1
0
D0
D1
D7
0/1
0
D0
D1
D7
0/1
1
Idle (mark)
state
RDRF
FER
RXI
request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI request
1 frame
Figure 10-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
10.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set
to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 10-9 shows an example of communication among different processors using a
multiprocessor format.
305
Communication Formats: Four formats are available. Parity-bit settings are ignored when a
multiprocessor format is selected. For details see table 10-8.
Clock: See the description of asynchronous mode.
Transmitting
processor
Serial communication line
Receiving
Receiving
Receiving
Receiving
processor A
processor B
processor C
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial data
H'01
H'AA
(MPB = 0)
(MPB = 1)
ID-sending cycle: receiving
processor address
Data-sending cycle:
data sent to receiving
processor specified by ID
Legend
MPB: Multiprocessor bit
Figure 10-9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
306
Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data: Figure 10-10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
Initialize
1
2
1. SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
2. SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
Start transmitting
Read TDRE flag in SSR
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
No
TDRE = 1?
Yes
3. To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be
written, write data in TDR, then clear
the TDRE flag to 0.
4. To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.
Write transmit data in
TDR and set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
3
Read TEND flag in SSR
No
No
TEND = 1?
Yes
Output break signal?
4
Yes
Clear DR bit to 0, set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 10-10 Sample Flowchart for Transmitting Multiprocessor Serial Data
307
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
— Start bit:
One 0 bit is output.
— Transmit data:
7 or 8 bits are output, LSB first.
— Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
— Stop bit:
One or two 1 bits (stop bits) are output.
— Mark state:
Output of 1 bits continues until the start bit of the next transmit data.
•
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 10-11 shows an example of SCI transmit operation using a multiprocessor format.
Multi-
processor
bit
Multi-
processor
bit
Start
bit
Stop Start
bit bit
Stop
bit
Data
Data
1
1
Serial
data
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle (mark)
state
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
request
TEI request
1 frame
Figure 10-11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
308
Receiving Multiprocessor Serial Data: Figure 10-12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
Initialize
1
2
1. SCI initialization: the receive data function
of the RxD pin is selected automatically.
2. ID receive cycle: set the MPIE bit to 1 in SCR.
3. SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor’s own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
Start receiving
Set MPIE bit to 1 in SCR
Read ORER and FER flags in SSR
4. SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
5. Receive error handling and break detection:
if a receive error occurs, read the
Yes
3
FER ORER = 1
No
Read RDRF flag in SSR
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
No
RDRF = 1?
Yes
Read receive data from RDR
No
Own ID?
Yes
Read ORER and FER flags in SSR
FER ORER = 1
Yes
No
Read RDRF flag in SSR
4
No
RDRF = 1?
Yes
Read receive data from RDR
No
No
5
Finished receiving?
Error handling
(continued on next page)
Yes
Clear RE bit to 0 in SCR
End
Figure 10-12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
309
5
Error handling
No
No
ORER = 1?
Yes
Overrun error handling
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit to 0 in SCR
Clear ORER, PER, and FER
flags to 0 in SSR
End
Figure 10-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
310
Figure 10-13 shows an example of SCI receive operation using a multiprocessor format.
Start
bit
Stop Start
Stop
bit
Data (ID1)
D0 D1
MPB
1
Data (data1)
D0 D1
MPB
0
1
1
bit
bit
0
D7
1
0
D7
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
RXI request
(multiprocessor
RXI handler reads
RDR data and clears MPIE bit is set
Not own ID, so
No RXI request,
RDR not updated
interrupt), MPIE = 0 RDRF flag to 0
to 1 again
a. Own ID does not match data
Start
bit
Stop Start
Stop
bit
Data (ID2)
D0 D1
MPB
1
Data (data2)
MPB
0
1
1
bit
bit
0
D7
1
0
D0
D1
D7
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
ID2
Data 2
RXI request
(multiprocessor
RXI interrupt handler Own ID, so receiving MPIE bit is set
reads RDR data and continues, with data to 1 again
interrupt), MPIE = 0 clears RDRF flag to 0 received by RXI
interrupt handler
b. Own ID matches data
Figure 10-13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
311
10.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 10-14 shows the general format in synchronous serial communication.
Transfer direction
One unit (character or frame) of serial data
*
*
Serial clock
Serial data
LSB
Bit 0
MSB
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Don’t care
Note: * High except in continuous transmitting or receiving
Don’t care
Figure 10-14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR. See table 10-9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. When the SCI is only receiving, it receives in
units of two characters, so it outputs 16 clock pulses. To receive in units of one character, an
external clock source must be selected.
312
Transmitting and Receiving Data
SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and
ORE flags and RDR, which retain their previous contents.
Figure 10-15 is a sample flowchart for initializing the SCI.
Start of initialization
1. Select the communication format in SMR.
2. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
3. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
Clear TE and RE
bits to 0 in SCR
MPIE, TE, and RE bits to 0.
4. Wait for at least the interval required to transmit or receive
one bit, then set the TE or RE bit to 1 in SCR. Also set
1
the RIE, TIE, TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI to use the
TxD or RxD pin.
Select communication
format in SMR
2
3
Set value in BRR
Set RIE, TIE, TEIE, MPIE,
CKE1, and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
Wait
No
1 bit interval
elapsed?
Yes
Set TE or RE to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
4
Start transmitting or receiving
Figure 10-15 Sample Flowchart for SCI Initialization
313
Transmitting Serial Data (Synchronous Mode): Figure 10-16 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
1. SCI initialization: the transmit data output function
Initialize
1
2
of the TxD pin is selected automatically.
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE flag
to 0.
Start transmitting
Read TDRE flag in SSR
No
TDRE = 1?
Yes
Write transmit data in
TDR and clear TDRE flag
to 0 in SSR
All data
transmitted?
No
3
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
Clear TE bit to 0 in SCR
End
Figure 10-16 Sample Flowchart for Serial Transmitting
314
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is output
from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
•
•
The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB,
holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end
interrupt (TEI) is requested at this time.
After the end of serial transmission, the SCK pin is held in a constant state.
315
Figure 10-17 shows an example of SCI transmit operation.
Transmit
direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6 Bit 7
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
TXI
request
TEI
request
1 frame
Figure 10-17 Example of SCI Transmit Operation
316
Receiving Serial Data: Figure 10-18 shows a sample flowchart for receiving serial data and
indicates the procedure to follow. When switching from asynchronous mode to synchronous
mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is
set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Initialize
1
2
1. SCI initialization: the receive data function of
the RxD pin is selected automatically.
2., 3. Receive error handling: if a receive error
occurs, read the ORER flag in SSR, then after
executing the necessary error handling, clear
the ORER flag to 0. Neither transmitting nor
receiving can resume while the ORER flag
remains set to 1.
Start receiving
Read ORER flag in SSR
4. SCI status check and receive data read: read
SSR, check that the RDRF flag is set to 1,
then read receive data from RDR and clear
the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be
given by the RXI interrupt.
Yes
ORER = 1?
No
3
Error handling
5. To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the MSB (bit 7) of the current
frame is received. If the DMAC is activated
by a receive-data-full interrupt request (RXI)
to read RDR, the RDRF flag is cleared
automatically.
Read RDRF flag in SSR
4
No
RDRF = 1?
Yes
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
5
No
Finished
receiving?
Yes
Clear RE bit to 0 in SCR
End
Figure 10-18 Sample Flowchart for Serial Receiving (1)
317
3
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
End
Figure 10-18 Sample Flowchart for Serial Receiving (2)
In receiving, the SCI operates as follows.
•
•
The SCI synchronizes with serial clock input or output and initializes internally.
Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the check does not pass (receive error), the SCI operates as indicated
in table 10-11.
•
After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a receive-
data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1,
the SCI requests a receive-error interrupt (ERI).
318
Figure 10-19 shows an example of SCI receive operation.
Receive direction
Serial clock
Serial data
RDRF
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
ORER
RXI
request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI
request
Overrun error,
ERI request
1 frame
Figure 10-19 Example of SCI Receive Operation
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 10-20
shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates
the procedure to follow.
319
1. SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
2. SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Initialize
1
2
Start transmitting and receiving
Read TDRE flag in SSR
No
TDRE = 1?
Yes
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
3. Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
Read ORER flag in SSR
ORER = 1?
4. SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
Yes
3
Error handling
No
5. To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that the
TDRE flag is (bit 7) of the current
frame is received. Also check that
the TDRE flag is set to 1, indicat-
ing that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
4
Read RDRF flag in SSR
No
RDRF = 1?
Yes
Read receive data from RDR
and clear RDRF flag to 0 in SSR
No
End of transmitting and
receiving?
5
Yes
Clear TE and RE bits to 0 in SCR
End
Note: * When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear the TE and RE bits both to 0,
then set the TE and RE bits both to 1.
Figure 10-20 Sample Flowchart for Serial Transmitting
320
10.4 SCI Interrupts
The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error
interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 10-12
lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled
by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent separately to the interrupt
controller.
The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is
requested when the TEND flag is set to 1 in SSR.
The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR.
Table 10-12 SCI Interrupt Sources
Interrupt Description
Priority
ERI
RXI
TXI
TEI
Receive error (ORER, FER, or PER)
High
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
Low
321
10.5 Usage Notes
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 10-13 indicates the state of SSR status flags when
multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are
not transferred to RDR, so receive data is lost.
Table 10-13 SSR Status Flags and Transfer of Receive Data
Receive Data
SSR Status Flags
Transfer
RDRF ORER FER
PER
RSR → RDR
Receive Errors
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
×
o
Overrun error
Framing error
o
Parity error
×
×
o
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error
×
Notes: o: Receive data is transferred from RSR to RDR.
Receive data is not transferred from RSR to RDR.
×
322
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the
level and direction (input or output) of which are determined by DR and DDR bits. This feature
can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an output port outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 10-21.
323
16 clocks
7
8 clocks
0
15 0
15 0
7
Internal
base clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
1
| D – 0.5 |
N
...................(1)
(1 + F) | × 100%
M = | (0.5 –
) – (L – 0.5) F –
2N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875%.................................................................................................(2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
324
Restrictions in Synchronous Mode: When an external clock source is used as the synchronous
clock, the serial clock must be input after at least five system clocks (5ø) have elapsed after TDR
has been updated. If the serial clock is input after only four system clocks have elapsed or less, an
error may occur (see figure 10-22).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: When using an external clock, t must be greater than four system clocks.
Figure 10-22 Example of Transmission Synchronous Mode
325
326
Section 11 A/D Converter
11.1 Overview
The H8/3001 includes a 10-bit successive-approximations A/D converter with a selection of up to
four analog input channels.
11.1.1 Features
A/D converter features are listed below.
•
•
•
10-bit resolution
Four input channels
High-speed conversion
Conversion time: maximum 8.4 µs per channel (with 16 MHz system clock)
Two conversion modes
•
•
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
•
•
Sample-and-hold function
A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
327
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the A/D converter.
On-chip
data bus
Module data bus
AVCC
10-bit D/A
AVSS
+
–
AN0
AN1
AN2
AN3
ø/8
Comparator
Analog
multi-
plexer
Control circuit
Sample-and-
hold circuit
ø/16
ADI
Legend
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 11-1 A/D Converter Block Diagram
328
11.1.3 Input Pins
Table 11-1 summarizes the A/D converter’s input pins. AV and AV are the power supply for
CC
SS
the analog circuits in the A/D converter.
Table 11-1 A/D Converter Pins
Abbrevi-
Pin Name
ation
AVCC
AVSS
AN0
I/O
Function
Analog power supply pin
Analog ground pin
Analog input pin 0
Analog input pin 1
Analog input pin 2
Analog input pin 3
Input Analog power supply
Input Analog ground and reference voltage
Input Analog inputs
AN1
Input
Input
Input
AN2
AN3
11.1.4 Register Configuration
Table 11-2 summarizes the A/D converter’s registers.
Table 11-2 A/D Converter Registers
Address*1
H'FFE0
H'FFE1
H'FFE2
H'FFE3
H'FFE4
H'FFE5
H'FFE6
H'FFE7
H'FFE8
H'FFE9
Name
Abbreviation
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCSR
R/W
R
Initial Value
H'00
A/D data register A (high)
A/D data register A (low)
A/D data register B (high)
A/D data register B (low)
A/D data register C (high)
A/D data register C (low)
A/D data register D (high)
A/D data register D (low)
A/D control/status register
A/D control register
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R/(W)*2 H'00
R/W H'7E
ADCR
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written in bit 7, to clear the flag.
329
11.2 Register Descriptions
11.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
15 14 13 12 11 10
9
8
7
6
5
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
ADDRn
Initial value
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
0
0
0
0
0
0
0
0
0
0
0
Read/Write
(n = A to D)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an
A/D data register are reserved bits that always read 0. Table 11-3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 11.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 11-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
A/D Data Register
ADDRA
AN0
AN1
AN2
AN3
ADDRB
ADDRC
ADDRD
330
11.2.2 A/D Control/Status Register (ADCSR)
Bit
7
ADF
0
6
ADIE
0
5
ADST
0
4
SCAN
0
3
2
1
0
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel select 2 to 0
These bits select analog
input channels
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
331
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing condition]
(Initial value)
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1
[Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE
Description
0
1
A/D end interrupt request (ADI) is disabled
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion.
Bit 5
ADST
Description
0
1
A/D conversion is stopped
(Initial value)
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion
ends.
Scan mode: A/D conversion starts and continues, cycling among the selected channels,
until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode.
332
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 11.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN
Description
Single mode
Scan mode
0
1
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS
Description
0
1
Conversion time = 266 states (maximum)
Conversion time = 134 states (maximum)
(Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
Channel Selection
Description
Scan Mode
CH2
CH1
CH0
0
Single Mode
AN0 (Initial value)
AN1
0
0
AN0
1
AN0, AN1
AN0 to AN2
AN0 to AN3
Illegal setting
1
0
AN2
1
AN3
1
—
—
Illegal setting
333
11.2.3 A/D Control Register (ADCR)
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
Reserved bits
Trigger enable
Enables or disables external triggering of A/D conversion
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7
TRGE
Description
0
1
A/D conversion cannot be externally triggered
Illegal setting
(Initial value)
Bits 6 to 0—Reserved: Read-only bits, always read as 1.
334
11.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 11-2 shows the data flow for access to an A/D data register.
Upper-byte read
Module data bus
CPU
Bus interface
(H'AA)
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower-byte read
Module data bus
CPU
(H'40)
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 11-2 A/D Data Register Access Operation (Reading H'AA40)
335
11.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
11.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software. The ADST bit remains set to 1 during
A/D conversion and is automatically cleared to 0 when conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN ) is selected in single mode are described next.
1
Figure 11-3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN is selected (CH2 = CH1 = 0,
1
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
336
Set*
Set*
ADIE
A/D conversion
starts
Set*
ADST
Clear*
Clear*
ADF
State of channel 0
Idle
Idle
Idle
Idle
(AN )
0
State of channel 1
Idle
A/D conversion 1
2
A/D conversion
Idle
(AN )
1
State of channel 2
(AN )
2
State of channel 3
(AN )
3
ADDRA
ADDRB
ADDRC
ADDRD
Read conversion result
Read conversion result
1
2
A/D conversion result
A/D conversion result
Note: *Vertical arrows ( ) indicate instructions executed by software.
11.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, A/D conversion starts on the first channel (AN ). When two or
0
more channels are selected, after conversion of the first channel ends, conversion of the second
channel (AN ) starts immediately. A/D conversion continues cyclically on the selected channels
1
until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D
data registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels (AN to AN ) are selected in scan mode are described
0
2
next. Figure 11-4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), analog input channels AN to AN are selected (CH2 = 0,
0
2
CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN ) is completed, the result is transferred into
0
ADDRA. Next, conversion of the second channel (AN ) starts automatically.
1
3. Conversion proceeds in the same way through the third channel (AN ).
2
4. When conversion of all selected channels (AN to AN ) is completed, the ADF flag is set to 1
0
2
and conversion of the first channel (AN ) starts again. If the ADIE bit is set to 1, an ADI
0
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN ).
0
338
Continuous A/D conversion
*1
*1
Set
Clear
ADST
Clear*1
ADF
A/D conversion time
State of channel 0
1
4
Idle
A/D conversion
Idle
A/D conversion
Idle
(AN )
0
State of channel 1
*2
5
2
Idle
A/D conversion
Idle
A/D conversion
Idle
Idle
(AN )
1
State of channel 2
3
A/D conversion
Idle
(AN )
2
State of channel 3
Idle
(AN )
3
Transfer
1
4
A/D conversion result
ADDRA
ADDRB
ADDRC
ADDRD
A/D conversion result
2
A/D conversion result
3
A/D conversion result
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
11.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t after the ADST bit is set to 1, then starts conversion. Figure 11-5 shows the A/D
D
conversion timing. Table 11-4 indicates the A/D conversion time.
As indicated in figure 11-5, the A/D conversion time includes t and the input sampling time. The
D
length of t varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 11-4.
In scan mode, the values given in table 11-4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
ø
(2)
Address bus
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
Legend
(1):
(2):
ADCSR write cycle
ADCSR address
tD
tSPL
:
Synchronization delay
Input sampling time
:
tCONV: A/D conversion time
Figure 11-5 A/D Conversion Timing
340
Table 11-4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Typ
—
Symbol
tD
Min
10
Typ
—
Max
17
Min
6
Max
9
Synchronization delay
Input sampling time
A/D conversion time
tSPL
—
80
—
—
—
40
—
tCONV
259
266
131
—
134
Note: Values in the table are numbers of states.
11.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
11.6 Usage Notes
When using the A/D converter, note the following points:
Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins
AN should be in the range AV ≤ AN ≤ AV . (n = 0 to 3)
n
SS
n
CC
AV and AV Input Voltages: AV should have the following value: AV = V .
SS
CC
SS
SS
SS
If the A/D converter is not used, set AV = V and AV = V .
SS
CC
CC
SS
341
342
Section 12 RAM
12.1 Overview
The H8/3001 has 512 bytes of on-chip static RAM. The RAM is connected to the CPU by a 16-bit
data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable
for rapid data transfer.
The on-chip RAM is assigned to addresses H'FFD10 to H'FFF0F in modes 1 and 2, and addresses
H'FFFD10 to H'FFFF0F in modes 3 and 4. The RAM enable bit (RAME) in the system control
register (SYSCR) can enable or disable the on-chip RAM.
12.1.1 Block Diagram
Figure 12-1 shows a block diagram of the on-chip RAM.
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
Bus interface
H'FD10*
H'FD11*
H'FD13*
H'FD12
On-chip RAM
H'FF0E*
H'FF0F*
Even addresses
Note: * Lower 16 bits of the address
Odd addresses
Figure 12-1 RAM Block Diagram
343
12.1.2 Register Configuration
The on-chip RAM is controlled by the system control register (SYSCR). Table 12-1 gives the
address and initial value of SYSCR.
Table 12-1 RAM Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * Lower 16 bits of the address
344
12.2 System Control Register (SYSCR)
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
UE
1
2
NMIEG
0
1
—
1
0
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable bit
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME Description
0
1
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
345
12.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFD10 to H'FFF0F in modes 1 and 2, and
to addresses H'FFFD10 to H'FFFF0F in modes 3 and 4, are directed to the on-chip RAM. When
the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
346
Section 13 Clock Pulse Generator
13.1 Overview
The H8/3001 has a built-in clock pulse generator (CPG) that generates the system clock (ø) and
other internal clock signals (ø/2 to ø/4096).
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, and the
prescalers.
13.1.1 Block Diagram
Figure 13-1 shows block diagrams of the clock pulse generator.
CPG
XTAL
Duty
adjustment
circuit
Oscillator
Prescalers
EXTAL
ø
ø/2 to ø/4096
Figure 13-1 Block Diagram of Clock Pulse Generator
347
13.2 Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
13.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 13-2.
The damping resistance Rd should be selected according to table 13-1. An AT-cut parallel-
resonance crystal should be used.
CL1
EXTAL
XTAL
CL1 = C L2 = 10 pF to 22 pF
CL2
Figure 13-2 Connection of Crystal Resonator (Example)
Table 13-1 Damping Resistance Value
Frequency (MHz)
2
4
8
10
0
12
0
14
0
Rd (Ω)
1 k
500
200
Crystal Resonator: Figure 13-3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 13-2.
CL
L
Rs
XTAL
EXTAL
AT-cut parallel-resonance type
CO
Figure 13-3 Crystal Resonator Equivalent Circuit
348
Table 13-2 Crystal Resonator Parameters
Frequency (MHz)
Rs max (Ω)
Co (pF)
2
4
8
10
12
16
500
120
80
70
60
50
7 pF max
Use a crystal resonator with a frequency equal to the system clock frequency (ø).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 13-4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
Avoid
CL2
Signal A
Signal B
H8/3001
XTAL
EXTAL
CL1
Figure 13-4 Example of Incorrect Board Design
349
13.2.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in
figure 13-5. In example b, the clock should be held high in standby mode.
If the XTAL pin is left open, the stray capacitance should be 10 pF.
EXTAL
XTAL
External clock input
Open
a. XTAL pin left open
EXTAL
XTAL
External clock input
74HC04
b. Complementary clock input at XTAL pin
Figure 13-5 External Clock Input (Examples)
350
External Clock
The external clock frequency should be equal to the system clock frequency (ø). Table 13-3 and
figure 13-6 indicate the clock timing.
Table 13-3 Clock Timing
VCC = 2.7 to 5.5 V
VCC = 5.0 V ± 10%
Item
Symbol Min
Max
Min
Max
Unit Test Conditions
External clock
rise time
tEXr
tEXf
—
—
10
—
5
ns
Figure 13-6
External clock
fall time
—
10
—
5
ns
External clock
input duty
30
40
70
60
30
40
70
60
%
%
ø ≥ 5 MHz Figure
13-6
ø < 5 MHz
cycle (a/tcyc
)
ø clock duty
—
40
60
40
60
%
cycle (b/tcyc
)
tcyc
a
EXTAL
VCC × 0.5
tEXr
tEXf
tcyc
b
ø
VCC × 0.5
Figure 13-6 External Clock Input Timing
351
13.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate a system clock (ø).
13.4 Prescalers
The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).
352
Section 14 Power-Down State
14.1 Overview
The H8/3001 has a power-down state that greatly reduces power consumption by halting CPU
functions. The power-down state includes the following three modes:
•
•
•
Sleep mode
Software standby mode
Hardware standby mode
Table 14-1 indicates the methods of entering and exiting these power-down modes and the status
of the CPU and on-chip supporting modules in each mode.
Table 14-1 Power-Down State
State
Entering
CPU
Supporting
I/O
Exiting
Mode
Conditions
Clock
CPU
Registers Functions
RAM
Ports
Conditions
Sleep
mode
SLEEP instruc-
tion executed
while SSBY = 0
in SYSCR
Active
Halted
Held
Held
Active
Held
Held
• Interrupt
• RES
• STBY
Software SLEEP instruc-
standby tion executed
mode
Halted
Halted
Halted
Halted
Halted
and
reset
Held
Held
• NMI
• IRQ0 and IRQ1
• RES
while SSBY = 1
in SYSCR
• STBY
Hardware Low input at
standby STBY pin
mode
Undeter-
mined
Halted
and
reset
Held*
High
impedance
• STBY
• RES
Notes: * The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware
standby mode.
Legend
SYSCR: System control register
SSBY: Software standby bit
353
14.2 Register Configuration
The H8/3001’s system control register (SYSCR) controls the power-down state. Table 14-2
summarizes this register.
Table 14-2 Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * Lower 16 bits of the address.
14.2.1 System Control Register (SYSCR)
Bit
7
SSBY
0
6
STS2
0
5
4
3
2
1
0
RAME
1
STS1
0
STS0
0
UE
1
NMIEG
0
—
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control
the power-down state. For information on the other SYSCR bits, see section 3.3, System Control
Register.
354
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
Description
0
1
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 8 ms. See table 14-3. If an external
clock is used, any setting is permitted.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
1
0
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Illegal setting
(Initial value)
1
0
1
1
0
1
—
—
355
14.3 Sleep Mode
14.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the
SLEEP instruction causes a transition from the program execution state to sleep mode.
Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal
registers are retained. On-chip supporting modules do not halt in sleep mode.
14.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt (except for an NMI interrupt) if it is masked by IPR and bits I and UI in CCR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
356
14.4 Software Standby Mode
14.4.1 Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset.
As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM
data are retained. The settings of the I/O ports are also held.
14.4.2 Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ , or IRQ
0
1
pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ , or IRQ , interrupt request signal is received, the clock
0
1
oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in
SYSCR, stable clock signals are supplied to the entire H8/3001 chip, software standby mode ends,
and interrupt exception handling begins. Software standby mode is not exited if the interrupt
enable bits of interrupts IRQ and IRQ are cleared to 0, or if these interrupts are masked by IPR
0
1
and bits I and UI in CCR.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire H8/3001 chip. The RES signal must be held low long enough
for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
357
14.4.3 Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR should be set as follows.
Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at
least 8 ms. Table 14-3 indicates the waiting times that are selected by STS2 to STS0 settings at
various system clock frequencies.
External Clock: Any value may be set.
Table 14-3 Clock Frequency and Waiting Time for Clock to Settle
Waiting
STS2 STS1 STS0 Time
16 MHZ 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit
0
0
0
0
1
1
0
0
1
1
0
1
0
8192
states
0.51
0.65
0.8
1.6
3.3
6.6
13.1
1.0
2.0
4.1
8.2
16.4
1.3
2.0
4.1
ms
1
16384
states
1.0
1.3
2.7
4.1
8.2
0
32768
states
2.0
2.7
5.5
8.2
16.4
32.8
65.5
1
65536
states
4.1
5.5
10.9
21.8
16.4
32.8
—
—
131072 8.2
states
10.9
Illegal setting
: Recommended setting
358
14.4.4 Sample Application of Software Standby Mode
Figure 14-1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal .
Clock
oscillator
ø
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby Oscillator
NMI exception
handling
mode (power-
down state)
settling time
(tosc2
)
SLEEP
instruction
Figure 14-1 NMI Timing for Software Standby Mode (Example)
14.4.5 Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
359
14.5 Hardware Standby Mode
14.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As
long as the specified voltage is supplied, on-chip RAM data is retained*. I/O ports are placed in
the high-impedance state.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby
mode.
Note: * Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
14.5.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
14.5.3 Timing for Hardware Standby Mode
Figure 14-2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
Clock
oscillator
RES
STBY
Oscillator
settling time
Reset
exception
handling
Figure 14-2 Hardware Standby Mode Timing
360
Section 15 Electrical Characteristics
15.1 Absolute Maximum Ratings
Table 15-1 lists the absolute maximum ratings.
Table 15-1 Absolute Maximum Ratings
Item
Symbol
VCC
Value
Unit
V
Power supply voltage
Input voltage (except port 7)
Input voltage (port 7)
Analog power supply voltage
Analog input voltage
Operating temperature
–0.3 to +7.0
VIN
–0.3 to VCC +0.3
V
VIN
–0.3 to AVCC +0.3
–0.3 to +7.0
V
AVCC
VAN
V
–0.3 to AVCC +0.3
Regular specifications: –20 to +75
Wide-range specifications: –40 to +85
–55 to +125
V
Topr
°C
°C
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
361
15.2 Electrical Characteristics
15.2.1 DC Characteristics
Table 15-2 lists the DC characteristics. Table 15-3 lists the permissible output currents.
Table 15-2 DC Characteristics
Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V*,
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
—
Max
Unit Test Conditions
–
Schmitt
trigger input
voltages
Ports 8, A, B VT
1.0
—
—
V
+
VT
—
VCC × 0.7 V
–
VT+ – VT 0.4
—
—
V
Input high
voltage
RES, STBY, VIH
NMI, MD2 to
MD0
VCC – 0.7 —
VCC + 0.3 V
EXTAL
V
CC × 0.7 —
VCC + 0.3 V
AVCC + 0.3 V
VCC + 0.3 V
Port 7
2.0
2.0
—
—
Ports 4, 6, 9,
D
15 to D8
Input low
voltage
RES, STBY, VIL
–0.3
–0.3
—
—
0.5
0.8
V
V
MD2 to MD0
NMI, EXTAL,
ports 4, 6, 7, 9,
D
15 to D8
Output high
voltage
All output pins VOH
VCC – 0.5 —
—
V
V
V
V
IOH = –200 µA
IOH = –1 mA
IOL = 1.6 mA
IOL = 10 mA
3.5
—
—
—
—
—
Output low
voltage
All output pins VOL
Port B,
0.4
—
1.0
A
19 to A0
Note: * If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
362
Table 15-2 DC Characteristics (cont)
*1
Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V ,
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
|IIN|
—
—
1.0
µA
VIN = 0.5 to
CC – 0.5 V
current
RES,
V
MD2 to MD0
Port 7
—
—
—
—
1.0
1.0
µA
µA
VIN = 0.5 to
AVCC – 0.5 V
Three-state Ports 4, 6, 8, |ITS1
|
VIN = 0.5 to
VCC – 0.5 V
leakage
current
9, A, B, A19 to
A0, D15 to D8
(off state)
Input pull-up Port 4
current
–IP
50
—
300
µA
pF
VIN = 0 V
Input
NMI
CIN
—
—
—
—
50
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
capacitance
All input pins
except NMI
Current
Normal
ICC
—
45
60
mA f = 16 MHz
dissipation*2 operation
Sleep mode
—
—
—
—
32
45
mA f = 16 MHz
Standby
mode*3
0.01
—
5.0
20.0
2.6
µA
µA
mA
Ta ≤ 50°C
50°C < Ta
Analog power During A/D
supply current conversion
AICC
1.5
Idle
—
0.02
—
10.0
—
µA
V
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
363
Table 15-2 DC Characteristics (cont)
Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V*,
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
—
Max
Unit Test Conditions
–
Schmitt
trigger input
voltages
Ports 8, A, B VT
VCC × 0.2
—
V
V
V
V
+
VT
VT+ – VT
RES, STBY, VIH
—
—
VCC × 0.7
–
VCC × 0.07 —
—
Input high
voltage
VCC × 0.9
—
VCC + 0.3
NMI, MD2 to
MD0
EXTAL
VCC × 0.7
VCC × 0.7
VCC × 0.7
—
—
—
VCC + 0.3
V
Port 7
AVCC + 0.3 V
VCC + 0.3
Ports 4, 6, 9,
V
D15 to D8
Input low
voltage
RES, STBY, VIL
–0.3
–0.3
—
V
V
CC × 0.1 V
CC × 0.2 V
MD2 to MD0
NMI, EXTAL,
—
VCC < 4.0 V
VCC
ports 4, 6, 7, 9,
0.8
V
=
D15 to D8
4.0 to 5.5 V
Output high All output pins VOH
voltage
VCC – 0.5 —
VCC – 1.0 —
—
V
V
V
V
IOH = –200 µA
IOH = –1 mA
IOL = 1.6 mA
—
Output low
voltage
All output pins VOL
Port B,
—
—
—
—
0.4
1.0
V
CC ≤ 4 V
A19 to A0
IOL = 5 mA,
4 V < VCC ≤ 5.5 V
I
OL = 10 mA
Note: * If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
364
Table 15-2 DC Characteristics (cont)
Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V ,
*1
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
|IIN|
—
—
1.0
µA
VIN = 0.5 to
CC – 0.5 V
current
RES,
V
MD2 to MD0
Port 7
—
—
—
—
1.0
1.0
µA
µA
VIN = 0.5 to
AVCC – 0.5 V
Three-state Ports 4, 5, 6, |ITS1
|
VIN = 0.5 to
leakage
current
(off state)
8, 9, A, B,
19 to A0,
D15 to D8
VCC – 0.5 V
A
Input pull-up Port 4
current
–IP
10
—
300
µA
pF
VCC = 2.7 V to
5.5 V,
V
IN = 0 V
Input
NMI
CIN
—
—
—
—
50
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
capacitance
All input pins
except NMI
*4
Current
Normal
ICC
—
—
12
33.8
mA f = 8 MHz
mA f = 8 MHz
dissipation*2 operation
(3.0 V) (5.5 V)
25.0
(3.0 V) (5.5 V)
Sleep mode
8
Standby
mode*3
—
—
—
—
—
2.0
0.01
—
5.0
20.0
2.4
—
µA
µA
Ta ≤ 50°C
50°C < Ta
Analog
power
supply
current
During A/D
conversion
AICC
1.2
1.5
0.02
—
mA AVCC = 3.0 V
mA AVCC = 5.0 V
Idle
10.0
—
µA
V
RAM standby voltage
VRAM
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
I
I
CCmax = 3.0 (mA) + 0.7 (mA/MHz ·V) × VCC × f [normal mode]
CCmax = 3.0 (mA) + 0.5 (mA/MHz ·V) × VCC × f [sleep mode]
365
Table 15-2 DC Characteristics (cont)
Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V*,
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
—
Max
Unit Test Conditions
–
Schmitt
trigger input
voltages
Ports 8, A, B VT
VCC × 0.2
—
V
V
V
V
+
VT
VT+ – VT
RES, STBY, VIH
—
—
VCC × 0.7
–
VCC × 0.07 —
—
Input high
voltage
VCC × 0.9
—
VCC + 0.3
NMI, MD2 to
MD0
EXTAL
VCC × 0.7
VCC × 0.7
VCC × 0.7
—
—
—
VCC + 0.3
V
Port 7
AVCC + 0.3 V
Ports 4, 6, 9,
VCC + 0.3
V
D15 to D8
Input low
voltage
RES, STBY, VIL
–0.3
–0.3
—
—
V
CC × 0.1
CC × 0.2
V
MD2 to MD0
NMI, EXTAL,
ports 4, 6, 7, 9,
V
V
V
VCC < 4.0 V
VCC
0.8
=
D
15 to D8
4.0 to 5.5 V
Output high All output pins VOH
voltage
VCC – 0.5
VCC – 1.0
—
—
—
—
—
—
V
V
V
V
IOH = –200 µA
IOH = –1 mA
IOL = 1.6 mA
—
Output low
voltage
All output pins VOL
Port B,
0.4
1.0
—
VCC ≤ 4 V
A19 to A0
IOL = 5 mA
4 V < VCC ≤ 5.5
I
OL = 10 mA
Note: * If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
366
Table 15-2 DC Characteristics (cont)
Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V ,
*1
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
|IIN|
—
—
1.0
µA
VIN = 0.5 to
CC – 0.5 V
current
RES,
V
MD2 to MD0
Port 7
—
—
—
—
1.0
1.0
µA
µA
VIN = 0.5 to
AVCC – 0.5 V
Three-state Ports 4, 6,
|ITS1
|
VIN = 0.5 to
leakage
current
(off state)
8 to B,
19 to A0,
D15 to D8
VCC – 0.5 V
A
Input pull-up Port 4
current
–IP
10
—
300
µA
pF
VCC = 3.0 V to
5.5 V,
V
IN = 0 V
Input
NMI
CIN
—
—
—
—
50
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
capacitance
All input pins
except NMI
*4
Current
Normal
ICC
—
—
15
41.5
mA f = 10 MHz
mA f = 10 MHz
dissipation*2 operation
(3.0 V) (5.5 V)
10 30.5
(3.0 V) (5.5 V)
Sleep mode
Standby
mode*3
—
—
—
—
—
2.0
0.01
—
5.0
20.0
2.4
—
µA
µA
Ta ≤ 50°C
50°C < Ta
Analog
power
supply
current
During A/D
conversion
AICC
1.2
1.5
0.02
—
mA AVCC = 3.0 V
mA AVCC = 5.0 V
Idle
10.0
—
µA
V
RAM standby voltage
VRAM
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS
.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
I
I
CCmax = 3.0 (mA) + 0.7 (mA/MHz ·V) × VCC × f [normal mode]
CCmax = 3.0 (mA) + 0.5 (mA/MHz ·V) × VCC × f [sleep mode]
367
Table 15-3 Permissible Output Currents
Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Item
Symbol Min
Typ
—
Max Unit
Permissible output
low current (per pin)
Ports 5 and B, A19 to A0
Other output pins
IOL
—
—
—
10
2.0
80
mA
mA
mA
—
Permissible output
low current (total)
Total of 24 pins including
port B and A19 to A0
ΣIOL
—
Total of all output pins,
including the above
—
—
—
—
—
—
120
2.0
40
mA
mA
mA
Permissible output
high current (per pin)
All output pins
IOH
Permissible output
high current (total)
Total of all output pins
ΣIOH
Notes: 1. To protect chip reliability, do not exceed the output current values in table 15-3.
2. When driving a darlington pair or LED, always insert a current-limiting resistor in the
output line, as shown in figures 15-1 and 15-2.
368
H8/3001
Port
2 kΩ
Darlington pair
Figure 15-1 Darlington Pair Drive Circuit (Example)
H8/3001
Ports 5 and B
600Ω
LED
Figure 15-2 LED Drive Circuit (Example)
369
15.2.2 AC Characteristics
Bus timing parameters are listed in table 15-4. Control signal timing parameters are listed in
table 15-5. Refresh controller bus timing parameters are listed in table 15-6. Timing parameters of
the on-chip supporting modules are listed in table 15-7.
Table 15-4 Bus Timing (1)
Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A
8 MHz
Condition B
10 MHz
Condition C
16 MHz
Test
Item
Symbol Min
Max
500
—
Min
Max
500
—
Min
Max
500
—
Unit Conditions
Clock cycle time
Clock low pulse width
tCYC
tCL
125
40
40
—
100
30
30
—
62.5
20
20
—
ns
Figure 15-4,
Figure 15-5
Clock high pulse width tCH
—
—
—
Clock rise time
tCR
tCF
20
15
10
Clock fall time
—
20
—
15
—
10
Address delay time
Address hold time
tAD
tAH
tASD
—
60
—
50
—
30
25
—
—
20
—
—
10
—
—
Address strobe delay
time
60
40
30
Write strobe delay time tWSD
Strobe delay time tSD
—
—
85
60
60
—
—
—
60
50
50
—
—
—
35
30
30
—
Write data strobe pulse tWSW1
width 1
*
*
Write data strobe pulse tWSW2
width 2
150
—
110
—
65
—
Address setup time 1
Address setup time 2
Read data setup time
Read data hold time
tAS1
tAS2
tRDS
tRDH
20
80
50
0
—
—
—
—
15
65
35
0
—
—
—
—
10
40
20
0
—
—
—
—
370
Table 15-4 Bus Timing (cont)
Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A
8 MHz
Condition B
10 MHz
Condition C
16 MHz
Test
Item
Symbol Min
Max
75
Min
Max
75
Min
Max
60
—
Unit Conditions
Write data delay time
tWDD
—
60
5
—
—
15
–5
20
—
ns
Figure 15-4,
Figure 15-5
Write data setup time 1 tWDS1
Write data setup time 2 tWDS2
—
40
–10
20
—
—
—
—
—
Write data hold time
tWDH
25
—
—
—
—
Read data access
time 1
tACC1
110
100
55
*
*
*
*
Read data access
time 2
tACC2
tACC3
tACC4
tPCH
—
—
—
230
55
—
—
—
200
50
—
—
—
115
25
Read data access
time 3
Read data access
time 4
160
150
85
Precharge time
Wait setup time
Wait hold time
85
40
10
40
—
—
—
—
—
60
60
40
10
40
—
—
—
—
—
50
40
25
5
—
—
—
—
30
*
tWTS
ns
ns
Figure 15-6
Figure 15-9
tWTH
Bus request setup ime tBRQS
40
—
Bus acknowledge
delay time 1
tBACD1
tBACD2
tBZD
Bus acknowledge
delay time 2
—
—
60
70
—
—
50
70
—
—
30
40
Bus-floating time
Note is on next page.
371
Note: In condition A, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tcyc – 78 (ns)
tACC2 = 2.5 × tcyc – 83 (ns)
tACC3 = 1.0 × tcyc – 70 (ns)
tACC4 = 2.0 × tcyc – 90 (ns)
tWSW1 = 1.0 × tcyc – 40 (ns)
tWSW2 = 1.5 × tcyc – 38 (ns)
tPCH = 1.0 × tcyc – 40 (ns)
In condition C, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tcyc – 39 (ns)
tACC2 = 2.5 × tcyc – 41 (ns)
tACC3 = 1.0 × tcyc – 38 (ns)
tACC4 = 2.0 × tcyc – 40 (ns)
tWSW1 = 1.0 × tcyc – 28 (ns)
tWSW2 = 1.5 × tcyc – 28 (ns)
tPCH = 1.0 × tcyc – 23 (ns)
372
Table 15-5 Control Signal Timing
Condition A: V = 2.7 V to 5.5 V, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A
8 MHz
Condition B
10 MHz
Condition C
16 MHz
Test
Item
Symbol Min
Max
—
Min
Max
—
Min
Max
—
Unit Conditions
RES setup time
RES pulse width
tRESS
tRESW
tNMIS
200
10
200
10
200
10
ns
Figure 15-7
Figure 15-8
—
—
—
tCYC
ns
NMI setup time
200
—
200
—
150
—
(NMI, IRQ4, IRQ1, IRQ0)
NMI hold time
(NMI, IRQ1, IRQ0)
tNMIH
tNMIW
10
—
—
10
—
—
10
—
—
Interrupt pulse width
(NMI, IRQ2 to IRQ0
when exiting software
standby mode)
200
200
200
Clock oscillator settling tOSC1
time at reset (crystal)
20
8
—
—
20
8
—
—
20
8
—
—
ms
ms
Figure 15-10
Figure 14-1
Clock oscillator settling tOSC2
time in software standby
(crystal)
373
Table 15-6 Timing of On-Chip Supporting Modules
Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A
8 MHz
Condition B
10 MHz
Condition C
16 MHz
Test
Conditions
Item
Symbol Min
Max
Min
Max
Min
Max
Unit
ITU
Timer output
delay time
tTOCD
—
50
50
100
—
50
50
1.5
2.5
4
100
—
50
50
1.5
2.5
4
100
ns
Figure 15-12
Timer input
setup time
tTICS
—
—
—
Timer clock
input setup time
tTCKS
—
—
—
Figure 15-13
Timer Single
clock edge
tTCKWH 1.5
tTCKWL 2.5
—
—
—
tCYC
pulse
width
Both
edges
—
—
—
SCI
Input Asyn-
tSCYC
4
—
—
—
Figure 15-14
clock chronous
cycle
Syn-
tSCYC
6
—
6
—
6
—
chronous
Input clock rise tSCKr
time
—
—
0.4
1.5
1.5
0.6
—
—
0.4
1.5
1.5
0.6
—
—
0.4
1.5
1.5
0.6
Input clock fall tSCKf
time
Input clock
pulse width
tSCKW
tSCYC
374
Table 15-7 Timing of On-Chip Supporting Modules (cont)
Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A Condition B Condition C
8 MHz 10 MHz 16 MHz
Symbol Min Max Min Max
Test
Item
Min
Max
Unit Conditions
SCI
Transmit data delay
time
tTXD
—
100
—
100
—
100
ns
Figure 15-15
Receive data setup
time (synchronous)
tRXS
100
100
0
—
100
100
0
—
100
100
0
—
Receive data Clock tRXH
—
—
—
hold time
input
(synchronous)
Clock tRXH
output
—
—
—
Ports Output data delay
tPWD
tPRS
tPRH
—
100
—
—
100
—
—
100
—
ns
Figure 15-11
and
time
TPC
Input data setup
50
50
50
50
50
50
time (synchronous)
Input data hold
—
—
—
time (synchronous)
5 V
C = 90 pF: ports 4, 6, 8, A19 to A ,
0
D
15 to D8, ø, AS, RD,
RL
HWR, LWR
H8/3001
output pin
C = 30 pF: ports 9, A, B
RL = 2.4 kΩ
RH = 12 kΩ
C
RH
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 15-3 Output Load Circuit
375
15.2.3 A/D Conversion Characteristics
Table 15-8 lists the A/D conversion characteristics.
Table 15-8 A/D Converter Characteristics
Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 10 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition C: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = AV = 0 V,
CC
CC
SS
SS
ø = 2 MHz to 16 MHz, T = –20°C to +75°C (regular specifications),
a
T = –40°C to +85°C (wide-range specifications)
a
Condition A
8 MHz
Condition B
10 MHz
Condition C
16 MHz
Item
Min
10
—
Typ
10
—
Max
Min
10
—
Typ
10
—
Max
Min
10
—
Typ
10
—
Max
Unit
bits
µs
Resolution
Conversion time
10
10
10
8.4
20
16.8
20
13.4
20
Analog input
capacitance
—
—
—
—
—
—
pF
Permissible signal-
source impedance
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10*1
5*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10*1
5*3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10*4
5*5
kΩ
Nonlinearity error
Offset error
±6.0
±4.0
±4.0
±0.5
±8.0
±6.0
±4.0
±4.0
±0.5
±8.0
±3.0
±2.0
±2.0
±0.5
±4.0
LSB
LSB
LSB
LSB
LSB
Full-scale error
Quantization error
Absolute accuracy
Notes: 1. The value is for 4.0 ≤ AVCC ≤ 5.5.
2. The value is for 2.7 ≤ AVCC < 4.0.
3. The value is for 3.0 ≤ AVCC < 4.0.
4. The value is for ø ≤ 12 MHz.
5. The value is for ø > 12 MHz.
376
15.3 Operational Timing
This section shows timing diagrams.
15.3.1 Bus Timing
Bus timing is shown as follows:
•
•
•
Basic bus cycle: two-state access
Figure 15-4 shows the timing of the external two-state access cycle.
Basic bus cycle: three-state access
Figure 15-5 shows the timing of the external three-state access cycle.
Basic bus cycle: three-state access with one wait state
Figure 15-6 shows the timing of the external three-state access cycle with one wait state
inserted.
377
T1
T2
tcyc
tCH
tCL
ø
tCF
tCR
tAD
A23 to A0
tPCH
tASD
tACC3
tSD
tAH
AS
tAS1
tPCH
tASD
tACC3
tSD
tAH
RD
(read)
tAS1
tACC1
tRDS
tRDH
D15 to D0
(read)
tPCH
tASD
tSD
tAH
HWR, LWR
(write)
tAS1
tWSW1
tWDS1
tWDH
tWDD
D15 to D0
(write)
Figure 15-4 Basic Bus Cycle: Two-State Access
378
T1
T2
T3
ø
A23 to A0
AS
tACC4
tACC4
RD (read)
tRDS
tACC2
D15 to D0
(read)
tWSD
tWSW2
HWR, LWR
(write)
tAS2
tWDS2
D15 to D0
(write)
Figure 15-5 Basic Bus Cycle: Three-State Access
379
T1
T2
TW
T3
ø
A23 to A0
AS
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tWTS
tWTS tWTH
tWTH
WAIT
Figure 15-6 Basic Bus Cycle: Three-State Access with One Wait State
380
15.3.2 Control Signal Timing
Control signal timing is shown as follows:
•
•
•
Reset input timing
Figure 15-7 shows the reset input timing.
Interrupt input timing
Figure 15-8 shows the input timing for NMI and IRQ , IRQ , and IRQ .
4
1
0
Bus-release mode timing
Figure 15-9 shows the bus-release mode timing.
ø
tRESS
tRESS
RES
tRESW
Figure 15-7 Reset Input Timing
381
ø
tNMIS tNMIH
tNMIS tNMIH
tNMIS
NMI
IRQE
IRQL
IRQE: Edge-sensitive IRQ I
IRQL : Level-sensitive IRQ I (I = 0, 1, 4)
tNMIW
NMI
IRQ J
(J = 0 to 2)
Figure 15-8 Interrupt Input Timing
ø
tBRQS
tBRQS
BREQ
BACK
tBACD2
tBACD1
tBZD
tBZD
A23 to A0,
AS, RD,
HWR, LWR
Figure 15-9 Bus-Release Mode Timing
382
15.3.3 Clock Timing
Clock timing is shown as follows:
•
Oscillator settling timing
Figure 15-10 shows the oscillator settling timing.
ø
VCC
STBY
RES
tOSC1
tOSC1
Figure 15-10 Oscillator Settling Timing
15.3.4 TPC and I/O Port Timing
TPC and I/O port timing is shown as follows.
T1
T2
T3
ø
tPRS
tPRH
Port 4,
6 to 9, A, B
(read)
tPWD
Port 4, 6,
8, 9, A, B
(write)
Figure 15-11 TPC and I/O Port Input/Output Timing
383
15.3.5 ITU Timing
ITU timing is shown as follows:
•
ITU input/output timing
Figure 15-12 shows the ITU input/output timing.
ITU external clock input timing
•
Figure 15-13 shows the ITU external clock input timing.
ø
tTOCD
Output
compare*1
tTICS
Input
capture*2
Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4
2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4
Figure 15-12 ITU Input/Output Timing
tTCKS
ø
tTCKS
TCLKA to
TCLKD
tTCKWL
tTCKWH
Figure 15-13 ITU Clock Input Timing
384
15.3.6 SCI Input/Output Timing
SCI timing is shown as follows:
•
SCI input clock timing
Figure 15-14 shows the SCI input clock timing.
SCI input/output timing (synchronous mode)
Figure 15-15 shows the SCI input/output timing in synchronous mode.
•
tSCKW
tSCKr
tSCKf
SCK
tScyc
Figure 15-14 SCK Input Clock Timing
tScyc
SCK
tTXD
TxD
(transmit
data)
tRXS tRXH
RxD
(receive
data)
Figure 15-15 SCI Input/Output Timing in Synchronous Mode
385
386
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol
Rd
Description
General destination register
General source register
General register
Rs
Rn
ERd
ERs
ERn
(EAd)
(EAs)
PC
General destination register (address register or 32-bit register)
General source register (address register or 32-bit register)
General register (32-bit register)
Destination operand
Source operand
Program counter
SP
Stack pointer
CCR
N
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
Z
V
V (overflow) flag in CCR
C (carry) flag in CCR
C
disp
→
Displacement
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
–
×
÷
Addition of the operands on both sides
Subtraction of the operand on the right from the operand on the left
Multiplication of the operands on both sides
Division of the operand on the left by the operand on the right
Logical AND of the operands on both sides
Logical OR of the operands on both sides
Exclusive logical OR of the operands on both sides
NOT (logical complement)
¬
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
387
Condition Code Notation
Symbol
Description
↕
*
Changed according to execution result
Undetermined (no guaranteed value)
Cleared to 0
0
1
Set to 1
—
∆
Not affected by execution of the instruction
Varies depending on conditions, described in notes
388
Table A-1 Instruction Set
1. Data transfer instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
0
0
0
0
C
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
B
B
B
B
#xx:8 → Rd8
Rs8 → Rd8
2
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
—
—
—
—
2
2
4
6
2
2
4
@ERs → Rd8
@(d:16, ERs) → Rd8
MOV.B @(d:16, ERs),
Rd
MOV.B @(d:24, ERs),
Rd
B
B
@(d:24, ERs) → Rd8
8
—
—
—
—
↕
↕
↕
↕
0
0
—
—
10
6
MOV.B @ERs+, Rd
@ERs → RD8
2
ERs32+1 → ERs32
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
B
B
B
B
B
@aa:8 → Rd8
2
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
—
—
—
—
—
4
6
8
4
6
@aa:16 → Rd8
@aa:24 → Rd8
Rs8 → @ERd
4
6
2
MOV.B Rs, @(d:16,
ERd)
Rs8 → @(d:16, ERd)
4
MOV.B Rs, @(d:24,
ERd)
B
B
Rs8 → @(d:24, ERd)
8
—
—
—
—
↕
↕
↕
↕
0
0
—
—
10
6
MOV.B Rs, @ERd
ERd32–1 → ERd32
Rs8 → @ERd
2
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
B
B
Rs8 → @aa:8
2
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
0
—
—
—
—
—
—
—
4
6
8
4
2
4
6
Rs8 → @aa:16
Rs8 → @aa:24
#xx:16 → Rd16
Rs16 → Rd16
B
W
W
W
W
4
2
2
4
MOV.W @ERs, Rd
@ERs → Rd16
@(d:16, ERs) → Rd16
MOV.W @(d:16, ERs),
Rd
MOV.W @(d:24, ERs),
Rd
W
W
W
@(d:24, ERs) → Rd16
8
2
4
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
0
0
0
—
—
—
10
6
MOV.W @ERs+, Rd
@ERs → Rd16
ERs32+2 → @ERd
MOV.W @aa:16, Rd
@aa:16 → Rd16
6
389
Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
0
0
0
C
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
W
W
W
@aa:24 → Rd16
Rs16 → @ERd
Rs16 → @(d:16, ERd)
6
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
—
—
—
8
4
6
2
MOV.W Rs, @(d:16,
ERd)
4
MOV.W Rs, @(d:24,
ERd)
W
W
Rs16 → @(d:24, ERd)
8
—
—
—
—
↕
↕
↕
↕
0
0
—
—
10
6
MOV.W Rs, @–ERd
ERd32–2 → ERd32
Rs16 → @ERd
2
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, Rd
MOV.L ERs, ERd
W
W
L
Rs16 → @aa:16
Rs16 → @aa:24
#xx:32 → Rd32
4
6
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
—
—
—
—
—
—
6
8
6
10
2
L
ERs32 → ERd32
@ERs → ERd32
@(d:16, ERs) → ERd32
2
4
6
MOV.L @ERs, ERd
L
8
MOV.L @(d:16, ERs),
ERd
L
10
MOV.L @(d:24, ERs),
ERd
L
L
@(d:24, ERs) → ERd32
10
—
—
—
—
↕
↕
↕
↕
0
0
—
—
14
10
MOV.L @ERs+, ERd
@ERs → ERd32
4
ERs32+4 → ERs32
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
L
L
L
L
@aa:16 → ERd32
@aa:24 → ERd32
ERs32 → @ERd
6
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
—
—
—
—
10
12
8
8
4
MOV.L ERs, @(d:16,
ERd)
ERs32 → @(d:16, ERd)
6
10
MOV.L ERs, @(d:24,
ERd)
L
L
ERs32 → @(d:24, ERd)
10
—
—
—
—
↕
↕
↕
↕
0
0
—
—
14
10
MOV.L ERs, @–ERd
ERd32–4 → ERd32
ERs32 → @ERd
4
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
L
L
ERs32 → @aa:16
ERs32 → @aa:24
6
8
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
0
0
0
—
—
—
10
12
6
W
@SP → Rn16
SP+2 → SP
2
4
POP.L ERn
L
@SP → ERn32
SP+4 → SP
—
—
↕
↕
0
—
10
390
Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
PUSH.W Rn
W
L
SP–2 → SP
2
4
—
—
↕
↕
0
—
6
Rn16 → @SP
PUSH.L ERn
SP–4 → SP
—
—
↕
↕
0
—
10
ERn32 → @SP
MOVFPE @aa:16,
Rd
B
B
Cannot be used in the
H8/3001
4
4
Cannot be used in the H8/3001
Cannot be used in the H8/3001
MOVTPE Rs,
@aa:16
Cannot be used in the
H8/3001
2. Arithmetic instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
↕
↕
1
N
Z
V
C
ADD.B #xx:8, Rd
ADD.B Rs, Rd
B
B
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
2
4
6
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
2
2
4
2
6
2
2
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
W
W
L
Rd16+#xx:16 → Rd16
Rd16+Rs16 → Rd16
1
ERd32+#xx:32 →
2
ERd32
ADD.L ERs, ERd
L
ERd32+ERs32 →
2
—
2
↕
↕
↕
↕
2
ERd32
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.L #1, ERd
ADDS.L #2, ERd
ADDS.L #4, ERd
INC.B Rd
B
B
L
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
ERd32+1 → ERd32
ERd32+2 → ERd32
ERd32+4 → ERd32
Rd8+1 → Rd8
2
—
—
—
—
—
—
—
—
↕
↕
↕
↕
3
↕
↕
↕
↕
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
—
—
—
—
—
—
—
—
—
↕
—
—
—
↕
↕
↕
—
—
—
—
—
—
L
L
B
W
W
↕ —
↕ —
↕ —
INC.W #1, Rd
Rd16+1 → Rd16
↕
INC.W #2, Rd
Rd16+2 → Rd16
↕
391
TIable A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
Operation
I
H
—
—
*
N
Z
V
C
L
L
ERd32+1 → ERd32
ERd32+2 → ERd32
2
2
2
—
—
—
↕
↕
↕
↕
↕
↕
↕ —
↕ —
2
2
2
B
Rd8 decimal adjust
*
—
→ Rd8
SUB.B Rs, Rd
B
W
W
L
Rd8–Rs8 → Rd8
2
2
—
—
—
—
↕
1
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
2
4
2
6
SUB.W #xx:16, Rd
SUB.W Rs, Rd
Rd16–#xx:16 → Rd16
Rd16–Rs16 → Rd16
4
6
1
SUB.L #xx:32, ERd
ERd32–#xx:32
2
→ ERd32
SUB.L ERs, ERd
L
ERd32–ERs32
2
—
2
↕
↕
↕
↕
2
→ ERd32
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
B
B
L
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
ERd32–1 → ERd32
ERd32–2 → ERd32
ERd32–4 → ERd32
Rd8–1 → Rd8
2
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
—
—
—
↕
↕
↕
↕
↕
↕
3
↕
↕
↕
↕
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
—
—
—
—
—
—
—
—
*
—
—
—
↕
↕
↕
↕
↕
↕
—
—
—
—
—
—
L
L
B
W
W
L
↕ —
↕ —
↕ —
↕ —
↕ —
DEC.W #1, Rd
DEC.W #2, Rd
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
Rd16–1 → Rd16
Rd16–2 → Rd16
ERd32–1 → ERd32
ERd32–2 → ERd32
L
B
Rd8 decimal adjust
*
—
—
—
—
—
—
→ Rd8
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
B
W
B
Rd8 × Rs8 → Rd16
2
2
4
4
2
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
6
—
—
—
—
14
22
16
24
14
(unsigned multiplication)
Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
↕ —
↕ —
(signed multiplication)
W
B
Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
7 —
(unsigned division
)
392
Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
DIVXU. W Rs, ERd
W
B
ERd32 ÷ Rs16 →ERd32
(Ed: remainder,
2
4
4
—
—
6
7
—
—
22
16
24
Rd: quotient)
(unsigned division)
DIVXS. B Rs, Rd
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
—
—
—
—
8
8
7
7
—
—
—
—
(signed division)
DIVXS. W Rs, ERd
W
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
B
B
Rd8–#xx:8
2
4
6
—
—
—
—
—
—
—
—
—
—
↕
↕
1
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
↕
↕
↕
↕
↕
↕
↕
↕
↕
—
2
2
4
2
6
2
2
2
2
2
Rd8–Rs8
2
2
W
W
L
Rd16–#xx:16
Rd16–Rs16
1
ERd32–#xx:32
ERd32–ERs32
0–Rd8 → Rd8
0–Rd16 → Rd16
0–ERd32 → ERd32
2
L
2
2
2
2
2
2
B
↕
↕
↕
—
NEG.W Rd
W
L
NEG.L ERd
EXTU.W Rd
W
0 → (<bits 15 to 8>
of Rd16)
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
L
W
L
0 → (<bits 31 to 16>
2
2
2
—
—
—
—
—
—
0
↕
↕
↕
0
0
0
—
—
—
2
2
2
of Rd32)
(<bit 7> of Rd16) →
↕
↕
(<bits 15 to 8> of Rd16)
(<bit 15> of Rd32) →
(<bits 31 to 16> of
ERd32)
393
Table A-1 Instruction Set (cont)
3. Logic instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
OR.B #xx:8, Rd
OR.B Rs, Rd
B
B
W
W
L
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
2
4
6
2
4
6
2
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
2
2
4
2
2
4
2
2
Rd16 #xx:16 → Rd16
Rd16 Rs16 → Rd16
ERd32 #xx:32 → ERd32
ERd32 ERs32 → ERd32
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
L
B
B
W
W
L
OR.W #xx:16, Rd
OR.W Rs, Rd
Rd16 #xx:16 → Rd16
Rd16 Rs16 → Rd16
ERd32 #xx:32 → ERd32
ERd32 ERs32 → ERd32
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
OR.L #xx:32, ERd
OR.L ERs, ERd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
NOT.B Rd
L
B
B
W
W
L
Rd16 #xx:16 → Rd16
Rd16 Rs16 → Rd16
ERd32 #xx:32 → ERd32
ERd32 ERs32 → ERd32
¬ Rd8 → Rd8
L
4
2
2
2
B
W
L
NOT.W Rd
¬ Rd16 → Rd16
NOT.L ERd
¬ Rd32 → Rd32
394
Table A-1 Instruction Set (cont)
4. Shift instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
↕
↕
↕
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
B
W
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C
0
MSB
LSB
LSB
LSB
LSB
B
W
L
C
MSB
B
W
L
C
0
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
MSB
B
W
L
0
C
MSB
B
W
L
C
MSB
LSB
B
W
L
C
MSB
LSB
B
W
L
C
MSB
LSB
B
W
L
C
MSB
LSB
395
Table A-1 Instruction Set (cont)
5. Bit manipulation instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
2
4
4
2
4
4
2
4
4
2
4
4
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
8
8
2
8
8
2
8
8
2
8
8
2
BSET Rn, @ERd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
B
B
B
B
B
(#xx:3 of @ERd) ←
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
8
2
8
8
¬ (#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
4
¬ (#xx:3 of @aa:8)
(Rn8 of Rd8) ←
2
4
4
¬ (Rn8 of Rd8)
BNOT Rn, @ERd
BNOT Rn, @aa:8
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
B
B
B
B
B
B
B
(#xx:3 of Rd8) → Z
(#xx:3 of @ERd) → Z
(#xx:3 of @aa:8) → Z
(Rn8 of @Rd8) → Z
(Rn8 of @ERd) → Z
(Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
2
4
4
2
4
4
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↕ —
↕ —
↕ —
↕ —
↕ —
↕ —
—
—
—
—
—
—
↕
2
6
6
2
6
6
2
BTST Rn, @ERd
BTST Rn, @aa:8
BLD #xx:3, Rd
—
—
396
Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
↕
↕
↕
↕
↕
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of @ERd) → C
(#xx:3 of @aa:8) → C
¬ (#xx:3 of Rd8) → C
¬ (#xx:3 of @ERd) → C
¬ (#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
4
2
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
BST #xx:3, Rd
4
4
2
BST #xx:3, @REd
BST #xx:3, @aa:8
BIST #xx:3, Rd
C → (#xx:3 of @ERd)
C → (#xx:3 of @aa:8)
C → (#xx:3 of Rd8)
4
4
2
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
C → (#xx:3 of @ERd24)
C → (#xx:3 of @aa:8)
C (#xx:3 of Rd8) → C
C (#xx:3 of @ERd24) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @ERd24) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @ERd24) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @ERd24) → C
C (#xx:3 of @aa:8) → C
4
4
2
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
4
4
2
4
4
2
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
4
4
2
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
4
4
C
C
C
C
C
C
(#xx:3 of Rd8) → C
(#xx:3 of @ERd24) → C
(#xx:3 of @aa:8) → C
(#xx:3 of Rd8) → C
2
4
4
2
(#xx:3 of @ERd24) → C
(#xx:3 of @aa:8) → C
4
4
397
Table A-1 Instruction Set (cont)
6. Branching instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
Operation
I
H
N
Z
V
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Always
Never
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
If condition
is true then
PC ←
PC+d else
next;
C
C
Z = 0
BHI d:16
BLS d:8
Z = 1
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
N
N
V = 0
BGE d:16
BLT d:8
V = 1
BLT d:16
Z
(N V)
BGT d:8
= 0
BGT d:16
398
Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
BLE d:8
Operation
I
H
N
Z
V
C
Z
(N V)
—
—
2
4
—
—
—
—
—
—
—
—
—
—
—
—
4
6
If condition
is true then
PC ←
= 1
BLE d:16
PC+d else
next;
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
—
—
—
—
PC ← ERn
2
4
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
PC ← aa:24
PC ← @aa:8
6
8
6
10
8
PC → @–SP
PC ← PC+d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
—
—
—
—
—
PC → @–SP
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
6
8
8
8
10
8
PC ← PC+d:16
PC → @–SP
PC ← @ERn
2
4
2
PC → @–SP
10
12
10
PC ← @aa:24
PC → @–SP
PC ← @aa:8
PC ← @SP+
2
399
Table A-1 Instruction Set (cont)
7. System control instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
TRAPA #x:2
—
PC → @–SP
2
—
—
—
—
—
—
14
16
CCR → @–SP
<vector> → PC
RTE
—
—
CCR ← @SP+
PC ← @SP+
↕
↕
↕
↕
↕
↕
10
2
SLEEP
Transition to power-
down state
—
—
—
—
—
—
LDC #xx:8, CCR
LDC Rs, CCR
B
B
#xx:8 → CCR
2
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
2
2
6
8
Rs8 → CCR
2
4
6
LDC @ERs, CCR
W
W
@ERs → CCR
@(d:16, ERs) → CCR
LDC @(d:16, ERs),
CCR
LDC @(d:24, ERs),
CCR
W
W
@(d:24, ERs) → CCR
10
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
12
8
LDC @ERs+, CCR
@ERs → CCR
4
ERs32+2 → ERs32
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
W
W
B
@aa:16 → CCR
@aa:24 → CCR
CCR → Rd8
6
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
8
10
2
8
2
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STC CCR, @ERd
W
W
CCR → @ERd
CCR → @(d:16, ERd)
6
STC CCR, @(d:16,
ERd)
8
STC CCR, @(d:24,
ERd)
W
W
CCR → @(d:24, ERd)
10
—
—
—
—
—
—
—
—
—
—
—
—
12
8
STC CCR, @–ERd
ERd32–2 → ERd32
CCR → @ERd
4
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
W
W
B
CCR → @aa:16
CCR → @aa:24
CCR #xx:8 → CCR
CCR #xx:8 → CCR
CCR #xx:8 → CCR
PC ← PC+2
6
8
—
—
↕
↕
↕
—
—
—
↕
↕
↕
—
—
—
↕
↕
↕
—
—
—
↕
↕
↕
—
—
—
↕
↕
↕
—
—
—
↕
↕
↕
—
8
10
2
2
2
2
B
2
B
2
—
2
2
400
Table A-1 Instruction Set (cont)
8. Block transfer instructions
Addressing Mode and
Instruction Length (bytes)
No. of
States
*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
EEPMOV. B
—
if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
4
—
—
—
—
—
—
8+
*2
4n
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
EEPMOV. W
—
if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
4
—
—
—
—
—
—
8+
*2
4n
R6+1 → R6
R4L–1 → R4
until
R4=0
else next
Notes: 1. The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory. For other cases see section A.3, Number of States
Required for Execution.
2. n is the value set in register R4L or R4.
1
2
3
4
5
Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
Retains its previous value when the result is zero; otherwise cleared to 0.
Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
6
7
8
Set to 1 when the divisor is negative; otherwise cleared to 0.
Set to 1 when the divisor is zero; otherwise cleared to 0.
Set to 1 when the quotient is negative; otherwise cleared to 0.
401
A.2 Operation Code Map (1)
Table A-2 Operation Code Map
1st byte 2nd byte
AH AL BH BL
Instruction code:
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
AL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
AH
Table A.2
(2)
Table A.2 Table A.2
(2) (2)
Table A.2
(2)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
STC
LDC
ORG
OR.B
XORC
XOR.B
ANDC
AND.B
LDC
MOV
CMP
ADDX
SUBX
ADD
SUB
Table A.2 Table A.2 Table A.2 Table A.2
Table A.2
(2)
Table A.2 Table A.2
Table A.2
(2)
(2)
(2)
(2)
(2)
(2)
(2)
BRA
BRN
BHI
BLS
BCC
RTS
BCS
BSR
BNE
RTE
BEQ
BVC
BVS
BPL
JMP
BMI
BGE
BSR
BLT
BGT
JSR
BLE
Table A.2
(2)
MULXU.B DIVXU.B MULXU.W DIVXU.W
TRAPA
BST
MOV
OR.W
XOR.W
AND.W
MOV.B
BIST
BLD
BSET
BNOT
BCLR
BTST
BOR
BIOR
BXOR
BIXOR
BAND
Table A.2 Table A.2
Table A.2
(3)
MOV.B/W
EEPMOV
(2)
(2)
BIAND
BILD
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Operation Code Map (2)
Table A-2 Operation Code Map (cont)
1st byte 2nd byte
AH AL BH BL
Instruction code:
BH
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
AH AL
Table A.2 Table A.2
Table A.2
(3)
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
LDC/STC
SLEEP
(3)
(3)
ADD
MOV
ADDS
DAA
INC
INC
ADDS
INC
INC
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHLL
SHAL
SHAR
ROTL
ROTR
NEG
SHAR
ROTL
ROTR
NEG
SHLR
ROTXL
ROTXR
NOT
EXTU
DEC
EXTU
DEC
BEQ
EXTS
DEC
BLT
EXTS
DEC
BLE
DEC
SUB
SUB
SUBS
DAS
CMP.L
BRA
BRN
ADD
ADD
BHI
CMP
CMP
BLS
SUB
SUB
BCC
OR
BCS
XOR
XOR
BNE
AND
AND
BVC
BVS
BPL
BMI
BGE
BGT
MOV
MOV
OR
Operation Code Map (3)
Table A-2 Operation Code Map (cont)
3rd byte
1st byte 2nd byte
4th byte
Instruction code:
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
AH AL BH BL CH CL DH DL
C
AH
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ALBH
BLCH
LDC
STC
LBC
LDC
LDC
STC
01406
STC
STC
01C05
01D05
01F06
MULXS
MULXS
DIVXS
DIVXS
OR
XOR
AND
*1
7Cr06
7Cr07
7Dr06
7Dr07
7Eaa6
7Eaa7
7Faa6
7Faa7
BTST
BTST
BOR
BIOR
BXOR
BAND
BLD
*1
*1
*1
*2
*2
*2
*2
BIXOR
BIAND
BILD
BST
BSET
BSET
BNOT
BNOT
BCLR
BCLR
BIST
BTST
BTST
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
BSET
BSET
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A-4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A-3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × S + J × S + K × S + L × S + M × S + N × S
N
I
J
K
L
M
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A-3, I = L = 2 and J = K = M = N = 0
From table A-2, S = 4 and S = 3
I
L
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A-3, I = J = K = 2 and L = M = N = 0
From table A-2, S = S = S = 4
I
J
K
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
405
Table A-3 Number of States per Cycle
Access Conditions
External Device
8-Bit Bus 16-Bit Bus
On-Chip Sup-
porting Module
On-Chip 8-Bit
Memory Bus
16-Bit
Bus
2-State 3-State 2-State 3-State
Access Access Access Access
Cycle
Instruction fetch
SI
2
6
3
4
6 + 2m
2
3 + m
Branch address read SJ
Stack operation
Byte data access
Word data access
Internal operation
Legend
SK
SL
SM
SN
3
6
2
4
3 + m
6 + 2m
1
m: Number of wait states inserted into external device access
406
Table A-4 Number of Cycles per Instruction
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS
ADDX
ADDS #1/2/4, ERd
1
ADDX #xx:8, Rd
ADDX Rs, Rd
1
1
AND
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC
BAND
ANDC #xx:8, CCR
1
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
2
1
1
Bcc
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
407
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
Bcc
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
BCLR
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND
BILD
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
BIOR
BIST
BIOR #xx:8, Rd
BIOR #xx:8, @ERd
BIOR #xx:8, @aa:8
1
2
2
1
1
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR
BLD
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
408
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
BNOT
BNOT #xx:3, Rd
1
2
2
1
2
2
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
2
2
2
2
BOR
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR
BSR d:8
Normal*1
2
2
2
2
1
2
1
2
Advanced
BSR d:16 Normal*1
Advanced
2
2
BST
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
1
2
2
2
2
BTST
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR
CMP
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA
DAS
DAA Rd
DAS Rd
1
1
409
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
DEC
DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DIVXS
DIVXU
DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV EEPMOV.B
EEPMOV.W
2
2
2n + 2*2
2n + 2*2
EXTS
EXTU
INC
EXTS.W Rd
EXTS.L ERd
1
1
EXTU.W Rd
EXTU.L ERd
1
1
INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP
JSR
JMP @ERn
2
2
2
JMP @aa:24
2
2
2
JMP @@aa:8 Normal*1
1
2
Advanced 2
JSR @ERn Normal*1
Advanced 2
JSR @aa:24 Normal*1
Advanced 2
JSR @@aa:8 Normal*1
Advanced 2
2
1
2
1
2
1
2
2
2
2
2
1
2
LDC
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
1
1
2
1
1
1
1
1
1
LDC @(d:16, ERs), CCR 3
LDC @(d:24, ERs), CCR 5
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
2
3
4
2
410
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
MOV MOV.B #xx:8, Rd
J
K
L
1
1
1
2
4
1
1
2
3
1
2
4
1
1
2
3
2
1
1
2
4
1
2
3
1
2
4
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
MOV.B Rs, Rd
MOV.B @ERs, Rd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
2
2
MOV.W @ERs, Rd
1
1
1
1
1
1
1
1
1
1
1
1
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs), ERd
MOV.L @(d:24, ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16, ERd)
MOV.L ERs, @(d:24, ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
411
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
MOVFPE
MOVTPE
MULXS
MOVFPE @aa:16, Rd*3
2
2
1*3
1*3
MOVTPE Rs, @aa:16*3
MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
12
20
MULXU
NEG
MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP
NOT
NOP
1
NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC
POP
ORC #xx:8, CCR
1
POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH
ROTL
PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR
ROTXL
ROTXR
RTE
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE
2
2
2
412
Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
RTS
RTS
Normal*1
2
2
1
2
2
Advanced
2
SHAL
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR
SHLL
SHLR
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP
STC
SLEEP
1
STC CCR, Rd
STC CCR, @ERd
1
2
1
1
1
1
1
1
STC CCR, @(d:16, ERd) 3
STC CCR, @(d:24, ERd) 5
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
2
3
4
2
SUB
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS
SUBX
SUBS #1/2/4, ERd
1
SUBX #xx:8, Rd
SUBX Rs, Rd
1
1
TRAPA
XOR
TRAPA #x:2 Normal*1
Advanced
2
2
1
2
2
2
4
4
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC
XORC #xx:8, CCR
1
Notes: 1. Normal mode is not available in the H8/3001.
2. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
3. Not available in the H8/3001.
413
Appendix B Register Field
B.1 Register Addresses and Bit Names
Data
Bus
Bit Names
Address Register
(low)
H'1C
H'1D
H'1E
H'1F
Name
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'20
H'21
H'22
H'23
H'24
H'25
H'26
H'27
H'28
H'29
H'2A
H'2B
H'2C
H'2D
H'2E
H'2F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'30
H'31
H'32
H'33
H'34
H'35
H'36
H'37
H'38
H'39
H'3A
H'3B
H'3C
H'3D
H'3E
H'3F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Continued on next page)
414
(Continued from preceding page)
Data
Bus
Width Bit 7
Bit Names
Bit 4
Address Register
(low)
H'40
H'41
H'42
H'43
H'44
H'45
H'46
H'47
H'48
H'49
H'4A
H'4B
H'4C
H'4D
H'4E
H'4F
H'50
H'51
H'52
H'53
H'54
H'55
H'56
H'57
H'58
H'59
H'5A
H'5B
H'5C
H'5D
H'5E
H'5F
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Module Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Continued on next page)
415
(Continued from preceding page)
Data
Bus
Bit Names
Address Register
(low)
H'60
H'61
H'62
H'63
H'64
H'65
H'66
H'67
H'68
H'69
H'6A
H'6B
H'6C
H'6D
H'6E
H'6F
Name
Width Bit 7
Bit 6
—
Bit 5
—
Bit 4
STR4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
TSTR
8
—
—
STR3
STR2
STR1
STR0
ITU
(all channels)
TSNC
8
—
—
SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
PWM4 PWM3 PWM2 PWM1 PWM0
TMDR
TFCR
8
MDF
—
FDIR
—
8
—
—
—
—
—
—
BFB4
BFA4
BFB3
BFA3
TCR0
8
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
ITU channel 0
TIOR0
TIER0
TSR0
8
IOB2
—
IOB1
—
IOB0
—
—
—
—
IOA2
OVIE
OVF
IOA1
IMIEB
IMFB
IOA0
IMIEA
IMFA
8
8
—
—
—
TCNT0H
TCNT0L
GRA0H
GRA0L
GRB0H
GRB0L
TCR1
16
16
16
8
8
—
—
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
ITU channel 1
TIOR1
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'70
H'71
H'72
H'73
H'74
H'75
H'76
H'77
H'78
H'79
H'7A
H'7B
H'7C
H'7D
H'7E
H'7F
TIER1
8
—
—
—
—
—
—
—
—
—
—
OVIE
OVF
IMIEB
IMFB
IMIEA
IMFA
TSR1
8
TCNT1H
TCNT1L
GRA1H
GRA1L
GRB1H
GRB1L
TCR2
16
16
16
8
—
—
—
—
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
ITU channel 2
TIOR2
8
IOB2
—
IOB1
—
IOB0
—
—
—
—
IOA2
OVIE
OVF
IOA1
IMIEB
IMFB
IOA0
IMIEA
IMFA
TIER2
8
TSR2
8
—
—
—
TCNT2H
TCNT2L
GRA2H
GRA2L
16
16
16
H'80
GRB2H
GRB2L
H'81
Legend
ITU: 16-bit integrated timer unit
(Continued on next page)
416
(Continued from preceding page)
Data
Bus
Width Bit 7
Bit Names
Bit 4 Bit 3
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Address Register
(low)
H'82
H'83
H'84
H'85
H'86
H'87
H'88
H'89
H'8A
H'8B
H'8C
H'8D
H'8E
H'8F
H'90
H'91
H'92
H'93
H'94
H'95
H'96
H'97
H'98
H'99
H'9A
H'9B
H'9C
H'9D
H'9E
H'9F
Legend
Name
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Module Name
TCR3
8
—
—
—
—
ITU channel 3
TIOR3
TIER3
8
IOB2
—
IOB1
—
IOB0
—
—
—
—
IOA2
OVIE
OVF
IOA1
IMIEB
IMFB
IOA0
IMIEA
IMFA
8
TSR3
8
—
—
—
TCNT3H
TCNT3L
GRA3H
GRA3L
GRB3H
GRB3L
BRA3H
BRA3L
BRB3H
BRB3L
TOER
16
16
16
16
16
8
—
—
—
—
—
—
—
—
—
—
—
—
EB3
—
EB4
—
EA4
—
EA3
—
ITU
(all channels)
—
TCR4
8
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
ITU channel 4
TIOR4
TIER4
8
IOB2
—
IOB1
—
IOB0
—
—
—
—
IOA2
OVIE
OVF
IOA1
IMIEB
IMFB
IOA0
IMIEA
IMFA
8
TSR4
8
—
—
—
TCNT4H
TCNT4L
GRA4H
GRA4L
GRB4H
GRB4L
BRA4H
BRA4L
BRB4H
BRB4L
16
16
16
16
16
ITU: 16-bit integrated timer unit
(Continued on next page)
417
(Continued from preceding page)
Data
Bus
Bit Names
Address Register
(low)
H'A0
H'A1
H'A2
H'A3
H'A4
Name
Width Bit 7
Bit 6
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
TPMR
TPCR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
—
—
—
—
—
—
G2NOV G1NOV G0NOV
TPC
—
G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
NDER11 NDER10 NDER9 NDER8
NDERB
NDERA
NDRB*
—
—
—
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
—
—
—
—
NDR11 NDR10 NDR9
NDR8
—
—
—
—
—
—
—
—
H'A5
H'A6
H'A7
NDRA*
NDRB*
NDRA*
NDR7
NDR7
—
NDR6
NDR6
—
NDR5
NDR5
—
NDR4
NDR4
—
NDR3
—
NDR2
—
NDR1
—
NDR0
—
—
—
—
—
—
—
—
—
NDR11 NDR10 NDR9
NDR8
—
—
—
—
—
—
—
—
—
—
—
—
NDR3
—
NDR2
—
NDR1
—
NDR0
—
H'A8
H'A9
H'AA
H'AB
H'AC
H'AD
H'AE
H'AF
TCSR
TCNT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'B0
H'B1
H'B2
H'B3
H'B4
H'B5
H'B6
H'B7
SMR
BRR
SCR
TDR
SSR
RDR
—
8
8
8
8
8
8
C/A
CHR
PE
O/E
STOP
MPIE
PER
MP
CKS1
CKE1
MPB
CKS0
CKE0
MPBT
SCI channel 0
TIE
RIE
TE
RE
TEIE
TEND
TDRE
RDRF
ORER FER
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: * The address depends on the output trigger setting.
Legend
TPC: Programmable timing pattern controller
SCI: Serial communication interface
(Continued on next page)
418
(Continued from preceding page)
Data
Bus
Bit Names
Address Register
(low)
H'B8
H'B9
H'BA
H'BB
H'BC
H'BD
H'BE
H'BF
Name
Width Bit 7
Bit 6
—
Bit 5
—
Bit 4
Bit 3
—
Bit 2
—
Bit 1
—
Bit 0
—
Module Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'C0
H'C1
H'C2
H'C3
H'C4
H'C5
H'C6
H'C7
H'C8
H'C9
H'CA
H'CB
H'CC
H'CD
H'CE
H'CF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P4DDR
—
8
8
8
8
P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR Port 4
7
6
5
4
3
2
1
0
—
P4
—
—
—
—
—
—
—
—
—
P4
—
—
—
—
—
—
—
—
—
P4
—
—
—
—
—
—
—
—
—
P4
—
—
—
—
—
—
—
—
—
P4
—
—
—
—
—
—
P7
—
—
P4
—
—
P4
—
—
P4
—
P4DR
—
Port 4
7
6
5
4
3
2
1
0
P6DDR
—
P6 DDR P6 DDR P6 DDR Port 6
2
1
0
—
P6
—
—
P7
—
—
P6
—
—
P6
—
P6DR
—
Port 6
2
1
0
P8DDR
P7DR
P8DR
8
8
8
P8 DDR P8 DDR Port 8
1
1
1
0
0
0
P7
P8
P7
P8
Port 7
Port 8
3
2
H'D0
H'D1
H'D2
H'D3
H'D4
H'D5
H'D6
H'D7
P9DDR
PADDR
P9DR
PADR
PBDDR
—
8
8
8
8
8
—
—
—
P9 DDR —
P9 DDR —
P9 DDR Port 9
0
4
2
PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Port A
7
6
5
4
4
3
2
2
1
0
0
—
PA
—
—
—
—
—
PA
—
—
—
—
—
PA
—
—
—
—
P9
—
P9
PA
—
P9
PA
Port 9
Port A
PA
—
—
—
—
PA
PA
7
6
5
4
3
2
1
0
PB DDR PB DDR PB DDR PB DDR Port B
3
2
1
0
—
—
—
—
PBDR
—
8
PB
—
PB
—
PB
—
PB
—
Port B
3
2
1
0
(Continued on next page)
419
(Continued from preceding page)
Data
Bus
Bit Names
Address Register
(low)
H'D8
H'D9
H'DA
H'DB
H'DC
H'DD
H'DE
H'DF
Name
Width Bit 7
Bit 6
—
Bit 5
—
Bit 4
Bit 3
—
Bit 2
—
Bit 1
—
Bit 0
—
Module Name
—
—
—
—
—
—
—
—
—
—
—
—
P4PCR
—
8
P4 PCR P4 PCR P4 PCR P4 PCR P4 PCR P4 PCR P4 PCR P4 PCR Port 4
7 6 5 4 3 2 1 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'E0
H'E1
H'E2
H'E3
H'E4
H'E5
H'E6
H'E7
H'E8
H'E9
H'EA
H'EB
H'EC
H'ED
H'EE
H'EF
Legend
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCSR
ADCR
8
8
8
8
8
8
8
8
8
8
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
ADF
TRGE
—
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
ADIE
—
AD7
—
AD6
—
AD5
—
AD4
—
AD3
—
AD2
—
A/D
AD7
—
AD6
—
AD5
—
AD4
—
AD3
—
AD2
—
AD7
—
AD6
—
AD5
—
AD4
—
AD3
—
AD2
—
AD7
—
AD6
—
AD5
—
AD4
—
AD3
—
AD2
—
ADST
—
SCAN
—
CKS
—
CH2
—
CH1
—
CH0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ABWCR
ASTCR
WCR
8
8
8
8
ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Bus controller
AST7
—
AST6
—
AST5
—
AST4
—
AST3
AST2
AST1
AST0
WC0
WMS1 WMS0 WC1
WCER
WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0
A/D: A/D converter
(Continued on next page)
420
(Continued from preceding page)
Data
Bus
Bit Names
Address Register
(low)
H'F0
H'F1
H'F2
H'F3
H'F4
H'F5
H'F6
H'F7
H'F8
H'F9
H'FA
H'FB
H'FC
H'FD
H'FE
H'FF
Name
Width Bit 7
Bit 6
—
Bit 5
—
Bit 4
Bit 3
—
Bit 2
—
Bit 1
—
Bit 0
—
Module Name
System control
Bus controller
—
—
—
MDCR
SYSCR
BRCR
ISCR
IER
ISR
—
8
8
8
8
8
8
—
—
—
—
—
MDS2
NMIEG
—
MDS1
—
MDS0
RAME
BRLE
SSBY
—
STS2
—
STS1
—
STS0
—
UE
—
—
—
—
—
IRQ4SC —
—
IRQ1SC IRQ0SC
IRQ1E IRQ0E
IRQ1F IRQ0F
Interrupt
controller
—
—
—
IRQ4E
IRQ4F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IPRA
IPRB
—
8
8
IPRA7 IPRA6
IPRB7 IPRB6
—
IPRA4
—
—
IPRA2 IPRA1 IPRA0
Interrupt
controller
—
IPRB3
—
—
—
—
—
—
—
—
IPRB1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
421
B.2 Register Descriptions
Register
acronym
Register
name
Address to which
the register is mapped
Name of on-chip
supporting
module
TSTR Timer Start Register
H'60
ITU (all channels)
Bit
numbers
Bit
7
—
1
6
—
1
5
—
1
4
STR4
0
3
STR3
0
2
STR2
0
1
STR1
0
0
STR0
0
Initial bit
values
Initial value
Read/Write
Names of the
bits. Dashes
(—) indicate
reserved bits.
—
—
—
R/W
R/W
R/W
R/W
R/W
Possible types of access
Counter start 0
R
Read only
Write only
0
1
TCNT0 is halted
TCNT0 is counting
W
R/W Read and write
Counter start 1
0
1
TCNT1 is halted
TCNT1 is counting
Full name
of bit
Counter start 2
0
1
TCNT2 is halted
TCNT2 is counting
Descriptions
of bit settings
Counter start 3
0
1
TCNT3 is halted
TCNT3 is counting
Counter start 4
0
1
TCNT4 is halted
TCNT4 is counting
422
TSTR—Timer Start Register
H'60
ITU (all channels)
Bit
7
—
1
6
—
1
5
—
1
4
STR4
0
3
STR3
0
2
STR2
0
1
STR1
0
0
STR0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Counter start 0
0
1
TCNT0 is halted
TCNT0 is counting
Counter start 1
0
1
TCNT1 is halted
TCNT1 is counting
Counter start 2
0
1
TCNT2 is halted
TCNT2 is counting
Counter start 3
0
1
TCNT3 is halted
TCNT3 is counting
Counter start 4
0
1
TCNT4 is halted
TCNT4 is counting
423
TSNC—Timer Synchro Register
H'61
ITU (all channels)
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
0
SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Initial value
Read/Write
0
0
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Timer sync 0
0
1
TCNT0 operates independently
TCNT0 is synchronized
Timer sync 1
0
1
TCNT1 operates independently
TCNT1 is synchronized
Timer sync 2
0
1
TCNT2 operates independently
TCNT2 is synchronized
Timer sync 3
0
1
TCNT3 operates independently
TCNT3 is synchronized
Timer sync 4
0
1
TCNT4 operates independently
TCNT4 is synchronized
424
TMDR—Timer Mode Register
H'62
ITU (all channels)
Bit
7
—
1
6
5
FDIR
0
4
3
2
1
0
MDF
0
PWM4 PWM3 PWM2
PWM1 PWM0
Initial value
Read/Write
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 0
0
1
Channel 0 operates normally
Channel 0 operates in PWM mode
PWM mode 1
0
1
Channel 1 operates normally
Channel 1 operates in PWM mode
PWM mode 2
0
1
Channel 2 operates normally
Channel 2 operates in PWM mode
PWM mode 3
0
1
Channel 3 operates normally
Channel 3 operates in PWM mode
PWM mode 4
0
1
Channel 4 operates normally
Channel 4 operates in PWM mode
Flag direction
0
1
OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0
1
Channel 2 operates normally
Channel 2 operates in phase counting mode
425
TFCR—Timer Function Control Register
H'63
ITU (all channels)
Bit
7
—
1
6
—
1
5
—
4
—
3
BFB4
0
2
BFA4
0
1
BFB3
0
0
BFA3
0
Initial value
Read/Write
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Buffer mode A3
0
1
GRA3 operates normally
GRA3 is buffered by BRA3
Buffer mode B3
0
1
GRB3 operates normally
GRB3 is buffered by BRB3
Buffer mode A4
0
1
GRA4 operates normally
GRA4 is buffered by BRA4
Buffer mode B4
0
1
GRB4 operates normally
GRB4 is buffered by BRB4
426
TCR0—Timer Control Register 0
H'64
ITU0
Bit
7
—
1
6
5
4
3
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer prescaler 2 to 0
Bit 1
Bit 2 Bit 0
TPSC2 TPSC1 TPSC0 TCNT Clock Source
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: ø
Internal clock: ø/2
Internal clock: ø/4
Internal clock: ø/8
1
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
Clock edge 1 and 0
Bit 4
CKEG1CKEG0 Counted Edges of External Clock
Bit 3
0
0
1
Rising edges counted
Falling edges counted
Both edges counted
1
—
Counter clear 1 and 0
Bit 6 Bit 5
CCLR1 CCLR0 TCNT Clear Source
0
0
1
0
1
TCNT is not cleared
TCNT is cleared by GRA compare match or input capture
TCNT is cleared by GRB compare match or input capture
1
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers
427
TIOR0—Timer I/O Control Register 0
H'65
ITU0
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
1
IOA1
0
0
IOA2
IOA0
0
Initial value
Read/Write
0
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0 GRA Function
0
0
1
0
1
0
1
0
1
0
1
0
1
GRA is an output No output at compare match
compare register
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
1
GRA is an input
capture register
I/O control B2 to B0
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0 GRB Function
0
0
1
0
1
0
1
0
1
0
1
0
1
GRB is an output No output at compare match
compare register
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
1
GRB is an input
capture register
428
TIER—Timer Interrupt Enable Register
H'66
ITU0
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVIE
0
1
IMIEB
0
0
IMIEA
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Input capture/compare match interrupt enable A
0
1
IMIA interrupt requested by IMFA is disabled
IMIA interrupt requested by IMFA is enabled
Input capture/compare match interrupt enable B
0
1
IMIB interrupt requested by IMFB is disabled
IMIB interrupt requested by IMFB is enabled
Overflow interrupt enable
0
1
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
429
TSR0—Timer Status Register 0
H'67
ITU0
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
IMFB
0
0
OVF
IMFA
Initial value
Read/Write
0
0
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Input capture/compare match flag A
0
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
[Setting conditions]
1
TCNT = GRA when GRA functions as a compare
match register.
TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
Input capture/compare match flag B
0
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1
[Setting conditions]
TCNT = GRB when GRB functions as a compare
match register.
TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
Overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed
from H'0000 to H'FFFF
Note:* Only 0 can be written, to clear the flag.
430
TCNT0 H/L—Timer Counter 0 H/L
H'68, H'69
ITU0
Bit
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
4
3
2
0
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
GRA0 H/L—General Register A0 H/L
H'6A, H'6B
ITU0
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
GRB0 H/L—General Register B0 H/L
H'6C, H'6D
ITU0
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
TCR1—Timer Control Register 1
H'6E
ITU1
Bit
7
—
1
6
5
4
3
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
431
TIOR1—Timer I/O Control Register 1
H'6F
ITU1
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
IOA2
0
1
IOA1
0
0
IOA0
0
Initial value
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER1—Timer Interrupt Enable Register 1
H'70
ITU1
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVIE
0
1
IMIEB
0
0
IMIEA
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR1—Timer Status Register 1
H'71
ITU1
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVF
0
1
IMFB
0
0
IMFA
0
Initial value
Read/Write
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
TCNT1 H/L—Timer Counter 1 H/L
H'72, H'73
ITU1
Bit
15 14 13 12 11 10
9
8
0
7
0
6
0
5
4
3
2
0
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
432
GRA1 H/L—General Register A1 H/L
H'74, H'75
ITU1
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB1 H/L—General Register B1 H/L
H'76, H'77
ITU1
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
TCR2—Timer Control Register 2
H'78
ITU2
Bit
7
—
1
6
5
4
3
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. Bit functions are the same as for ITU0.
2.
When channel 2 is used in phase counting mode, the counter clock source selection by
bits TPSC2 to TPSC0 is ignored.
433
TIOR2—Timer I/O Control Register 2
H'79
ITU2
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
1
IOA1
0
0
IOA2
IOA0
0
Initial value
Read/Write
0
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
434
TIER2—Timer Interrupt Enable Register 2
H'7A
ITU2
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVIE
0
1
IMIEB
0
0
IMIEA
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR2—Timer Status Register 2
H'7B
ITU2
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVF
0
1
IMFB
0
0
IMFA
0
Initial value
Read/Write
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Bit functions are the
same as for ITU0.
Overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
1
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: *Only 0 can be written, to clear the flag.
TCNT2 H/L—Timer Counter 2 H/L
H'7C, H'7D
ITU2
Bit
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
4
3
2
0
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Phase counting mode: up/down counter
Other modes:
up-counter
435
GRA2 H/L—General Register A2 H/L
H'7E, H'7F
ITU2
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB2 H/L—General Register B2 H/L
H'80, H'81
ITU2
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
TCR3—Timer Control Register 3
H'82
ITU3
Bit
7
—
1
6
5
4
3
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIOR3—Timer I/O Control Register 3
H'83
ITU3
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
IOA2
0
1
IOA1
0
0
IOA0
0
Initial value
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
436
TIER3—Timer Interrupt Enable Register 3
H'84
ITU3
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
IMIEB
0
0
OVIE
IMIEA
0
Initial value
Read/Write
0
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR3—Timer Status Register 3
H'85
ITU3
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVF
0
1
IMFB
0
0
IMFA
0
Initial value
Read/Write
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Bit functions are the
same as for ITU0
Overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
1
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: *Only 0 can be written, to clear the flag.
TCNT3 H/L—Timer Counter 3 H/L
H'86, H'87
ITU3
Bit
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
4
3
2
0
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Complementary PWM mode: up/down counter
Other modes:
up-counter
437
GRA3 H/L—General Register A3 H/L
H'88, H'89
ITU3
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
GRB3 H/L—General Register B3 H/L
H'8A, H'8B
ITU3
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
BRA3 H/L—Buffer Register A3 H/L
H'8C, H'8D
ITU3
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRA
BRB3 H/L—Buffer Register B3 H/L
H'8E, H'8F
ITU3
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRB
438
TOER—Timer Output Enable Register
H'90
ITU (all channels)
Bit
7
—
1
6
—
1
5
—
4
—
3
2
1
0
EB3
1
EB4
1
EA4
1
EA3
1
Initial value
Read/Write
1
1
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Master enable TIOCA3
0
1
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings
TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings
Master enable TIOCA4
0
1
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings
TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings
Master enable TIOCB4
0
1
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
Master enable TIOCB3
0
1
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings
TIOCB3 is enabled for output according to TIOR3 and TFCR settings
439
TCR4—Timer Control Register 4
H'92
ITU4
Bit
7
—
1
6
5
4
3
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
Read/Write
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIOR4—Timer I/O Control Register 4
H'93
ITU4
Bit
7
—
1
6
IOB2
0
5
IOB1
0
4
IOB0
0
3
—
1
2
IOA2
0
1
IOA1
0
0
IOA0
0
Initial value
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER4—Timer Interrupt Enable Register 4
H'94
ITU4
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVIE
0
1
IMIEB
0
0
IMIEA
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR4—Timer Status Register 4
H'95
ITU4
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
OVF
0
1
IMFB
0
0
IMFA
0
Initial value
Read/Write
—
—
—
—
—
R/(W)* R/(W)* R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
440
TCNT4 H/L—Timer Counter 4 H/L
H'96, H'97
ITU4
Bit
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
4
3
2
0
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRA4 H/L—General Register A4 H/L
H'98, H'99
ITU4
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRB4 H/L—General Register B4 H/L
H'9A, H'9B
ITU4
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
BRA4 H/L—Buffer Register A4 H/L
H'9C, H'9D
ITU4
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
441
BRB4 H/L—Buffer Register B4 H/L
H'9E, H'9F
ITU4
Bit
15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
4
3
2
1
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
TPMR—TPC Output Mode Register
H'A0
TPC
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
2
1
0
G2NOV G1NOV G0NOV
Initial value
Read/Write
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Group 0 non-overlap
0
Normal TPC output in group 0.
Output values change at compare match A in the selected ITU channel.
1
Non-overlapping TPC output in group 0, controlled by compare match
A and B in the selected ITU channel
Group 1 non-overlap
0
Normal TPC output in group 1.
Output values change at compare match A in the selected ITU channel.
1
Non-overlapping TPC output in group 1, controlled by compare match
A and B in the selected ITU channel
Group 2 non-overlap
0
Normal TPC output in group 2.
Output values change at compare match A in the selected ITU channel.
1
Non-overlapping TPC output in group 2, controlled by compare match
A and B in the selected ITU channel
442
TPCR—TPC Output Control Register
H'A1
TPC
Bit
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 0 compare match select 1 and 0
Bit 1 Bit 0
G0CMS1 G0CMS0 Description
0
0
1
0
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3
1
Group 1 compare match select 1 and 0
Bit 3 Bit 2
G1CMS1 G1CMS0 Description
0
0
1
0
1
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 0
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 1
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 2
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 3
1
Group 2 compare match select 1 and 0
Bit 5 Bit 4
G2CMS1 G2CMS0 Description
0
0
1
0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 0
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 1
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 2
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 3
1
Group 3 compare match select 1 and 0
Bit 7 Bit 6
G3CMS1 G3CMS0 Description
0
0
1
0
1
TPC output group 3 is triggered by compare match in ITU channel 0
TPC output group 3 is triggered by compare match in ITU channel 1
TPC output group 3 is triggered by compare match in ITU channel 2
TPC output group 3 is triggered by compare match in ITU channel 3
1
443
NDERB—Next Data Enable Register B
H'A2
TPC
Bit
7
—
6
—
5
—
4
—
3
2
1
0
NDER11 NDER10 NDER9 NDER8
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 11 to 8
Bits 3 to 0
NDER11 to NDER8 Description
0
TPC outputs TP11 to TP8 are disabled
(NDR11 to NDR8 are not transferred to PB3 to PB0)
1
TPC outputs TP11 to TP8 are enabled
(NDR11 to NDR8 are transferred to PB3 to PB0)
NDERA—Next Data Enable Register A
H'A3
TPC
Bit
7
6
5
4
3
2
1
0
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
Bits 7 to 0
NDER7 to NDER0 Description
0
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
1
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
444
NDRB—Next Data Register B
Same output trigger for TPC output groups 2 and 3
H'A4/H'A6
TPC
•
Address H'FFA4
Bit
7
—
6
—
5
—
4
—
3
2
1
NDR9
0
0
NDR8
0
NDR11 NDR10
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next output data for
TPC output group 2
Address H'FFA6
Bit
7
6
5
4
3
2
—
1
1
—
1
0
—
1
—
1
—
1
—
1
—
1
—
1
Initial value
Read/Write
—
—
—
—
—
—
—
—
•
Different output triggers for TPC output groups 2 and 3
Address H'FFA4
Bit
7
—
6
—
5
—
4
—
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
—
—
—
—
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
1
—
1
—
1
—
1
NDR11 NDR10
NDR9
0
NDR8
0
Initial value
Read/Write
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Next output data for
TPC output group 2
445
NDRA—Next Data Register A
Same output trigger for TPC output groups 0 and 1
H'A5/H'A7
TPC
•
Address H'FFA5
Bit
7
NDR7
0
6
NDR6
0
5
NDR5
0
4
NDR4
0
3
NDR3
0
2
1
0
NDR2
0
NDR1
0
NDR0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next output data for
TPC output group 1
Next output data for
TPC output group 0
Address H'FFA7
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
—
—
—
—
—
—
—
—
•
Different output triggers for TPC output groups 0 and 1
Address H'FFA5
Bit
7
NDR7
0
6
NDR6
0
5
NDR5
0
4
NDR4
0
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next output data for
TPC output group 1
Address H'FFA7
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
NDR3
0
2
NDR2
0
1
NDR1
0
0
NDR0
0
Initial value
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Next output data for
TPC output group 0
446
SMR—Serial Mode Register
H'B0
SCI
Bit
7
6
5
PE
0
7
3
STOP
0
2
MP
0
1
CKS1
0
0
CKS0
0
C/A
0
CHR
0
O/E
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 1 and 0
Bit 1 Bit 0
CKS1 CKS0 Clock Source
0
0
1
0
1
ø clock
Multiprocessor mode
ø/4 clock
ø/16 clock
ø/64 clock
0
1
Multiprocessor function disabled
Multiprocessor format selected
1
Stop bit length
0
1
One stop bit
Two stop bits
Parity mode
0
1
Even parity
Odd parity
Parity enable
0
1
Parity bit is not added or checked
Parity bit is added and checked
Character length
0
1
8-bit data
7-bit data
Communication mode
0
1
Asynchronous mode
Synchronous mode
447
BRR—Bit Rate Register
H'B1
SCI
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial communication bit rate setting
448
SCR—Serial Control Register
H'B2
SCI
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
MPIE
0
2
TEIE
0
1
CKE1
0
0
CKE0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable 1 and 0
Bit 1 Bit 0
CKE1 CKE0 Clock Selection and Output
0
0
Asynchronous mode Internal clock, SCK pin available for generic input/
output
Synchronous mode Internal clock, SCK pin used for serial clock output
Asynchronous mode Internal clock, SCK pin used for clock output
Synchronous mode Internal clock, SCK pin used for serial clock output
Asynchronous mode External clock, SCK pin used for clock input
Synchronous mode External clock, SCK pin used for serial clock input
Asynchronous mode External clock, SCK pin used for clock input
Synchronous mode External clock, SCK pin used for serial clock input
1
0
1
1
Transmit-end interrupt enable
0
1
Transmit-end interrupt requests (TEI) are disabled
Transmit-end interrupt requests (TEI) are enabled
Multiprocessor interrupt enable
0
1
Multiprocessor interrupts are disabled (normal receive operation)
Multiprocessor interrupts are enabled
Receive enable
Transmit enable
0
1
Transmitting is disabled
Transmitting is enabled
0
1
Transmitting is disabled
Transmitting is enabled
Receive interrupt enable
0
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Transmit interrupt enable
0
1
Transmit-data-empty interrupt request (TXI) is disabled
Transmit-data-empty interrupt request (TXI) is enabled
449
TDR—Transmit Data Register
H'B3
SCI
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit data
450
SSR—Serial Status Register
H'B4
SCI
Bit
7
TDRE
1
6
RDRF
0
5
ORER
0
4
FER
0
3
PER
0
2
1
MPB
0
0
TEND
MPBT
0
Initial value
Read/Write
1
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Multiprocessor bit
Multiprocessor bit transfer
0
Multiprocessor bit value in
receive data is 0
0
Multiprocessor bit value in
transmit data is 0
1
Multiprocessor bit value in
receive data is 1
1
Multiprocessor bit value in
transmit data is 1
Transmit end
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1
[Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
Parity error
Framing error
0
[Clearing conditions]
0
[Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
1
[Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/E in SMR)
1
[Setting condition]
Framing error (stop bit is 0)
Overrun error
Receive data register full
0
[Clearing conditions]
0
[Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
1
[Setting condition]
1
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Overrun error (reception of next serial data
ends when RDRF = 1)
Transmit data register empty
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1
[Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Note: *Only 0 can be written, to clear the flag.
451
RDR—Receive Data Register
H'B5
SCI
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Serial receive data
P4DDR—Port 4 Data Direction Register
H'C5
Port 4
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 4 input/output select
0
1
Generic input pin
Generic output pin
P4DR—Port 4 Data Register
H'C7
Port 4
Bit
7
6
5
4
3
2
1
0
P47
0
P46
0
P45
0
P44
0
P43
0
P42
0
P41
0
P40
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 4 pins
452
P6DDR—Port 6 Data Direction Register
H'C9
Port 6
Bit
7
—
1
6
—
0
5
—
0
4
—
0
3
—
0
2
1
0
P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
—
W
W
W
W
W
W
W
Port 6 input/output select
0
1
Generic input
Generic output
P6DR—Port 6 Data Register
H'CB
Port 6
Bit
7
—
1
6
—
0
5
—
0
4
—
0
3
—
0
2
1
0
P62
0
P61
0
P60
0
Initial value
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 6 pins
P8DDR—Port 8 Data Direction Register
H'CD
Port 8
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
1
0
—
0
P81DDR P80DDR
Initial value
Read/Write
0
0
—
—
—
W
W
W
W
W
Port 81 input/output select
Port 80 input/output selec
0
1
Generic input
—
0
1
Generic input
Generic output
453
P7DR—Port 7 Data Register
H'CE
Port 7
Bit
7
6
5
4
3
2
1
0
—
1*
R
—
1*
R
—
1*
R
—
1*
R
P73
—*
R
P72
—*
R
P71
—*
R
P70
—*
R
Initial value
Read/Write
Data for port 7 pins
Note: * Determined by pins P73 to P70.
P8DR—Port 8 Data Register
H'CF
Port 8
Bit
7
—
1
6
—
1
5
—
1
4
—
0
3
2
1
0
—
0
—
0
P81
0
P80
Initial value
Read/Write
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Data for port 8 pins
P9DDR—Port 9 Data Direction Register
H'D0
Port 9
Bit
7
—
1
6
—
1
5
—
0
4
3
—
0
2
1
—
0
0
P94DDR
P92DDR
P90DDR
Initial value
Read/Write
0
0
0
—
—
W
W
W
W
W
W
Port 9 input/output select
0
1
Generic input
Generic output
454
PADDR—Port A Data Direction Register
H'D1
Port A
Bit
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
Read/Write
Initial value
Read/Write
0
W
1
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
0
W
0
Modes
1, 2
Modes
3, 4
—
W
W
W
W
W
W
W
Port A input/output select
0
1
Generic input
Generic output
P9DR—Port 9 Data Register
H'D2
Port 9
Bit
7
—
1
6
5
4
3
—
2
1
0
—
1
—
0
P94
0
P92
0
—
0
P90
Initial value
Read/Write
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 9 pins
PADR—Port A Data Register
H'D3
Port A
Bit
7
6
5
4
3
2
1
0
PA7
0
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port A pins
455
PBDDR—Port B Data Direction Register
H'D4
Port B
Bit
7
—
0
6
—
0
5
—
0
4
—
0
3
2
1
0
PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
Read/Write
0
0
0
0
W
W
W
W
W
W
W
W
Port B input/output select
0
1
Generic input
Generic output
PBDR—Port B Data Register
H'D6
Port B
Bit
7
—
6
—
5
—
4
—
3
PB3
0
2
1
0
PB2
0
PB1
0
PB0
0
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port B pins
P4PCR—Port 4 Input Pull-Up Control Register
H'DA
Port 4
Bit
7
6
5
4
3
2
1
0
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 input pull-up control 7 to 0
0
1
Input pull-up transistor is off
Input pull-up transistor is on
Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
456
ADDRA H/L—A/D Data Register A H/L
H'E0, H'E1
A/D
Bit
15 14 13 12 11 10
9
8
7
6
5
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRAH
ADDRAL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRB H/L—A/D Data Register B H/L
H'E2, H'E3
A/D
Bit
15 14 13 12 11 10
9
8
7
6
5
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRBH
ADDRBL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRC H/L—A/D Data Register C H/L
H'E4, H'E5
A/D
Bit
15 14 13 12 11 10
9
8
7
6
5
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRCH
ADDRCL
A/D conversion data
10-bit data giving an
A/D conversion result
457
ADDRD H/L—A/D Data Register D H/L
H'E6, H'E7
A/D
Bit
15 14 13 12 11 10
9
8
7
6
5
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRDH
ADDRDL
A/D conversion data
10-bit data giving an
A/D conversion result
ADCR—A/D Control Register
H'E9
A/D
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
Trigger enable
0
1
A/D conversion cannot be externally triggered
Illegal setting
458
ADCSR—A/D Control/Status Register
H'E8
A/D
Bit
7
ADF
0
6
ADIE
0
5
ADST
0
4
SCAN
0
3
2
1
0
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select
0
1
Conversion time = 266 states (maximum)
Conversion time = 134 states (maximum)
Channel select 2 to 0
Group
Selection
Channel
Selection
Description
CH2
0
CH1
0
CH0 Single Mode Scan Mode
0
1
AN0
AN0
Scan mode
AN1
AN0, AN1
AN0 to AN2
AN0 to AN3
0
1
Single mode
Scan mode
1
0
AN2
1
AN3
1
—
—
Illegal setting
A/D start
0
1
A/D conversion is stopped
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a
transition to standby mode
A/D interrupt enable
0
1
A/D end interrupt request is disabled
A/D end interrupt request is enabled
A/D end flag
0
[Clearing condition]
Read ADF while ADF = 1, then write 0 in ADF
[Setting conditions]
1
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
Note: * Only 0 can be written, to clear flag.
459
ABWCR—Bus Width Control Register
H'EC
Bus controller
Bit
7
ABW7
1
6
ABW6
1
5
ABW5
1
4
ABW4
1
3
2
ABW2
1
1
ABW1
1
0
ABW0
1
ABW3
Mode 1, 3
Mode 2, 4
1
0
Initial
value
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 bus width control
Bits 7 to 0
ABW7 to ABW0
Bus Width of Access Area
0
1
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
ASTCR—Access State Control Register
H'ED
Bus controller
Bit
7
AST7
1
6
AST6
1
5
AST5
1
4
AST4
1
3
AST3
1
2
AST2
1
1
0
AST1
1
AST0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 access state control
Bits 7 to 0
AST7 to AST0
Number of States in Access Cycle
0
1
Areas 7 to 0 are two-state access areas
Areas 7 to 0 are three-state access areas
460
WCR—Wait Control Register
H'EE
Bus controller
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
WC1
1
0
WC0
1
WMS1 WMS0
Initial value
Read/Write
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Wait mode select 1 and 0
Bit 3 Bit 2
Wait count 1 and 0
Bit 1 Bit 0
WMS1 WMS0 Wait Mode
WC1 WC0 Number of Wait States
0
0
1
Programmable wait mode
0
0
No wait states inserted by
wait-state controller
No wait states inserted by
wait-state controller
1
0
1
1 state inserted
2 states inserted
3 states inserted
1
0
1
Pin wait mode 1
1
Pin auto-wait mode
WCER—Wait Controller Enable Register
H'EF
Bus controller
Bit
7
WCE7
1
6
5
4
3
2
WCE2
1
1
0
WCE6 WCE5
WCE4 WCE3
WCE1 WCE0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wait state controller enable 7 to 0
0
1
Wait-state control is disabled (pin wait mode 0)
Wait-state control is enabled
461
MDCR—Mode Control Register
H'F1
System control
Bit
7
—
1
6
—
1
5
—
0
4
—
0
3
—
0
2
MDS2
—*
1
0
MDS0
—*
MDS1
—*
Initial value
Read/Write
—
—
—
—
—
R
R
R
Mode select 2 to 0
Bit 2 Bit 1 Bit 0
MD2 MD1 MD0 Operating mode
0
0
1
0
1
0
1
0
1
0
1
0
1
—
Mode 1
Mode 2
Mode 3
Mode 4
—
1
—
—
Note: * Determined by the state of the mode pins (MD2 to MD0).
462
SYSCR—System Control Register
H'F2
System control
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
UE
1
2
NMIEG
0
1
0
—
1
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
0
1
On-chip RAM is disabled
On-chip RAM is enabled
NMI edge select
0
1
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
User bit enable
0
1
CCR bit 6 (UI) is used as an interrupt mask bit
CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Standby Timer
0
0
1
0
1
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Illegal setting
0
1
1
0
1
—
—
Software standby
0
1
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
463
BRCR—Bus Release Control Register
H'F3
Bus controller
Bit
7
6
—
5
—
4
3
2
1
0
BRLE
0
—
—
1
—
1
—
1
—
1
Initial value
1
—
1
1
Modes 1, 2
—
—
—
—
—
—
—
—
—
—
R/W
R/W
Read/
Write
Modes 3, 4 R/W
R/W
R/W
Bus release enable
0
1
The bus cannot be released to an external device
The bus can be released to an external device
ISCR—IRQ Sense Control Register
H'F4 Interrupt controller
Bit
7
—
6
—
5
4
IRQ4SC
0
3
—
2
—
1
0
—
0
IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ4, IRQ1, IRQ0 sense control
0
1
Interrupts are requested when IRQ4, IRQ1, IRQ0 inputs are low
Interrupts are requested by falling-edge input at IRQ4, IRQ1, IRQ0
464
IER—IRQ Enable Register
H'F5 Interrupt controller
Bit
7
—
6
—
5
—
4
IRQ4E
0
3
—
2
—
1
0
IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
0
0
0
0
R/(W)
R/(W)
R/(W)
R/W
R/W
R/W
R/W
R/W
IRQ4, IRQ1, IRQ0 enable
0
1
IRQ4, IRQ1, IRQ0 interrupts are disabled
IRQ4, IRQ1, IRQ0 interrupts are enabled
ISR—IRQ Status Register
H'F6 Interrupt controller
Bit
7
—
0
6
5
4
3
—
0
2
—
0
1
0
—
0
—
0
IRQ4F
0
IRQ1F IRQ0F
Initial value
Read/Write
0
0
—
—
—
R/(W)*
—
—
R/(W)* R/(W)*
IRQ4, IRQ1, IRQ0 flags
Bit n
IRQnF
0
Setting and Clearing Conditions
[Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
(n = 4, 1, 0)
Note: * Only 0 can be written, to clear the flag.
465
IPRA—Interrupt Priority Register A
H'F8 Interrupt controller
Bit
7
IPRA7
0
6
IPRA6
0
5
—
4
IPRA4
0
3
—
2
IPRA2
0
1
0
IPRA1 IPRA0
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority level A7, A6, A4, A2, A1, A0
0
1
Priority level 0 (low priority)
Priority level 1 (high priority)
•
Interrupt sources controlled by each bit
Bit 7
IPRA7 IPRA6
Bit 6
Bit 5
—
Bit 4
IPRA4
Bit 3
—
Bit 2
Bit 1
Bit 0
IPRA2 IPRA1 IPRA0
Interrupt IRQ0 IRQ1
source
—
IRQ4
—
ITU
chan-
nel 0
ITU
chan-
nel 1
ITU
chan-
nel 2
IPRB—Interrupt Priority Register B
H'F9 Interrupt controller
Bit
7
IPRB7
0
6
IPRB6
0
5
—
0
4
—
3
2
—
1
IPRB1
0
0
—
IPRB3
0
Initial value
Read/Write
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority level B7, B6, B3, B1
0
1
Priority level 0 (low priority)
Priority level 1 (high priority)
•
Interrupt sources controlled by each bit
Bit 7
IPRB7 IPRB6
Bit 6
Bit 5
—
Bit 4
—
Bit 3
IPRB3
Bit 2
—
Bit 1
IPRB1
Bit 0
—
Interrupt ITU
ITU
—
—
SCI
—
A/D
—
source
chan-
nel 3
chan-
nel 4
con-
verter
466
Appendix C I/O Port Block Diagrams
C.1 Port 4 Block Diagram
Reset
R
Q
Q
Q
D
P4nPCR
C
RP4P
WP4P
Reset
R
D
Write to external
address
P4nDDR
C
WP4D
Reset
R
D
P4n
P4n DR
C
WP4
RP4
Read external
address
WP4P: Write to P4PCR
RP4P: Read P4PCR
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
n = 0 to 7
Figure C-1 Port 4 Block Diagram
467
C.2 Port 6 Block Diagrams
Reset
R
Q
D
P60 DDR
C
Bus controller
WP6D
Reset
R
Wait input
enable
P60
Q
D
P60DR
C
WP6
RP6
Bus controller
WAIT
input
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C-2 (a) Port 6 Block Diagram (Pin P6 )
0
468
Reset
R
Bus
controller
Q
Q
D
P61DDR
C
WP6D
Reset
Bus release
enable
R
P61
D
P61DR
C
WP6
RP6
BREQ input
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C-2 (b) Port 6 Block Diagram (Pin P6 )
1
469
Reset
R
Q
Q
D
P62DDR
C
WP6D
Reset
R
D
P62
P62DR
C
Bus controller
WP6
Bus release
enable
BACK
output
RP6
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C-2 (c) Port 6 Block Diagram (Pin P6 )
2
470
C.3 Port 7 Block Diagram
RP7
P7
n
A/D converter module
Analog input
Input enable
RP7: Read port 7
n = 0 to 3
Figure C-3 Port 7 Block Diagram (Pin P7 )
n
471
C.4 Port 8 Block Diagrams
Reset
R
Q
Q
D
P80DDR
C
WP8D
Reset
R
P80
D
P80DR
C
WP8
RP8
Interrupt
controller
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
IRQ0
input
Figure C-4 (a) Port 8 Block Diagram (Pin P8 )
0
472
Reset
R
Q
Q
D
P81DDR
C
WP8D
Reset
P81
R
D
P81DR
C
WP8
RP8
Interrupt
controller
IRQ1 input
WP8D Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Figure C-4 (b) Port 8 Block Diagram (Pin P8 )
1
473
C.5 Port 9 Block Diagrams
Reset
R
Q
Q
D
P90DDR
C
WP9D
Reset
R
D
P90
P90 DR
C
SCI
WP9
Output
enable
Serial
transmit
data
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C-5 (a) Port 9 Block Diagram (Pin P9 )
0
474
Reset
R
Q
Q
D
P92DDR
C
SCI
WP9D
Reset
Input enable
R
P92
D
P92 DR
C
WP9
RP9
Serial receive
data
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C-5 (b) Port 9 Block Diagram (Pin P9 )
2
475
Reset
R
Q
Q
D
P94DDR
C
SCI module
WP9D
Reset
Clock input
enable
R
D
P94
P94 DR
C
WP9
Clock output
enable
Clock output
RP9
Clock input
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Interrupt
controller
IRQ4 input
Figure C-5 (c) Port 9 Block Diagram (Pins P9 )
4
476
C.6 Port A Block Diagrams
Reset
R
Q
Q
D
PAnDDR
C
TPC
WPAD
Reset
TPC
output
enable
R
PAn
D
PAnDR
C
Next data
WPA
Output
trigger
ITU
RPA
Counter
clock input
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
n = 0 and 1
Figure C-6 (a) Port A Block Diagram (Pins PA , PA )
0
1
477
Reset
R
Q
Q
D
PAnDDR
C
TPC
WPAD
Reset
TPC
output
enable
R
D
PAn
PAnDR
C
Next
data
WPA
Output
trigger
ITU
Output
enable
Compare
match
output
RPA
Input
capture
Counter
clock
WPAD: Write to PADDR
input
WPA: Write to port A
RPA: Read port A
n = 2 and 3
Figure C-6 (b) Port A Block Diagram (Pins PA , PA )
2
3
478
Software standby
External bus released
Mode 3, 4
Reset
R
Q
Q
D
PAnDDR
C
TPC
TPC
output
enable
WPAD
Reset
R
PAn
D
Next
data
PAnDR
C
WPA
Output
trigger
ITU
Output
enable
Compare
match
output
RPA
Input
capture
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
n = 4 to 7
Figure C-6 (c) Port A Block Diagram (Pins PA to PA )
4
7
479
C.7 Port B Block Diagrams
Reset
R
Q
Q
D
PBnDDR
C
TPC
WPBD
Reset
TPC output
enable
R
D
PBn
PBnDR
C
Next data
WPB
Output trigger
ITU
Output enable
Compare
match output
RPB
Input
capture
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
n = 0 to 3
Figure C-7 Port B Block Diagram (Pins PB to PB )
0
3
480
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