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HMS1M32M8V-12 [HANBIT]

SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V; SRAM模块4Mbyte （ 1M ×32位） 3.3V
HMS1M32M8V-12
型号： HMS1M32M8V-12
厂家： HANBIT ELECTRONICS CO.,LTD    HANBIT ELECTRONICS CO.,LTD
描述：

SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V
SRAM模块4Mbyte （ 1M ×32位） 3.3V

静态存储器
文件： 总9页 (文件大小：193K)
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HANBit  
HMS1M32M8V  
H A N  
SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V  
B I T  
HMS1M32M8V, HMS1M32Z8V  
Part No.  
GENERAL DESCRIPTION  
The HMS1M32M8V is a high-speed static random access memory (SRAM) module containing 1,048,576 words  
organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 72-pin, double-  
sided, FR4-printed circuit board.  
PD0 to PD3 identify the module’s density allowing interchangeable use of alternate density, industry- standard  
modules. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes  
independently. Output enable (/OE) and write enable(/WE) can set the memory input and output.  
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.  
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.  
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be  
powered from a single +3.3V DC power supply and all inputs and outputs are fully LVTTL-compatible.  
PIN ASSIGNMENT  
FEATURES  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
/ CE4  
/ CE3  
A17  
A16  
/ OE  
Vss  
DQ24  
DQ16  
DQ25  
DQ17  
DQ26  
DQ18  
DQ27  
DQ19  
A3  
A10  
A4  
A11  
A5  
A12  
Vcc  
A13  
A6  
DQ20  
DQ28  
DQ21  
DQ29  
DQ22  
DQ30  
DQ23  
DQ31  
Vss  
A18  
A19  
NC  
NC  
1
2
3
4
5
6
7
8
NC  
NC  
PD2  
PD3  
Vss  
PD0  
PD1  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
Vcc  
Part identification  
- HMS1M32M8V : SIMM design  
- HMS1M32Z8V : ZIP design  
→ Pin-Compatible with the HMS1M32M8V  
Fast access times : 10, 12ns and 15ns  
High-density 4MByte design  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
High-reliability high-speed design  
Single + 3.3V ±0.3V power supply  
Easy memory expansion /CE and /OE functions  
All inputs and outputs are LVTTL-compatible  
Industry-standard pinout  
A0  
A7  
A1  
A8  
A2  
A9  
DQ12  
DQ4  
DQ13  
DQ5  
DQ14  
DQ6  
DQ15  
DQ7  
Vss  
/ WE  
A15  
A14  
/ CE2  
/ CE1  
FR4-PCB design  
Low power Dissipation  
OPTIONS  
Timing  
MARKING  
10ns access  
12ns access  
15ns access  
-10  
-12  
-15  
PD0 = Vss  
PD1 = Open  
PD2 = Vss  
PD3 = Open  
SIMM  
TOP VIEW  
Packages  
72-pin SIMM  
M
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
FUNCTIONAL BLOCK DIAGRAM  
32  
DQ0 - DQ31  
20  
A0 - A19  
A0-19  
A0-19  
DQ 0-3  
DQ 4-7  
/WE  
/OE  
/WE  
/OE  
U1  
U5  
/CE  
/CE  
/CE1  
A0-19  
A0-19  
DQ 8-11  
DQ12-15  
/WE  
/OE  
/WE  
/OE  
U2  
U6  
/CE  
/CE  
/CE2  
A0-19  
A0-19  
DQ16-19  
DQ20-23  
/WE  
/OE  
/WE  
/OE  
U3  
U7  
/CE  
/CE  
/CE3  
A0-19  
A0-19  
DQ24-27  
DQ28-31  
/WE  
/OE  
/WE  
/OE  
/WE  
/OE  
U4  
U8  
/CE  
/CE  
/CE4  
MODE  
/OE  
X
/CE  
H
/WE  
X
OUTPUT  
HIGH-Z  
HIGH-Z  
Dout  
POWER  
STANDBY  
STANDBY  
ACTIVE  
ACTIVE  
ACTIVE  
NOT SELECTED  
READ  
H
L
H
L
L
H
WRITE  
X
L
L
Din  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Voltage on Any Pin Relative to Vss  
Voltage on Vcc Supply Relative to Vss  
Power Dissipation  
SYMBOL  
VIN,OUT  
VCC  
RATING  
-0.5V to +4.6V  
-0.5V to +4.6V  
8W  
PD  
o
o
Storage Temperature  
TSTG  
-65 C to +150 C  
o
o
Operating Temperature  
TA  
0 C to +70 C  
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated  
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
o
RECOMMENDED DC OPERATING CONDITIONS  
( T =0 to 70 C )  
A
PARAMETER  
Supply Voltage  
SYMBOL  
VCC  
MIN  
3.0V  
0
TYP.  
MAX  
3.6V  
3.3V  
Ground  
VSS  
0
-
0
Input High Voltage  
Input Low Voltage  
VIH  
2.0  
Vcc+0.3V**  
0.8V  
VIL  
-0.3*  
-
*
V (Min.) = -2.0V (Pulse Width 10ns) for I 20 mA  
≤ ≤  
IL  
V (Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA  
**  
≤
≤
IH  
o
o
DC AND OPERATING CHARACTERISTICS (1)(0 C  
T
70 C ; Vcc = 3.3V 0.3V )  
≤
≤
±
A
SYMBO  
L
PARAMETER  
TEST CONDITIONS  
VIN = Vss to Vcc  
MIN  
MAX  
UNITS  
Input Leakage Current  
ILI  
-2  
2
A
µ
/CE=VIH or /OE =VIH or /WE=VIL  
VOUT=Vss to VCC  
Output Leakage Current  
IL0  
-2  
2
A
µ
Output High Voltage  
Output Low Voltage  
IOH = -4.0Ma  
VOH  
VOL  
2.4  
V
IOL = 8.0mA  
0.4  
V
o
* Vcc=3.3V, Temp=25 C  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
DC AND OPERATING CHARACTERISTICS (2)  
MAX  
DESCRIPTION  
TEST CONDITIONS  
Min. Cycle, 100% Duty  
/CE=VIL, VIN=VIH or VIL,  
IOUT=0mA  
SYMBOL  
-12  
150  
-15  
-20  
UNIT  
Power Supply  
Current:Operating  
lCC  
145  
140  
mA  
Min. Cycle, /CE=VIH  
lSB  
70  
20  
70  
20  
70  
20  
mA  
mA  
Power Supply  
Current:Standby  
f=0MHZ, /CE V -0.2V,  
≥
CC  
lSB1  
VIN V -0.2V or V 0.2V  
≥
≤
CC  
IN  
CAPACITANCE  
DESCRIPTION  
TEST CONDITIONS  
VI/O=0V  
SYMBOL  
MAX  
UNIT  
Input /Output Capacitance  
Input Capacitance  
CI/O  
CIN  
8
7
pF  
pF  
VIN=0V  
*
: Capacitance is sampled and not 100% tested  
NOTE  
o
o
AC CHARACTERISTICS (0 C  
T
70 C ; Vcc = 3.3V 0.3V, unless otherwise specified)  
≤
≤
±
A
TEST CONDITIONS  
PARAMETER  
Input Pulse Level  
VALUE  
0 to 3V  
3ns  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
1.5V  
See below  
Output Load (B)  
Output Load (A)  
VL=1.5V  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+3.3V  
50  
Ω
319  
Ω
DOUT  
DOUT  
Z0=50  
Ω
353  
Ω
30pF  
5pF*  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
READ CYCLE  
-12  
-15  
-20  
PARAMETER  
SYMBOL  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Read Cycle Time  
tRC  
tAA  
tCO  
tOE  
tOLZ  
tLZ  
12  
15  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
12  
12  
6
15  
15  
7
20  
20  
9
Chip Select to Output  
Output Enable to Output  
Output Enable to Low-Z Output  
Chip Enable to Low-Z Output  
Output Disable to High-Z Output  
Chip Disable to High-Z Output  
Output Hold from Address Change  
Chip Select to Power Up Time  
Chip Select to Power Down Time  
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
tOHZ  
tHZ  
tOH  
tPU  
6
6
7
7
9
9
tPD  
12  
15  
20  
WRITE CYCLE  
-12  
-15  
-20  
PARAMETER  
SYMBOL  
UNIT  
MIN  
12  
8
MAX  
MIN  
15  
10  
0
MAX  
MIN  
20  
12  
0
MAX  
Write Cycle Time  
tWC  
tCW  
tAS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Select to End of Write  
Address Set-up Time  
0
Address Valid to End of Write  
Write Pulse Width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
8
10  
10  
0
12  
12  
0
8
Write Recovery Time  
0
Write to Output High-Z  
Data to Write Time Overlap  
Data Hold from Write Time  
End of Write to Output Low-Z  
0
6
0
7
0
9
6
7
9
0
0
0
tOW  
3
3
3
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
TIMING DIAGRAMS  
( Address Controlled)( /CE =/OE = V , /WE = V )  
TIMING WAVEFORM OF READ CYCLE  
IL  
IH  
tRC  
Address  
tAA  
tOH  
Data out  
Previous Data Valid  
Data Valid  
( /WE = V  
)
TIMING WAVEFORM OF READ CYCLE  
IH  
tRC  
Address  
tHZ(3,4,5)  
tAA  
tCO  
/CE  
/OE  
tLZ(4,5)  
tOHZ  
tOE  
tOH  
tOLZ  
High-Z  
Data Out  
Data Valid  
tPD  
tPU  
50%  
lCC  
lSB  
Vcc Supply  
Current  
50%  
(Read Cycle)  
Notes  
1. /WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH  
or VOL levels.  
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device  
to device.  
5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100%  
±
tested.  
6. Device is continuously selected with /CE = VIL.  
7. Address valid prior to coincident with /CE transition low.  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
(/OE = Clock )  
TIMING WAVEFORM OF WRITE CYCLE  
tWC  
Address  
/OE  
tAW  
tWR(5)  
tCW(3)  
/CE  
tAS(4)  
tWP(2)  
/WE  
tDW  
tDH  
High-Z  
Data In  
Data Valid  
tOHZ  
tOW  
Data Out  
High-Z  
(/OE Low Fixed)  
TIMING WAVEFORM OF WRITE CYCLE  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
/CE  
tAS(4)  
tOH  
tWP(2)  
/WE  
tDW  
tDH  
High-Z  
Data In  
Data Valid  
tOW  
tWHZ(6,7)  
(10)  
(9)  
High-Z(8)  
Data Out  
(Write Cycle)  
Notes  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among  
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.  
tWP is measured from the beginning of write to the end of write.  
3. tCW is measured from the later of /CE going low to the end of write.  
4. tAS is measured from the address valid to the beginning of wirte.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.  
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
opposite phase of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and  
write cycle.  
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.  
9. DOUT is the read data of the new address.  
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output  
should not be applied.  
FUNCTIONAL DESCRIPTION  
/CE  
H
/WE  
X*  
H
/OE  
X
MODE  
Not Select  
Output Disable  
Read  
I/O PIN  
High-Z  
High-Z  
DOUT  
SUPPLY CURRENT  
l SB, l SB1  
lCC  
L
H
L
H
L
lCC  
L
L
X
Write  
DIN  
lCC  
Note: X means Don't Care  
PACKAGING DIMMENSIONS  
SIMM Design  
1 0 8 .2 0 m m  
3 .1 8 m m  
TYP(2 x)  
1 6 m m  
6 .3 5 m m  
7 2  
1
2 .0 3 m m  
1 .0 2 m m  
6 .3 5 m m  
1 .2 7 m m  
3 .3 4 m m  
9 5 .2 5 m m  
2 .5 4 m m  
MIN  
0 .2 5 m m MAX  
1 .2 9 m m  
Gold : 1 .0 4  
±0 .1 0 m m  
1 .2 7  
Sold er : 0 .9 1 4 ±0 .1 0 m m  
(Solder & Gold Plating Lead)  
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8V  
ORDERING INFORMATION  
1
2
3
4
5
6
7
8
H M S 1 M 3 2 M8 V-1 5  
15ns Access Time  
HANBit  
Component, 3.3V  
SIMM  
Memory  
Modules  
x32bit  
SRAM  
1M  
1. - Product Line Identifier  
HANBit ------------------------------------------------------- H  
2. - Memory Modules  
3. - SRAM  
4. - Depth : 1M  
5. - Width : x 32bit  
6. - Package Code  
SIMM ------------------------------------------------------- M  
ZIP  
------------------------------------------------------- Z  
7. - Number of Memory Components, 3.3V --------------V  
8. - Access time  
10 ----------------------------------------------------------- 10ns  
12 ----------------------------------------------------------- 12ns  
15 ----------------------------------------------------------- 15ns  
17 ----------------------------------------------------------- 17ns  
20 ----------------------------------------------------------- 20ns  
HANBit Electronics Co.,Ltd.  

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