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HMS1M32M8S-15 [HANBIT]

High-Speed SRAM MODULE 4Mbyte(1M x 32-Bit); 高速SRAM模块4Mbyte （ 1M ×32位）
HMS1M32M8S-15
型号： HMS1M32M8S-15
厂家： HANBIT ELECTRONICS CO.,LTD    HANBIT ELECTRONICS CO.,LTD
描述：

High-Speed SRAM MODULE 4Mbyte(1M x 32-Bit)
高速SRAM模块4Mbyte （ 1M ×32位）

静态存储器
文件： 总10页 (文件大小：191K)
中文：  中文翻译
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HANBit  
HMS1M32M8S  
H A N  
High-Speed SRAM MODULE 4Mbyte(1M x 32-Bit)  
B I T  
HMS1M32M8S, HMS1M32Z8S  
Part No.  
GENERAL DESCRIPTION  
The HMS1M32M8S is a high-speed static random access memory (SRAM) module containing 1,048,576 words  
organized in a x32-bit configuration. The module consists of eight 512K x 8 SRAMs mounted on a 72-pin, double-  
sided, FR4-printed circuit board.  
The HMS1M32M8S also support low data retention voltage for battery back-up operations with low data retention  
current. Eight chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1, /CE_LL1, /CE_UU2, /CE_UM2, /CE_LM2,  
/CE_LL2) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable(/WE) can  
set the memory input and output.  
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.  
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.  
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be  
powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible  
PIN ASSIGNMENT  
FEATURES  
Part identification  
A18  
A16  
Vss  
A6  
Vcc  
A5  
A4  
Vcc  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
Vss  
A3  
A2  
A1  
A0  
Vcc  
A11  
/ OE  
A10  
1
2
3
4
5
6
7
8
9
- HMS1M32M8S : SIMM design  
- HMS1M32Z8S : ZIP design  
Pin-Compatible with the HMS1M32M8S  
Access times : 10, 12, 15, 17 and 20ns  
High-density 4MByte design  
High-reliability, high-speed design  
Single + 5V ±0.5V power supply  
All inputs and outputs are TTL-compatible  
FR4-PCB design  
/ CE_UM2  
/ CE_UM1  
DQ23  
DQ16  
DQ17  
DQ18  
DQ22  
DQ21  
DQ20  
DQ19  
Vcc  
Vcc 10  
/ CE_LL2 11  
/ CE_LL1 12  
DQ7 13  
DQ0 14  
DQ1 15  
DQ2 16  
DQ6 17  
DQ5 18  
DQ4 19  
DQ3 20  
A15 21  
A17 22  
/ WE 23  
A13 24  
Vcc 25  
DQ8 26  
DQ9 27  
A14  
A12  
A7  
Vcc  
A8  
A9  
72-Pin SIMM Design  
OPTIONS  
Timing  
MARKING  
DQ24  
DQ25  
DQ26  
/ CE_UU2  
/ CE_UU1  
DQ31  
DQ30  
DQ29  
DQ28  
DQ27  
Vss  
10ns access  
12ns access  
15ns access  
17ns access  
20ns access  
Packages  
-10  
-12  
-15  
-17  
-20  
DQ10 28  
/ CE_LM2 29  
Vcc 30  
/ CE_LM1 31  
DQ15 32  
DQ14 33  
DQ13 34  
DQ12 35  
DQ11 36  
SIMM  
TOP VIEW  
72-pin SIMM  
M
1
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
FUNCTIONAL BLOCK DIAGRAM  
DQ 32  
A20  
DQ 0-DQ31  
A0-A19  
A0-19  
A0-19  
DQ24-31  
DQ24-31  
U5  
/ WE  
/ OE  
/ WE  
U1  
/ OE  
/ CE  
/ CE  
/ CE-UU2  
/ CE-UU1  
A0-19  
A0-19  
DQ16-23  
DQ16-23  
/ WE  
/ OE  
/ WE  
U2  
U6  
/ OE  
/ CE  
/ CE  
/ CE-UM1  
/ CE-UM2  
A0-19  
A0-19  
DQ 8-15  
DQ 8-15  
/ WE  
/ OE  
/ WE  
U7  
U3  
/ OE  
/ CE  
/ CE  
/ CE-LM1  
/ CE-LM2  
A0-19  
DQ 0-7  
A0-19  
DQ 0-7  
/ WE  
/ OE  
/ WE  
/ OE  
/ WE  
/ WE  
/ OE  
U8  
U4  
/ OE  
/ CE  
/ CE  
/ CE-LL1  
/ CE-LL2  
TRUTH TABLE  
MODE  
/OE  
X
/CE  
H
/WE  
X
DQ  
HIGH-Z  
HIGH-Z  
Q
POWER  
STANDBY  
STANDBY  
ACTIVE  
ACTIVE  
ACTIVE  
NOT SELECTED  
READ  
H
L
H
L
L
H
WRITE or ERASE  
X
L
L
D
2
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
NOTE: X m ean s don ’t care  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Voltage on Any Pin Relative to Vss  
Voltage on Vcc Supply Relative to Vss  
Power Dissipation  
SYMBOL  
VIN,OUT  
VCC  
RATING  
-0.5V to +7.0V  
-0.5V to +7.0V  
8W  
PD  
o
o
Storage Temperature  
TSTG  
-55 C to +125 C  
o
o
Operating Temperature  
TA  
0 C to +70 C  
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated  
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
o
RECOMMENDED DC OPERATING CONDITIONS  
( T =0 to 70 C )  
A
PARAMETER  
Supply Voltage  
SYMBOL  
VCC  
MIN  
4.5V  
0
TYP.  
MAX  
5.5V  
5.0V  
Ground  
VSS  
0
-
0
Input High Voltage  
Input Low Voltage  
VIH  
2.2  
Vcc+0.5V**  
0.8V  
VIL  
-0.5*  
-
*
V (Min.) = -2.0V (Pulse Width 10ns) for I 20 mA  
≤ ≤  
IL  
V (Max.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA  
**  
≤
≤
IH  
DC AND OPERATING CHARACTERISTICS (1)  
o
o
(0 C  
T
70 C ; Vcc = 5V 0.5V )  
≤ ±  
≤
A
SYMBO  
L
PARAMETER  
TEST CONDITIONS  
VIN = Vss to Vcc  
MIN  
MAX  
UNITS  
Input Leakage Current  
Output Leakage Current  
ILI  
-2  
2
A
µ
/CE=VIH or /OE =VIH or /WE=VIL  
VOUT=Vss to VCC  
IL0  
-2  
2
A
µ
Output High Voltage  
Output Low Voltage  
IOH = -4.0mA  
VOH  
VOL  
2.4  
-
V
IOL = 8.0mA  
0.4  
V
o
* Vcc=5.0V, Temp=25 C  
3
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
DC AND OPERATING CHARACTERISTICS (2)  
MAX  
-17  
DESCRIPTION  
TEST CONDITIONS  
Min. Cycle, 100% Duty  
/CE=VIL, VIN=VIH or VIL,  
IOUT=0mA  
SYMBOL  
-15  
-20  
UNIT  
Power Supply  
Current: Operating  
lCC  
170  
165  
160  
mA  
Min. Cycle, /CE=VIH  
lSB  
50  
10  
50  
10  
50  
10  
mA  
mA  
Power Supply  
Current: Standby  
f=0MHZ, /CE V -0.2V,  
≥
CC  
lSB1  
VIN V -0.2V or V 0.2V  
≥
≤
CC  
IN  
CAPACITANCE  
DESCRIPTION  
TEST CONDITIONS  
VI/O=0V  
SYMBOL  
MAX  
UNIT  
Input /Output Capacitance  
Input Capacitance  
CI/O  
CIN  
8
7
pF  
pF  
VIN=0V  
*
: Capacitance is sampled and not 100% tested  
NOTE  
o
o
AC CHARACTERISTICS (0 C  
TEST CONDITIONS  
T
70 C ; Vcc = 5V 0.5V, unless otherwise specified)  
≤
≤
±
A
PARAMETER  
VALUE  
0.V to 3V  
3ns  
Input Pulse Level  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
1.5V  
See below  
Output  
Load  
Output Load (B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+5V  
+5V  
480  
Ω
480  
Ω
DOUT  
DOUT  
255  
Ω
30pF*  
255  
Ω
5pF*  
* Including scope and jig capacitance  
4
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
READ CYCLE  
-15  
-17  
-20  
PARAMETER  
SYMBOL  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Read Cycle Time  
tRC  
tAA  
tCO  
tOE  
tOLZ  
tLZ  
15  
-
-
15  
15  
7
17  
-
-
17  
17  
8
20  
-
-
20  
20  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
-
-
-
Output Enable to Output  
-
-
-
Output Enable to Low-Z Output  
Chip Enable to Low-Z Output  
Output Disable to High-Z Output  
Chip Disable to High-Z Output  
Output Hold from Address Change  
Chip Select to Power Up Time  
Chip Select to Power Down Time  
0
3
0
0
3
0
-
-
0
3
0
0
3
0
-
-
0
3
0
0
3
0
-
-
-
-
-
tOHZ  
tHZ  
tOH  
tPU  
7
8
9
7
8
9
-
-
-
-
-
-
tPD  
15  
17  
20  
WRITE CYCLE  
-15  
-17  
-20  
PARAMETER  
SYMBOL  
UNIT  
MIN  
15  
12  
0
MAX  
MIN  
17  
13  
0
MAX  
MIN  
20  
14  
0
MAX  
Write Cycle Time  
tWC  
tCW  
tAS  
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
-
9
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Select to End of Write  
Address Set-up Time  
Address Valid to End of Write  
Write Pulse Width (/OE=High)  
Write Recovery Time (/OE=Low)  
Write to Output High-Z  
tAW  
tWP  
tWR  
tWZ  
tDW  
tDH  
tOW  
12  
12  
0
13  
13  
0
14  
14  
0
0
0
0
Data to Write Time Overlap  
Data Hold from Write Time  
End of Write to Output Low-Z  
8
9
10  
0
0
0
3
3
3
5
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
TIMING DIAGRAMS  
(Address Controlled) ( /CE = /OE = V , /WE = V )  
TIMING WAVEFORM OF READ CYCLE  
IL  
IH  
tRC  
Address  
tAA  
tOH  
Data out  
Previous Data Valid  
Data Valid  
(/WE = V )  
TIMING WAVEFORM OF READ CYCLE  
IH  
tRC  
Address  
tHZ(3,4)  
tAA  
tCO  
/CE  
tLZ(4)  
tOHZ  
tOE  
/OE  
tOH  
tOLZ  
High-Z  
Data Out  
Data Valid  
(Read Cycle)  
Notes  
1. /WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH  
or VOL levels.  
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device  
to device.  
6
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
( /WE Controlled )  
TIMING WAVEFORM OF WRITE CYCLE  
tWC  
Address  
/OE  
tAW  
tWR(5)  
tCW(3)  
/CE  
tAS(4)  
tWP(2)  
/WE  
tDW  
tDH  
High-Z  
Data In  
Data Valid  
tOHZ  
Data Out  
High-Z  
( /OE Low Fixed )  
TIMING WAVEFORM OF WRITE CYCLE  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
/CE  
tAS(4)  
tOH  
tWP(2)  
/WE  
tDW  
tDH  
High-Z  
Data In  
Data Valid  
tWHZ(6,7)  
tOW  
(10)  
(9)  
High-Z(8)  
Data Out  
( Write Cycle)  
Notes  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among  
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.  
tWP is measured from the beginning of write to the end of write.  
3. tCW is measured from the later of /CE going low to the end of write.  
7
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.  
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of  
opposite phase of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and  
write cycle.  
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.  
9. DOUT is the read data of the new address.  
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output  
should not be applied.  
FUNCTIONAL DESCRIPTION  
/CE  
H
/WE  
X*  
H
/OE  
X
MODE  
Not Select  
Output Disable  
Read  
I/O PIN  
High-Z  
High-Z  
DOUT  
SUPPLY CURRENT  
I SB, I SB1  
ICC  
L
H
L
H
L
ICC  
L
L
X
Write  
DIN  
ICC  
Note: X means Don't Care  
8
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
PACKAGING DIMMENSIONS  
SIMM Design  
1 0 8 .2 0 m m  
3 .1 8 m m  
TYP(2 x)  
1 6 m m  
6 .3 5 m m  
7 2  
1
2 .0 3 m m  
1 .0 2 m m  
6 .3 5 m m  
1 .2 7 m m  
3 .3 4 m m  
9 5 .2 5 m m  
2 .5 4 m m  
MIN  
0 .2 5 m m MAX  
1 .2 9 ±0 .0 8 m m  
Gold : 1 .0 4 ±0 .1 0 m m  
1 .2 7  
Sold er : 0 .9 1 4 ±0 .1 0 m m  
(Solder & Gold Plating Lead)  
9
HANBit Electronics Co.,Ltd.  
HANBit  
HMS1M32M8S  
ORDERING INFORMATION  
1
2
3
4
5
6
7
8
H M S 1 M 3 2 M8 S-1 5  
15ns Access Time  
HANBit  
Component, Customer  
SIMM  
Memory  
Modules  
x32bit  
SRAM  
1M  
1. - Product Line Identifier  
HANBit Technology --------------------------------------- H  
2. - Memory Modules  
3. - SRAM  
4. - Depth : 1M  
5. - Width : x 32bit  
6. - Package Code  
SIMM ------------------------------------------------------- M  
ZIP  
------------------------------------------------------- Z  
7. - Number of Memory Components---8, Customer-----S  
8. - Access time  
10 ----------------------------------------------------------- 10ns  
12 ----------------------------------------------------------- 12ns  
15 ----------------------------------------------------------- 15ns  
17 ----------------------------------------------------------- 17ns  
20 ----------------------------------------------------------- 20ns  
10  
HANBit Electronics Co.,Ltd.  

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