GS882Z36CGD-150T_技术文档

GS882Z18/36CB/D-xxx

333 MHz–150 MHz

9Mb Pipelined and Flow Through

119-bump and 165-bump BGA

Commercial Temp

2.5 V or 3.3 V V

DD

Synchronous NBT SRAM

2.5 V or 3.3 V I/O

Features

Functional Description

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

The GS882Z18/36C882Z18C is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA and 165-bump FPBGA

packages

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• RoHS-compliant 119-bump and 165-bump BGA packages

available

The GS882Z18/36C may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising edge triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge-triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

The GS882Z18/36C is implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 119-bump BGA and 165-bump FPBGA packages.

Parameter Synopsis

-333

-300

-250

-200

-150

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

ns

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

240

280

225

260

195

225

170

195

140

160

mA

t_KQ

4.5

5.0

5.5

6.5

7.5

ns

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

180

205

165

190

160

180

140

160

128

145

mA

Rev: 1.05 7/2012

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

GS882Z36C Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V

NC

V

DDQ

NC

E2

ADV

E3

NC

A

V

A

DD

DQC

DQPC

DQC

V

ZQ

E1

G

V

DQPB

DQB

SS

V

DDQ

G

H

J

DQC

BC

A

BB

DQB

DQC

V

W

V

DQB

SS

V

NC

V

NC

V

DDQ

DD

K

L

DQD

DQPD

A

V

CK

V

DQA

DQPA

A

DQA

SS

DQD

BD

NC

CKE

A1

BA

DQA

M

N

P

R

T

V

DDQ

SS

DQD

V

DQA

DQD

NC

A0

DQA

PE

LBO

A

V

FT

A

DD

NC

A

NC

ZZ

U

V

TMS

TDI

TCK

TDO

NC

V

DDQ

Rev: 1.05 7/2012

2/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

GS882Z18C Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V

NC

V

DDQ

NC

E2

ADV

E3

NC

A

V

A

DD

DQB

NC

DQB

NC

DQB

NC

V

ZQ

E1

G

V

DQPA

NC

DQA

NC

DQA

NC

SS

V

DQA

V

DDQ

G

H

J

NC

BB

A

NC

DQA

DQB

V

W

V

NC

SS

V

NC

V

NC

V

DDQ

DD

K

L

NC

DQB

NC

V

CK

V

NC

DQA

NC

DQA

NC

A

DQA

SS

DQB

NC

CKE

A1

BA

NC

M

N

P

R

T

V

DQB

NC

V

DDQ

SS

DQB

V

NC

DQPB

A

A0

DQA

PE

LBO

A

V

FT

A

DD

A

NC

A

ZZ

U

V

TMS

TDI

TCK

TDO

NC

V

DDQ

Rev: 1.05 7/2012

3/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

165 Bump BGA—x18 Commom I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

CKE

ADV

A17

A18

A

B

C

D

E

F

NC

A

E2

NC

BA

CK

W

G

NC

A

NC

DQA

ZZ

NC

V

NC

ZQ

DQA

NC

A

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCH

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

NC

V

NC

A

DDQ

K

L

NC

V

K

L

NC

M

N

P

R

NC

M

N

P

R

DNU

NC

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.05 7/2012

4/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

165 Bump BGA—x36 Common I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

CKE

ADV

A17

NC

A

B

C

D

E

F

NC

DQPC

DQC

FT

A

E2

BD

BA

CK

W

G

NC

A

NC

DQPB

DQB

ZZ

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCH

DQD

DNU

NC

V

DQB

ZQ

G

H

J

G

H

J

NC

DQD

DQPD

NC

V

DQA

NC

DQA

DQPA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.05 7/2012

5/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

GS882Z18/36C BGA Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

In

—

I

Byte Write signal for data inputs DQA; active low

Byte Write signal for data inputs DQB; active low

Byte Write signal for data inputs DQC; active low

Byte Write signal for data inputs DQD; active low

No Connect

BA

BB

BC

BD

NC

Clock Input Signal; active high

Clock Enable; active low

CK

I

CKE

W

I

Write Enable; active low

I

Chip Enable; active low

E1

I

Chip Enable; active low

E3

I

Chip Enable; active high

E2

I

Output Enable; active low

G

I

Burst address counter advance enable; active high

Byte A Data Input and Output pins

Byte B Data Input and Output pins

Byte C Data Input and Output pins

Byte D Data Input and Output pins

9th Data I/O Pin; Byte A

ADV

DQA

DQB

DQC

DQD

DQPA

DQPB

DQPC

DQPD

ZZ

I/O

I

9th Data I/O Pin; Byte B

9th Data I/O Pin; Byte C

9th Data I/O Pin; Byte D

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

I

FT

I

LBO

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I

ZQ

I

Scan Test Mode Select

Scan Test Data In

TMS

TDI

Rev: 1.05 7/2012

6/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

GS882Z18/36C BGA Pin Description

Symbol

TDO

Type

Description

Scan Test Data Out

Scan Test Clock

O

I

TCK

—

I

Must Connect High

Do Not Use

MCH

DNU

V

Core power supply

I/O and Core Ground

Output driver power supply

DD

V

I

SS

V

I

DDQ

Rev: 1.05 7/2012

7/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable

inputs will deactivate the device.

Function

Read

W

H

L

BA

X

BB

X

BC

X

BD

X

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write all Bytes

Write Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three

chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.

The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,

matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At

the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is

required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Rev: 1.05 7/2012

8/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Synchronous Truth Table

Operation

Read Cycle, Begin Burst

Read Cycle, Continue Burst

NOP/Read, Begin Burst

Dummy Read, Continue Burst

Write Cycle, Begin Burst

Write Abort, Begin Burst

Write Cycle, Continue Burst

Write Abort, Continue Burst

Deselect Cycle, Power Down

Deselect Cycle, Continue

Sleep Mode

Type

R

Address

External

W

H

X

H

X

L

Bx E1 E2 E3

G

L

ZZ

L

H

L

DQ

Q

Notes

L-H

X

L

X

H

L

H

L

X

L

X

L

H

X

H

X

H

X

L

X

L

B

L

Q

1,10

2

1,2,10

3

R

External

H

X

High-Z

D

B

H

L

X

L

X

L

W

D

External

None

1

L

H

L

High-Z

D

1,3,10

B

H

L

X

H

X

H

X

B

X

High-Z 1,2,3,10

High-Z

D

None

D

None

L

High-Z

D

None

L

High-Z

1

4

D

None

H

X

High-Z

-

None

Clock Edge Ignore, Stall

Current

L-H

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect

cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is

sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.05 7/2012

9/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read

New Write

R

W

B

R

W

R

Burst Read

Burst Write

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Rev: 1.05 7/2012

10/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Pipeline Mode Data I/O State Diagram

Intermediate

R

W

B

Intermediate

R

B

Data Out

(Q Valid)

High Z

(Data In)

W

D

Intermediate

D

Intermediate

W

R

High Z

B

D

Intermediate

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+2)

Intermediate State (N+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Intermediate

State

Current State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.05 7/2012

11/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Flow Through Mode Data I/O State Diagram

R

W

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

W

R

High Z

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.05 7/2012

12/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive

strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

Burst Order Control

LBO

H

L

H or NC

L or NC

H

Output Register Control

Power Down Control

FT

ZZ

ZQ

PE

Active

Standby, I = I

DD SB

L

High Drive (Low Impedance)

Low Drive (High Impedance)

FLXDrive Output Impedance Control

9th Bit Enable

H or NC

L or NC

H

Activate DQPx I/Os (x18/x3672 mode)

Deactivate DQPx I/Os (x16/x3272 mode)

Note:

There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ and PE pins, so those input pins can be unconnected and

the chip will operate in the default states as specified in the above tables.

Rev: 1.05 7/2012

13/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

00

10

11

10

11

10

00

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

ZZ

tZZR

tZZS

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal

found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V or V

on pipelined parts and V

DD

DDQ

SS

on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.

Rev: 1.05 7/2012

14/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

V_DD

Description

Value

Unit

V

Voltage on V_DDPins

Voltage in V_DDQPins

–0.5 to 4.6

V_DDQ

V_I/O1

V_I/O2

V_IN

V

–0.5 to V_DD+0.5 (≤ 4.6 V max.)

Voltage on I/O Pins

V

–0.5 to V_DDQ+0.5 (≤ 4.6 V max.)

–0.5 to V_DD+0.5 (≤ 4.6 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I_IN

+/–20

mA

W

I_OUT

P_D

1.5

^oC

T_STG

–55 to 125

T_BIAS

Temperature Under Bias

Notes:

1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-

mended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect

reliability of this component.

2. Both V

V

must be met.

I/O1 and I/O2

Power Supply Voltage Ranges

Parameter

3.3 V Supply Voltage

Symbol

V_DD3

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

V

V_DD2

2.5 V Supply Voltage

2.3

2.5

2.7

V

3.3 V V_DDQI/O Supply Voltage

V_DDQ3

V_DDQ2

V_DD

3.0

3.3

V

2.5 V V_DDQI/O Supply Voltage

2.3

2.5

V

Note:

V

must be less than or equal to V + 0.3 V at all times.

DD

DDQ

Rev: 1.05 7/2012

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GS882Z18/36CB/D-xxx

V

Range Logic Levels

DD3

Parameter

Symbol

V_IH

Min.

2.0

Typ.

—

Max.

Unit

V

V_DD+ 0.3

V_DDQ+ 0.3

Input High Voltage

Input High Voltage for Data I/O pins

Input Low Voltage

V_IH(I/O)1

V_IH(I/O)2

V_IL

2.0

—

V

2.0

—

V

–0.3

—

0.8

V

Notes:

1.

2.

3.

4.

V

(max) must be met for any instantaneous value of V .

DD

IH

(max) must be met for any instantaneous value of V

.

DD

IH(I/O)1

.

IH(I/O)2

DDQ

needs to power-up before or at the same time as V

to make sure V (max) is not exceeded.

IH

DD

DDQ

V

Range Logic Levels

DD2

Parameter

Symbol

V_IH

Min.

Typ.

—

Max.

Unit

V

0.6*V_DD

V

_DD+ 0.3

Input High Voltage

Input High Voltage for Data I/O pins

Input Low Voltage

V_IH(I/O)1

V_IH(I/O)2

V_IL

V_DD+ 0.3

—

V

_DDQ+ 0.3

0.3*V_DD

—

V

–0.3

—

V

Notes:

1.

2.

3.

4.

V

(max) must be met for any instantaneous value of V .

DD

IH

(max) must be met for any instantaneous value of V

.

DD

IH(I/O)1

.

IH(I/O)2

DDQ

needs to power-up before or at the same time as V

to make sure V (max) is not exceeded.

IH

DD

DDQ

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

T_A

Ambient Temperature (Commercial Range Versions)

0

25

70

°C

Note:

Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

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GS882Z18/36CB/D-xxx

Thermal Impedance

Test PCB

Substrate

θ JA (C°/W)

Airflow = 0 m/s

θ JA (C°/W)

Airflow = 1 m/s

θ JA (C°/W)

Airflow = 2 m/s

Package

θ JB (C°/W)

θ JC (C°/W)

119 BGA

165 BGA

4-layer

28.0

27.4

24.8

24.2

23.7

23.2

17.4

15.3

8.3

7.8

4-layer

Notes:

1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Note:

Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

Max.

Unit

pF

Input Capacitance

4

6

5

7

C_I/O

V_OUT= 0 V

Input/Output Capacitance

pF

Note:

These parameters are sample tested.

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GS882Z18/36CB/D-xxx

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

V_DD– 0.2 V

0.2 V

Input slew rate

1 V/ns

V_DD/2

Input reference level

V_DDQ/2

Output reference level

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I_IL

V_IN= 0 to V_DD

–1 uA

1 uA

V_DD≥ V_IN≥ V_IH

0 V ≤ V_IN≤ V_IH

–1 uA

1 uA

100 uA

I_IN1

ZZ Input Current

V_DD≥ V_IN≥ V_IL

0 V ≤ V_IN≤ V_IL

–100 uA

–1 uA

1 uA

I_IN2

FT, ZQ Input Current

I_OL

Output Disable, V_OUT= 0 to V_DD

I_OH= –8 mA, V_DDQ= 2.375 V

I_OH= –8 mA, V_DDQ= 3.135 V

I_OL= 8 mA

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

V_OH2

V_OH3

V_OL

—

0.4 V

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GS882Z18/36CB/D-xxx

Operating Currents

-333

0

-300

0

-250

0

-200

0

-150

0

Parameter

Test Conditions

Mode

Symbol

Unit

to 70°C to 70°C to 70°C to 70°C to 70°C

I_DD

240

40

225

35

195

30

170

25

140

20

Pipeline

mA

I_DDQ

(x32/x36)

(x18)

I_DD

180

25

165

25

155

25

140

20

130

15

Device Selected;

All other inputs

≥V_IHor ≤ V_IL

Flow Through

Pipeline

I_DDQ

Operating

Current

I_DD

220

20

205

20

180

15

155

15

130

10

Output open

I_DDQ

I_DD

165

15

150

15

145

15

130

10

120

8

Flow Through

I_DDQ

I_SB

I_DD

Pipeline

Flow Through

Pipeline

25

70

25

65

25

65

25

65

25

60

mA

Standby

Current

ZZ ≥ V_DD– 0.2 V

—

Device Deselected;

All other inputs

≥ V_IHor ≤ V_IL

Deselect

Current

I_DD

Flow Through

70

65

60

mA

Notes:

1.

I

and I

apply to any combination of V , V , V

, and V

operation.

DDQ2

DD

DDQ

DD3 DD2 DDQ3

2. All parameters listed are worst case scenario.

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GS882Z18/36CB/D-xxx

AC Electrical Characteristics

-333

-300

-250

-200

-150

Parameter

Symbol

Unit

Min

3.0

—

Max

—

2.5

—

4.5

—

Min

3.3

—

Max

—

2.5

—

5.0

—

Min

4.0

—

Max

—

2.5

—

5.5

—

Min

5.0

—

Max

—

3.0

—

6.5

—

Min

6.7

—

Max

—

3.8

—

7.5

—

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

tKC

tKQ

ns

tKQX

1.5

1.0

0.1

4.5

—

1.5

1.0

0.1

5.0

—

1.5

1.2

0.2

5.5

—

1.5

1.4

0.4

6.5

—

1.5

0.5

7.5

—

Pipeline

tLZ¹

tS

Clock to Output in Low-Z

Setup time

Hold time

tH

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

2.0

1.3

0.3

1.0

2.0

1.4

0.4

1.0

2.0

1.5

0.5

1.3

2.0

1.5

0.5

1.3

2.0

1.5

0.5

1.5

Flow

Through

tLZ¹

tS

Clock to Output in Low-Z

Setup time

Hold time

tH

Clock HIGH Time

tKH

Clock LOW Time

tKL

1.2

1.5

—

1.2

1.5

—

1.5

—

1.5

—

1.7

1.5

—

ns

Clock to Output in

High-Z

tHZ¹

tOE

2.5

3.0

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

—

0

2.5

—

2.5

—

0

2.5

—

2.5

—

0

2.5

—

2.5

—

0

3.0

—

3.0

—

0

3.8

—

3.0

—

ns

tOLZ¹

tOHZ¹

tZZS²

tZZH²

tZZR

—

5

—

5

—

5

—

5

—

5

ZZ hold time

1

ZZ recovery

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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GS882Z18/36CB/D-xxx

Pipeline Mode Timing (NBT)

Write A

Read B

Suspend

tKH

Read C

tKC

Write D

Write No-op Read E

Deselect

tKL

CK

A

tH

tS

A

B

C

D

E

tS

CKE

E*

ADV

W

tH

tS

Bn

tH

tLZ

tKQ

tHZ

tS

tKQX

D(A)

Q(B)

Q(C)

D(D)

Q(E)

DQ

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GS882Z18/36CB/D-xxx

Flow Through Mode Timing (NBT)

Write A

Write B

Write B+1 Read C

tKL

Cont

Read D

Write E

Read F

Write G

tKH

tKC

CK

CKE

E

tH

tS

ADV

W

Bn

A0–An

A

B

C

D

E

F

G

tKQ

tLZ

tH

tKQ

tLZ

D(B+1)

tKQX

tS

D(A)

tHZ

Q(D)

tKQX

D(G)

DQ

D(B)

Q(C)

D(E)

Q(F)

tOLZ

tOE

tOHZ

G

*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1

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GS882Z18/36CB/D-xxx

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

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GS882Z18/36CB/D-xxx

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

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GS882Z18/36CB/D-xxx

ID Register Contents

GSI Technology

JEDEC Vendor

ID Code

Not Used

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0 1 1 0 1 1 0 0 1

0

1

X

0

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

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GS882Z18/36CB/D-xxx

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

0

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

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GS882Z18/36CB/D-xxx

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

RFU

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

RFU

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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GS882Z18/36CB/D-xxx

JTAG Port Recommended Operating Conditions and DC Characteristics (2.5/3.3 V Version)

Parameter

Symbol

Min.

Max.

Unit Notes

V

0.6 * V

V

+0.3

DD2

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

IHJ2

DD2

V

–0.3

0.3 * V

DD2

ILJ2

V

+0.3

DD3

2.0

–0.3

–300

–1

V

1

IHJ3

V

0.8

V

1

ILJ3

I

1

100

1

uA

V

2

INHJ

I

3

INLJ

I

–1

4

OLJ

V

Test Port Output High Voltage

1.7

—

0.4

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

Test Port Output Low Voltage

—

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

Rev: 1.05 7/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

DQ

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

*

50Ω

30pF

Input slew rate

V

/2

DDQ

V

/2

Input reference level

DDQ

* Distributed Test Jig Capacitance

/2

Output reference level

DDQ

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

TMS

tTKQ

TDO

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

TCK Cycle Time

50

—

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

tTH

—

Rev: 1.05 7/2012

29/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

Package Dimensions—119-Bump FPBGA (Package B, Variation 3)

TOP VIEW

BOTTOM VIEW

A1

S

A1

Ø0.10

C

S

Ø0.30 C A

B

Ø0.60~0.90 (119x)

1

2

3

4

5

6

7

6

5

4 3

2

1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

M

N

P

K

L

M

N

P

R

T

U

R

T

U

B

1.27

7.62

14±0.10

A

0.20(4x)

SEATING PLANE

C

Rev: 1.05 7/2012

30/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.05 7/2012

31/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Ordering Information—GSI NBT Synchronous SRAM

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

512K x 18

256K x 36

512K x 18

256K x 36

512K x 18

256K x 36

GS882Z18CB-333

GS882Z18CB-300

GS882Z18CB-250

GS882Z18CB-200

GS882Z18CB-150

GS882Z36CB-333

GS882Z36CB-300

GS882Z36CB-250

GS882Z36CB-200

GS882Z36CB-150

GS882Z18CGB-333

GS882Z18CGB-300

GS882Z18CGB-250

GS882Z18CGB-200

GS882Z18CGB-150

GS882Z36CGB-333

GS882Z36CGB-300

GS882Z36CGB-250

GS882Z36CGB-200

GS882Z36CGB-150

GS882Z18CD-333

GS882Z18CD-300

GS882Z18CD-250

GS882Z18CD-200

GS882Z18CD-150

GS882Z36CD-333

GS882Z36CD-300

GS882Z36CD-250

GS882Z36CD-200

NBT Pipeline/Flow Through

119 BGA (var. 3)

333/4.5

300/5

C

119 BGA (var. 3)

250/5.5

200/6.5

150/7.5

333/4.5

300/5

119 BGA (var. 3)

250/5.5

200/6.5

150/7.5

333/4.5

300/5

119 BGA (var. 3)

RoHS-compliant 119 BGA (var. 3)

165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

150/7.5

333/4.5

300/5

165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

165 BGA

250/5.5

200/6.5

165 BGA

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36CB-150T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.05 7/2012

32/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

Ordering Information—GSI NBT Synchronous SRAM (Continued)

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

256K x 36

512K x 18

256K x 36

GS882Z36CD-150

GS882Z18CGD-333

GS882Z18CGD-300

GS882Z18CGD-250

GS882Z18CGD-200

GS882Z18CGD-150

GS882Z36CGD-333

GS882Z36CGD-300

GS882Z36CGD-250

GS882Z36CGD-200

GS882Z36CGD-150

NBT Pipeline/Flow Through

165 BGA

150/7.5

333/4.5

300/5

C

RoHS-compliant 165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

150/7.5

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36CB-150T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.05 7/2012

33/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36CB/D-xxx

9Mb Sync SRAM Datasheet Revision History

Types of Changes

File Name

Revision

Format or Content

• Creation of new datasheet

882Z18C_r1

• Updated 119-BGA package (var. 3)

• Update to MP datasheet

882Z18C_r1_01

882Z18C_r1_02

Content

• Updated Absolute Maximum Ratings

• Deleted conditional text

882Z18C_r1_03

882Z18C_r1_04

882Z18C_r1_05

Content

• Updated Absolute Maximum Ratings

• Added thermal information

• Updated Absolute Maximum Ratings

• Removed all Ind Temp references

Rev: 1.05 7/2012

34/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS882Z36CGD-150T
厂家：	GSI TECHNOLOGY
描述：	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 静态存储器内存集成电路
文件：	总34页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS882Z36CGD-150T [GSI]

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