GS882Z36BD-225IT_技术文档

GS882Z18/36BB/D-250/225/200/166/150/133

119 and 165 BGA

Commercial Temp

Industrial Temp

250 MHz–133 MHz

9Mb Pipelined and Flow Through

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

Synchronous NBT SRAM

Features

Functional Description

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

The GS882Z18/36B is a 9Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA and 165-bump FPBGA

packages

-250 -225 -200 -166 -150 -133 Unit

The GS882Z18/36B may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising edge triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge-triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

Pipeline

3-1-1-1

t

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

KQ

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x32/x36) 330 300 270 230 215 190 mA

3.3 V

2.5 V

Curr (x18) 275 250 230 195 180 165 mA

Curr (x32/x36) 320 295 265 225 210 185 mA

Flow

Through

2-1-1-1

t

5.5 6.0 6.5 7.0 7.5 8.5 ns

KQ

tCycle

The GS882Z18/36B is implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 119-bump BGA and 165-bump FPBGA packages.

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

3.3 V

2.5 V

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

A

R

B

C

R

D

E

R

F

Read/Write

W

Flow Through

Data I/O

Q

D

Q

D

Q

E

A

B

C

D

Pipelined

Data I/O

Q

D

Q

E

A

B

C

D

Rev: 1.00b 12/2002

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS882Z18/36BB/D-250/225/200/166/150/133

GS882Z36B Pad Out

119 Bump BGA—Top View (Package B)

1

2

3

4

5

6

7

A

B

C

D

E

F

V

A6

A7

A4

A3

NC

A8

A9

V

DDQ

NC

E2

ADV

A15

A14

E3

NC

A5

V

A16

DD

DQC4

DQC3

DQC9

DQC8

DQC7

DQC6

DQC5

V

ZQ

E1

G

V

DQB9

DQB8

DQB7

DQB6

DQB5

DQB4

DQB3

SS

V

DDQ

G

H

J

DQC2

DQC1

BC

A17

W

BB

DQB2

DQB1

V

SS

V

NC

V

NC

V

DDQ

DD

K

L

DQD1

DQD2

DQD5

DQD6

DQD7

DQD8

DQD9

A2

V

CK

NC

CKE

A1

V

DQA5

DQA6

DQA7

DQA8

DQA9

A13

DQA1

DQA2

SS

BD

BA

M

N

P

R

T

V

DDQ

SS

DQD3

DQD4

NC

V

DQA3

DQA4

PE

A0

LBO

A10

V

FT

DD

NC

A11

A12

NC

ZZ

U

V

TMS

TDI

TCK

TDO

NC

V

DDQ

Rev: 1.00b 12/2002

2/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

GS882Z18B Pad Out

119 Bump BGA—Top View (Package B)

1

2

3

4

5

6

7

A

B

C

D

E

F

V

A6

A7

A4

A3

NC

A8

A9

V

DDQ

NC

E2

ADV

A15

A14

E3

NC

A5

V

A16

DD

DQB1

NC

V

ZQ

E1

G

V

DQA9

NC

SS

DQB2

NC

V

DQA8

V

DQA7

NC

V

DDQ

G

H

J

NC

DQB3

NC

BB

A17

W

NC

DQA6

NC

DQB4

V

DQA5

SS

V

NC

V

NC

V

DDQ

DD

K

L

NC

DQB5

NC

V

CK

NC

CKE

A1

V

NC

DQA3

NC

DQA4

NC

SS

DQB6

NC

BA

M

N

P

R

T

V

DQB7

NC

V

DDQ

SS

DQB8

NC

V

DQA2

NC

DQA1

PE

DQB9

A2

A0

NC

LBO

A11

V

FT

A13

DD

NC

A10

NC

A12

A18

ZZ

U

V

TMS

TDI

TCK

TDO

NC

V

DDQ

Rev: 1.00b 12/2002

3/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

165 Bump BGA—x18 Commom I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

CKE

ADV

A17

A18

A

B

C

D

E

F

NC

A

E2

NC

BA

CK

W

G

NC

A

NC

ZQ

NC

DQA

ZZ

NC

V

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCH

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

NC

V

DQA

NC

A

NC

DDQ

K

L

NC

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

DNU

NC

V

NC

TDI

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

A

TDO

TCK

A

NC

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

165 Bump BGA—x36 Common I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

CKE

ADV

A17

NC

A

B

C

D

E

F

NC

A

E2

BD

BA

CK

W

G

NC

A

NC

DQB

ZZ

DQC

FT

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCH

DQD

DNU

NC

V

DQB

ZQ

G

H

J

G

H

J

NC

DQD

NC

V

DQA

NC

DQA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

GS882Z18/36B BGA Pin Description

Symbol

A⁰, A¹

An

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

A^17,A¹⁸

DQ^A1–DQ^A9

DQ^B1–DQ^B9

DQ^C1–DQ^C9

DQ^D1–DQ^D9

I/O

Data Input and Output pins

B^A, B^B, B^C, B^D

I

—

I

Byte Write Enable for DQ^A, DQ^B, DQ^C, DQ^DI/Os; active low

No Connect

NC

CK

CKE

W

Clock Input Signal; active high

Clock Enable; active low

I

Write Enable; active low

E¹

I

Chip Enable; active low

E³

I

Chip Enable; active low

E²

I

Chip Enable; active high

G

I

Output Enable; active low

ADV

ZZ

I

Burst address counter advance enable; active high

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

I

FT

I

LBO

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

ZQ

I

Scan Test Mode Select

Scan Test Data In

TMS

TDI

O

I

Scan Test Data Out

Scan Test Clock

TDO

TCK

MCH

DNU

—

I

Must Connect High

Do Not Use

V

Core power supply

I/O and Core Ground

Output driver power supply

DD

V

I

SS

V

I

DDQ

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E¹, E^2,and E³). Deassertion of any one of the Enable

inputs will deactivate the device.

Function

Read

W

H

L

B^A

X

B^B

X

B^C

X

B^D

X

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write all Bytes

Write Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three

chip enables (E¹, E^2,and E³) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.

The Byte Write Enable inputs (B^A, B^B, B^C,and B^D) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,

matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At

the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is

required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Synchronous Truth Table

Operation

Deselect Cycle, Power Down

Deselect Cycle, Continue

Read Cycle, Begin Burst

Read Cycle, Continue Burst

NOP/Read, Begin Burst

Dummy Read, Continue Burst

Write Cycle, Begin Burst

Write Cycle, Continue Burst

NOP/Write Abort, Begin Burst

Write Abort, Continue Burst

Clock Edge Ignore, Stall

Sleep Mode

Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

D

R

B

None

H

X

L

X

L

X

H

X

L

H

L

X

H

X

H

X

L

X

L

X

L

H

X

L-H High-Z

None

L

None

X

H

X

H

X

H

X

H

X

H

L

1

External

L-H

Q

X

L

X

L

H

L

1,10

2

R

B

External

H

X

L-H High-Z

X

L

X

L

H

L

L-H High-Z 1,2,10

W

B

External

L-H

D

3

X

L

X

L

H

L

X

L

1,3,10

2,3

W

B

None

H

X

L-H High-Z

X

H

X

L-H High-Z 1,2,3,10

Current

None

L-H

X

-

4

High-Z

Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a

Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin

is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read

New Write

R

W

B

R

W

R

Burst Read

Burst Write

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Pipeline Mode Data I/O State Diagram

Intermediate

R

B

W

B

Intermediate

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

Intermediate

D

Intermediate

W

R

High Z

B

D

Intermediate

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+2)

Intermediate State (N+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Intermediate

State

Current State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Flow Through Mode Data I/O State Diagram

R

B

W

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

W

R

High Z

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive

strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name

Burst Order Control

Power Down Control

State

Function

Name

L

Linear Burst

Interleaved Burst

Active

LBO

H

L or NC

H

ZZ

Standby, I = I

DD SB

Note:

There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and

the chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

tZZR

ZZ

Sleep

tZZS

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found

on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V or V

on pipelined parts and V on flow

DD

DDQ

SS

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 4.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

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Power Supply Voltage Ranges

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

Notes

V

3.3 V Supply Voltage

2.5 V Supply Voltage

V

DD3

V

2.3

2.5

2.7

DD2

3.3 V V

2.5 V V

I/O Supply Voltage

V

3.0

3.3

3.6

DDQ

DDQ3

V

2.3

2.5

2.7

DDQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

V

Range Logic Levels

Parameter

DDQ3

Symbol

Min.

2.0

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

+ 0.3

DD

V

1

DD

IH

V

Input Low Voltage

V

–0.3

2.0

—

0.8

+ 0.3

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

—

1,3

DDQ

IHQ

DDQ

V

–0.3

—

0.8

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

V

Range Logic Levels

Parameter

DDQ2

Symbol

Min.

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

0.6*V

V

+ 0.3

DD

V

1

DD

IH

DD

V

Input Low Voltage

V

0.3*V

DD

–0.3

—

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

0.6*V

V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

DD

V

0.3*V

DD

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

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Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

70

Unit

°C

Notes

T

Ambient Temperature (Commercial Range Versions)

2

A

T

Ambient Temperature (Industrial Range Versions)

Note:

–40

25

85

°C

A

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

50%

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

Input/Output Capacitance

pF

I/O

Note: These parameters are sample tested.

Package Thermal Characteristics

Rating

Junction to Ambient (at 200 lfm)

Junction to Case (TOP)

Notes:

Layer Board

Symbol

Max

40

Unit

Notes

1,2

R

single

four

—

°C/W

ΘJA

ΘJC

24

1,2

9

3

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.

Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

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AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ and PE Input Current

FT, ZQ Input Current

IN1

IN2

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

DD

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

OL

OUT

DDQ

V

I

= –8 mA, V

= 2.375 V

= 3.135 V

OH2

OH3

OH

—

V

I

= 8 mA

OL

0.4 V

OL

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AC Electrical Characteristics

-250

-225

-200

-166

-150

-133

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

4.0

—

2.5

—

5.5

—

4.4

—

2.7

—

6.0

—

5.0

—

3.0

—

6.5

—

6.0

—

3.4

—

7.0

—

6.7

—

3.8

—

7.5

—

7.5

—

1.5

0.5

8.5

—

3.0

1.5

0.5

1.7

2

—

4.0

—

8.5

—

ns

tKQX

1.5

1.2

0.2

5.5

—

3.0

1.5

0.5

1.3

1.5

1.3

0.3

6.0

—

3.0

1.5

0.5

1.3

1.5

1.4

0.4

6.5

—

3.0

1.5

0.5

1.3

1.5

0.5

7.0

—

3.0

1.5

0.5

1.3

1.5

0.5

7.5

—

3.0

1.5

0.5

1.5

1.7

Pipeline

1

tLZ

tS

tH

Hold time

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

tKQX

Flow

Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.5

2.5

1.5

2.7

1.5

3.0

1.5

3.0 1.5 3.0 1.5 3.0

ns

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.5

—

2.5

—

0

2.7

—

2.7

—

0

3.2

—

3.0

—

0

3.5

—

3.0

—

0

3.8

—

3.0

—

0

4.0

—

3.0

—

ns

1

tOLZ

tOHZ

1

—

5

—

5

—

5

—

5

—

5

—

5

2

tZZS

tZZH

2

ZZ hold time

1

ZZ recovery

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and

0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising

edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI

and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

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Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1 0

·

· · ·

Boundary Scan Register

n

2 1 0

· · · · · · · · ·

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

1

x36

x18

X

0

1

0

1

0

0 1 1 0 1 1 0 0 1

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Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

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SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the

Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it

is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although

allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be

stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-

DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The

EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST

command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK

when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,

the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-

ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the

value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-

ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

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JTAG TAP Instruction Set Summary

Instruction

EXTEST

IDCODE

Code

000

001

Description

Notes

1

1, 2

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

100

101

110

111

1

GSI

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

2.0

Max.

Unit Notes

V

+0.3

DD3

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

IHJ3

V

–0.3

0.8

+0.3

ILJ3

V

0.6 * V

V

1

IHJ2

DD2

V

0.3 * V

1

–0.3

–300

–1

V

1

ILJ2

DD2

I

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

Test Port Output High Voltage

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

Test Port Output Low Voltage

—

0.4

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

—

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

V

– 0.2 V

Input high level

Input low level

DQ

DD

0.2 V

1 V/ns

*

50Ω

Input slew rate

30pF

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

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JTAG Port Timing Diagram

tTKL

tTS

tTKH

tTKC

TCK

tTH

TMS

TDI

TDO

tTKQ

JTAG Port AC Electrical Characteristics

Parameter

TCK Cycle Time

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

ns

tTH

—

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

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Package Dimensions—119-Bump PBGA

Pin 1

A

Corner

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

H

D

B

J

S

K

L

M

N

P

R

T

U

R

Bottom View

Top View

Package Dimensions—119-Pin PBGA

Symbol

Description

Width

Min. Nom. Max

13.9 14.0 14.1

21.9 22.0 22.1

A

B

Length

C

Package Height (including ball) 1.73 1.86 1.99

D

Ball Size

0.60 0.75 0.90

0.50 0.60 0.70

E

Ball Height

F

Package Height (excluding balls) 1.16 1.26 1.36

G

Width between Balls

Package Height above board

Width of package between balls

Length of package between balls

Variance of Ball Height

1.27

K

0.65 0.70 0.75

R

7.62

20.32

0.15

S

T

Unit: mm

Side View

BPR 1999.05.18

Rev: 1.00b 12/2002

29/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.50 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.07

B

0.20(4x)

SEATING PLANE

C

Rev: 1.00b 12/2002

30/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

Ordering Information—GSI NBT Synchronous SRAM

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

512K x 18

256K x 36

512K x 18

256K x 36

512K x 18

Notes:

GS882Z18BB-250

GS882Z18BB-225

GS882Z18BB-200

GS882Z18BB-166

GS882Z18BB-150

GS882Z18BB-133

GS882Z36BB-250

GS882Z36BB-225

GS882Z36BB-200

GS882Z36BB-166

GS882Z36BB-150

GS882Z36BB-133

GS882Z18BB-250I

GS882Z18BB-225I

GS882Z18BB-200I

GS882Z18BB-166I

GS882Z18BB-150I

GS882Z18BB-133I

GS882Z36BB-250I

GS882Z36BB-225I

GS882Z36BB-200I

GS882Z36BB-166I

GS882Z36BB-150I

GS882Z36BB-133I

GS882Z18BD-250

GS882Z18BD-225

GS882Z18BD-200

GS882Z18BD-166

GS882Z18BD-150

GS882Z18BD-133

NBT Pipeline/Flow Through

119 BGA

165 BGA

250/5.5

225/6

C

I

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

C

200/6.5

166/7

150/7.5

133/8.5

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36B-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.00b 12/2002

31/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

256K x 36

GS882Z36BD-250

GS882Z36BD-225

GS882Z36BD-200

GS882Z36BD-166

GS882Z36BD-150

GS882Z36BD-133

NBT Pipeline/Flow Through

165 BGA

250/5.5

225/6

C

I

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

512K x 18 GS882Z18BD-250I

512K x 18 GS882Z18BD-225I

512K x 18 GS882Z18BD-200I

512K x 18 GS882Z18BD-166I

512K x 18 GS882Z18BD-150I

512K x 18 GS882Z18BD-133I

256K x 36 GS882Z36BD-250I

256K x 36 GS882Z36BD-225I

256K x 36 GS882Z36BD-200I

256K x 36 GS882Z36BD-166I

256K x 36 GS882Z36BD-150I

256K x 36 GS882Z36BD-133I

Notes:

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

I

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36B-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.00b 12/2002

32/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882Z18/36BB/D-250/225/200/166/150/133

9Mb Sync SRAM Datasheet Revision History

Types of Changes

Format or Content

DS/DateRev. Code: Old;

Page;Revisions;Reason

New

• Creation of new datasheet

882Z18B_r1

Rev: 1.00b 12/2002

33/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS882Z36BD-225IT
厂家：	GSI TECHNOLOGY
描述：	ZBT SRAM, 256KX36, 6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 静态存储器内存集成电路
文件：	总33页 (文件大小：1021K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS882Z36BD-225IT [GSI]

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