GS8672Q37BE-300I [GSI]
72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM;型号: | GS8672Q37BE-300I |
厂家: | GSI TECHNOLOGY |
描述: | 72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM 时钟 静态存储器 内存集成电路 |
文件: | 总27页 (文件大小:480K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS8672Q19/37BE-450/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
450 MHz–300 MHz
1.8 V V
TM
72Mb SigmaQuad -II+
DD
TM
1.5 V I/O
Burst of 2 ECCRAM
Features
Clocking and Addressing Schemes
• 2.0 Clock Latency
The GS8672Q19/37BE SigmaQuad-II+ ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
Each internal read and write operation in a SigmaQuad-II+ B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B2 ECCRAM is always one address
pin less than the advertised index depth (e.g., the 4M x18 has
an 2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable ECCRAMs with no On-Chip
ECC, which typically have an SER of 200 FITs/Mb or more.
SER quoted above is based on reading taken at sea level.
SigmaQuad™ ECCRAM Overview
The GS8672Q19/37BE are built in compliance with the
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)
ECCRAMs. The GS8672Q19/37BE SigmaQuad ECCRAMs
are just one element in a family of low power, low voltage
HSTL I/O ECCRAMs designed to operate at the speeds needed
to implement economical high performance networking
systems.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
Parameter Synopsis
-450
2.2 ns
0.45 ns
-400
-375
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
tKHKH
tKHQV
2.5 ns
2.67 ns
0.45 ns
0.45 ns
Rev: 1.02c 8/2017
1/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
2M x 36 SigmaQuad-II+ ECCRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC
(288Mb)
NF
(144Mb)
A
CQ
SA
W
BW2
K
BW1
R
SA
CQ
B
C
D
E
F
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
SA
BW3
SA
K
BW0
SA
SA
D17
D16
Q16
Q15
D14
Q13
Q17
Q7
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
V
D15
D6
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
Q14
D13
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
Q31
D32
Q24
Q34
D26
D35
TCK
D23
Q23
D24
D25
Q25
Q26
SA
D12
Q12
D11
D10
Q10
Q9
Q4
D3
K
L
V
V
V
V
V
V
Q11
Q1
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
SA
SA
SA
V
D9
SA
SA
QVLD
ODT
SA
SA
D0
SA
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35.
2. Pins A2 and A10 are the expansion addresses.
Rev: 1.02c 8/2017
2/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
4M x 18 SigmaQuad-II+ ECCRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC
(144Mb)
A
CQ
SA
W
BW1
K
NF
R
SA
SA
CQ
B
C
D
E
F
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
Q9
NC
D9
SA
NF
SA
K
BW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D6
NC
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
D10
Q10
Q11
D12
Q13
V
SA
V
SS
SS
SS
SS
D11
NC
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
D14
Q14
D15
D16
Q16
Q17
SA
NC
Q4
K
L
V
NC
NC
NC
NC
NC
SA
D3
NC
Q1
Q15
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
D17
NC
V
SA
SA
SA
SA
SA
SA
SA
V
NC
D0
SA
SA
QVLD
ODT
SA
SA
TCK
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. Pin A2 is the expansion address.
Rev: 1.02c 8/2017
3/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Pin Description Table
Symbol
Description
Synchronous Address Inputs
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Input Clock
Type
Input
Comments
SA
R
—
Input
Active Low
W
Input
Active Low
BW0–BW3
K
Input
Active Low
Input
Active High
K
Input Clock
Input
Active Low
TMS
TDI
Test Mode Select
Input
—
Test Data Input
Input
—
TCK
TDO
VREF
Test Clock Input
Input
—
Test Data Output
Output
Input
—
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when low
Output Echo Clock
—
ZQ
Qn
Input
—
Output
Input
—
Dn
—
Active Low
—
Input
Doff
CQ
CQ
VDD
Output
Output
Supply
Output Echo Clock
—
Power Supply
1.8 V Nominal
VDDQ
VSS
Isolated Output Buffer Supply
Supply
1.5 V Nominal
Power Supply: Ground
Q Valid Output
Supply
Output
Input
—
—
—
—
—
—
QVLD
ODT
On-Die Termination
No Connect
NC
NF
No Function
—
Notes:
1. NC = Not Connected to die or any other pin
2. NF= No Function. There is an electrical connection to this input pin, but the signal has no function in the device. It can be left unconnected,
or tied to V or V
SS
DDQ.
3. K, or K cannot be set to V
voltage.
REF
Rev: 1.02c 8/2017
4/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate
I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers
from Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II+ B2 ECCRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable pin, R, begins
a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of K, and after the following rising edge of
K with a rising edge of K. Clocking in a high on the Read Enable pin, R, begins a read port deselect cycle.
SigmaQuad-II+ B2 ECCRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
Rev: 1.02c 8/2017
5/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Power-Up Sequence for SigmaQuad-II+ ECCRAMs
SigmaQuad-II+ ECCRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
1. After power supplies power-up and clocks (K, K) are stablized, 163,840 cycles are required to set Output Driver
Impedance.
2. Thereafter, an additional 65,536 clock cycles are required to lock the DLL after it has been enabled.
3. Begin Read and Write operations.
For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
On-Chip Error Correction
SigmaQuad-II+ ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on
each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9],
D/Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible
to the user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a
single SER event very rarely causes a multi-bit error across any given "transmitted data unit", where a "transmitted data unit"
represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-
bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one "error bit" per eight "data bits", in any 9-bit
"data byte") for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such
error-bit allocation is unnecessary with ECCRAMs —the entire memory array can be utilized for data storage, effectively
providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Rev: 1.02c 8/2017
6/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Note: If “Half Write” operations (i.e., write operations in which a BWn pin is asserted for only half of a DDR write data transfer
on the associated 9-bit data bus, causing only 9 bits of the 18-bit DDR data word to be written) are initiated, the on-chip ECC will
be disabled for as long as the SRAM remains powered up thereafter. This must be done because ECC is implemented across entire
18-bit data words, rather than across individual 9-bit data bytes.
Byte Write Truth Table
The truth table below applies to write operations to Address "m", where Address "m" is the 18-bit memory location comprising the
2 beats of DDR write data associated with each BWn pin in a given clock cycle.
BWn
Input Data Byte n
Operation
Result
K
K
K
K
(Beat 1)
(Beat 2)
(Beat 1)
(Beat 2)
0
0
1
1
0
1
0
1
D0
D0
X
D1
X
Full Write
Half Write
Half Write
Abort
D0 and D1 written to Address m
Only D0 written to Address m
Only D1 written to Address m
Address m unchanged
D1
X
X
Notes:
1. BW0 is associated with Input Data Byte D[8:0].
2. BW1 is associated with Input Data Byte D[17:9].
3. BW2 is associated with Input Data Byte D[26:18] (in x36 only).
4. BW3 is associated with Input Data Byte D[35:27] (in x36 only).
5. ECC is disabled if a “Half Write” operation is initiated.
Rev: 1.02c 8/2017
7/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ ECCRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the ECCRAM to monitor and adjust its output driver impedance. The value of RQ must
be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously
is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by
drifts in supply voltage and temperature. The ECCRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ ECCRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock
(K/K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating -the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is
enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and V ) used to
SS
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175 and 250. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Note:
When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K
inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the
input termination will pull the signal to V
/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver
DDQ
to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result in the
device’s operating currents being higher.
Rev: 1.02c 8/2017
8/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Separate I/O SigmaQuad-II+ ECCRAM Read Truth Table
A
R
Output Next State
Q
Q
K
K
K
K
K
(t )
(t )
(t )
(t
)
(t
)
n
n
n
n+2
n+2½
X
V
1
0
Deselect
Read
Hi-Z/0
Q0
Hi-Z/0
Q1
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
4. Users should not clock in metastable addresses.
5. When On-Die Termination is disabled (ODT = 0), Q drivers are disabled (i.e., Q pins are tri-stated) for one cycle in response to NOP and
Write commands, 2.0 cycles after the command is sampled.
6. When On-Die Termination is enabled (ODT = 1), Q drivers are enabled Low (i.e., Q pins are driven Low) for one cycle in response to
NOP and Write commands, 2.0 cycles after the command is sampled. This is done so that the ASIC/Controller can enable On-Die
Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs to VDDQ/2 (i.e., to the switch point
of the data input receivers).
Separate I/O SigmaQuad-II+ ECCRAM Write Truth Table
A
W
BWn
K
BWn
K
Input Next State
D
D
K
K
K
K
K K
(t
)
(t )
(t )
(t
)
(tn), (tn + ½
)
(t )
(t
)
n + ½
n
n
n + ½
n
n + ½
V
V
V
X
X
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Write Byte Dx0, Write Byte Dx1
Write Byte Dx0, Write Abort Byte Dx1
Write Abort Byte Dx0, Write Byte Dx1
Write Abort Byte Dx0, Write Abort Byte Dx1
Deselect
D0
D0
X
D1
X
D1
X
X
X
X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
Rev: 1.02c 8/2017
9/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
x36 Byte Write Enable (BWn) Truth Table
BW0
BW1
BW2
BW3
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
Rev: 1.02c 8/2017
10/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
Description
Value
–0.5 to 2.4
Unit
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage in VREF Pins
V
VDDQ
VREF
VI/O
–0.5 to VDD
V
V
–0.5 to VDDQ
–0.5 to VDDQ +0.5 ( 2.4 V max.)
–0.5 to VDDQ +0.5 ( 2.4 V max.)
Voltage on I/O Pins
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
V
IIN
+/–100
+/–100
120
mA dc
mA dc
IOUT
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
oC
oC
TJ
TSTG
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
VDD
Min.
1.7
Typ.
1.8
—
Max.
1.9
Unit
V
VDDQ
VREF
I/O Supply Voltage
Reference Voltage
1.4
1.6
V
VDDQ/2 – 0.05
VDDQ/2 + 0.05
—
V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The power
DD DDQ REF
down sequence must be the reverse. V
must not exceed V . For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
DD
DDQ
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
85
C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
25
100
C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.02c 8/2017
11/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Thermal Impedance
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
JA (C°/W)
Airflow = 1 m/s
JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
JC (C°/W)
Package
165 BGA
4-layer
15.25
12.38
11.41
4.79
1.31
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Input Reference Voltage
Symbol
Min
Max
/2 + 0.05
Units
Notes
—
V
/2 – 0.05
V
VREF
V
V
V
V
V
DDQ
DDQ
V
V
+ 0.1
+ 0.3
– 0.1
+ 0.3
VIH1
VIL1
VIH2
VIL2
1
Input High Voltage
Input Low Voltage
Input High Voltage
REF
DDQ
V
V
–0.3
0.7 * V
1
REF
2,3
2,3
DDQ
DDQ
0.3 * V
–0.3
Input Low Voltage
DDQ
Notes:
1. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
3. Parameters apply to ZQ during JTAG boundary scan testing only.
HSTL I/O AC Input Characteristics
Parameter
Input Reference Voltage
Symbol
Min
Max
/2 + 0.08
Units
Notes
—
V
/2 – 0.08
V
VREF
V
V
V
V
V
DDQ
DDQ
V
+ 0.2
V
+ 0.5
– 0.2
+ 0.5
VIH1
VIL1
VIH2
VIL2
1,2,3
1,2,3
4,5
Input High Voltage
Input Low Voltage
Input High Voltage
REF
DDQ
V
–0.5
– 0.2
REF
V
V
DDQ
DDQ
Input Low Voltage
–0.5
0.2
4,5
Notes:
1.
V
and V
apply for pulse widths less than one-quarter of the cycle time.
IL(MIN)
IH(MAX)
2. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
3. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
Rev: 1.02c 8/2017
12/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
4
Max.
5
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0 V
4.5
5.5
pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
1.25 V
0.25 V
Max. input slew rate
Input reference level
Output reference level
2 V/ns
0.75 V
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 (HSTL I/O)
= 0.75 V
V
REF
50
VT = V /2
DDQ
Input and Output Leakage Characteristics
Parameter
Symbol
IIL
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
VIN = 0 to VDDQ
–2 uA
2 uA
IILDOFF
IIL ODT
VIN = 0 to VDDQ
VIN = 0 to VDDQ
Doff
–2uA
100 uA
100 uA
ODT
–2 uA
Output Disable,
VOUT = 0 to VDDQ
IOL
Output Leakage Current
–2 uA
2 uA
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
VOH1
Min.
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
Vss
Max.
Units
Notes
1
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
V
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
VOL1
2
VOH2
V
3, 4
3, 5
6, 7
VOL2
0.2
V
ROUT
(RQ/5) * 0.88
(RQ/5) * 1.12
Output Driver Impedance
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175 RQ 275
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175 RQ 275
OL
DDQ
OL
DDQ
3. 0RQ
4.
I
= –1.0 mA
OH
5.
I
= 1.0 mA
OL
6. Parameter applies when 175 RQ 275
7. Tested at V = V * 0.2 and V * 0.8
OUT
DDQ
DDQ
Operating Currents
-450
-400
-375
-333
-300
Parameter
Symbol
Test Conditions
0°
to
–40°
to
0°
to
–40°
to
0°
to
–40°
to
0°
to
–40° 0° –40°
to to to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min
OperatingCurrent
(x36): DDR
2050
mA
2070
mA
1860 1880 1760 1780 1600 1620 1480 1500
mA mA mA mA mA mA mA mA
IDD
2, 3
2, 3
VDD = Max, IOUT = 0 mA
OperatingCurrent
(x18): DDR
1490
mA
1510
mA
1360 1380 1300 1320 1190 1210 1100 1120
mA mA mA mA mA mA mA mA
IDD
Cycle Time tKHKH Min
Notes:
1. Power measured with output pins floating.
2. Minimum cycle, I = 0 mA
OUT
3. Operating current is calculated with 50% read cycles and 50% write cycles.
Rev: 1.02c 8/2017
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
AC Electrical Characteristics
-450
-400
-375
-333
-300
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tKVar
K, K Clock Cycle Time
2.2
—
6.0
0.15
—
2.5
—
6.0
0.2
—
2.66
—
6.0
0.2
—
—
—
—
—
—
3.0
—
6.0
0.2
—
—
—
—
—
—
3.3
—
6.0
0.2
—
ns
ns
tK Variable
4
tKHKL
tKLKH
tKHKH
tKHKH
tKLock
tKReset
K, K Clock High Pulse Width
K, K Clock Low Pulse Width
K to K High
0.4
0.4
0.4
1.06
1.06
64K
30
0.4
0.4
0.4
1.28
1.28
64K
30
0.4
0.4
1.40
1.40
64K
30
cycle
cycle
ns
0.4
—
—
0.4
—
0.94
0.94
64K
30
—
—
1.13
1.13
64K
30
—
K to K High
—
—
—
ns
DLL Lock Time
—
—
—
cycle
ns
5
K Static to DLL reset
—
—
—
Output Times
tKHQV
tKHQX
K, K Clock High to Data Output Valid
—
0.45
—
—
–0.45
—
0.45
—
—
0.45
—
—
0.45
—
—
–0.45
—
0.45
—
ns
ns
ns
ns
ns
ns
ns
K, K Clock High to Data Output Hold
K, K Clock High to Echo Clock Valid
K, K Clock High to Echo Clock Hold
CQ, CQ High Output Valid
–0.45
—
–0.45
—
–0.45
—
tKHCQV
tKHCQX
tCQHQV
tCQHQX
tQVLD
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
0.15
—
0.2
—
0.2
—
0.2
—
0.2
—
CQ, CQ High Output Hold
–0.15
–0.15
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
CQ, CQ High to QVLD
0.15
0.2
0.2
0.2
0.2
tCQHCQH
tCQHCQH
CQ Phase Distortion
0.85
—
1.0
—
1.08
—
1.25
—
1.40
—
ns
tKHQZ
K Clock High to Data Output High-Z
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
ns
ns
tKHQX1
K Clock High to Data Output Low-Z
Setup Times
–0.45
–0.45
–0.45
–0.45
–0.45
tAVKH
tIVKH
Address Input Setup Time
0.275
0.275
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
1
2
Control Input Setup Time
(R, W)
Control Input Setup Time
(BWX)
tIVKH
0.22
0.22
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
3
tDVKH
Data Input Setup Time
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.275
0.275
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
1
2
Control Input Hold Time
(R, W)
Control Input Hold Time
(BWX)
tKHIX
0.22
0.22
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
3
tKHDX
Data Input Hold Time
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W.
3. Control signals are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.
V
DD
DD
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Read NOP CQ-Based Timing Diagram
Read A0 / Write NOP Read A1 / Write NOP Read A2 / Write NOP Read A3 / Write NOP NOOP
NOOP
NOOP
K
K
tKHAX
tAVKH
Addr
R
A0
A1
A2
A3
tKHIX
tIVKH
tKHIX
tIVKH
W
QVLD
Q
Q0
Q0+1
Q1
Q1+1
Q2
Q2+1
Q3
Q3+1
tCQLQV
tCQHQV
tCQLQX
tCQHQX
tCQLQX
CQ
CQ
tCQLQV
tQVLD
tCQHQV
tCQHQX
tQVLD
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Read-Write CQ-Based Timing Diagram
Read A0/ Write A8
Read A1/ Write A7
Read A2/ Write A6
Read A3/ Write A5
NOOP
NOOP
NOOP
K
K
tAVKH
tKHAX
tKHAX
tAVKH
Addr
R
A0
A8
A1
A7
A2
A6
A3
A5
tIVKH
tKHIX
tIVKH
tKHIX
W
tIVKH
tKHIX
BWx
tDVKH
tDVKH
tKHDX
tKHDX
D
QVLD
Q
D8
D8+1
D7
D7+1
D6
D6+1
D5
D5+1
Q0
Q0+1
Q1
Q1+1
Q2
Q2+1
Q3
Q3+1
tCQHQX
tCQHQV
tCQLQV
tCQLQX
tCQHQX
CQ
CQ
tCQLQV
tCQLQX
tQVLD
tCQHQV
tQVLD
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Write NOP TIming Diagram
0ns
5ns
10ns
15ns
20ns
Read No-op / Write A0 Read No-op / Write A1 Read No-op / Write A2 Read No-op / Write A3 NO-OP
NO-OP
NO-OP
K
K
tKHAX
tAVKH
Addr
R
A0
A1
A2
A3
tKHIX
tIVKH
tKHIX
tIVKH
W
tKHIX
tIVKH
BWx
D
tKHDX
tDVKH
D0
D0+1
D1
D1+1
D2
D2+1
D3
D3+1
Rev: 1.02c 8/2017
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TMS
TDI
Test Mode Select
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Rev: 1.02c 8/2017
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology
See BSDL Model
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
1
7
1
6
0
5
1
4
1
3
0
2
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
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GS8672Q19/37BE-450/400/375/333/300
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
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GS8672Q19/37BE-450/400/375/333/300
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
Rev: 1.02c 8/2017
22/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z except CQ.
SAMPLE-Z
010
1
GSI
SAMPLE/PRELOAD
GSI
011
100
101
110
111
GSI private instruction.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
1
1
1
GSI
GSI private instruction.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VILJ
Min.
–0.3
Max.
Unit Notes
0.3 * VDD
VDD +0.3
Test Port Input Low Voltage
V
V
1
1
VIHJ
0.7 * VDD
Test Port Input High Voltage
IINHJ
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
–300
–1
1
100
1
uA
uA
uA
V
2
IINLJ
3
IOLJ
–1
4
VOHJ
VOLJ
VOHJC
VOLJC
VDD – 0.2
—
0.2
—
0.1
5, 6
5, 7
5, 8
5, 9
—
V
VDD – 0.1
V
—
V
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V
+1 V not to exceed 2.4 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
V V
ILJ
IN
DDn
3. 0 V V V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V supply.
DD
6.
7.
8.
9.
I
I
I
I
= –2 mA
OHJ
= + 2 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
Rev: 1.02c 8/2017
23/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
JTAG Port AC Test Conditions
Parameter
Input high level
Input low level
Conditions
JTAG Port AC Test Load
TDO
VDD – 0.2 V
0.2 V
1 V/ns
VDD/2
*
50
30pF
Input slew rate
V
/2
Input reference level
DD
* Distributed Test Jig Capacitance
VDD/2
Output reference level
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTH
tTS
tTS
TDI
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Rev: 1.02c 8/2017
24/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.02c 8/2017
25/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Ordering Information—GSI SigmaQuad-II+ ECCRAM
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
J
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
2M x 36
2M x 36
GS8672Q19BE-450
GS8672Q19BE-400
GS8672Q19BE-375
GS8672Q19BE-333
GS8672Q19BE-300
GS8672Q19BE-450I
GS8672Q19BE-400I
GS8672Q19BE-375I
GS8672Q19BE-333I
GS8672Q19BE-300I
GS8672Q37BE-450
GS8672Q37BE-400
GS8672Q37BE-375
GS8672Q37BE-333
GS8672Q37BE-300
GS8672Q37BE-450I
GS8672Q37BE-400I
GS8672Q37BE-375I
GS8672Q37BE-333I
GS8672Q37BE-300I
GS8672Q19BGE-450
GS8672Q19BGE-400
GS8672Q19BGE-375
GS8672Q19BGE-333
GS8672Q19BGE-300
GS8672Q19BGE-450I
GS8672Q19BGE-400I
GS8672Q19BGE-375I
GS8672Q19BGE-333I
GS8672Q19BGE-300I
GS8672Q37BGE-450
GS8672Q37BGE-400
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
165-bump BGA
165-bump BGA
450
400
375
333
300
450
400
375
333
300
450
400
375
333
300
450
400
375
333
300
450
400
375
333
300
450
400
375
333
300
450
400
C
C
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
165-bump BGA
C
C
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
C
C
C
C
C
I
I
I
I
I
C
C
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8672Q37BE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02c 8/2017
26/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8672Q19/37BE-450/400/375/333/300
Ordering Information—GSI SigmaQuad-II+ ECCRAM (Continued)
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
J
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
GS8672Q37BGE-375
GS8672Q37BGE-333
GS8672Q37BGE-300
GS8672Q37BGE-450I
GS8672Q37BGE-400I
GS8672Q37BGE-375I
GS8672Q37BGE-333I
GS8672Q37BGE-300I
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
SigmaQuad-II+ ECCRAM
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
375
333
300
450
400
375
333
300
C
C
C
I
I
I
I
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8672Q37BE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
SigmaQuad-II+ ECCRAM Revision History
File Name
Format/Content
Description of changes
• Creation of datasheet
(Rev1.00a: Updated Write NOP Timing Diagram)
8672Q19_37B_r1
• Added Operating Currents data
8672Q19_37B_r1_01
8672Q19_37B_r1_02
Content
• (Rev1.01a: Editorial updates)
• (Rev1.01b: Corrected 165 thermal numbers)
• Updated to reflect MP status
• Added 450 MHz speed bin
• (Rev1.02a: Removed V reference in Abs Max section)
TIN
Content
• (Rev1.02b: Removed “due to ECC” from Byte Write bullet on page
1)
• (Rev1.02c: Corrected erroneous information in Input and Output
Leakage Characteristics table)
Rev: 1.02c 8/2017
27/27
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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