GS840FH18AGT-8.5I [GSI]
256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs; 256K ×18 , 128K ×32 , 128K ×36的4Mb同步突发静态存储器型号: | GS840FH18AGT-8.5I |
厂家: | GSI TECHNOLOGY |
描述: | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
文件: | 总21页 (文件大小:544K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS840FH18/32/36AT-8/8.5/10/12
8 ns–12 ns
TQFP
Commercial Temp
Industrial Temp
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
Features
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
Designing For Compatibility
The JEDEC standard for Burst RAMs calls for a FT mode pin
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
option (Pin 14 on TQFP). Board sites for flow through Burst
RAMs should be designed with V connected to the FT pin
SS
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s pipeline/flow through-configurable Burst
RAMs or any vendor’s flow through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable flow through Burst
RAM, (e.g., GS840FH18/32/36A), to achieve flow through
functionality.
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840FH18/32/36A is
available in a JEDEC-standard 100-lead TQFP package.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Core and Interface Voltages
The GS840FH18/32/36A operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V
) pins are used to decouple
DDQ
output noise from the internal circuit.
Parameter Synopsis
-8
-8.5
-10
-12
Flow
tKQ
8 ns
8.5 ns
10 ns
10 ns
12 ns
12 ns
15 ns
Through tCycle 9 ns
2-1-1-1 IDD
210 mA 190 mA 165 mA 135 mA
Rev: 1.07 10/2004
1/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
GS840FH18 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
NC
V
DDQ
DDQ
SS
V
NC
DQPA
DQA
DQA
V
V
V
SS
NC
NC
DQB
DQB
256K x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
DDQ
DQA
DQA
DQB
DQB
V
NC
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
DQB
DQB
DDQ
V
V
V
DQA
DQA
NC
NC
V
V
NC
NC
NC
DDQ
SS
V
SS
DQB
DQB
DQPB
NC
V
DDQ
SS
DDQ
SS
V
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.07 10/2004
2/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
GS84FH32 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 32
Top View
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
DDQ
DQB
DQB
DQC
DQC
V
NC
SS
NC
V
DD
V
ZZ
NC
DD
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
SS
V
V
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
V
SS
DDQ
SS
V
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.07 10/2004
3/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
GS840FH36 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQPC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQC
V
V
V
DDQ
DDQ
SS
V
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 36
Top View
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
DDQ
DQB
DQB
DQC
DQC
NC
V
SS
NC
V
DD
V
ZZ
NC
DD
V
SS
DQA
DQA
DQD
DQD
DDQ
V
V
V
DDQ
SS
V
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
DDQ
SS
V
V
DDQ
DQA
DQD
DQA
DQD
DQPA
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.07 10/2004
4/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BW
BA, BB
BC, BD
CK
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
Clock Input Signal; active high
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
E1, E3
E2
Chip Enable; active high
G
Output Enable; active low
ADV
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADSP, ADSC
ZZ
LBO
Linear Burst Order mode; active low
Core power supply
V
DD
V
I
I
I/O and Core Ground
Output driver power supply
No Connect
SS
V
DDQ
NC
—
Rev: 1.07 10/2004
5/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
GS840FH18/32/36A Block Diagram
RegisteQr
A0–An
D
A0
A0
A1
D0
D1
Counter
Load
Q0
Q1
A1
A
LBO
ADV
CK
Memory
Array
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E3
E2
D
Q
Register
D
Q
0
G
1
Power Down
Control
DQx0–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.07 10/2004
6/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Active
Burst Order Control
LBO
H or NC
L or NC
H
Power Down Control
ZZ
Standby, I = I
DD SB
Note:
There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
4th address
4th address
Note:
Note:
The burst counter wraps to initial state on the 5th clock.
The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Read
H
1
Write byte A
Write byte B
Write byte C
Write byte D
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.07 10/2004
7/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Write Cycle, Suspend Burst
Notes:
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.07 10/2004
8/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
CR
First Write
First Read
CW
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.07 10/2004
9/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
CR
First Write
First Read
CR
CW
CW
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.07 10/2004
10/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
–0.5 to V
DD
V
DDQ
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
–0.5 to V +0.5 (≤ 4.6 V max.)
V
CK
I/O
V
V
DDQ
V
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to V +0.5 (≤ 4.6 V max.)
V
IN
IN
DD
I
+/–20
+/–20
mA
mA
W
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
STG
BIAS
C
o
T
Temperature Under Bias
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
Supply Voltage
3.135
2.375
1.7
3.3
2.5
—
3.6
V
V
DD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
1
2
2
3
3
DDQ
DD
V
V +0.3
DD
V
IH
V
–0.3
0
—
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
25
25
70
85
°C
°C
A
T
Ambient Temperature (Industrial Range Versions)
–40
A
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V
≤ 2.375 V (i.e., 2.5 V I/O)
DDQ
and 3.6 V ≤ V
≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case.
DDQ
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.07 10/2004
11/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+– 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
C
V
= 3.3 V
= 0 V
Control Input Capacitance
Input Capacitance
3
4
6
4
5
7
pF
pF
pF
I
DD
C
V
IN
IN
C
V
= 0 V
OUT
Output Capacitance
OUT
Note:
This parameter is sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Rev: 1.07 10/2004
12/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
2.3 V
0.2 V
Input slew rate
1 V/ns
1.25 V
1.25 V
Fig. 1& 2
Input reference level
Output reference level
Output load
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t , and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225Ω
DQ
*
50Ω
30pF
*
225Ω
5pF
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
–1 uA
–1 uA
1 uA
300 uA
DD
IN
IH
IH
I
ZZ Input Current
INZZ
0V ≤ V ≤ V
IN
V
≥ V ≥ V
–300 uA
–1 uA
1 uA
1 uA
DD
IN
IL
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0V ≤ V ≤ V
IN
Output Disable,
V
I
–1 uA
1 uA
OL
= 0 to V
OUT
DD
V
I
I
= –mA, V
= –mA, V
= 2.375 V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
OH
OH
OH
DDQ
DDQ
V
= 3.135 V
OH
V
I
= mA
OL
0.4 V
OL
Rev: 1.07 10/2004
13/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Operating Currents
-8
-8.5
-10
-12
0
to
-40
to
0
to
-40
to
0
to
-40
to
0
to
-40
to
Parameter
Test Conditions
Symbol
Unit
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
All other inputs
≥VIH or ≤ VIL
Operating
Current
IDD
210
20
40
220
30
50
190
20
40
200
30
50
165
20
35
175
30
45
135
20
35
145
30
45
mA
mA
mA
Flow Through
Output open
Standby
Current
ISB
ZZ ≥ V – 0.2 V
DD
Flow Through
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
IDD
Flow Through
AC Electrical Characteristics
-8
-8.5
-10
-12
Parameter
Symbol
Unit
Min
9.0
—
Max
—
Min
Max
Min
Max
Min
Max
—
12
—
—
—
—
5
Clock Cycle Time
tKC
tKQ
10.0
—
—
8.5
—
10.0
—
—
10
—
15.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
8.0
—
Flow
Through
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
1
—
—
—
tLZ
tKH
tKL
—
—
—
Clock LOW Time
—
—
—
1
Clock to Output in High-Z
G to Output Valid
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
tHZ
tOE
5
1
G to output in Low-Z
0
0
0
0
—
tOLZ
1
G to output in High-Z
Setup time
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
5
ns
ns
ns
ns
tOHZ
tS
tH
—
—
—
Hold time
2
ZZ setup time
tZZS
2
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
tZZH
tZZR
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.07 10/2004
14/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Flow Through Mode Timing
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.07 10/2004
15/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Rev: 1.07 10/2004
16/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
GS840FH18/32/36A Output Driver Characteristics
120.0
100.0
80.0
Pull Down Drivers
60.0
40.0
VDDQ
20.0
I Out
0.0
VOut
VSS
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
-140.0
Pull Up Drivers
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
Rev: 1.07 10/2004
17/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
TQFP Package Drawing (Package T)
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.07 10/2004
18/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
Ordering Information for GSI Synchronous Burst RAMS
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
GS840FH18AT-8
GS840FH18AT-8.5
GS840FH18AT-10
GS840FH18AT-12
GS840FH32AT-8
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
TQFP
TQFP
8
8.5
10
12
8
C
C
C
C
C
C
C
C
C
C
C
C
I
TQFP
TQFP
TQFP
GS840FH32AT-8.5
GS840FH32AT-10
GS840FH32AT-12
GS840FH36AT-8
TQFP
8.5
10
12
8
TQFP
TQFP
TQFP
GS840FH36AT-8.5
GS840FH36AT-10
GS840FH36AT-12
GS840FH18AT-8I
GS840FH18AT-8.5I
GS840FH18AT-10I
GS840FH18AT-12I
GS840FH32AT-8I
GS840FH32AT-8.5I
GS840FH32AT-10I
GS840FH32AT-12I
GS840FH36AT-8I
GS840FH36AT-8.5I
GS840FH36AT-10I
GS840FH36AT-12I
GS840FH18AGT-8
GS840FH18AGT-8.5
GS840FH18AGT-10
GS840FH18AGT-12
GS840FH32AGT-8
GS840FH32AGT-8.5
TQFP
8.5
10
12
8
TQFP
TQFP
TQFP
TQFP
8.5
10
12
8
I
TQFP
I
TQFP
I
TQFP
I
TQFP
8.5
10
12
8
I
TQFP
I
TQFP
I
TQFP
I
TQFP
8.5
10
12
8
I
TQFP
I
TQFP
I
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
C
C
C
C
C
C
8.5
10
12
8
8.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 10/2004
19/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
GS840FH32AGT-10
GS840FH32AGT-12
GS840FH36AGT-8
GS840FH36AGT-8.5
GS840FH36AGT-10
GS840FH36AGT-12
GS840FH18AGT-8I
GS840FH18AGT-8.5I
GS840FH18AGT-10I
GS840FH18AGT-12I
GS840FH32AGT-8I
GS840FH32AGT-8.5I
GS840FH32AGT-10I
GS840FH32AGT-12I
GS840FH36AGT-8I
GS840FH36AGT-8.5I
GS840FH36AGT-10I
GS840FH36AGT-12I
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
10
12
8
C
C
C
C
C
C
I
8.5
10
12
8
8.5
10
12
8
I
I
I
I
8.5
10
12
8
I
I
I
I
8.5
10
12
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 10/2004
20/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840FH18/32/36AT-8/8.5/10/12
4Mb Burst Datasheet Revision History
Types of Changes
Format or Content
Rev. Code: Old;
Page /Revisions;Reason
New
• Updated pin description table
840FH18A_r1_02
Content
• Updated table on page 1
• Updated Operating Currents table on page 14
• Updated AC Electrical Characteristics table on page 14
• Updated Ordering Information table on page 21
• Updated entire document to comply with Technical
Publications standards
840FH18A_r1_02;
840FH18A_r1_03
Content/Format
• Reduced I by 20 mA in table on page 1 and Operating
Currents table
840FH18A_r1_03;
840FH18A_r1_04
DD
Content
Content
• Removed 7.5 ns references from entire datasheet
840FH18A_r1_04;
840FH18A_r1_05
• Updated format
840FH18A_r1_05;
840FH18A_r1_06
Content
Content
• Matched current numbers to NBT parts
• Removed Preliminary banner
• Added Pb-free information to TQFP
840FH18A_r1_06;
840FH18A_r1_07
Rev: 1.07 10/2004
21/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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