GS8342S18AE-200 [GSI]
DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165;
| 型号： | GS8342S18AE-200 |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总36页 (文件大小：1520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS8342S08/09/18/36AE-250/200/167
250 MHz–167 MHz
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb Burst of 2
SigmaSIO DDR-II™ SRAM
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
Clocking and Addressing Schemes
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write (x36, x18, and x9) and Nybble Write (x8) function
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input regiter clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internlly to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with 72Mb and 144Mb devices
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAs two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 4M x 8 has an 2M
addressable index).
SigmaSIO DDR-II™ Family Overview
GS8342S08/09/18/36AE are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Parameter Synopsis
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
tKHKH
tKHQV
6.0 ns
0.5 ns
Rev: 1.07 8/2012
1/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
4M x 8 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
NC
SA
R/W
NW1
K
NC
LD
SA
SA
CQ
NC
NC
NC
NC
NC
NC
NC
NC
D4
NC
NC
D5
NC
NC
NC
Q4
NC
Q5
SA
NC
SA
K
NW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
D2
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
V
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
D
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
D
V
V
V
V
REF
OFF
REF
DDQ
DDQ
NC
NC
NC
NC
Q1
K
L
NC
NC
NC
Q6
NC
D6
NC
NC
Q7
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
NC
D7
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
NC
TCK
SA
A
SA
SA
NC
TDO
C
TMS
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
2
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. It is recommended that H1 be tied low for compatibility with future devices.
3. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs
SS
Expansion Address
A2
A7
B5
72Mb
144Mb
288Mb
Rev: 1.07 8/2012
2/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
4M x 9 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
NC
SA
R/W
NC
K
NC
LD
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
D6
NC
NC
NC
Q5
NC
Q6
SA
NC
SA
K
BW
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
D3
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
V
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
D
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
Q2
K
L
NC
Q7
NC
D7
NC
NC
Q8
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
D8
V
V
NC
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
TCK
SA
A
SA
SA
D0
C
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. It is recommended that H1 be tied low for compatibility with future devices.
3. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs
SS
Expansion Address
A2
A7
B5
72Mb
144Mb
288Mb
Rev: 1.07 8/2012
3/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
2M x 18 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
NC
SA
R/W
BW1
K
NC
LD
SA
NC
CQ
NC
NC
NC
NC
NC
NC
Q9
NC
D9
SA
NC
SA
K
BW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D6
NC
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
D10
Q10
Q11
D12
Q13
V
V
SA
V
SS
SS
SS
SS
D11
NC
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
D
V
V
V
V
REF
OFF
REF
DDQ
DDQ
NC
NC
D14
Q14
D15
D16
Q16
Q17
SA
NC
Q4
K
L
NC
NC
NC
Q15
NC
V
NC
NC
NC
NC
NC
SA
D3
NC
Q1
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
V
V
SS
SS
SS
SS
NC
D17
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
D0
NC
SA
SA
SA
SA
TDO
TCK
C
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. It is recommended that H1 be td low for compatibility with future devices.
3. A2, A7, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Expansion Address
A10
A2
72Mb
144Mb
288Mb
A7
Rev: 1.07 8/2012
4/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
1M x 36 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
NC
NC
R/W
BW2
K
BW1
LD
SA
NC
CQ
Q27
D27
D28
Q29
Q30
D30
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
SA
BW3
SA
K
BW0
SA
SA
17
D16
Q16
Q15
D14
Q13
Q17
Q7
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
D15
D6
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
Q14
D13
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
D
V
V
V
V
REF
OFF
REF
DDQ
DDQ
D31
Q31
D23
Q23
D24
D25
Q25
Q26
SA
D12
Q12
D11
D10
Q10
Q9
Q4
K
L
Q32
Q33
D33
D34
Q35
TDO
D32
Q24
Q34
D26
D35
TCK
V
D3
Q11
Q1
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
D9
SA
SA
SA
SA
D0
C
SA
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. BW2 controls writes to D18:D2. BW3 controls writes to D27:D35.
3. It is recommended that H1 be tied low for compatibility with future devices.
4. A2, A3, and A10 are resrved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs.
SS
Expansion Addresses
A3
A10
A2
72Mb
144Mb
288Mb
Rev: 1.07 8/2012
5/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Pin Description Table
Symbol
SA
Description
Synchronous Address Inputs
No Connect
Type
Input
—
Comments
—
NC
—
R/W
Read/Write Contol Pin
Input
Write Active Low; Read Active High
Active Low
x08 Version
NW0–NW1
BW0–BW1
BW0–BW3
Synchronous Nybble Writes
Synchronous Byte Writes
Synchronous Byte Writes
Input
Input
Input
Active Low
x18 Version
Active Low
x36 Version
K
Input Clock
Input Clock
Input
Input
Input
Input
Input
Output
Input
Input
Input
Output
—
Active High
C
Active High
TMS
TDI
TCK
TDO
Test Mode Select
—
Test Data Input
—
—
Test Clock Input
Test Data Output
—
V
HSTL Input Reference Voltage
Output Impedance Matching Input
Input Clock
—
REF
ZQ
K
—
Active Low
Active Low
Active Low
Active Low
Active Low
Active High
—
C
Input Clock
D
DLL Disable
OFF
LD
CQ
CQ
Dn
Qn
Synchronous Load Pin
Output Echo Clock
Output Echo Clock
Synconous Data Inputs
Synchronous Data Outputs
Power Supply
—
Output
Output
Input
Output
Supply
—
V
1.8 V Nominal
DD
V
Isolated Output Buffer Supply
Power Supply: Ground
Supply
Supply
1.8 or 1.5 V Nominal
—
DDQ
V
SS
Notes:
1. C, C, K, or K cannot be set to V
voltage.
REF
2. NC = Not Connected o die or any other pin.
Rev: 1.07 8/2012
6/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing
so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would
keep both ports running at capacity full time. On the other hand, the SigmaSIO device can acpt a continuous stream of read
commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts
the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice
the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device.
SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO
SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic
between two electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, anSigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 Sigma SIO-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is
clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data
chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.
Burst of 2 Sigma SIO-II SRAM DDR Write
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the
R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
Rev: 1.07 8/2012
7/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD
.
1b. Apply VDDQ
.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of cln K clocks are always required to re-
lock the DLL after reset.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar ).
• The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.07 8/2012
8/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-it byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the 8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
Data In
D9–D17
Don’t Care
Data In
Beat 1
Beat 2
0
1
1
0
Don’t Care
Resulting Write Operation
Beat 1
Beat 2
D0–D8
D9–D17
D0–D8
D9–D17
Written
Unchanged
Unchanged
Written
Output Register Control
SigmaSIO DDR-II SRAMs offer two mechanisms r controlling the output data registers. Typically, control is handled by the
Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing
of the output registers by allowing the user to deay driving data out as much as a few nanoseconds beyond the next rising edges of
the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
Rev: 1.07 8/2012
9/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Example Four Bank Depth Expansion Schematic
R/W
3
LD
3
R/W
2
LD
2
R/W
1
LD
R/W
1
0
LD
0
A –A
0
n
K
D –D
1
n
Bank 3
Bank 1
Bank 2
Bank 0
A
A
A
A
R/W
R/W
R/W
R/W
LD
LD
K
LD
K
LD
K
K
D
C
Q
D
C
Q
D
C
Q
D
C
Q
C
Q –Q
1
n
Note:
For simplicity BWn is not shown.
Rev: 1.07 8/2012
10/36
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GS8342S08/09/18/36AE-250/200/167
Burst of 2 SigmaSIO DDR-II SRAM Depth Expansion
Write A
Read B
Write C
Read D
Write E
Read F
Read G
Read H
NOP
K
K
Address
A
B
C
D
E
F
G
H
LD(Bank_1)
LD(Bank_2)
R/W(Bank_1)
R/W(Bank_2)
BWx(Bank_1)
BWx(Bank_2)
D(Bank_1)
D(Bank_2)
C(Bank_1)
C(Bank_1)
Q(Bank_1)
CQ(Bank)1
CQ(Bank_1)
C(Bank_2)
C(Bank_2)
Q(Bank_2)
CQ(Bank_2)
CQ(Bank_2)
A
A
A+1
A+1
E
E
E+1
E+1
C
C
C+1
C+1
D
D+1
G
B
B+1
F
F+1
Rev: 1.07 8/2012
11/36
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
Current
A
LD
R/W
D
D
Q
Q
Operation
K ↑
K ↑
K ↑
K ↑
K ↑
K ↑
K ↑
K ↑
(t )
(t )
(t )
(t )
(t
)
(t
)
(t
)
½
(t
)
n
n
n
n
n+1
n+1
n+1
Hi-Z
Q0
n+2
X
V
1
0
0
X
1
0
Deselect
Read
X
—
—
X
—
Q1
—
V
Write
D0
D1
Hi-Z
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data trferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
Rev: 1.07 8/2012
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
x18 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K ↑
K ↑
K ↑
K ↑
K ↑
(t
)
(t
)
(t )
(t
)
(t
)
n+1
n+2
n
n+1
n+2
Write
T
T
D1
D2
Dx stored if BWn = 0 in both data transfers
Write
T
F
F
F
T
F
D1
X
X
D2
X
Dx stored if BWn = 0 in 1st data transfer only
Write
Dx stored if BWn = 0 in 2nd data transfer only
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
x36 Byte Write Enable (BWn) Truth Table
BW3
BW2 BW1 BW0
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D0–D8
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
x8 Nybble Write Enable (NWn) Truth Table
NW1
NW0
D9–D17
Don’t Care
Don’t Care
Data In
D0–D8
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
Voltage on V Pins
DD
–0.5 to 2.9
V
DD
V
Voltage in V
Voltage in V
Pins
Pins
–0.5 to V
V
V
DDQ
DDQ
REF
DD
V
–0.5 to V
REF
DDQ
V
–0.5 to V
–0.5 to V
+0.3 (≤ 2.9 V max.)
Voltage on I/O Pins
V
I/O
DDQ
DDQ
V
+0.3 (≤ 2.9 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
V
IN
I
+/–100
+/–100
125
mA dc
mA dc
IN
I
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
OUT
o
T
C
J
o
T
–55 to 125
C
STG
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are eceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
Min.
1.7
Typ.
1.8
—
Max.
1.9
Unit
V
V
V
V
DD
V
I/O Supply Voltage
Reference Voltage
1.4
1.9
DDQ
V
0.68
—
0.95
REF
Notes:
1. Unless otherwise noted, all performance spcifications quoted are evaluated for worst case at both 1.4 V ≤ V
≤ 1.6 V (i.e., 1.5 V I/O)
DDQ
and 1.7 V ≤ V
≤ 1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
DDQ
2. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The
DD DDQ REF
power down sequence must be the reverse. V
must not exceed V .
DD
DDQ
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
T
0
25
70
°C
A
Ambient Temperature
(Industrial Range Versions)
T
–40
25
85
°C
A
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
HSTL I/O DC Input Characteristics
Parameter
DC Input Logic High
Symbol
Min
Max
Units
mV
Notes
V
(dc)
V
+ 0.1
V
+ 0.3
DDQ
1
1
IH
REF
V (dc)
V
– 0.1
REF
DC Input Logic Low
–0.3
mV
IL
Note:
Compatible with both 1.8 V and 1.5 V I/O drivers
HSTL I/O AC Input Characteristics
Parameter
AC Input Logic High
Symbol
Min
Max
Units
Notes
2,3
V
(ac)
V
+ 0.2
REF
—
mV
mV
mV
IH
V (ac)
V
– 0.2
REF
AC Input Logic Low
—
—
2,3
IL
V
Peak-to-Peak AC Voltage
V
(ac)
5% V
(DC)
REF
1
REF
REF
Notes:
1. The peak-to-peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks mst be within 10% of each other.
IH IL
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKHKH
V
+ 1.0 V
DD
V
SS
50%
50%
V
DD
V
– 1.0 V
SS
20% tKHKH
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
Output Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
pF
OUT
Note:
This parameter is sample tested.
Rev: 1.07 8/2012
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
AC Test Conditions
Parameter
Conditions
V
Input high level
Input low level
DDQ
0 V
Max. input slew rate
Input reference level
2 V/ns
V
V
/2
/2
DDQ
DDQ
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
= 0.75 V
V
REF
50Ω
VT = V /2
DDQ
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–2 uA
2 uA
IL
V
≥ V ≥ V
IN
–100 uA
–2 uA
2 uA
2 uA
DD
IL
IL
I
Doff
INDOFF
0 V ≤ V ≤ V
IN
Output Disable,
= 0 to V
I
Output Leakage Current
–2 uA
2 uA
OL
V
OUT
DDQ
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Max.
Units Notes
V
V
V
/2 – 0.12
V
V
/2 + 0.12
DDQ
Output High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
1, 3
2, 3
4, 5
4, 6
OH1
DDQ
V
/2 – 0.12
– 0.2
/2 + 0.12
DDQ
OL1
DDQ
V
V
V
DDQ
OH2
DDQ
V
Output Low Voltage
Vss
0.2
OL2
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
OL
DDQ
OL
DDQ
3. Parameter tested with RQ = 250Ω and V
4. 0Ω ≤ RQ ≤ ∞Ω
= 1.5 V or 1.8 V
DDQ
5.
I
= –1.0 mA
OH
OL
6.
I
= 1.0 mA
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Operating Currents
-250
-200
-167
Parameter
Symbol
Test Conditions
Notes
0
to
–40
to
0
to
–40
to
0
to
–40
to
70°C
85°C
70°C
8°C
70°C
85°C
VDD = Max, IOUT = 0 mA
650
mA
600
mA
500
mA
IDD
IDD
IDD
IDD
Operating Current (x36): DDR
Operating Current (x18): DDR
Operating Current (x9): DDR
Operating Current (x8): DDR
660 mA
610 mA
560 mA
560 mA
610 mA
560 mA
510 mA
510 mA
510 mA
460 mA
410 mA
410 mA
2, 3
2, 3
2, 3
2, 3
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
600
mA
50
mA
450
mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
550
mA
500
mA
400
mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
550
mA
500
mA
400
mA
Cycle Time ≥ tKHKH Min
Device deselected,
IOUT = 0 mA, f = Max,
220
mA
210
mA
200
mA
ISB1
Standby Current (NOP): DDR
230 mA
220 mA
210 mA
2, 4
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
1.
2.
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
3.
4.
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
AC Electrical Characteristics
-250
-200
-167
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tCHCH
K, K Clock Cycle Time
C, C Clock Cycle Time
4.0
—
8.4
0.2
—
5.0
—
8.4
0.2
—
6.0
—
8.4
0.2
—
ns
ns
ns
tKCVar
tTKC Variable
5
tKHKL
tCHCL
K, K Clock High Pulse Width
C, C Clock High Pulse Width
1.6
2.0
2.4
tKLKH
tCLCH
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
1.6
1.8
1.8
—
—
—
2.0
2.2
2.2
—
—
—
2.4
2.7
2.7
—
—
—
ns
ns
ns
tKHKH
tCHCH
K to K High
C to C High
tKHKH
tCHCH
K to K High
C to C High
tKHCH
tKCLock
tKCReset
K, K Clock High to C, C Clock High
DLL Lock Time
0
1.8
—
0
2.3
—
0
2.8
—
ns
cycle
ns
1024
30
1024
30
1024
30
6
K Static to DLL reset
—
—
—
Output Times
tKHQV
tCHQV
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
—
0.45
—
—
0.45
—
—
–0.5
—
0.5
—
ns
ns
ns
ns
3
3
tKHQX
tCHQX
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
–0.45
—
–0.45
—
tKHCQV
tCHCQV
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
0.45
—
0.45
—
0.5
—
tCQX
tCHCQX
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
–0.45
–0.45
–0.5
tCQHQV
tCQHQX
tCQHCQH
tCQHCQH
tKHQZ
tCHQZ
tKHQX1
tCHQX1
CQ, CQ High Output Valid
CQ, CQ High Output Hold
—
0.30
—
—
0.35
—
—
0.40
—
ns
ns
7
7
–0.30
–0.35
–0.40
CQ Phase Distortion
1.55
—
—
0.45
—
1.95
—
—
0.45
—
2.45
—
—
0.5
—
ns
ns
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
3
3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
–0.45
–0.45
–0.5
Setup Times
tAVKH
tIVKH
Address Input Setup Time
0.5
0.5
—
—
—
0.6
0.6
0.4
—
—
—
0.7
0.7
0.5
—
—
—
ns
ns
ns
Control Input Setup Time
Data Input Setup Time
2
tDVKH
0.35
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GS8342S08/09/18/36AE-250/200/167
AC Electrical Characteristics (Continued)
-250
-200
-167
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.5
0.5
—
—
—
0.6
0.6
0.4
—
—
—
0.7
0.7
0.5
—
—
—
ns
ns
ns
Control Input Hold Time
tKHDX
Data Input Hold Time
0.35
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
3. If C, C are tied high, K, K become the references for C, C timing parameters
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-
tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX
parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-
tures.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6.
V
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.
D
D
D
D
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
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GS8342S08/09/18/36AE-250/200/167
Rev: 1.07 8/2012
22/36
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Rev: 1.07 8/2012
23/36
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Rev: 1.07 8/2012
24/36
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GS8342S08/09/18/36AE-250/200/167
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25/36
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register hods the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.07 8/2012
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© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Regiser
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.07 8/2012
27/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
ID Register Contents
GSI Technology
JEDEC Vendor
ID Code
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor ll input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significat bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.07 8/2012
28/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved tthe Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default stte identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.07 8/2012
29/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when he TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z except CQ.
SAMPLE-Z
RFU
010
011
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/PRELOAD
GSI
100
101
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
110
111
1
1
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expresed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.07 8/2012
30/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
Test Port Input Low Voltage
V
V
1
1
ILJ
DD
V
0.6 * V
V
+0.3
DD
Test Port Input High Voltage
IHJ
DD
I
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
V
V
– 200 mV
—
0.4
—
5, 6
5, 7
5, 8
5, 9
OHJ
DD
V
—
V
OLJ
V
– 100 mV
V
OHJC
DD
V
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V
+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
ILJn
3. 0 V ≤ V ≤ V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V supply.
DD
6.
7.
8.
9.
I
I
I
I
= –2 mA
OHJ
= + 2 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
TDO
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
/2
DD
V
V
/2
Input reference level
DD
* Distributed Test Jig Capacitance
/2
Output reference level
DD
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.07 8/2012
31/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Rev: 1.07 8/2012
32/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.07 8/2012
33/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaSIODDR-II SRAM
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
A
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
4M x 9
GS8342S36AE-250
GS8342S36AE-200
GS8342S36AE-167
GS8342S36AE-250I
GS8342S36AE-200I
GS8342S36AE-167I
GS8342S18AE-250
GS8342S18AE-200
GS8342S18AE-167
GS8342S18AE-250I
GS8342S18AE-200I
GS8342S18AE-167I
GS8342S09AE-250
GS8342S09AE-200
GS8342S09AE-167
GS8342S09AE-250I
GS8342S09AE-200I
GS8342S09AE-167I
GS8342S08AE-250
GS8342S08AE-200
GS8342S08AE-167
GS8342S08AE-250I
GS8342S08AE-200I
GS8342S08AE167I
GS8342S36AGE-250
GS8342S36AGE-200
GS832S36AGE-167
GS8342S36AGE-250I
GS8342S36AGE-200I
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
165-Pin BGA
165-Pin BGA
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
C
C
C
I
165-Pin BGA
165-Pin BGA
165-Pin BGA
I
165-Pin BGA
I
165-Pin BGA
C
C
C
I
165-Pin BGA
165-Pin BGA
165-Pin BGA
165-Pin BGA
I
165-Pin BGA
I
165-Pin BGA
C
C
C
I
4M x 9
165-Pin BGA
4M x 9
165-Pin BGA
4M x 9
165-Pin BGA
4M x 9
165-Pin BGA
I
4M x 9
165-Pin BGA
I
4M x 8
165-Pin BGA
C
C
C
I
4M x 8
165-Pin BGA
4M x 8
165-Pin BGA
4M x 8
165-Pin BGA
4M x 8
165-Pin BGA
I
4M x 8
165-Pin BGA
I
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
C
C
C
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8342S36AE-200T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.07 8/2012
34/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaSIODDR-II SRAM
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
A
1M x 36
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
4M x 9
4M x 9
4M x 9
4M x 9
4M x 9
4M x 9
4M x 8
4M x 8
4M x 8
4M x 8
4M x 8
4M x 8
GS8342S36AGE-167I
GS8342S18AGE-250
GS8342S18AGE-200
GS8342S18AGE-167
GS8342S18AGE-250I
GS8342S18AGE-200I
GS8342S18AGE-167I
GS8342S09AGE-250
GS8342S09AGE-200
GS8342S09AGE-167
GS8342S09AGE-250I
GS8342S09AGE-200I
GS8342S09AGE-167I
GS8342S08AGE-250
GS8342S08AGE-200
GS8342S08AGE-167
GS8342S08AGE-250I
GS8342S08AGE-200I
GS8342S08AGE-167I
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
SigmaSIO DDR-II SRAM
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-PBGA
RoHS-compliant 165Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
RoHS-compliant 165-Pin BGA
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
250
200
167
I
C
C
C
I
I
I
C
C
C
I
I
I
C
C
C
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8342S36AE-200T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.07 8/2012
35/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342S08/09/18/36AE-250/200/167
SigmaSIO DDR-II Revision History
File Name
Format/Content
Description of changes
8342SxxA_r1
Creation of datasheet
• Updated MAX tKHKH
8342SxxA_r1; 8342SxxA_r1_01
Content
Content
• (Rev. 1.01a: Updated Note 4 in HSTL Output Driver DC Electrical
Characteristics table)
• Updated tKHKH, tKHCH in AC Char table
• Added tKHKH and CQ Phase Distortion to AC Char table
8342SxxA_r1_01; 8342SxxA_r1_02
• Added Power-up sequencsection
• Added CZ operating current data
8342SxxA_r1_02; 8342SxxA_r1_03
8342SxxA_r1_03; 8342SxxA_r1_04
Content
Content
• Updated status to PQ
• Added V
note to Pin Description table
REF
8342SxxA_r1_04; 8342SxxA_r1_05
Content
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status
• Updated 165 BGA Package Mechanical Drawing
• UpdateHSTL I/O AC Input Definitions
• (Rev1.06a: Editorial updates)
8342SxxA_r1_05; 8342SxxA_r1_06
8342SxxA_r1_06; 8342SxxA_r1_07
Content
Content
• Removed 333 & 300 MHz bins
Rev: 1.07 8/2012
36/36
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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