GS8342R18AE-300I_技术文档

GS8342R08/09/18/36AE-333/300/250/200/167

167 MHz–333 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

36Mb SigmaDDR-II™

Burst of 4 SRAM

1.8 V V

DD

1.8 V and 1.5 V I/O

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Features

• Simultaneous Read and Write SigmaDDR-II™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Each internal read and write operation in a SigmaDDR-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed.

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

When a new address is loaded into a x18 or x36 version of the

part, A0 and A1 are used to initialize the pointers that control

the data multiplexer / de-multiplexer so the RAM can perform

"critical word first" operations. From an external address point

of view, regardless of the starting point, the data transfers

always follow the same linear sequence {00, 01, 10, 11} or

{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where

the digits shown represent A1, A0).

SigmaDDR-II™ Family Overview

The GS8342R08/09/18/36AE are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342R08/09/18/36AE SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Unlike the x18 and x36 versions, the input and output data

multiplexers of the x8 and x9 versions are not preset by

address inputs and therefore do not allow "critical word first"

operations. The address fields of the x8 and x9 SigmaDDR-II

B4 RAMs are two address pins less than the advertised index

depth (e.g., the 4M x 8 has a 1M addressable index, and A0 and

A1 are not accessible address pins).

Clocking and Addressing Schemes

The GS8342R08/09/18/36AE SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

Parameter Synopsis

-333

-300

3.3 ns

-250

4.0 ns

-200

-167

tKHKH

tKHQV

3.0 ns

5.0 ns

6.0 ns

0.5 ns

0.45 ns 0.45 ns 0.45 ns 0.45 ns

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

1M x 36 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

NC

SA

R/W

BW2

K

BW1

LD

SA

NC

CQ

NC

Doff

NC

TDO

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

SA

BW3

SA

K

BW0

SA1

SA

NC

DQ17

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

V

SA0

V

SS

DQ29

NC

V

SS

DD

SS

DD

V

DQ15

NC

DDQ

DQ30

DQ31

V

DDQ

G

H

J

V

NC

V

REF

DDQ

NC

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

SA

NC

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

V

NC

SA

DQ33

NC

V

DDQ

SS

M

N

P

R

V

DQ11

NC

SS

DQ35

NC

V

SA

C

SA

V

SA

DQ9

TMS

TCK

C

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to

DQ27:DQ35

2. A2 and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs.

SS

Expansion Addresses

A10

A2

72Mb

144Mb

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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2M x 18 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

NC

SA

R/W

BW1

K

NC

LD

SA

CQ

NC

Doff

NC

TDO

DQ9

NC

SA

NC

SA

K

BW0

SA1

SA

NC

DQ7

NC

DQ8

NC

V

SA0

V

SS

NC

DQ10

DQ11

NC

V

NC

SS

DD

SS

DD

NC

V

NC

DQ6

DQ5

NC

DDQ

DQ12

NC

V

NC

DDQ

G

H

J

DQ13

V

NC

V

REF

ZQ

REF

DDQ

NC

DQ14

NC

DQ4

NC

K

L

V

NC

SA

DQ3

DQ2

NC

DQ15

NC

V

NC

DDQ

SS

M

N

P

R

NC

V

DQ1

NC

SS

NC

DQ16

DQ17

SA

V

SA

C

SA

V

NC

SA

NC

DQ0

TDI

TCK

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17

2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs.

SS

Expansion Address

A2

A7

B5

72Mb

144Mb

288Mb

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

4M x 9 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

NC

SA

R/W

NC

K

NC

LD

SA

CQ

NC

Doff

NC

TDO

NC

SA

NC

SA

K

BW

SA

NC

DQ4

NC

V

NC

V

SS

NC

V

NC

SS

DD

SS

DD

DQ5

NC

V

DQ3

NC

DDQ

V

DDQ

G

H

J

DQ6

V

NC

V

ZQ

REF

DDQ

REF

NC

DQ8

SA

NC

DQ2

NC

K

L

NC

DQ7

NC

V

NC

SA

NC

V

DQ1

NC

DDQ

SS

M

N

P

R

V

NC

SS

NC

V

SA

C

SA

V

NC

SA

NC

DQ0

TDI

TCK

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to

0 at the beginning of each access.

2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs.

SS

Expansion Address

A2

A7

B5

72Mb

144Mb

288Mb

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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4M x 8 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

NC

SA

R/W

NW1

K

NC

LD

SA

CQ

NC

Doff

NC

TDO

NC

SA

NC

SA

K

NW0

SA

NC

DQ3

NC

DQ2

NC

ZQ

V

NC

V

SS

NC

V

SS

DD

SS

DD

DQ4

NC

V

DDQ

V

DDQ

G

H

J

DQ5

V

REF

DDQ

NC

DQ7

SA

NC

DQ1

NC

DQ0

NC

TDI

K

L

NC

DQ6

NC

V

NC

SA

NC

V

DDQ

SS

M

N

P

R

V

NC

SS

NC

V

SA

C

SA

V

NC

SA

NC

TCK

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to

0 at the beginning of each access.

2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7

3. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V , NC, or MCL by some vendors of compatible SRAMs.

SS

Expansion Address

A2

A7

B5

72Mb

144Mb

288Mb

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Pin Description Table

Symbol

SA

Description

Synchronous Address Inputs

No Connect

Type

Input

—

Comments

—

NC

R/W

Synchronous Read/Write

Input

Active Low

x18/x36 only

BW0–BW3

NW0–NW1

Synchronous Byte Writes

Nybble Write Control Pin

Input

Active Low

x8 only

LD

K

Synchronous Load Pin

Input Clock

Input

Active Low

Active High

K

Input Clock

Input

Active Low

C

Output Clock

Input

Active High

C

Output Clock

Input

Active Low

TMS

TDI

TCK

TDO

Test Mode Select

Test Data Input

Input

—

Input

—

Test Clock Input

Input

—

Test Data Output

HSTL Input Reference Voltage

Output Impedance Matching Input

Data I/O

Output

Input

—

V

—

REF

ZQ

DQ

Doff

CQ

Input

Input/Output

Input

Three State

Active Low

—

Disable DLL when low

Output Echo Clock

Power Supply

Output

Supply

—

V

1.8 V Nominal

DD

V

Isolated Output Buffer Supply

Power Supply: Ground

Supply

1.5 V Nominal

—

DDQ

V

SS

Notes:

1. NC = Not Connected to die or any other pin.

2. C, C, K, or K cannot be set to V voltage.

REF

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are

unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated

in the timing diagrams. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less

often, if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from

loading read or write command

inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.

SigmaDDR-II B4 SRAM Read Cycles

The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst

transfer in

response to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins

are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined

reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces

data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data

is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of

four transfers per address load.

SigmaDDR-II B4 SRAM Write Cycles

The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst

transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/

W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is

checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the

rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst

of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the

next rising edge of K#, for a total of four transfers per address load.

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Power-Up Sequence for SigmaQuad-II SRAMs

SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.

Power-Up Sequence

1. Power-up and maintain Doff at low state.

1a. Apply V_DD

.

1b. Apply V_DDQ

.

1c. Apply V_REF(may also be applied at the same time as V_DDQ).

2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.

3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.

Note:

The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of clean K clocks are always required to re-

lock the DLL after reset.

DLL Constraints

• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t_KCVar).

• The DLL cannot operate at a frequency lower than that specified by the t_KHKHmaximum specification for the desired operating clock frequency.

• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during

the initial stage.

Note:

If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.

Special Functions

Byte Write and Nybble Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,

“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample

BW0

BW1

D0–D8

D9–D17

Time

Beat 1

Beat 2

Beat 3

Beat 4

0

1

0

1

0

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Written

Unchanged

Written

Unchanged

Written

Beat 1

Beat 2

Beat 3

Beat 4

Output Register Control

SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Example Four Bank Depth Expansion Schematic

LD

3

R /W

3

LD

2

R /W

2

1

0

LD

1

R /W

1

LD

0

R /W

0

A –A

0

n

K

Bank 3

Bank 1

Bank 2

Bank 0

A

R/W

LD

CQ

K

CQ

K

CQ

DQ

CQ

DQ

K

DQ

DQ -DQ

1

n

CQ

0

CQ

1

CQ

2

3

Note:

For simplicity BWn not shown.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps.

Common I/O SigmaDDR-II B4 SRAM Truth Table

DQ

K

LD

R/W

Operation

n

A + 0

Hi-Z

A + 1

Hi-Z

A + 2

Hi-Z

A + 3

Hi-Z

↑

1

0

X

0

Deselect

Write

D@K

n+2

↑

n+1

n+2

Q@K

or

Q@K

or

Q@K

or

Q@K

or

n+1

n+2

n+3

↑

0

1

Read

C

n+1

n+2

n+3

Note:

Q is controlled by K clocks if C clocks are not used.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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B4 Byte Write Clock Truth Table

BW

Current Operation

D

K ↑

n+1

K ↑

n+2

K ↑

n+2½

K ↑

n+1

K ↑

n+1½

K ↑

n+2

K ↑

n+2½

K ↑

(t_n+1½

(t

)

(t

)

(t

)

(t

)

(t

)

(t

)

(t

)

(t )

n

Write

T

F

T

F

T

D0

D2

D3

D4

Dx stored if BWn = 0 in all four data transfers

Write

T

F

T

F

T

F

D0

X

D1

X

Dx stored if BWn = 0 in 1st data transfer only

Write

Dx stored if BWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if BWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if BWn = 0 in 4th data transfer only

Write Abort

F

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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B4 Nybble Write Clock Truth Table

NW

Current Operation

D

K ↑

n+1

K ↑

n+1½

K ↑

n+2

K ↑

n+2½

K ↑

n+1

K ↑

n+1½

K ↑

n+2

K ↑

n+2½

(t

)

(t

)

(t

)

(t

)

(t

)

(t

)

(t

)

(t

)

(t )

n

Write

T

D0

D2

D3

D4

Dx stored if NWn = 0 in all four data transfers

Write

T

F

T

F

T

F

T

F

D0

X

D1

X

Dx stored if NWn = 0 in 1st data transfer only

Write

Dx stored if NWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if NWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if NWn = 0 in 4th data transfer only

Write Abort

F

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more NWn = 0, then NW = “T”, else NW = “F”.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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x36 Byte Write Enable (BWn) Truth Table

BW0 BW1 BW2 BW3

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

D18–D26

Don’t Care

Data In

D27–D35

Don’t Care

Data In

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

x18 Byte Write Enable (BWn) Truth Table

BW0 BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

x8 Nybble Write Enable (NWn) Truth Table

NW0 NW1

D0–D3

Don’t Care

Data In

D4–D7

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

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Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

DD

–0.5 to 2.9

V

DD

V

Voltage in V

Pins

–0.5 to V

V

DDQ

REF

DD

V

–0.5 to V

REF

DDQ

V

–0.5 to V

+0.5 (≤ 2.9 V max.)

Voltage on I/O Pins

V

I/O

DDQ

V

+0.5 (≤ 2.9 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

V

IN

I

+/–100

125

mA dc

IN

I

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

OUT

o

T

C

J

o

T

–55 to 125

C

STG

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

Min.

1.7

Typ.

1.8

—

Max.

1.9

Unit

V

DD

V

I/O Supply Voltage

Reference Voltage

1.4

1.9

DDQ

V

0.68

—

0.95

REF

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V

≤ 1.6 V (i.e., 1.5 V I/O)

DDQ

and 1.7 V ≤ V

≤ 1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.

DDQ

2. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The

DD DDQ REF

power down sequence must be the reverse. V

must not exceed V ..

DDQ

DD

Operating Temperature

Parameter

Symbol

Min.

Typ.

Max.

Unit

Ambient Temperature

(Commercial Range Versions)

T

0

25

70

°C

A

Ambient Temperature

(Industrial Range Versions)

T

–40

25

85

°C

A

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HSTL I/O DC Input Characteristics

Parameter

DC Input Logic High

Symbol

Min

Max

Units

Notes

V

(dc)

V

+ 0.10

V

+ 0.3 V

DD

V

1

IH

REF

V (dc)

– 0.10

DC Input Logic Low

–0.3 V

IL

REF

Notes:

1. Compatible with both 1.8 V and 1.5 V I/O drivers.

2. These are DC test criteria. DC design criteria is V

± 50 mV. The AC V /V levels are defined separately for measuring timing parame-

REF

IH IL

ters.

3. V (Min) DC = –0.3 V, V (Min) AC = –1.5 V (pulse width ≤ 3 ns).

IL

4.

V

(Max) DC = V

+ 0.3 V, V (Max) AC = V

+ 0.85 V (pulse width ≤ 3 ns).

IH

DDQ

IH

DDQ

HSTL I/O AC Input Characteristics

Parameter

AC Input Logic High

Symbol

Min

Max

Units

Notes

2,3

V

(ac)

V

+ 0.20

REF

—

V

IH

V (ac)

V

– 0.20

REF

AC Input Logic Low

—

2,3

IL

V

Peak-to-Peak AC Voltage

V

(ac)

5% V

(DC)

REF

—

1

REF

Notes:

1. The peak-to-peak AC component superimposed on V

may not exceed 5% of the DC component of V

.

REF

2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.

IH IL

3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKHKH

V

+ 1.0 V

DD

V

SS

50%

V

DD

V

– 1.0 V

SS

20% tKHKH

V

IL

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Capacitance

o

(T = 25 C, f = 1 MHZ, V = 3.3 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

Output Capacitance

Clock Capacitance

4

6

5

7

6

IN

C

V

OUT

= 0 V

pF

OUT

C

—

pF

CLK

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Conditions

V

Input high level

Input low level

DDQ

0 V

Max. input slew rate

Input reference level

2 V/ns

V

/2

DDQ

Output reference level

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 Ω (HSTL I/O)

= 0.75 V

V

REF

50Ω

VT = V /2

DDQ

Input and Output Leakage Characteristics

Parameter

Symbol

Test Conditions

Min.

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–2 uA

2 uA

IL

V

≥ V ≥ V

IN

–100 uA

–2 uA

2 uA

DD

IL

I

Doff

INDOFF

0 V ≤ V ≤ V

IN

Output Disable,

= 0 to V

I

Output Leakage Current

–2 uA

2 uA

OL

V

OUT

DDQ

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Programmable Impedance HSTL Output Driver DC Electrical Characteristics

Parameter

Symbol

Min.

Max.

Units Notes

V

/2

V

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

V

1, 3

2, 3

4, 5

4, 6

OH1

DDQ

V

/2

DDQ

Vss

OL1

V

– 0.2

V

DDQ

OH2

DDQ

V

Vss

0.2

OL2

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

OL

DDQ

OL

DDQ

3. Parameter tested with RQ = 250Ω and V

4. 0Ω ≤ RQ ≤ ∞Ω

= 1.5 V or 1.8 V

DDQ

5.

I

= –1.0 mA

OH

6.

I

= 1.0 mA

OL

Operating Currents

-333

-300

-250

-200

-167

Parameter

Symbol

Test Conditions

Notes

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

V_DD= Max, I_OUT= 0 mA

Operating Current (x36):

DDR

550

mA

560

mA

500

mA

510

mA

450

mA

460

mA

400

mA

410

mA

350

mA

360

mA

I_DD

2, 3

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Operating Current (x18):

DDR

500

mA

510

mA

450

mA

460

mA

400

mA

410

mA

350

mA

360

mA

300

mA

310

mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Operating Current (x9):

DDR

450

mA

460

mA

400

mA

410

mA

350

mA

360

mA

300

mA

310

mA

250

mA

260

mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Operating Current (x8):

DDR

450

mA

460

mA

400

mA

410

mA

350

mA

360

mA

300

mA

310

mA

250

mA

260

mA

Cycle Time ≥ t_KHKHMin

Device deselected,

^OUT= 0 mA, f = Max,

Standby Current (NOP):

DDR

245

mA

255

mA

235

mA

245

mA

220

mA

230

mA

210

mA

220

mA

200

mA

210

mA

I_SB1

I

2, 4

^{All Inputs}≤ 0.2 V or ≥ V_DD– 0.2 V

Notes:

1.

2.

Power measured with output pins floating.

Minimum cycle, I_OUT= 0 mA

Operating current is calculated with 50% read cycles and 50% write cycles.

Standby Current is only after all pending read and write burst operations are completed.

3.

4.

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GS8342R08/09/18/36AE-333/300250/200/167

AC Electrical Characteristics

-333

-300

-250

-200

-167

Parameter

Symbol

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

t_KHKH

t_CHCH

K, K Clock Cycle Time

C, C Clock Cycle Time

3.0

—

5.0

0.2

—

3.3

—

5.0

0.2

—

4.0

—

8.4

0.2

—

5.0

—

8.4

0.2

—

6.0

—

8.4

0.2

—

ns

t_KCVar

tTKC Variable

6

t_KHKL

t_CHCL

K, K Clock High Pulse Width

C, C Clock High Pulse Width

1.2

1.32

1.6

2.0

2.4

t_KLKH

t_CLCH

K, K Clock Low Pulse Width

C, C Clock Low Pulse Width

1.2

—

1.32

1.49

—

1.6

1.8

—

2.0

2.2

—

2.4

2.7

—

ns

t_KHKH

t_CHCH

K to K High

C to C High

1.35

t_KHKH

t_CHCH

K to K High

C to C High

1.35

0

1.49

0

1.8

0

2.2

0

2.7

0

t_KHCH

t_KCLock

t_KCReset

K, K Clock High to C, C Clock High

DLL Lock Time

1.3

—

1.45

—

1.8

—

2.3

—

2.8

—

ns

cycle

ns

1024

30

1024

30

1024

30

1024

30

1024

30

7

K Static to DLL reset

—

Output Times

t_KHQV

t_CHQV

K, K Clock High to Data Output Valid

C, C Clock High to Data Output Valid

—

0.45

—

0.45

—

0.45

—

0.45

—

–0.5

—

0.5

—

ns

4

t_KHQX

t_CHQX

K, K Clock High to Data Output Hold

C, C Clock High to Data Output Hold

–0.45

—

–0.45

—

–0.45

—

–0.45

—

t_KHCQV

t_CHCQV

K, K Clock High to Echo Clock Valid

C, C Clock High to Echo Clock Valid

0.45

—

0.45

—

0.45

—

0.45

—

0.5

—

t_KHCQX

t_CHCQX

K, K Clock High to Echo Clock Hold

C, C Clock High to Echo Clock Hold

–0.45

–0.5

t_CQHQV

t_CQHQX

t_CQHCQH

t_KHQZ

t_CHQZ

t_KHQX1

t_CHQX1

CQ, CQ High Output Valid

CQ, CQ High Output Hold

—

0.25

—

0.27

—

0.30

—

0.35

—

0.40

—

ns

8

–0.25

–0.27

–0.30

–0.35

–0.40

CQ Phase Distortion

1.10

—

0.45

—

1.24

—

0.45

—

1.55

—

0.45

—

1.95

—

0.45

—

2.45

—

0.5

—

ns

K Clock High to Data Output High-Z

C Clock High to Data Output High-Z

4

K Clock High to Data Output Low-Z

C Clock High to Data Output Low-Z

–0.45

–0.5

Setup Times

t_AVKH

t_IVKH

t_DVKH

Address Input Setup Time

0.4

—

0.4

0.3

—

0.5

—

0.6

0.4

—

0.7

0.5

—

ns

Control Input Setup Time (RW, LD)

Control Input Setup Time (BWX, NWX)

Data Input Setup Time

2

3

0.4

0.5

0.28

0.35

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GS8342R08/09/18/36AE-333/300250/200/167

AC Electrical Characteristics (Continued)

-333

-300

-250

-200

-167

Parameter

Symbol

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Hold Times

t_KHAX

t_KHIX

t_KHDX

Address Input Hold Time

0.4

—

0.4

0.3

—

0.5

—

0.6

0.4

—

0.7

0.5

—

ns

Control Input Hold Time (RW, LD)

Control Input Hold Time (BWX, NWX)

2

3

0.4

0.5

Data Input Hold Time

0.28

0.35

Notes:

1.

2.

3.

4.

5.

All Address inputs must meet the specified setup and hold times for all latching clock edges.

Control singles are RW.

Control singles BW0, BW1, and NW0, NW1 for x8 and BW2, BW3 for x36

If C, C are tied high, K, K become the references for C, C timing parameters

To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN

parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two

SRAMs on the same board to be at such different voltages and temperatures.

6.

7.

Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

V_DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DDand input clock are stable.

8.

Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard

bands and test setup variations.

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JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DD

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

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Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

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ID Register Contents

GSI Technology

JEDEC Vendor

ID Code

Not Used

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0 1 1 0 1 1 0 0 1

0

1

X

0

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

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JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Rev: 1.06a 11/2011

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z except CQ.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

RFU

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.06a 11/2011

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

–0.3

Max.

Unit Notes

V

0.3 * V

Test Port Input Low Voltage

V

1

ILJ

DD

V

0.6 * V

V

+0.3

DD

Test Port Input High Voltage

IHJ

DD

I

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

–300

–1

1

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

– 200 mV

—

0.4

—

5, 6

5, 7

5, 8

5, 9

OHJ

DD

V

—

V

OLJ

V

– 100 mV

V

OHJC

DD

V

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –1 V < Vi < V

+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V supply.

DD

6.

7.

8.

9.

I

= –2 mA

OHJ

= + 2 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

TDO

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

*

50Ω

30pF

Input slew rate

V

/2

Input reference level

DD

V

/2

DD

/2

Output reference level

* Distributed Test Jig Capacitance

DD

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

Rev: 1.06a 11/2011

30/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

ns

TCK Cycle Time

50

—

20

10

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

ns

—

ns

—

ns

tTH

—

ns

Rev: 1.06a 11/2011

31/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Package Dimensions—165-Bump FPBGA (Package E)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.06a 11/2011

32/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Ordering Information—GSI SigmaDDR-II SRAM

Speed

2

Org

Part Number1

Type

Package

TA

(MHz)

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

4M x 8

4M x 9

2M x 18

GS8342R08AE-333

GS8342R08AE-300

GS8342R08AE-250

GS8342R08AE-200

GS8342R08AE-167

GS8342R08AE-333I

GS8342R08AE-300I

GS8342R08AE-250I

GS8342R08AE-200I

GS8342R08AE-167I

GS8342R09AE-333

GS8342R09AE-300

GS8342R09AE-250

GS8342R09AE-200

GS8342R09AE-167

GS8342R09AE-333I

GS8342R09AE-300I

GS8342R09AE-250I

GS8342R09AE-200I

GS8342R09AE-167I

GS8342R18AE-333

GS8342R18AE-300

GS8342R18AE-250

GS8342R18AE-200

GS8342R18AE-167

GS8342R18AE-333I

GS8342R18AE-300I

GS8342R18AE-250I

GS8342R18AE-200I

SigmaDDR-II B4 SRAM

165-Pin BGA

C

I

C

I

C

I

2M x 18

I

Notes:

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T.

2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Rev: 1.06a 11/2011

33/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Ordering Information—GSI SigmaDDR-II SRAM

Speed

2

Org

Part Number1

Type

Package

TA

(MHz)

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

2M x 18

1M x 36

4M x 8

4M x 9

GS8342R18AE-167I

GS8342R36AE-333

GS8342R36AE-300

GS8342R36AE-250

GS8342R36AE-200

GS8342R36AE-167

GS8342R36AE-333I

GS8342R36AE-300I

GS8342R36AE-250I

GS8342R36AE-200I

GS8342R36AE-167I

GS8342R08AGE-333

GS8342R08AGE-300

GS8342R08AGE-250

GS8342R08AGE-200

GS8342R08AGE-167

GS8342R08AGE-333I

GS8342R08AGE-300I

GS8342R08AGE-250I

GS8342R08AGE-200I

GS8342R08AGE-167I

GS8342R09AGE-333

GS8342R09AGE-300

GS8342R09AGE-250

GS8342R09AGE-200

GS8342R09AGE-167

GS8342R09AGE-333I

GS8342R09AGE-300I

GS8342R09AGE-250I

GS8342R09AGE-200I

GS8342R09AGE-167I

SigmaDDR-II B4 SRAM

165-Pin BGA

I

C

I

165-Pin BGA

I

165-Pin BGA

I

165-Pin BGA

I

165-Pin BGA

I

RoHS-compliant 165-Pin BGA

C

I

C

I

4M x 9

I

Notes:

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T.

2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Rev: 1.06a 11/2011

34/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Ordering Information—GSI SigmaDDR-II SRAM

Speed

2

Org

Part Number1

Type

Package

TA

(MHz)

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

2M x 18

1M x 36

GS8342R18AGE-333

GS8342R18AGE-300

GS8342R18AGE-250

GS8342R18AGE-200

GS8342R18AGE-167

GS8342R18AGE-333I

GS8342R18AGE-300I

GS8342R18AGE-250I

GS8342R18AGE-200I

GS8342R18AGE-167I

GS8342R36AGE-333

GS8342R36AGE-300

GS8342R36AGE-250

GS8342R36AGE-200

GS8342R36AGE-167

GS8342R36AGE-333I

GS8342R36AGE-300I

GS8342R36AGE-250I

GS8342R36AGE-200I

GS8342R36AGE-167I

SigmaDDR-II B4 SRAM

RoHS-compliant 165-Pin BGA

C

I

C

I

1M x 36

I

Notes:

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS834x36E-300T.

2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Rev: 1.06a 11/2011

35/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342R08/09/18/36AE-333/300250/200/167

Revision History

Types of

Changes

Format or

Content

Rev. Code: Old; New

Revisions

• Creation of new datasheet

GS8342RxxA_r1

• Updated MAX tKHKH

GS8342RxxA_r1; GS8342RxxA_r1_01

Content

• (Rev. 1.01a: Updated Note 4 in HSTL Output Driver DC Electri-

cal Characteristics table)

• Updated tKHKH, tKHCH in AC Char table

• Added tKHKH and CQ Phase Distortion to AC Char table

GS8342RxxA_r1_01; GS8342RxxA_r1_02

• Added Power-up sequence section

• Added CZ operating current numbers

GS8342RxxA_r1_02; GS8342RxxA_r1_03

GS8342RxxA_r1_03; GS8342RxxA_r1_04

Content

• Changed status to PQ

• Added V

note to Pin Description table

REF

GS8342RxxA_r1_04;

GS8342RxxA_r1_05

Content

• Updated FLXDrive-II Output Driver Impedance Control section

• Removed Preliminary banner due to production status

• Revised AC Characteristics Table

• Revised Four Bank Depth Expansion Schematic(pg. 10)

• Updated JTAG Port AC Test Conditions (pg. 31)

• Updated 165 BGA package drawing (pg. 33)

• (Rev1.06a: Editorial updates)

GS8342RxxA_r1_05;

GS8342RxxA_r1_06

Rev: 1.06a 11/2011

36/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8342R18AE-300I
厂家：	GSI TECHNOLOGY
描述：	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165 双倍数据速率静态存储器内存集成电路
文件：	总36页 (文件大小：667K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8342R18AE-300I [GSI]

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