GS8324Z72C-133IT [GSI]
ZBT SRAM, 512KX72, 10ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209;
| 型号： | GS8324Z72C-133IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 512KX72, 10ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器 |
| 文件： | 总46页 (文件大小：1157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
250 MHz–133MHz
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
2M x 18, 1M x 36, 512K x 72
2.5 V or 3.3 V V
DD
36Mb Sync NBT SRAMs
2.5 V or 3.3 V I/O
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• FT pin for user-configurable flow through or pipeline operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
Curr (x18) 365 335 305 265 245 215 mA
Curr (x36) 560 510 460 400 370 330 mA
Curr (x72) 660 600 540 460 430 380 mA
FLXDrive™
3.3 V
2.5 V
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Curr (x18) 360 330 305 260 240 215 mA
Curr (x36) 550 500 460 390 360 330 mA
Curr (x72) 640 590 530 450 420 370 mA
Sleep Mode
Flow
Through
2-1-1-1
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
tKQ
tCycle
6.0 6.5 7.5 8.5 10 11 ns
7.0 7.5 8.5 10 10 15 ns
Curr (x18) 235 230 210 200 195 150 mA
Curr (x36) 300 300 270 270 270 200 mA
Curr (x72) 350 350 300 300 300 220 mA
Core and Interface Voltages
3.3 V
2.5 V
The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
Curr (x18) 235 230 210 200 195 145 mA
Curr (x36) 300 300 270 270 270 190 mA
Curr (x72) 340 340 300 300 300 220 mA
circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
Rev: 1.00 10/2001
1/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z72B Pad Out
209-Bump BGA—Top View
1
2
3
4
E2
5
6
ADV
W
7
8
E3
9
10
11
A
B
C
D
DQG5
DQG6
DQG7
DQG8
DQG1
DQG2
DQG3
DQG4
A13
BC
BH
VSS
A14
NC
NC
NC
VDD
A15
A16
NC
NC
VDD
A17
BF
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
A
B
C
D
BG
BD
BB
E1
BE
BA
VSS
NC
VDDQ
G
NC
VDDQ
VDDQ
VSS
VDDQ
VSS
VDD
VDDQ
VSS
VDDQ
VSS
E
F
DQPG9
DQC4
DQC3
DQC2
DQC1
NC
DQPC9
DQC8
DQC7
DQC6
DQC5
NC
DQPF9
DQF8
DQF7
DQF6
DQF5
NC
DQPB9
DQF4
DQF3
DQF2
DQF1
NC
E
F
VSS
VDDQ
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDQ
VSS
ZQ
MCH
MCL
MCH
MCL
FT
G
H
J
G
H
J
VDDQ
VDDQ
VDDQ
VDDQ
K
L
CK
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
K
L
DQH1
DQH2
DQH3
DQH4
DQPD9
DQH5
DQH6
DQH7
DQH8
DQPH9
DQA5
DQA6
DQA7
DQA8
DQPA9
DQA1
DQA2
DQA3
DQA4
DQPE9
M
N
P
R
MCL
MCH
ZZ
M
N
P
R
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VDD
VDDQ
T
U
V
DQD8
DQD7
DQD6
DQD5
DQD4
DQD3
DQD2
DQD1
NC
A12
A8
NC
NC
A7
A3
LBO
A11
A1
PE
A18
A6
NC
A10
A5
DQE4
DQE3
DQE2
DQE1
DQE8
DQE7
DQE6
DQE5
T
U
V
NC
A9
NC
A4
W
TMS
TDI
A0
A2
TDO
TCK
W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001
2/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z36C Pad Out
209-Bump BGA—Top View
1
2
3
4
E2
5
6
ADV
W
7
8
E3
9
10
11
A
B
C
D
NC
NC
NC
NC
NC
NC
NC
NC
A13
BC
NC
VSS
A14
A19
NC
A15
A16
NC
NC
VDD
A17
NC
BA
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
A
B
C
D
NC
BD
BB
E1
NC
NC
VDDQ
VSS
NC
VDDQ
NC
G
VDDQ
VSS
VDDQ
VSS
VDD
VDD
VDDQ
VSS
VDDQ
VSS
E
F
NC
DQC4
DQC3
DQC2
DQC1
NC
DQPC9
DQC8
DQC7
DQC6
DQC5
NC
NC
NC
DQPB9
NC
E
F
VSS
VDDQ
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDQ
VSS
ZQ
MCH
MCL
MCH
MCL
FT
G
H
J
NC
NC
G
H
J
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
K
L
CK
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
NC
NC
K
L
NC
NC
DQA5
DQA6
DQA7
DQA8
DQPA9
DQA1
DQA2
DQA3
DQA4
NC
M
N
P
R
NC
NC
MCL
MCH
ZZ
M
N
P
R
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
NC
NC
NC
VDDQ
VDD
VDDQ
DQPD9
NC
T
U
V
DQD8
DQD7
DQD6
DQD5
DQD4
DQD3
DQD2
DQD1
NC
A12
A8
NC
NC
A7
A3
LBO
A11
A1
PE
A18
A6
NC
A10
A5
NC
NC
NC
NC
NC
NC
NC
NC
T
U
V
NC
A9
NC
A4
W
TMS
TDI
A0
A2
TDO
TCK
W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001
3/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18C Pad Out
209-Bump BGA—Top View
1
2
3
4
5
6
ADV
W
7
8
9
10
11
A
B
C
D
NC
NC
NC
NC
NC
NC
NC
NC
A13
BB
VDD
NC
A14
A19
NC
A15
A16
A20
NC
VSS
NC
A17
NC
BA
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
NC
VSS
NC
E1
NC
VSS
NC
NC
G
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
VSS
VDDQ
VSS
E
F
NC
DQB4
DQB3
DQB2
DQB1
NC
DQPB9
DQB8
DQB7
DQB6
DQB5
NC
NC
NC
NC
NC
E
F
VSS
VDDQ
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDQ
VSS
ZQ
MCH
MCL
MCH
MCL
FT
G
H
J
NC
NC
G
H
J
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
K
L
CK
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
NC
VDDQ
VSS
NC
NC
K
L
NC
NC
DQA5
DQA6
DQA7
DQA8
DQPA9
DQA1
DQA2
DQA3
DQA4
NC
M
N
P
R
NC
NC
MCL
VDD
ZZ
M
N
P
R
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
NC
NC
NC
VDDQ
VDD
VDDQ
NC
NC
T
U
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
A12
A8
NC
NC
A7
A3
LBO
A11
A1
PE
A18
A6
NC
A10
A5
NC
NC
NC
NC
NC
NC
NC
NC
T
U
V
NC
A9
NC
A4
W
TMS
TDI
A0
A2
TDO
TCK
W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001
4/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location
Symbol Type
Description
W6, V6
A0, A1
I
Address field LSBs and Address Counter Preset Inputs.
W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,
A3, A5, A7, B7, A9, U7
An
I
Address Inputs
B5
C7
A19
A20
I
I
Address Inputs (x36/x18 Versions)
Address Inputs (x18 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10 DQA1–DQA9
A10, B10, C10, D10, A11, B11, C11, D11, E11 DQB1–DQB9
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11 DQE1–DQE9
J11, H11, G11, F11, J10, H10, G10, F10, E10 DQF1–DQF9
DQC1–DQC9
DQD1–DQD9
I/O
I/O
Data Input and Output pins (x72 Version)
Data Input and Output pins (x36 Version)
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQG1–DQG9
DQH1–DQH9
L11, M11, N11, P11, L10, M10, N10, P10, R10 DQA1–DQA9
A10, B10, C10, D10, A11, B11, C11, D11, E11 DQB1–DQB9
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
DQC1–DQC9
DQD1–DQD9
L11, M11, N11, P11, L10, M10, N10, P10, R10 DQA1–DQA9
I/O
Data Input and Output pins (x18 Version)
J1, H1, G1, F1, J2, H2, G2, F2, E2
DQB1–DQB9
C9, B8
I
I
Byte Write Enable for DQA, DQB I/Os; active low
BA, BB
Byte Write Enable for DQC, DQD I/Os; active low
(x72/x36 Versions)
B3, C4
BC,BD
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
(x72 Version)
C8, B9, B4, C3
I
BE, BF, BG,BH
B5
C7
NC
NC
—
—
No Connect (x72 Version)
No Connect (x72/x36 Versions)
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,
B4, C3
NC
—
No Connect (x36/x18 Versions)
B3, C4
NC
NC
—
—
No Connect (x18 Version)
No Connect
C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,
K11, T4, T5, T7, T8, U3, U5, U9
K3
C6
A8
A4
D6
A6
CK
E1
I
I
I
I
I
I
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active low (x72/x36 Versions)
Chip Enable; active high (x72/x36 Versions)
Output Enable; active low
E3
E2
G
Burst address counter advance enable
ADV
Rev: 1.00 10/2001
5/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location
Symbol Type
Description
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
P6
I
I
I
I
I
ZZ
FT
L6
T6
LBO
MCH
MCH
MCL
MCL
W
G6, J6
N6
Must Connect High (x72 and x36 versions)
Must Connect Low
H6, J6, K6, M6
A8, N6
B6
Must Connect Low (x18 version)
Write Enable; active low
I
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36
Mode)
T7
PE
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
F6
I
ZQ
W3
W4
I
I
Scan Test Mode Select
Scan Test Data In
TMS
TDI
W8
O
I
Scan Test Data Out
TDO
TCK
VDD
W9
Scan Test Clock
A4, N6
I
Core power supply (x18 version)
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7
VDD
I
I
I
Core power supply
I/O and Core Ground
D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
VSS
E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
VDDQ
Output driver power supply
Rev: 1.00 10/2001
6/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z36B Pad Out
119-Bump BGA—Top View
1
2
3
4
5
6
7
A
VDDQ
A6
A7
A18
A8
A9
VDDQ
A
B
C
NC
NC
E2
A5
A4
A3
ADV
VDD
A15
A14
E3
NC
NC
B
C
A16
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
ZQ
E1
G
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
VDDQ
D
E
F
DQB
G
H
DQC
DQC
DQC
DQC
BC
A17
W
BB
DQB
DQB
DQB
DQB
G
H
VSS
VSS
J
VDDQ
DQD
VDD
NC
VDD
CK
NC
VDD
VDDQ
DQA
J
K
DQD
VSS
VSS
DQA
K
L
DQD
VDDQ
DQD
DQD
BD
NC
BA
DQA
DQA
DQA
L
M
VSS
CKE
VSS
VDDQ
M
N
P
R
DQD
DQD
NC
DQD
DQPD
A2
VSS
VSS
LBO
A1
A0
VSS
VSS
FT
DQA
DQPA
A13
DQA
DQA
PE
N
P
R
VDD
T
NC
NC
A10
TDI
A11
A12
A19
ZZ
T
U
VDDQ
TMS
TCK
TDO
NC
VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.00 10/2001
7/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18B Pad Out
119-Bump BGA—Top View
1
2
3
4
5
6
7
A
VDDQ
A6
A7
A18
A8
A9
VDDQ
A
B
C
NC
NC
VDD
A4
A3
ADV
VDD
A15
A14
VSS
NC
NC
B
C
A5
A16
D
E
F
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
ZQ
E1
G
VSS
VSS
VSS
DQPA
NC
NC
D
E
F
DQA
VDDQ
VDDQ
DQA
G
H
NC
DQB
NC
BB
A17
W
NC
NC
DQA
NC
G
H
DQB
VSS
VSS
DQA
J
VDDQ
NC
VDD
NC
VDD
CK
NC
VDD
NC
VDDQ
DQA
J
K
DQB
VSS
VSS
K
L
DQB
NC
NC
VDD
BA
DQA
NC
NC
L
M
VDDQ
DQB
VSS
CKE
VSS
VDDQ
M
N
P
R
DQB
NC
NC
DQPB
A2
VSS
VSS
LBO
A1
A0
VSS
VSS
FT
DQA
NC
NC
DQA
PE
N
P
R
NC
VDD
A13
T
NC
A10
A11
TDI
A20
A12
A19
NC
ZZ
T
U
VDDQ
TMS
TCK
TDO
VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.00 10/2001
8/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36 119-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
R2, C3, B3, C2, A2, A3, A5, A6, T3,
T5, R6, C5, B5, C6, G4, A4
An
I
Address Inputs
T4, T6
T2
An
NC
An
Address Input (x36 Version)
No Connect (x36 Version)
Address Input (x18 Version)
—
I
T2, T6, T4
K7, L7, N7, P7, K6, L6, M6, N6
H7, G7, E7, D7, H6, G6, F6, E6
H1, G1, E1, D1, H2, G2, F2, E2
K1, L1, N1, P1, K2, L2, M2, N2
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins. (x36 Version)
DQA9, DQB9,
DQC9, DQD9
P6, D6, D2, P2
I/O
I
Data Input and Output pins. (x36 Version)
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)
Data Input and Output pins (x18 Version)
L5, G5, G3, L3
BA, BB, BC, BD
DQA1–DQA9
D1, E2, G2, H1, K2, L1, M2, N1, P2 DQB1–DQB9
P7, N6, L6, K7, H6, G7, F6, E7, D6
I/O
L5, G3
BA, BB
NC
I
Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)
No Connect
B1, C1, R1, T1, U6, B7, C7, J3, J5
—
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3
NC
—
No Connect (x18 Version)
L4
K4
M4
H4
E4
B6
B2
F4
B4
T7
R5
R3
NC
CK
CKE
W
—
I
No Connect (x36 Version)
Clock Input Signal; active high
Clock Enable; active low
I
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low (x36 version)
Chip Enable; active high (x36 version)
Output Enable; active low
E2
I
G
I
ADV
ZZ
I
Burst address counter advance enable
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
I
FT
I
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],
High = High Impedance [Low Drive])
D4
ZQ
I
R7
U2
U3
PE
TMS
TDI
I
I
I
Parity Bit Enable; active low
Scan Test Mode Select
Scan Test Data In
Rev: 1.00 10/2001
9/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36 119-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
Scan Test Data Out
U5
U4
O
I
TDO
TCK
VDD
Scan Test Clock
J2, C4, J4, R4, J6
B2, L4
I
Core power supply
VDD
VSS
I
Core power supply (x18 version)
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
I
I
I
I/O and Core Ground
I/O and Core Ground (x18 version)
Output driver power supply
VSS
B6
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
Rev: 1.00 10/2001
10/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
36
D
Q
36
Register
E1
D
Q
36
Register
D
Q
FT
G
36
DQx0–DQx9
Power Down
Control
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.00 10/2001
11/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18 Die Layout
Inputs
Die A
x18
Die B
x18
TDI
TDO
TDI
TDO
16Mb
16Mb
18 I/Os
GS8324Z36 Die Layout
Inputs
Die A
x18
Die B
x18
TDI
TDO
TDI
TDO
16Mb
16Mb
18 I/Os
18 I/Os
GS8324Z72 Die Layout
Inputs
Die A
x36
Die B
x36
TDI
TDO
TDI
TDO
32Mb
32Mb
36 I/Os
36 I/Os
Rev: 1.00 10/2001
12/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.00 10/2001
13/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.00 10/2001
14/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Synchronous Truth Table (x72 and x36 209-Bump BGA)
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a
Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00 10/2001
15/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA)
Type Address E1 ZZ ADV W Bx G CKE CK DQ Notes
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
D
D
D
D
R
B
None
None
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered
into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs
when the W pin is sampled low but no Byte Write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off
during write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write
cycle, the bus will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/
Write signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00 10/2001
16/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.00 10/2001
17/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.00 10/2001
18/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.00 10/2001
19/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Pin
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Parity Enable
State
Function
Name
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
LBO
H
L
FT
ZZ
PE
ZQ
H or NC
L or NC
H
Active
Standby, IDD = ISB
L or NC Activate 9th I/O’s (x18/36 Mode)
H
L
Deactivate 9th I/O’s (x16/32 Mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
H or NC
Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and a pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.
Enable/Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Rev: 1.00 10/2001
20/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
x16/32/64 Mode (PE = 0) Read Parity Error Output Timing Diagram
CK
Address A
Address B
D Out A
Address C
D Out B
Address D
D Out C
Address E
D Out D
Address F
D Out E
DQ
tKQ
tLZ
tKQX
tHZ
QE
DQ
Err A
Err C
D Out A
D Out B
D Out C
D Out D
tKQ
tLZ
tKQX
tHZ
QE
Err A
Err C
Rev: 1.00 10/2001
21/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
x18/x36 Mode (PE = 1) Write Parity Error Output Timing Diagram
CK
DQ
D In A
D In B
D In C
tKQX
D In D
D In E
tKQ
tLZ
tHZ
QE
DQ
Err A
Err C
D In A
D In B
D In C
D In D
tKQX
tHZ
D In E
tKQ
tLZ
QE
Err A
Err C
BPR 1999.05.18
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Rev: 1.00 10/2001
22/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on . Not all vendors offer this option, however most mark as VDD or VDDQ on pipelined parts and VSS on flow through
parts. GSI NBT SRAMs are fully compatible with these sockets.
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
–0.5 to 4.6
Unit
V
Voltage on VDD Pins
VDDQ
VCK
Voltage in VDDQ Pins
–0.5 to 4.6
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
–0.5 to VDD +0.5 (£ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.00 10/2001
23/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Power Supply Voltage Ranges
Parameter
3.3 V Supply Voltage
Symbol
VDD3
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
V
V
V
VDD2
2.5 V Supply Voltage
2.3
2.5
2.7
3.3 V VDDQ I/O Supply Voltage
VDDQ3
VDDQ2
3.0
3.3
3.6
2.5 V VDDQ I/O Supply Voltage
Notes:
2.4
2.5
2.7
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
DDQ3
Parameter
Symbol
VIH
Min.
1.7
Typ.
—
Max.
Unit
Notes
VDD Input High Voltage
VDD Input Low Voltage
VDDQ I/O Input High Voltage
VDDQ I/O Input Low Voltage
VDD + 0.3
V
V
V
V
1
VIL
–0.3
1.7
—
0.8
1
VIHQ
VILQ
VDDQ + 0.3
—
1,3
1,3
–0.3
—
0.8
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
V
Range Logic Levels
DDQ2
Parameter
Symbol
VIH
Min.
Typ.
—
Max.
VDD + 0.3
0.3*VDD
Unit
Notes
VDD Input High Voltage
VDD Input Low Voltage
VDDQ I/O Input High Voltage
VDDQ I/O Input Low Voltage
0.6*VDD
V
V
V
V
1
VIL
–0.3
—
1
VIHQ
VILQ
0.6*VDD
VDDQ + 0.3
0.3*VDD
—
1,3
1,3
–0.3
—
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.00 10/2001
24/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
TA
TA
Ambient Temperature (Commercial Range Versions)
2
2
Ambient Temperature (Industrial Range Versions)
Note:
–40
25
85
°C
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
VDD
50%
V
SS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
6.5
6
Max.
7.5
7
Unit
pF
Input Capacitance
CI/O
VOUT = 0 V
Input/Output Capacitance (x36/x72)
Input/Output Capacitance (x18)
Note: These parameters are sample tested.
pF
CI/O
VOUT = 0 V
8.5
9.5
pF
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.00 10/2001
25/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
DQ
30pF*
50W
5pF*
225W
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–2 uA
2 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
100 uA
IIN1
ZZ and PE Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–100 uA
–1 uA
1 uA
1 uA
IIN2
FT, SCD, ZQ, DP Input Current
IOL
IOL
Output Disable, VOUT = 0 to VDD
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output Leakage Current (x36/x72)
Output Leakage Current (x18)
Output High Voltage
–1 uA
–2 uA
1.7 V
2.4 V
—
1 uA
2 uA
—
VOH2
VOH3
VOL
Output High Voltage
—
Output Low Voltage
0.4 V
Rev: 1.00 10/2001
26/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Rev: 1.00 10/2001
27/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
4.0
—
—
2.3
—
—
—
6.0
—
—
—
—
4.4
—
—
2.5
—
—
—
6.0
—
—
—
—
5.0
—
—
3.0
—
—
—
7.5
—
—
—
—
6.0
—
—
3.4
—
—
—
8.5
—
—
—
—
6.7
—
—
3.8
—
7.5
—
—
4.0
—
—
—
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
7.0
—
1.5
1.5
7.5
—
1.5
1.5
8.5
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
15.0
—
tLZ1
tKC
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
10.0
—
10.0 ns
Flow
Through
tKQX
3.0
3.0
1.3
1.5
3.0
3.0
1.3
1.5
3.0
3.0
1.3
1.5
3.0
3.0
1.3
1.5
3.0
3.0
1.5
1.7
3.0
3.0
1.7
2
—
—
—
—
ns
ns
ns
ns
tLZ1
tKH
tKL
—
—
Clock LOW Time
—
Clock to Output in
High-Z
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.5 1.5 3.8 1.5 4.0
ns
G to Output Valid
tOE
—
2.3
—
2.5
—
3.2
—
3.5
—
3.8
—
4.0
ns
ns
tOLZ1
G to output in Low-Z
0
—
0
—
0
—
0
—
0
—
0
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
2.3
—
—
—
—
1.5
0.5
5
2.5
—
—
—
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
4.0
—
—
—
ns
ns
ns
ns
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
100
100
100
100
100
100
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00 10/2001
28/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
(A4+1)
DQA–DQD
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tH
tS
tOEHZ
tOELZ
G
Write
D(A5)
Write
D(A2) Write
D(A2+1)
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.00 10/2001
29/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A5
A3
A4
tKHQZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQHZ
NOP
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
CONTINUE
DESELECT
Write
D(A1)
DESELECT
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.00 10/2001
30/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
A7
A0–An
A1
A2
A3
A4
A5
A6
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
DQ
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
(A4+1)
tOELZ
tKQX
tH
tS
tOEHZ
G
Write
D(A5)
Write
D(A2)
BURST Read
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
Write
Q(A3)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.00 10/2001
31/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
tKHQZ
Q(A3)
Q(A2)
D(A1)
Q(A5)
D(A4)
NOP
DQ
tKQHZ
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
DESELECT
CONTINUE
DESELECT
Write
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.00 10/2001
32/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
JTAG Port Operation
Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes
the behavior of each die.
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Rev: 1.00 10/2001
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.00 10/2001
34/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
Configuration
ID Code
I/O
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
1
1
x72
x36
x32
x18
x16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.00 10/2001
35/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
Rev: 1.00 10/2001
36/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.00 10/2001
37/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VIHJ3
VILJ3
Min.
2.0
Max.
Unit Notes
VDD3 +0.3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
–0.3
0.8
VIHJ2
VILJ2
0.6 * VDD2
VDD2 +0.3
0.3 * VDD2
V
1
–0.3
V
1
IINHJ
–300
1
100
1
uA
uA
uA
V
2
IINLJ
–1
3
IOLJ
–1
4
VOHJ
VOLJ
Test Port Output High Voltage
Test Port Output Low Voltage
1.7
—
—
5, 6
5, 7
5, 8
5, 9
0.4
V
VOHJC
VOLJC
VDDQ – 100 mV
Test Port Output CMOS High
—
V
Test Port Output CMOS Low
—
100 mV
V
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. ILJ £ VIN £ VDDn
V
3. 0 V £ VIN £ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
JTAG Port AC Test Load
2.3 V
0.2 V
DQ
Input low level
30pF*
Input slew rate
1 V/ns
1.25 V
1.25 V
50W
Input reference level
Output reference level
VT = 1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 1.00 10/2001
38/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
TCK Cycle Time
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tTH
—
ns
Rev: 1.00 10/2001
39/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 Boundary Scan Chain Order
Bump
Order
x72
x36
x18
x72 x36 x18
1(TBD)
Notes:
1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.
2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.
3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.
4. 1 = no connect, internally set to logic value 1
5. 0 = no connect, internally set to logic value 0
6. X = no connect, value is undefined
Rev: 1.00 10/2001
40/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
209 BGA Package Drawing
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1
A
Side View
D
aaa
D1
e
Bottom View
Æb
e
Symbol
Min
Typ
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
Æb
c
0.40
0.50
0.31
21.9
0.50
0.60
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
14.1
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
aaa
Rev 1.0
Rev: 1.00 10/2001
41/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Package Dimensions—119-Pin PBGA
119-Bump BGA Package
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
G
D
B
S
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
U
R
Bottom View
Top View
Package Dimensions—119-Pin PBGA
Symbol
Description
Width
Min. Nom. Max
13.9 14.0 14.1
21.9 22.0 22.1
A
B
Length
C
Package Height (including ball) 1.73 1.86 1.99
D
Ball Size
0.60 0.75 0.90
0.50 0.60 0.70
E
Ball Height
F
Package Height (excluding balls) 1.16 1.26 1.36
G
Width between Balls
Package Height above board
Width of package between balls
Length of package between balls
Variance of Ball Height
1.27
K
0.65 0.70 0.75
R
7.62
20.32
0.15
S
T
Unit: mm
Side View
Rev: 1.00 10/2001
42/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Ordering Information for GSI Synchronous NBT SRAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
GS8324Z18B-250
GS8324Z18B-225
GS8324Z18B-200
GS8324Z18B-166
GS8324Z18B-150
GS8324Z18B-133
GS8324Z18C-250
GS8324Z18C-225
GS8324Z18C-200
GS8324Z18C-166
GS8324Z18C-150
GS8324Z18C-133
GS8324Z36B-250
GS8324Z36B-225
GS8324Z36B-200
GS8324Z36B-166
GS8324Z36B-150
GS8324Z36B-133
GS8324Z36C-250
GS8324Z36C-225
GS8324Z36C-200
GS8324Z36C-166
GS8324Z36C-150
GS8324Z36C-133
GS8324Z72C-250
GS8324Z72C-225
GS8324Z72C-200
GS8324Z72C-166
GS8324Z72C-150
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
250/6
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 10/2001
43/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Ordering Information for GSI Synchronous NBT SRAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
133/11
250/6
512K x 72
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
GS8324Z72C-133
GS8324Z18B-250I
GS8324Z18B-225I
GS8324Z18B-200I
GS8324Z18B-166I
GS8324Z18B-150I
GS8324Z18B-133I
GS8324Z18C-250I
GS8324Z18C-225I
GS8324Z18C-200I
GS8324Z18C-166I
GS8324Z18C-150I
GS8324Z18C-133I
GS8324Z36B-250I
GS8324Z36B-225I
GS8324Z36B-200I
GS8324Z36B-166I
GS8324Z36B-150I
GS8324Z36B-133I
GS8324Z36C-250I
GS8324Z36C-225I
GS8324Z36C-200I
GS8324Z36C-166I
GS8324Z36C-150I
GS8324Z36C-133I
GS8324Z72C-250I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
209 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 10/2001
44/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Ordering Information for GSI Synchronous NBT SRAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
225/6.5
200/7.5
166/8.5
150/10
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
GS8324Z72C-225I
GS8324Z72C-200I
GS8324Z72C-166I
GS8324Z72C-150I
GS8324Z72C-133I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
I
I
I
I
I
133/11
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 10/2001
45/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
36Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8324Z18_r1
Rev: 1.00 10/2001
46/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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