GS832218E-250V [GSI]
Cache SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165;
| 型号： | GS832218E-250V |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165 静态存储器 内存集成电路 |
| 文件： | 总42页 (文件大小：2057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS832218/36/72(B/E/C)-xxxV
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
250 MHz–133 MHz
2M x 18, 1M x 36, 512K x 72
36Mb S/DCD Sync Burst SRAMs
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Flow Through/Pipeline Reads
Features
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causig output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the ising-edge-triggered Data Output
Register.
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
• RoHS-compliant packages available
SCD and DCD Pipelined Reads
The GS832218/36/72-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read cmmands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
commanor one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Functional Description
Applications
The GS832218/36/72-xxxV is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
FLXDrive™
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Core and Interface Voltages
The GS832218/36/72-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuits and are 1.8 V or 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
tKQ
3.0
4.0
3.0
4.4
3.0
5.0
3.5
6.0
3.8
6.7
4.0
7.5
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x36)
Curr (x72)
285
350
440
265
320
410
245
295
370
220
260
320
210 185
240 215
300 265
mA
mA
mA
tKQ
6.5
6.5
7.0
7.0
7.5
7.5
8.0
8.0
8.5
8.5
8.5
8.5
ns
ns
tCycle
Flow
Through
2-1-1-1
Curr (x18)
Curr (x36)
Curr (x72)
205
235
315
195
225
295
185
210
265
175
200
255
165 155
190 175
240 230
mA
mA
mA
Rev: 1.07 9/2008
1/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
209-Bump BGA—x72 Common I/O—Top View (Package C)
1
2
3
4
5
ADSP
NC
6
ADSC
BW
E1
7
8
9
10
11
A
B
C
D
DQG
DQG
DQG
DQG
DQG
DQG
DQG
DQG
A
E2
BG
BD
NC
ADV
A
E3
BB
BE
NC
A
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
A
B
C
D
BC
BH
BF
BA
NC
NC
GW
V
V
SS
NC
G
SS
V
V
V
V
V
V
V
V
V
V
E
F
DQPG
DQC
DQC
DQC
DQC
NC
DQPC
DQC
DQC
DQC
DQC
NC
DQPF
DQF
DQF
DQF
DQF
NC
DQPB
DQF
DQF
DQF
DQF
NC
E
F
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
V
V
V
V
V
V
ZQ
MCH
MCL
MCL
MCL
FT
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
G
H
J
G
H
J
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
K
L
CK
NC
NC
NC
K
L
SS
V
V
V
V
V
V
DDQ
DQH
DQH
DQH
DQH
DQPD
DQH
DQH
DQH
DQH
DQPH
DQA
DQA
DQA
DQA
DQPA
DQA
DQA
DQA
DQA
DQPE
DDQ
DDQ
DD
DD
DDQ
V
V
V
V
V
V
SS
M
N
P
R
MCL
SCD
ZZ
M
N
P
R
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
V
V
V
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
V
V
T
U
V
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
NC
A
NC
A
LBO
A
NC
A
NC
A
DQE
DQE
DQE
DQE
DQE
DQE
DQE
DQE
T
U
V
SS
SS
NC
A
A
A
A
A1
A0
A
A
A
W
TMS
T
A
A
TDO
TCK
W
2
11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch
Rev: 1.07 9/2008
2/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
GS832272C-xxxV 209-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
I
I
Byte Write Enable for DQA, DQB I/Os; active low
Byte Write Enable for DQC, DQD I/Os; active low
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
No Connect
BA, BB
BC,BD
I
BE, BF, BG,BH
NC
CK
—
I
Clock Input Signal; active high
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1
I
Chip Enable; active low
E3
I
Chip Enable; active high
E2
I
Output Enable; active low
G
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADV
ADSP, ADSC
ZZ
I
I
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
FT
I
LBO
SCD
MCH
MCL
BW
I
I
Must Connect Low
I
I
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
ZQ
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
Rev: 1.07 9/2008
3/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
GS832272C-xxxV 209-Bump BGA Pin Description (Continued)
Symbol
Type
Description
V
I
I
I
Core power supply
DD
V
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.07 9/2008
4/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
165-Bump BGA—x18 Commom I/O—Top View (Package E)
1
2
3
4
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
NC
NC
NC
NC
ZQ
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCL
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
DQA
DQA
DQA
DQA
NC
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
SCD
NC
V
NC
TDI
A
NC
V
NC
DDQ
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
LBO
A
A
TMS
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.07 9/2008
5/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
165-Bump BGA—x36 Common I/O—Top View (Package E)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
SCD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
A
NC
V
SS
DDQ
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
LBO
A
A
TMS
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.07 9/2008
6/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
GS832218/36E-xxxV 165-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Osctive low (x36 Version)
No Connect
NC
CK
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Wtes all bytes; active low
Chip Enable; active low
GW
I
E1
I
E3
I
Chinable; active low
E2
I
Chip Enable; active high
G
ADV
I
Output Enable; active low
I
Burst address counter advance enable; active l0w
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
ADSC, ADSP
ZZ
I
I
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
TMS
TDI
O
I
Scan Test Data Out
TDO
TCK
MCL
SCD
Scan Test Clock
—
—
I
Must Connect Low
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Core power supply
V
DD
V
I/O and Core Ground
SS
V
I
Output driver power supply
DDQ
Rev: 1.07 9/2008
7/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
119-Bump BGA—x36 Common I/O—Top View
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
V
V
DDQ
A
B
C
D
E
F
ADSP
ADSC
A
B
C
D
E
F
DDQ
NC
NC
A
A
NC
NC
V
A
A
DD
V
V
DQC
DQC
DQPC
DQC
DQC
DQC
DQC
ZQ
E1
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
G
DDQ
G
H
J
DQC2
BC
ADV
GW
BB
DQB
G
H
J
V
V
SS
DQC
DQB
SS
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD
DDQ
DQA
DQA
V
V
K
L
DQD
DQD
DQD
DQD
DQD
DQD
DQPD
A
CK
SCD
BW
A1
DQA
DQA
DQA
DQA
DQPA
A
K
L
SS
SS
BD
BA
V
V
V
V
DDQ
M
N
P
R
T
M
N
P
R
T
DDQ
SS
SS
V
V
DQD
DQD
NC
DQA
SS
SS
V
V
A0
DQA
NC
ZZ
SS
SS
V
LBO
A
FT
A
DD
NC
NC
A
TCK
2
A
V
V
DDQ
U
TMS
TDI
TDO
NC
U
DDQ
7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch
Rev: 1.07 9/2008
8/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
119-Bump BGA—x18 Common I/O—Top View
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
V
V
DDQ
A
B
C
D
E
F
ADSP
ADSC
A
B
C
D
E
F
DDQ
NC
NC
A
A
NC
NC
V
A
A
DD
V
V
DQB
NC
NC
DQB
NC
DQB
NC
ZQ
E1
DQPA
NC
DQA
NC
DQA
NC
SS
SS
SS
SS
SS
SS
V
V
V
V
DQA
V
V
DDQ
G
DDQ
G
H
J
NC
BB
ADV
GW
NC
DQA
G
H
J
V
V
DQB
NC
SS
SS
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD
DDQ
DQA
NC
V
V
K
L
NC
DQB
NC
CK
SCD
BW
A1
NC
DQA
NC
DQA
NC
A
K
L
SS
SS
DQB
NC
BA
V
V
V
V
DDQ
M
N
P
R
T
DQB
NC
M
N
P
R
T
DDQ
SS
SS
V
V
DQB
NC
SS
SS
V
V
NC
NC
NC
DQPB
A
A0
DQA
NC
ZZ
SS
SS
V
LBO
A
FT
A
DD
A
A
TCK
2
A
V
V
DDQ
U
TMS
TDI
TDO
NC
U
DDQ
7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch
Rev: 1.07 9/2008
9/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
GS832218/36B-xxxV 119-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
BA, BB, BC, BD
NC
Clock Input Signal; active high
CK
I
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip nable; active low
BW
I
GW
I
E1
I
Output Enable; active low
G
ADV
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
I
ADSP, ADSC
ZZ
I
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FT
I
LBO
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I
ZQ
I
I
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Scan Test Mode Select
Scan Test Data In
SCD
TMS
TDI
I
O
I
Scan Test Data Out
TDO
TCK
Scan Test Clock
V
I
Core power supply
DD
V
V
I
I
I
I/O and Core Ground
I/O and Core Ground
SS
SS
V
Output driver power supply
DDQ
Rev: 1.07 9/2008
10/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
GS832218/36/72-xxxV Block Diagram
Register
A0–An
D
Q
A0
A0
A1
D0
D1
Q0
A1
Q1
Counter
Load
A
LBO
ADV
Memory
Aray
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
36
D
Q
36
36
Rister
D
E1
Q
Register
D
Q
FT
G
36
DCD=S
CD
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.07 9/2008
11/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
H or NC
L or NC
H
Output Register Control
FT
ZZ
Active
Power Down Control
Standby, I = I
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
Low Drive (High Impedance)
H or NC
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on te ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.07 9/2008
12/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Byte Write Truth Table
Function
Read
GW
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
H
H
H
H
H
H
H
L
Write No Bytes
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
L
2, 3
L
H
H
H
L
2, 3
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.07 9/2008
13/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Synchronous Truth Table
Operation
State
Diagram
Address
Used
3
E1
E2
E3
ADSP ADSC ADV
W
DQ
Key
X
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
L
L
L
L
H
L
X
L
H
X
H
X
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
X
High-Z
None
X
X
L
X
X
L
High-Z
None
X
L
High-Z
None
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
L
L
X
X
X
X
X
X
X
X
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Write Cycle, Suspend Burst
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.07 9/2008
14/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the iagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.07 9/2008
15/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.07 9/2008
16/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage on V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
–0.5 to V
+0.5 (≤ 4.6 V ax.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are eeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol
Min.
1.7
Typ.
1.8
Max.
2.0
Unit
Notes
V
1.8 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD1
V
2.3
2.5
2.7
DD2
1.8 V V
I/O Supply Voltage
V
V
1.7
1.8
DDQ
DDQ
DDQ1
DD
2.5 V V
I/O Supply Voltage
V
V
2.3
2.5
DDQ2
DD
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.07 9/2008
17/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
V
& V
Range Logic Levels
DDQ2
DDQ1
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
V
Notes
V
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
1
1
DD
IH
DD
Input Low Voltage
V
0.3*V
DD
–0.3
—
V
DD
IL
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
°C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
8
Max.
10
Unit
pF
C
V
= 0 V
Input Capacitance
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
12
14
pF
I/O
Note:
These parameters are sample tested.
Rev: 1.07 9/2008
18/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Figure 1
Output Load 1
Input slew rate
V
DQ
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
*
50Ω
30pF
Fig. 1
Notes:
V
DDQ/2
* Distributed Test Jig Capacitance
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
I
V
≥ V ≥ 0 V
DD IN
FT, SCD, ZQ, ZZ Input Current
Output Leakage Current
–100 uA
–1 uA
100 uA
1 uA
IN
I
Output Disable, V
= 0 to V
OL
OUT DD
DC Output Characteristics (1.8 V/2.5 V Version)
Parameter
Symbol
Test Conditions
Min
Max
—
V
I
= –4 mA, V
= 1.7 V
V
– 0.4 V
DDQ
1.8 V Output High Voltage
2.5 V Output High Voltage
1.8 V Output Low Voltage
2.5 V Output Low Voltage
OH1
OH
DDQ
V
I
= –8 mA, V
= 2.375 V
DDQ
1.7 V
—
OH2
OH
V
I
I
= 4 mA
= 8 mA
—
—
0.4 V
0.4 V
OL1
OL
OL
V
OL2
Rev: 1.07 9/2008
19/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS832218/36/72(B/E/C)-xxxV
Rev: 1.07 9/2008
20/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
4.0
—
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
4.4
—
—
3.0
—
—
—
—
—
7.0
—
—
—
—
—
5.0
—
—
3.0
—
—
—
—
—
7.5
—
—
—
—
—
6.0
—
—
3.5
—
—
—
—
—
8.0
—
—
—
—
—
6.7
—
—
3.8
—
—
—
—
—
8.5
—
—
—
—
—
7.5
—
—
4.0
—
—
—
—
—
8.5
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.5
0.2
6.5
—
1.5
1.5
1.5
0.3
7.0
—
1.5
1.5
1.5
0.4
7.5
—
1.5
1.5
1.5
0.5
8.0
—
1.5
1.5
1.5
0.5
8.5
—
1.5
1.5
1.5
0.5
8.5
—
Pipeline
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
Clock to Output Invalid
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.5
3.0
3.0
1.5
0.5
1.7
Flow
Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.7
1.5
—
1.7
1.5
—
1.7
1.5
—
1.7
1.5
—
1.7
1.5
—
2
—
ns
ns
Clock to Output in
High-Z (x18/x36)
tHZ1
2.5
2.7
3.0
3.0
3.0
1.5
3.0
Clock to Output in
High-Z (x72)
tHZ1
tOE
tOE
1.5
—
—
3.0
2.5
3.0
1.5
—
—
3.0
2.7
3.0
1.5
—
—
3.0
3.0
3.0
1.5
—
—
3.0
3.5
3.5
1.5
—
—
3.0
3.8
3.8
1.5
—
—
3.0
4.0
4.0
ns
ns
ns
G to Output Valid
(x18/x36)
G to Output Valid
(x72)
tOLZ1
tOHZ1
tOHZ1
tZZS2
tZZH2
tZZR
G to output in Low-Z
G to output in High-Z (x18/x36)
G to output in High-Z (x72)
ZZ setup time
0
—
—
5
—
2.5
3.0
—
—
—
0
—
—
5
—
2.7
3.0
—
—
—
0
—
—
5
—
3.0
3.0
—
—
—
0
—
—
5
—
3.0
3.0
—
—
—
0
—
—
5
—
3.0
3.0
—
—
—
0
—
—
5
—
3.0
3.0
—
—
—
ns
ns
ns
ns
ns
ns
ZZ hold time
1
1
1
1
1
1
ZZ reery
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.07 9/2008
21/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Pipeline Mode Timing (SCD)
Begin
Read A Cont
Single Read
Cont
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
Deselect
Single Write
tKL
Burst Read
tKH
tKC
CK
ADSP
tS
tS
tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
A
B
C
A0–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E1 masks ADSP
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
G
tS
D(B)
tKQ
tKQX
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
Q(C)
Q(C+1)
Q(C+2) Q(C+3)
DQa–DQd
Rev: 1.07 9/2008
22/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Flow Through Mode Timing (SCD)
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.07 9/2008
23/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Pipeline Mode Timing (DCD)
Begin
Read A Cont
Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
tKL
Deselect Deselect
tKH
tKC
CK
ADSP
tS
tS
ADSC initiated read
tH
ADSC
ADV
tS
tH
tH
A
B
C
Ao–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E2 and E3 only sampled with ADSC
tH
tH
E2
E3
G
tS
D(B)
tKQ
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
tKQX
Hi-Z
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
DQa–DQd
Rev: 1.07 9/2008
24/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Flow Through Mode Timing (DCD)
Begin
Read A Cont
tKH
Deselect Write B
tKC
Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tKL
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
Ao–An
GW
tH
tS
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tH
tS
Ba–Bd
E1
tS
Deselected with E1
tH
E1 masks ADSP
tS
tH
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
E2
tS
tH
E3
G
tH
tS
tOE
tKQ
tKQX
tHZ
tOHZ
D(B)
tLZ
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.07 9/2008
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asychronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. ThereforeSleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI nd TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Regiters is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falliedge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register tat can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also incudes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology
Not Used
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction egister are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
St DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s cntents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the istruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Registr between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
1.8 V Test Port Input Low Voltage
2.5 V Test Port Input Low Voltage
1.8 V Test Port Input High Voltage
2.5 V Test Port Input High Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
ILJ1
DD1
V
0.3 * V
DD2
–0.3
ILJ2
V
0.6 * V
V
V
+0.3
+0.3
V
1
IHJ1
DD1
DD1
DD2
V
0.6 * V
DD2
V
1
IHJ2
I
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
0.4
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTH
tTS
tTS
TDI
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Package Dimensions—209-Bump BGA (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
BOTTOM VIEW
M
M
Ø0.10
C
Ø0.30 C A B
Ø0.50~0.70 (209x)
A1 CORNER
TOP VIEW
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9 10 11
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
K
L
M
N
P
R
T
U
V
W
U
V
W
1.0
1.0
B
10.0
14.0
A
0.20(4x)
SEATING PLANE
C
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
A1
S
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
U
K
L
M
N
P
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.05
B
0.20(4x)
SEATING PLANE
C
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
GS832218B-250V
GS832218B-225V
GS832218B-200V
GS832218B-166V
GS832218B-150V
GS832218B-133V
GS832218E-250V
GS832218E-225V
GS832218E-200V
GS832218E-166V
GS832218E-150V
GS832218E-133V
GS832236B-250V
GS832236B-225V
GS832236B-200V
GS832236B-166V
GS832236B-150V
GS832236B-133V
GS832236E-250V
GS832236E-225V
GS832236E-200V
GS832236E-166V
GS832236E-150V
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DD
SC/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
119 BGA (var.2)
119 BGA (var.2)
119 BGA (vr.2)
119 BGA var.2)
119 BGA (var.2)
119 BGA (var.2)
165 BGA
250/6.5
225/7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
133/8.5
250/6.5
225/7
165 BGA
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
165 BGA
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
GS832236E-133V
GS832272C-250V
GS832272C-225V
GS832272C-200V
GS832272C-166V
GS832272C-150V
GS832272C-133V
GS832218B-250IV
GS832218B-225IV
GS832218B-200IV
GS832218B-166IV
GS832218B-150IV
GS832218B-133IV
GS832218E-250IV
GS832218E-225IV
GS832218E-200IV
GS832218E-166IV
GS832218E-150IV
GS832218E-133IV
GS832236B-250IV
GS832236B-225IV
GS832236B-200IV
GS832236B-166IV
GS83236B-150IV
GS832236B-133IV
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
165 BGA
209 BGA
133/8.5
250/6.5
225/7
C
C
C
C
C
C
C
I
209 BGA
209 BGA
200/7.5
166/8
209 BGA
209 BGA
150/8.5
133/8.5
250/6.5
225/7
209 BGA
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
165 BGA
I
200/7.5
166/8
I
I
150/8.5
133/8.5
250/6.5
225/7
I
I
I
165 BGA
I
165 BGA
200/7.5
166/8
I
165 BGA
I
165 BGA
150/8.5
133/8.5
250/6.5
225/7
I
165 BGA
I
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
119 BGA (var.2)
I
I
200/7.5
166/8
I
I
150/8.5
133/8.5
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 9/2008
38/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
GS832236E-250IV
GS832236E-225IV
GS832236E-200IV
GS832236E-166IV
GS832236E-150IV
GS832236E-133IV
GS832272C-250IV
GS832272C-225IV
GS832272C-200IV
GS832272C-166IV
GS832272C-150IV
GS832272C-133IV
GS832218GB-250V
GS832218GB-225V
GS832218GB-200V
GS832218GB-166V
GS832218GB-150V
GS832218GB-133V
GS832218GE-250V
GS832218GE-225V
GS832218GE-200V
GS832218GE-166V
GS832218GE-150V
GS8328GE-133V
GS832236GB-250V
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
165 BGA
165 BGA
250/6.5
225/7
I
I
165 BGA
200/7.5
166/8
I
165 BGA
I
165 BGA
150/8.5
133/8.5
250/6.5
225/7
I
165 BGA
I
209 BGA
I
209 BGA
I
209 BGA
200/7.5
166/8
I
209 BGA
I
209 BGA
150/8.5
133/8.5
250/6.5
225/7
I
209 BGA
I
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 119 BGA (var.2)
C
C
C
C
C
C
C
C
C
C
C
C
C
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
200/7.5
166/8
150/8.5
133/8.5
250/6.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 9/2008
39/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
GS832236GB-225V
GS832236GB-200V
GS832236GB-166V
GS832236GB-150V
GS832236GB-133V
GS832236GE-250V
GS832236GE-225V
GS832236GE-200V
GS832236GE-166V
GS832236GE-150V
GS832236GE-133V
GS832272GC-250V
GS832272GC-225V
GS832272GC-200V
GS832272GC-166V
GS832272GC-150V
GS832272GC-133V
GS832218GB-250IV
GS832218GB-225IV
GS832218GB-200IV
GS832218GB-166IV
GS832218GB-150IV
GS832218GB-133IV
GS83228GE-250IV
GS832218GE-225IV
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 165 BGA
225/7
200/7.5
166/8
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
200/7.5
166/8
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
200/7.5
166/8
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 209 BGA
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 165 BGA
I
200/7.5
166/8
I
I
150/8.5
133/8.5
250/6.5
225/7
I
I
I
RoHS-compliant 165 BGA
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 9/2008
40/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
GS832218GE-200IV
GS832218GE-166IV
GS832218GE-150IV
GS832218GE-133IV
GS832236GB-250IV
GS832236GB-225IV
GS832236GB-200IV
GS832236GB-166IV
GS832236GB-150IV
GS832236GB-133IV
GS832236GE-250IV
GS832236GE-225IV
GS832236GE-200IV
GS832236GE-166IV
GS832236GE-150IV
GS832236GE-133IV
GS832272GC-250IV
GS832272GC-225IV
GS832272GC-200IV
GS832272GC-166IV
GS832272GC-150IV
GS832272GC-133IV
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
SCD/DCD
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BA
RoHS-compliant 165 BGA
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 119 BGA (var.2)
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
200/7.5
166/8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
150/8.5
133/8.5
250/6.5
225/7
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
200/7.5
166/8
150/8.5
133/8.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT.
2. The speed column indices the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = CommerciaTemperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.07 9/2008
41/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36/72(B/E/C)-xxxV
36Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8322Vxx_r1
• Updated AC Characteristics table with +1 numbers
• Removed address pin numbers (exept 0 and 1)
• Corrected “E” package mechanicadrawing thickness to 1.4
mm
8322Vxx_r1; 8322Vxx_r1_01
Content
• Updated Thermal Characteristics table
• Basic format updates
8322Vxx_r1_01;
8322Vxx_r1_02
Content/Format
Content/Format
Content
• Updated format
• Updated mechanicals
8322Vxx_r1_02;
8322Vxx_r1_03
• Pb-free information added
8322Vxx_r1_03;
8322Vxx_r1_04
• Updated entire document to reflect change in part
nomenclature
8322Vxx_r1_04;
8322xx_V_r1_05
Content
• Updated Truth Tables (pg. 13, 14)
8322Vxx_r1_05;
8322xx_V_r1_06
• Rev1.06a: updated coplanarity for 119, 165 and 209 BGA
mechancal, removed Status column from Ordering
Information table.
Content
Content
• anged V
and V
to V
and V
in footnote on
DDQ1
8322Vxx_r1_06;
8322xx_V_r1_07
DD3
DDQ3
DD1
Operating Currents table
Rev: 1.07 9/2008
42/42
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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