GS8180DV18GD-200T_技术文档

GS8180DV18D-250/200/167/133/100

250 MHz–100 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

18Mb Burst of 4

SigmaQuad SRAM

2.5 V V

DD

1.8 V or 1.5 V I/O

SigmaQuad SRAMs are offered in a number of configurations.

Some emulate and enhance other synchronous separate I/O

SRAMs. A higher performance SDR (Single Data Rate) Burst

of 2 version is also offered. The logical differences between

the protocols employed by these RAMs hinge mainly on

various combinations of address bursting, output data

registering, and write cueing. Along with the Common I/O

family of SigmaRAMs, the SigmaQuad family of SRAMs

allows a user to implement the interface protocol best suited to

the task at hand.

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual DoubleData Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 2.5 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

• Pb-Free 165-bump BGA package available

Clocking and Addressing Schemes

A Burst of 4 SigmaQuad SRAM is a synchronous device. It

employs two input register clock inputs, K and K. K and K are

independent single-ended clock inputs, not differential inputs

to a single differential clock input buffer. The device also

allows the user to manipulate the output register clock inputs

quasi independently with the C and C clock inputs. C and C are

also independent single-ended clock inputs, not differential

inputs. If the C clocks are tied high, the K clocks are routed

internally to fire the output registers instead.

SigmaRAM™ Family Overview

GS8180DV18 are built in compliance with the SigmaQuad

SRAM pinout standard for Separate I/O synchronous SRAMs.

They are18,874,368-bit (18Mb) SRAMs. These are the first in

a family of wide, very low voltage HSTL I/O SRAMs designed

to operate at the speeds needed to implement economical high

performance networking systems.

Because Separate I/O Burst of 4 RAMs always transfer data in

four packets, A0 and A1 are internally set to 0 for the first read

Parameter Synopsis

-250

-200

5.0 ns

2.3 ns

-167

6.0 ns

2.5 ns

-133

-100

10 ns

3.0 ns

tKHKH

tKHQV

4.0 ns

2.1 ns

7.5 ns

3.0 ns

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GS8180DV18D-250/200/167/133/100

1M x 18 SigmaQuad SRAM—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(144Mb) (36Mb)

NC/SA

MCL/SA

(72Mb)

A

NC

W

BW1

K

NC

R

SA

NC

B

C

D

E

F

NC

TDO

Q9

NC

D9

SA

NC

SA

K

BW0

SA

NC

Q7

NC

D6

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

D10

Q10

Q11

D12

Q13

V

NC

V

SS

D11

NC

V

SS

DD

SS

DD

V

DDQ

Q12

D13

V

DDQ

G

H

J

V

REF

DDQ

NC

D14

NC

Q4

D3

K

L

NC

Q15

NC

Q14

D15

D16

Q16

Q17

SA

V

NC

SA

V

NC

Q1

DDQ

SS

M

N

P

R

V

SS

D17

NC

V

SA

C

SA

V

NC

D0

SA

TCK

C

TMS

11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch

Notes:

1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb

2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

3. MCL = Must Connect Low

4. It is recommended that H1 be tied low for compatibility with future devices.

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GS8180DV18D-250/200/167/133/100

Pin Description Table

Symbol

Description

Synchronous Address Inputs

No Connect

Type

Input

—

Comments

SA

—

NC

—

R

Synchronous Read

Synchronous Write

Synchronous Byte Writes

Input Clock

Input

Output

Input

—

Active Low

W

Active Low

BW0–BW1

Active Low

K

Active High

Input Clock

Active Low

C

Output Clock

Active High

C

Output Clock

Active Low

TMS

TDI

TCK

TDO

Test Mode Select

—

Test Data Input

—

Test Clock Input

—

Test Data Output

—

V

HSTL Input Reference Voltage

Output Impedance Matching Input

Must Connect Low

Synchronous Data Inputs

Synchronous Data Outputs

Power Supply

—

REF

ZQ

—

MCL

—

D0–D17

Q0–Q17

Input

Output

Supply

—

V

2.5 V Nominal

DD

V

Isolated Output Buffer Supply

Power Supply: Ground

Supply

1.8 or 1.5 V Nominal

—

DDQ

V

SS

Note:

NC = Not Connected to die or any other pin

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate

I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement

some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving

instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance

metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is

determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the

truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s

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GS8180DV18D-250/200/167/133/100

interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The

user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at

hand.

Alternating Read-Write Operations

SigmaQuad SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

Burst of 4 SigmaQuad SRAM DDR Read

The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. The

four resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the

C, the rising edge of C after that, the next rising edge of C, and finally by the next rising edge of C.

Burst of 4 Double Data Rate SigmaQuad SRAM Read First

Read A

NOP

Read B

Write C

Read D

Write E

NOP

K

Address

A

B

C

D

E

R

W

BWx

D

C

C+1

C+2

C+3

E

E+1

C

Q

A

A+1

A+2

A+3

B

B+1

B+2

B+3

D

D+1

D+2

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GS8180DV18D-250/200/167/133/100

Burst of 4 SigmaQuad SRAM DDR Write

The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K.

Burst of 4 Double Data Rate SigmaQuad SRAM Write First

Write A

NOP

Write B

Read C

NOP

Read D

NOP

K

Kbar

Address

Rbar

Wbar

BWx bar

D

A

B

C

D

B+3

A

A+1

A+2

A+3

B

B+1

B+2

C

Cbar

Q

C

C+1

C+2

C+3

D

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

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Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample

BW0

BW1

D0–D8

D9–D17

Time

Beat 1

Beat 2

Beat 3

Beat 4

0

1

0

1

0

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Resulting Write Operation

Beat 1

D0–D8

Beat 1

D9–D17

Beat 2

D0–D8

Beat 2

D9–D17

Beat 3

D0–D8

Beat 3

D9–D17

Beat 4

D0–D8

Beat 4

D9–D17

Written

Unchanged

Written

Unchanged

Written

Output Register Control

SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.

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GS8180DV18D-250/200/167/133/100

Example Four Bank Depth Expansion Schematic

R₃

W₃

R₂

W₂

R₁

W₁

R₀

W₀

A₀–A_n

K

D₁–D_n

Bank 3

Bank 1

Bank 2

Bank 0

A

W

R

W

R

K

R

K

R

K

D

C

Q

D

C

Q

D

C

Q

D

C

Q

C

Q –Q

1

n

Note: For simplicity BWn, K, and C are not shown.

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FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V

SS

via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a

vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the

impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance

evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time

towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires

32K start-up cycles, selected or deselected, after V_DDreaches its operating range to reach its programmed output driver impedance.

Separate I/O Burst of 4 SigmaQuad SRAM Truth Table

Current

Operation

A

R

W

D

Q

K ↑

(t_n)

K ↑

(t_n)

K ↑

(t_n)

K ↑

(t_n)

K ↑

(t_n+1½

K ↑

(t_n+2½

K ↑

(t_n+1½

K ↑

(t_n+2½)

(t_n-1

)

(t_n+1

)

(t_n+2

)

(t_n+1

)

(t_n+2

)

X

V

1

X

1

0

X

0

1

X

1

Deselect

Write

Deselect

Write

X

D2

X

D3

X

—

D2

—

D2

—

D3

—

D3

—

Hi-Z

Q2

Hi-Z

Q3

—

Read

—

0

Deselect

Read

D0

X

D1

X

Hi-Z

Q0

Hi-Z

Q1

—

X

0

Read

Q2

—

Q3

—

Write

D0

D2

D1

D3

Q2

Q3

V

X

Write

Read

Q0

Q1

Q2

Q3

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”

2. “—” indicates that the input requirement or output state is determined by the next operation.

3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.

4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.

5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-

ceded by a Read command.

6. Users should not clock in metastable addresses.

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GS8180DV18D-250/200/167/133/100

Byte Write Clock Truth Table

BW

Current Operation

D

K ↑

(t

)

(t

)

(t

)

(t

)

(t )

(t

)

(t

)

(t

)

(t

)

n+1

n+1½

n+2

n+2½

n

n+1

n+1½

n+2

n+2½

Write

T

D0

D2

X

D3

D4

X

Dx stored if BWn = 0 in all four data transfers

Write

T

F

T

F

T

F

T

F

D0

X

Dx stored if BWn = 0 in 1st data transfer only

Write

D1

X

Dx stored if BWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if BWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if BWn = 0 in 4th data transfer only

Write Abort

F

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

x18 Byte Write Enable (BWn) Truth Table

BW0 BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

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GS8180DV18D-250/200/167/133/100

State Diagram

Power-

Read NOP

Write NOP

WRITE

READ

WRITE

READ

Load New

WRITE

Load New

Read Address

R Count = 0

READ

R Count = 2

Write Address

W Count = 2

W Count = 0

READ

R Count = 2

WRITE

Always

W Count = 2

DDR Read

DDR Write

R Count = R Count + 1

W Count = W Count + 1

READ

Always

WRITE

Always

R Count = 1

W Count = 1

Increment

Read Address

Write Address

Notes:

1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.

2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for

“WRITE” and “WRITE”.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

5. R Count is the read counter; Burst of 4 must complete 2 DDR reads.

6. W Count is the write counter; Burst of 4 must complete 2 DDR writes.

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Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

–0.5 to 3.6

–0.5 to V

Unit

V

Voltage on V Pins

DD

V

DD

V

Voltage in V

Pins

V

DDQ

REF

V

REF

DDQ

V

–0.5 to V

+0.5 (≤ 3.6 V max.)

+/–100

Voltage on I/O Pins

V

I/O

DDQ

V

Voltage on Other Input Pins

Input Current on Any Pin

V

IN

I

mA dc

IN

I

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

+/–100

OUT

o

T

125

C

J

o

T

–55 to 125

C

STG

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

Min.

2.4

Typ.

2.5

Max.

2.6

Unit

Notes

V

DD

V

1.8 V I/O Supply Voltage

1.5 V I/O Supply Voltage

1.7

1.8

1.95

1.6

1

DDQ

V

1.4

1.5

DDQ

Ambient Temperature

(Commercial Range Versions)

T

0

25

70

85

°C

2

A

Ambient Temperature

(Industrial Range Versions)

T

–40

A

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V

≤ 1.6 V (i.e., 1.5 V I/O)

DDQ

and 1.7 V ≤ V

≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.

DDQ

2. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The

DD DDQ REF

power down sequence must be the reverse. V

must not exceed V .

DD

DDQ

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number

of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

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GS8180DV18D-250/200/167/133/100

HSTL I/O DC Input Characteristics

Parameter

DC Input Logic High

Symbol

Min

Max

Units

mV

Notes

V

(dc)

V

+ 200

REF

1

IH

V (dc)

V

– 200

REF

DC Input Logic Low

mV

IL

V

DC Voltage

V

(dc)

V

(min)/2

V

(max)/2

DDQ

V

REF

DDQ

Note:

Compatible with both 1.8 V and 1.5 V I/O drivers

HSTL I/O AC Input Characteristics

Parameter

AC Input Logic High

Symbol

Min

Max

Units

Notes

3,4

V

(ac)

V

+ 400

REF

mV

IH

V (ac)

V

– 400

REF

AC Input Logic Low

3,4

IL

V

Peak to Peak AC Voltage

V

(ac)

5% V

(DC)

REF

1

REF

Notes:

1. The peak to peak AC component superimposed on V

may not exceed 5% of the DC component of V

.

REF

2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.

IH IL

3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

4. See AC Input Definition drawing below.

HSTL I/O AC Input Definitions

V

(ac)

IH

V

REF

V (ac)

IL

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GS8180DV18D-250/200/167/133/100

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKHKH

V

+ 1.0 V

DD

V

SS

50%

V

DD

V

– 1.0 V

SS

20% tKHKH

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 3.3 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

Output Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

pF

OUT

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Conditions

V

Input high level

Input low level

DDQ

0 V

Max. input slew rate

Input reference level

2 V/ns

V

/2

DDQ

Output reference level

Notes:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 Ω (HSTL I/O)

= 0.75 V

V

REF

50Ω

VT = V /2

DDQ

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Input and Output Leakage Characteristics

Parameter

Symbol

Test Conditions

Min.

Max

Notes

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–2 uA

2 uA

IL

Output Disable,

= 0 to V

I

Output Leakage Current

–2 uA

2 uA

OL

V

OUT

DDQ

Programmable Impedance HSTL Output Driver DC Electrical Characteristics

Parameter

Symbol

Min.

Max.

Units Notes

V

/2

V

Output High Voltage

Output Low Voltage

Output High Voltage

V

1, 3

2, 3

4, 5

4, 6

OH1

DDQ

V

/2

DDQ

Vss

OL1

V

– 0.2

V

DDQ

OH2

DDQ

V

Output Low Voltage

Vss

0.2

OL2

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

OL

DDQ

OL

DDQ

3. Parameter tested with RQ = 250Ω and V

= 1.5 V or 1.8 V

DDQ

4. Minimum Impedance mode, ZQ = V

SS

5.

6.

I

= –1.0 mA

= 1.0 mA

OH

OL

Operating Currents

-250

-200

–40°C

-167

–40°C

-133

-100

Parameter

Org Symbol

Test Conditions

0°C

to

–40°C

to

0°C

to

0°C

to

0°C

to

–40°C

to

0°C

to

–40°C

to

70°C

+85°C

70°C

+85°C

70°C

+85°C

70°C

+85°C

70°C

+85°C

460

mA

400

mA

340

mA

280

mA

R and W ≤ V_ILMax.

tKHKH ≥ tKHKH Min.

All other inputs

V_IN≤ V_ILMax. or V_IN≥ V_IHMin.

IDD

x18

TBD

Operating

Current

IDDQ

95 mA

85 mA

70 mA

65 mA

130

mA

120

mA

115

mA

110

mA

R and W ≥ V_IHMin.

tKHKH ≥ tKHKH Min.

All other inputs

ISB1

x18

Chip

Disable

Current

ISBQ1

5 mA

V_IN≤ V_ILMax. or V_IN≥ V_IHMin.

Note:

Power measured with output pins floating.

Rev: 2.04 4/2005

15/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

AC Electrical Characteristics

-250

-200

-167

-133

-100

Parameter

Symbol

Units Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

KHKH

K, K Clock Cycle Time

C, C Clock Cycle Time

4.0

1.5

1.8

—

5.0

1.9

2.2

—

6.0

2.4

2.7

—

7.5

3.0

3.4

—

10

3.0

4.6

—

ns

t

CHCH

t

KHKL

K, K Clock High Pulse Width

C, C Clock High Pulse Width

—

t

CHCL

t

KLKH

K, K Clock Low Pulse Width

C, C Clock Low Pulse Width

t

CLCH

t

KHKH

K Clock High to K Clock High

C Clock High to C Clock High

ns

4

t

CHCH

t

KHKH

K Clock High to K Clock High

C Clock High to C Clock High

t

CHCH

t

K, K Clock High to C, C Clock High

Address Input Setup Time

Address Input Hold Time

Control Input Setup Time

Control Input Hold Time

0

1.8

—

0

2.3

—

0

2.0

—

0

2.5

—

0

3.0

—

ns

KHCH

t

0.5

0.6

0.7

0.8

1.0

AVKH

KHAX

BVKH

KHBX

t

1

Data and Byte Write Input Setup

Time

t

0.5

—

0.6

—

0.7

—

0.8

—

1.0

—

ns

DVKH

KHDX

t

Data and Byte Write Input Hold Time

t

KHQV

K, K Clock High to Data Output Valid

C, C Clock High to Data Output Valid

—

2.1

—

1.0

—

2.2

—

1.2

—

2.5

—

1.2

—

3.0

—

1.2

—

3.0

—

ns

t

CHQV

t

KHQX

K, K Clock High to Data Output Hold

C, C Clock High to Data Output Hold

0.5

2

t

CHQX

t

KHQX1

K Clock High to Data Output Low-Z

C Clock High to Data Output Low-Z

—

2,3

t

CHQX1

t

KHQZ

K Clock High to Data Output High-Z

C Clock High to Data Output High-Z

2.1

2.2

2.5

3.0

t

CHQZ

Notes:

1. These parameters apply to control inputs R and W.

2. These parameters are guaranteed by design and characterization. Not 100% tested.

3. These parameters are measured at ±50mV from steady state voltage.

4.

t

Max is specified by t

Min. t

Max is specified by t

Min.

KHKH

CHCH

Rev: 2.04 4/2005

16/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Rev: 2.04 4/2005

17/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Rev: 2.04 4/2005

18/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Port Registers

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Rev: 2.04 4/2005

19/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 2.04 4/2005

20/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Tap Controller Instruction Set

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Configuration

Not Used

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

1

x18

X

0

X

1

0

1

0

1

0

1

0

0 0 1 1 0 1 1 0 0 1

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

Rev: 2.04 4/2005

21/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

Rev: 2.04 4/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 2.04 4/2005

23/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

DQ

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

*

50Ω

30pF

Input slew rate

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

* Distributed Test Jig Capacitance

DDQ

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

RFU

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 2.04 4/2005

24/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

V

0.6 * V

V

+0.3

DD2

Test Port Input High Voltage

V

1

IHJ

DD

V

0.3 * V

1

Test Port Input Low Voltage

–0.3

–300

–1

ILJ

DD

I

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

—

0.4

—

V

OLJ

V

– 100 mV

DDQ

V

OHJC

V

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be – V > Vi < V

+ V not to exceed .6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

ILJn

3. 0 V ≤ V ≤ V

IN

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

Rev: 2.04 4/2005

25/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Cycle Time

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

ns

20

10

ns

—

ns

—

ns

tTH

—

ns

Rev: 2.04 4/2005

26/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Package Dimensions—165-Bump FPBGA (Package D; Variation 3)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.44~0.64 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 2.04 4/2005

27/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8180DV18D-250/200/167/133/100

Ordering Information—GSI SigmaQuad SRAM

Speed

(MHz)

3

1

Org

Type

Package

T

Part Number

A

1M x 18

GS8180DV18D-250

GS8180DV18D-200

GS8180DV18D-167

GS8180DV18D-133

GS8180DV18D-100

GS8180DV18D-250I

GS8180DV18D-200I

GS8180DV18D-167I

GS8180DV18D-133I

GS8180DV18D-100I

GS8180DV18GD-250

GS8180DV18GD-200

GS8180DV18GD-167

GS8180DV18GD-133

GS8180DV18GD-100

GS8180DV18GD-250I

GS8180DV18GD-200I

GS8180DV18GD-167I

GS8180DV18GD-133I

GS8180DV18GD-100I

SigmaQuad SRAM

1 mm Pitch, 165-Pin BGA (var. 3)

250

200

167

133

100

250

200

167

133

100

250

200

167

133

100

250

200

167

133

100

C

I

1 mm Pitch, 165-Pin BGA (var. 3)

I

1 mm Pitch, 165-Pin BGA (var. 3)

I

1 mm Pitch, 165-Pin BGA (var. 3)

I

1 mm Pitch, 165-Pin BGA (var. 3)

I

Pb-Free 1 mm Pitch, 165-Pin BGA (var. 3)

C

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS818x18D-200T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

Rev: 2.04 4/2005

28/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8180DV18GD-200T
厂家：	GSI TECHNOLOGY
描述：	暂无描述静态存储器
文件：	总28页 (文件大小：849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8180DV18GD-200T [GSI]

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