GS8162Z18AB-150I
更新时间:2024-09-18 14:13:29
品牌:GSI
描述:ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, PLASTIC, BGA-119
GS8162Z18AB-150I 概述
ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, PLASTIC, BGA-119 SRAM
GS8162Z18AB-150I 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | BGA |
包装说明: | BGA, | 针数: | 119 |
Reach Compliance Code: | compliant | ECCN代码: | 3A991.B.2.B |
HTS代码: | 8542.32.00.41 | 风险等级: | 5.68 |
Is Samacsys: | N | 最长访问时间: | 7.5 ns |
其他特性: | FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 3.3V SUPPLY | JESD-30 代码: | R-PBGA-B119 |
JESD-609代码: | e0 | 长度: | 22 mm |
内存密度: | 18874368 bit | 内存集成电路类型: | ZBT SRAM |
内存宽度: | 18 | 湿度敏感等级: | 3 |
功能数量: | 1 | 端子数量: | 119 |
字数: | 1048576 words | 字数代码: | 1000000 |
工作模式: | SYNCHRONOUS | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 组织: | 1MX18 |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | BGA |
封装形状: | RECTANGULAR | 封装形式: | GRID ARRAY |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | NOT SPECIFIED |
认证状态: | Not Qualified | 座面最大高度: | 1.99 mm |
最大供电电压 (Vsup): | 2.7 V | 最小供电电压 (Vsup): | 2.3 V |
标称供电电压 (Vsup): | 2.5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子面层: | TIN LEAD | 端子形式: | BALL |
端子节距: | 1.27 mm | 端子位置: | BOTTOM |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 宽度: | 14 mm |
Base Number Matches: | 1 |
GS8162Z18AB-150I 数据手册
通过下载GS8162Z18AB-150I数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
300 MHz–150 MHz
18Mb Pipelined and Flow Through
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Synchronous NBT SRAM
Features
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
The GS8162Z18A(B/D)/36A(B/D)/72A(C) may be
configured by the user to operate in Pipeline or Flow Through
mode. Operating as a pipelined synchronous device, in
addition to the rising-edge-triggered registers that capture input
signals, the device incorporates a rising edge triggered output
register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge-triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165-, or 209-Bump BGA package
Functional Description
The GS8162Z18A(B/D)/36A(B/D)/72A(C) is an 18Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
The GS8162Z18A(B/D)/36A(B/D)/72A(C) is implemented
with GSI's high performance CMOS technology and is
available in a JEDEC-standard 119-bump (x18 & x36), 165-
bump (x18 & x36), or 209-bump (x72) BGA package.
Parameter Synopsis
-300
-250
-200
-150
Unit
tKQ(x18/x36)
tKQ(x72)
tCycle
2.5
2.8
3.3
2.5
3.0
4.0
3.0
3.0
5.0
3.8
3.8
6.7
ns
ns
ns
Pipeline
3-1-1-1
335
390
495
280
330
425
230
270
345
185
210
270
mA
mA
mA
Curr (x18)
Curr (x32/x36)
Curr (x72)
tKQ
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
230
270
345
210
240
315
185
205
275
170
190
250
mA
mA
mA
Curr (x18)
Curr (x32/x36)
Curr (x72)
Rev: 1.03a 5/2003
1/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z72 Pad Out
209-Bump BGA—Top View (Package C)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
A
E2
A
ADV
W
A
E3
A
DQB
DQB
DQB
DQB
DQPF
DQF
DQF
DQF
DQF
NC
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
BC
BG
NC
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
NC
A
A
BB
BF
BH
BD
E1
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
PE
NC
A
BE
BA
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CK
NC
G
NC
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDD
ZQ
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
G
H
J
MCH
MCL
MCH
CKE
FT
K
L
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
M
N
P
R
T
MCL
MCH
ZZ
VDD
LBO
A
U
V
A
A
A
A
A1
A
A
W
TMS
TDI
A
A0
A
TDO
TCK
Rev 10
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.03a 5/2003
2/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z72 BGA Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
BA, BB, BC,BD, BE, BF,
BG,BH
I
NC
CK
—
No Connect
Clock Input Signal; active high
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
I
I
I
I
I
I
I
I
I
W
E1, E3
E2
Chip Enable; active high
Output Enable; active low
G
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
ZZ
FT
LBO
MCH
MCL
PE
Must Connect Low
I
I
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Clock Enable; active low
CKE
BW
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
I
ZQ
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.03a 5/2003
3/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
W
G
A
A
NC
NC
NC
NC
NC
ZQ
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCH
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
DQA
DQA
DQA
DQA
NC
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
DNU
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
A
A
A
TDO
TCK
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003
4/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
W
G
A
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
DNU
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003
5/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z36 Pad Out
119 Bump BGA—Top View (Package B)
1
2
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
A
A
V
DDQ
DDQ
NC
NC
E2
ADV
E3
NC
NC
A
V
A
DD
DQC
DQC
DQPC
DQC
DQC
DQC
DQC
V
ZQ
E1
G
V
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
DDQ
G
H
J
DQC
BC
A
BB
DQB
DQC
V
W
V
DQB
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
DQA
DQA
DQA
DQA
DQA
DQPA
A
V
CK
V
DQA
DQA
DQA
DQA
DQPA
A
DQA
SS
SS
DQA
BD
NC
CKE
A1
BA
DQA
M
N
P
R
T
V
V
V
V
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DQA
V
V
V
V
DQA
DQA
NC
A0
DQA
PE
LBO
A
V
FT
DD
NC
NC
A
A
NC
ZZ
U
V
TMS
TDI
TCK
TDO
NC
V
DDQ
DDQ
Rev: 1.03a 5/2003
6/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z18A Pad Out
119 Bump BGA—Top View (Package B)
1
2
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
A
A
V
DDQ
DDQ
NC
NC
E2
ADV
E3
NC
NC
A
V
A
DD
DQB
NC
NC
DQB
NC
DQB
NC
V
ZQ
E1
G
V
DQPA
NC
DQA
NC
DQA
NC
SS
SS
SS
SS
SS
SS
V
V
V
V
DQA
V
V
DDQ
DDQ
G
H
J
NC
BB
A
NC
DQA
DQB
V
W
V
NC
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
NC
DQB
NC
V
CK
V
NC
DQA
NC
DQA
NC
A
DQA
SS
SS
DQB
NC
NC
CKE
A1
BA
NC
M
N
P
R
T
V
DQB
NC
V
V
V
V
V
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DQB
V
V
NC
NC
NC
NC
DQPB
A
A0
DQA
PE
LBO
A
V
FT
DD
A
NC
A
A
ZZ
U
V
TMS
TDI
TCK
TDO
NC
V
DDQ
DDQ
Rev: 1.03a 5/2003
7/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
PE
W
Clock Input Signal; active high
I
Clock Enable; active low
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Write Enable; active low
I
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable; active high
Sleep mode control; active high
I
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
I/O and Core Ground
DD
V
I
SS
V
I
Output driver power supply
DDQ
BPR1999.05.18
Rev: 1.03a 5/2003
8/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03a 5/2003
9/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a
Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03a 5/2003
10/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.03a 5/2003
11/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03a 5/2003
12/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03a 5/2003
13/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Pin
Mode Name
State
Function
Name
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H
L
H or NC
L or NC
H
Output Register Control
FT
ZZ
Active
Power Down Control
Standby, I = I
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Activate 9th I/Os
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
SCD
ZQ
H or NC
L
H or NC
L or NC
H
9th I/O Enable
Note:
PE
Deactivate 9th I/Os
There arepull-up devices on the ZQ, SCD, and FT pins and pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM.
Rev: 1.03a 5/2003
14/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V or V
on pipelined parts and V on flow
DD
DDQ
SS
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.03a 5/2003
15/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 4.6
V
DDQ
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.03a 5/2003
16/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
3.3 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD3
V
2.3
2.5
2.7
DD2
3.3 V V
2.5 V V
I/O Supply Voltage
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
Parameter
DDQ3
Symbol
Min.
2.0
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
V
Input Low Voltage
V
–0.3
2.0
—
0.8
+ 0.3
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
—
1,3
1,3
DDQ
IHQ
DDQ
V
V
–0.3
—
0.8
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
V
Range Logic Levels
Parameter
DDQ2
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.03a 5/2003
17/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
Note:
–40
25
85
°C
A
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
Note: These parameters are sample tested.
pF
I/O
Rev: 1.03a 5/2003
18/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
I
ZZ and PE Input Current
FT, ZQ Input Current
IN1
IN2
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135 V
OH2
OH3
OH
OH
—
V
I
= 8 mA
OL
0.4 V
OL
Rev: 1.03a 5/2003
19/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Rev: 1.03a 5/2003
20/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
AC Electrical Characteristics
-300
-250
-200
-150
Parameter
Symbol
Unit
Min
3.3
—
Max
—
2.5
2.8
—
—
—
—
—
5.0
—
—
—
—
—
Min
4.0
—
Max
—
2.5
3.0
—
—
—
—
—
5.5
—
—
—
—
—
Min
5.0
—
Max
—
3.0
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid (x18/x36)
Clock to Output Valid (x72)
tKQ
—
—
—
—
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKQX
1.5
1.5
1.0
0.1
5.0
—
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
3.0
3.0
1.4
0.4
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.5
Flow Through
tLZ1
tS
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.5
—
1.5
—
1.5
—
1.7
—
ns
Clock to Output in
High-Z
tHZ1
1.5
2.5
1.5
2.5
1.5
3.0
1.5
3.0
ns
(x18/x36)
Clock to Output in
High-Z
tHZ1
tOE
1.5
2.8
2.5
1.5
3.0
2.5
1.5
3.0
3.0
1.5
3.0
3.8
ns
ns
(x72)
G to Output Valid
(x18/x36)
—
—
—
—
G to Output Valid
(x72)
tOE
—
0
2.8
—
2.5
—
0
3.0
—
2.5
—
0
3.0
—
3.0
—
0
3.8
—
3.8
ns
ns
ns
tOLZ1
tOHZ1
G to output in Low-Z
G to output in High-Z
(x18/x36)
—
—
—
—
G to output in High-Z
(x72)
tOHZ1
—
2.8
—
3.0
—
3.0
—
3.8
ns
tZZS2
tZZH2
tZZR
ZZ setup time
ZZ hold time
ZZ recovery
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
ns
ns
ns
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as
specified above.
Rev: 1.03a 5/2003
21/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Rev: 1.03a 5/2003
22/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Rev: 1.03a 5/2003
23/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Rev: 1.03a 5/2003
24/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.03a 5/2003
25/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
Configuration
ID Code
I/O
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
1
1
x72
x36
x32
x18
x16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.03a 5/2003
26/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Rev: 1.03a 5/2003
27/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the
sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in
parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the
Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
000
001
Description
Notes
1
1, 2
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
100
101
110
111
1
1
1
1
GSI
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03a 5/2003
28/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 1.03a 5/2003
29/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
ns
ns
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.03a 5/2003
30/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A1
C
A
Side View
D
aaa
D1
e
Bottom View
b
e
Symbol
Min
—
Typ
—
Max
1.70
0.60
0.70
0.38
22.1
—
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
b
0.40
0.50
0.31
21.9
—
0.50
0.60
c
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
—
14.1
—
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
—
—
aaa
—
—
Rev 1.0
Rev: 1.03a 5/2003
31/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.50 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
J
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
13±0.07
1.0
B
0.20(4x)
SEATING PLANE
C
Rev: 1.03a 5/2003
32/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Package Dimensions—119-Pin PBGA (Package B)
Pin 1
A
Corner
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
G
D
B
S
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
U
R
Bottom View
Top View
Package Dimensions—119-Pin PBGA
Symbol
Description
Width
Min. Nom. Max
13.9 14.0 14.1
21.9 22.0 22.1
A
B
Length
C
Package Height (including ball) 1.73 1.86 1.99
D
Ball Size
0.60 0.75 0.90
0.50 0.60 0.70
E
Ball Height
F
Package Height (excluding balls) 1.16 1.26 1.36
G
Width between Balls
Package Height above board
Width of package between balls
Length of package between balls
Variance of Ball Height
1.27
K
0.65 0.70 0.75
R
7.62
20.32
0.15
S
T
Unit: mm
Side View
BPR 1999.05.18
Rev: 1.03a 5/2003
33/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
1M x 18
1M x 18
GS8162Z18AB-300
GS8162Z18AB-250
GS8162Z18AB-200
GS8162Z18AB-150
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
209 BGA
209 BGA
209 BGA
209 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
165 BGA
165 BGA
300/5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
300/5
512K x 36 GS8162Z36AB-300
512K x 36 GS8162Z36AB-250
512K x 36 GS8162Z36AB-200
512K x 36 GS8162Z36AB-150
250/5.5
200/6.5
150/7.5
300/5
1M x 18
1M x 18
1M x 18
1M x 18
GS8162Z18AD-300
GS8162Z18AD-250
GS8162Z18AD-200
GS8162Z18AD-150
250/5.5
200/6.5
150/7.5
300/5
512K x 36 GS8162Z36AD-300
512K x 36 GS8162Z36AD-250
512K x 36 GS8162Z36AD-200
512K x 36 GS8162Z36AD-150
256K x 72 GS8162Z72AC-300
256K x 72 GS8162Z72AC-250
256K x 72 GS8162Z72AC-200
256K x 72 GS8162Z72AC-150
250/5.5
200/6.5
150/7.5
300/5
250/5.5
200/6.5
150/7.5
300/5
1M x 18
1M x 18
1M x 18
1M x 18
GS8162Z18AB-300I
GS8162Z18AB-250I
GS8162Z18AB-200I
GS8162Z18AB-150I
250/5.5
200/6.5
150/7.5
300/5
I
I
I
512K x 36 GS8162Z36AB-300I
512K x 36 GS8162Z36AB-250I
512K x 36 GS8162Z36AB-200I
512K x 36 GS8162Z36AB-150I
I
250/5.5
200/6.5
150/7.5
300/5
I
I
I
1M x 18
1M x 18
Notes:
GS8162Z18AD-300I
GS8162Z18AD-250I
I
250/5.5
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36AB-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03a 5/2003
34/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS8162Z18AD-200I
GS8162Z18AD-150I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
209 BGA
209 BGA
209 BGA
209 BGA
200/6.5
150/7.5
300/5
I
I
I
I
I
I
I
I
I
I
512K x 36 GS8162Z36AD-300I
512K x 36 GS8162Z36AD-250I
512K x 36 GS8162Z36AD-200I
512K x 36 GS8162Z36AD-150I
256K x 72 GS8162Z72AC-30I
256K x 72 GS8162Z72AC-250I
256K x 72 GS8162Z72AC-200I
256K x 72 GS8162Z72AC-150I
Notes:
250/5.5
200/6.5
150/7.5
300/5
250/5.5
200/6.5
150/7.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36AB-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03a 5/2003
35/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
18Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• Creation of new datasheet
GS8162Z18A_r1
• Updated Flow Through power numbers in table on page 1 and
Operating Currents table
• Updated Pipeline and Flow Through numbers in AC Charac-
teristics table
8162Z18A_r1;
• Added 165-bump BGA package, pinout, and pinout descrip-
tion
Content
8162Z18_r1_01
• Removed ByteSafe pins and references
• Updated ZZ timing diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
• Removed parity I/O bit designation from 165 BGA pinout
• Updated both 209 BGA and 119 BGA pin description tables
• Removed BSR table
8162Z18A_r1_01;
8162Z18_r1_02
Content
Content
• Removed pin locations from pin description tables
• Entire datasheet rewritten due to design changes
GS8162ZxxA_r1_02;
GS8162ZxxA_r1_03
Rev: 1.03a 5/2003
36/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18AB-150I 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
GS8162Z18AB-150IT | GSI | ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 | |
GS8162Z18AB-225I | GSI | ZBT SRAM, 1MX18, 6ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 | |
GS8162Z18AB-275IT | GSI | ZBT SRAM, 1MX18, 5.25ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 | |
GS8162Z18AD-200T | GSI | ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 | 获取价格 | |
GS8162Z18AD-275I | GSI | ZBT SRAM, 1MX18, 5.25ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 | 获取价格 | |
GS8162Z18AD-275IT | GSI | ZBT SRAM, 1MX18, 5.25ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 | 获取价格 | |
GS8162Z18AD-275T | GSI | ZBT SRAM, 1MX18, 5.25ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 | 获取价格 | |
GS8162Z18AGB-200I | GSI | ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 | |
GS8162Z18AGB-200IT | GSI | ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 | |
GS8162Z18AGB-200T | GSI | ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, PLASTIC, BGA-119 | 获取价格 |
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