GL860A-PNGXX [GENESYS]
USB 2.0 UVC Camera Controller; USB 2.0 UVC摄像头控制器型号: | GL860A-PNGXX |
厂家: | GENESYS LOGIC |
描述: | USB 2.0 UVC Camera Controller |
文件: | 总42页 (文件大小:997K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Genesys Logic, Inc.
GL860A
USB 2.0 UVC Camera Controller
Datasheet
Revision 1.00
May 09, 2007
GL860A USB 2.0 UVC Camera Controller
Copyright:
Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR
EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC
BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING
FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS
MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE
MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registered trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http://www.genesyslogic.com
©2007 GenesysLogic, Inc. - All rights reserved.
Page 2
GL860A USB 2.0 UVC Camera Controller
Revision History
Revision
0.9
Date
Description
21/12/2006 First draft release
01/03/2007 Update register
0.91
1.00
09/05/2007 Add 46pin package information
©2007 GenesysLogic, Inc. - All rights reserved.
Page 3
GL860A USB 2.0 UVC Camera Controller
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION................................................... 7
CHAPTER 2 FEATURES .............................................................................. 8
CHAPTER 3 PIN ASSIGNMENT................................................................. 9
3.1 PINOUT ....................................................................................................... 9
3.2 PIN
3.3 PIN
L
IST.................................................................................................... 11
D
ESCRIPTIONS ................................................................................... 12
CHAPTER 4 REGISTERS .......................................................................... 14
4.1 REGISTERS
4.2 REGISTERS
B
ASE
A
DDRESS...................................................................... 14
D
ESCRIPTIONS ...................................................................... 17
4.2.1 Global Control Register Part......................................................... 17
4.2.2 USB Register Part........................................................................... 20
4.2.3 Sensor Register Part ....................................................................... 27
CHAPTER 5 FUNCTIONAL DESCRIPTION ......................................... 34
5.1 FUNCTION
B
LOCK .................................................................................... 34
ODE................................................................................... 35
5.2 OPERATION
M
5.2.1 with Flash Memory......................................................................... 35
5.2.2 without Flash Memory ................................................................... 35
CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 36
6.1 MAXIMUM RATINGS................................................................................. 36
6.2 DC CHARACTERISTICS ............................................................................ 36
CHAPTER 7 PACKAGE DIMENSION..................................................... 37
CHAPTER 8 ORDERING INFORMATION ............................................ 40
APPENDIX A. APPLICATION CIRCUIT................................................... 41
©2007 GenesysLogic, Inc. - All rights reserved.
Page 4
GL860A USB 2.0 UVC Camera Controller
LIST OF FIGURES
F
F
F
F
F
F
IGURE 3.1 - 48 PIN LQFN/LQFP PINOUT
IAGRAM ................................................................. 10
IAGRAM ......................................................................................... 34
DIAGRAM ....................................................... 9
IGURE 3.2 - 46 PIN LQFN PINOUT
D
IGURE 5.1 - BLOCK
D
IGURE 7.1 - GL860A 48 PIN LQFP PACKAGE................................................................ 37
IGURE 7.2 - GL860A 48 PIN LQFN PACKAGE ............................................................... 38
IGURE 7.3 - GL860A 46 PIN LQFN PACKAGE ............................................................... 39
©2007 GenesysLogic, Inc. - All rights reserved.
Page 5
GL860A USB 2.0 UVC Camera Controller
LIST OF TABLES
T
T
T
T
T
T
T
T
ABLE 3.1 - 48-PIN LQFP/LQFN PIN
ABLE 3.2 - 46-PIN LQFN PIN IST.................................................................................. 12
ABLE 3.3 - 48-PIN LQFP/LQFN PIN ESCRIPTIONS ..................................................... 12
ABLE 3.4 - 46-PIN LQFN PIN ESCRIPTIONS ................................................................. 13
EGISTERS .................................................................... 14
ATINGS ...................................................................................... 36
XCEPT USB SIGNALS ............................................ 36
NFORMATION ............................................................................. 40
LIST...................................................................... 11
L
D
D
ABLE 4.1 - BASE
ADDRESS FOR R
ABLE 6.1 - MAXIMUM
R
ABLE 6.2 - DC CHARACTERISTICS
E
ABLE 8.1 - ORDERING
I
©2007 GenesysLogic, Inc. - All rights reserved.
Page 6
GL860A USB 2.0 UVC Camera Controller
CHAPTER 1 GENERAL DESCRIPTION
The GL860A is a high performance USB 2.0 Video class compliant controller for PC Camera and NB
camera application. With the Genesys Logic’s highly recognized self-developed USB high-speed transceiver,
GL860A provides up to 30 fps at VGA or capture still images at 2 Mega pixels for fulfilling the mass
bandwidth demand of video transferring. GL860A also support USB isochronous mode to provide certain
bandwidth to insure user can get satisfied usage experience on video application even running high bandwidth
consumption devices concurrently.
The GL860A, compliant with Video Class 1.1 in USB Device Class (UVC), can be worked with Microsoft
native driver. It makes you use USB PC Camera as you use an USB flash disk. Additionally, the GL860A
provides an alternative proprietary driver to meet better image performance requirement.
The GL860A integrates a highly flexible sensor interface to make it easily adopted with variety sensors in
which include most popular CCD sensor module and CMOS sensors. The GL860A’s low power consumption,
low operation temperature characteristic also make it easy to implement a high quality PC Camera without
worry about the noise signals of sensors to affect by high performance USB controller.
©2007 GenesysLogic, Inc. - All rights reserved.
Page 7
GL860A USB 2.0 UVC Camera Controller
CHAPTER 2 FEATURES
ꢀ
USB specification compliance
-
-
-
Complies with 480Mbps Universal Serial Bus specification rev. 2.0.
Complies with 12Mbps Universal Serial Bus specification rev. 2.0.
Support USB 2.0 Isochronous Video pipe to 24MB/s.
ꢀ
Sensor interface
-
Programmable interface for popular general CCD module/CMOS sensor
ꢀ
ꢀ
Non-process video streaming (USB High-speed connection)
Support 4 USB endpoints
-
-
-
-
Endpoint 0: Control PIPE.
Endpoint 1: Isochronous/Bulk data in (configurable).
Endpoint 2: Interrupt OUT.
Endpoint 3: Interrupt IN.
ꢀ
Embedded 8052 micro-controller
-
-
Operate @ 15 MHz clock.
8K ROM.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Support USB remote wakeup..
3.3V/1.8V operation.
3.3V to 1.8V regulator is built-in.
Capability to support on-line download program
Available in 100-pin QFP and 48-pin LQFP package.
Pass WHQL (Windows Hardware Quality Lab)
Pass USB-IF (USB Implementers Forum) test
Application
Support OS
NB Cam, PC Cam, UMPC, Game Console
XP, Vista, MCE, XP64, Win2K
USB Video Class V1.1 compliant
-
-
-
The sensor, UVC, property control setting stored in external EEPROM (24Cxxx). (<= 8K bytes)
Support alternative proprietary driver to enhance image performance.
Non-UVC mode (Non-EEPROM), worked with proprietary driver
Support YUV/RGB/I420 format
Video stream up to 12 fps in UXGA, 15 fps in SXGA, 30 fps in VGA
UVC Class mode (External EEPROM), worked with OS native driver
Support UVC uncompressed YUY2 format
-
-
Video stream up to 6 fps in UXGA, 9 fps in SXGA, 30 fps in VGA
Still image captured up to UXGA
©2007 GenesysLogic, Inc. - All rights reserved.
Page 8
GL860A USB 2.0 UVC Camera Controller
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinout
Figure 3.1 - 48 Pin LQFN/LQFP Pinout Diagram
©2007 GenesysLogic, Inc. - All rights reserved.
Page 9
GL860A USB 2.0 UVC Camera Controller
Figure 3.2 - 46 Pin LQFN Pinout Diagram
©2007 GenesysLogic, Inc. - All rights reserved.
Page 10
GL860A USB 2.0 UVC Camera Controller
3.2 Pin List
Three type packages:
Case 1
ꢀ
ꢀ
ꢀ
ꢀ
Case 2
48 pin
8 bit sensor interface
12 GPIO pins
LQFP/LQFN package
ꢀ
46 pin
ꢀ
ꢀ
ꢀ
8 bit sensor interface
12 GPIO pins
LQFN package
Table 3.1 - 48-Pin LQFP/LQFN Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1
2
3
4
5
6
7
8
9
DVDD
P
I
13 HRST_
14 GPIO13
15 GPIO14
16 VDD
I
25 DVDD
P
I
37 VDD
P
P
CMS_DAT6
CMS_DAT7
CMS_DAT8
CMS_DAT9
GPIO0
I/O 26 X1
I/O 27 X2
38 DGND
I
I/O 39 DVDD
40 VDD
P
I
P
P
P
P
28 DGND
P
P
I
17 DGND
29 GPIO4
30 GPIO5
31 GPIO6
I/O 41 DGND
P
I/O 18 AGND
I/O 19 AVDD
I/O 20 DM
I/O 21 DP
I/O 42 CMS_DAT2
I/O 43 CMS_DAT3
I/O 44 CMS_DAT4
I/O 45 CMS_DAT5
I/O 46 VSYNC
I
GPIO1
I
GPIO2
I/O 32 GPIO7
I/O 33 GPIO8
I
GPIO3
I
10 CMS_DAT1 I/O 22 AGND
P
A
P
34 GPIO9
35 CMS_CLK
36 TEST
I/O
I/O
P
11 DGND
12 VDD
P
P
23 RREF
24 AVDD
I/O 47 HSYNC
I
48 DGND
©2007 GenesysLogic, Inc. - All rights reserved.
Page 11
GL860A USB 2.0 UVC Camera Controller
Table 3.2 - 46-Pin LQFN Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1
2
3
4
5
6
7
8
9
DVDD
P
I
13 HRST_
14 GPIO13
15 GPIO14
16 VDD
I
25 DVDD
P
I
37 VDD
P
P
CMS_DAT6
CMS_DAT7
CMS_DAT8
CMS_DAT9
GPIO0
I/O 26 X1
I/O 27 X2
38 DGND
I
I/O 39 DVDD
40 VDD
P
I
P
P
P
P
28 DGND
P
P
I
17 DGND
29 GPIO4
30 GPIO5
31 GPIO6
I/O 41 CMS_DAT2
I/O 42 CMS_DAT3
I/O 43 CMS_DAT4
I/O 44 CMS_DAT5
I/O 45 VSYNC
I/O 46 HSYNC
I/O
I
I/O 18 AGND
I/O 19 AVDD
I/O 20 DM
I/O 21 DP
I
GPIO1
I
GPIO2
I/O 32 GPIO7
I/O 33 GPIO8
I
GPIO3
I/O
I/O
10 CMS_DAT1 I/O 22 AGND
P
A
P
34 GPIO9
35 CMS_CLK
36 TEST
11 DGND
12 VDD
P
P
23 RREF
24 AVDD
I
3.3 Pin Descriptions
Table 3.3 - 48-Pin LQFP/LQFN Pin Descriptions
Pin Name
Pin#
12,16,37,40
Type
Description
VDD
P
I
1.8V power for crystal
Sensor data bit 1~9
CMS_DAT1~9 10,42~45,2~5
I/O
(pd)
6~9,29~34,
GPIO0~9,13,14
GPIO pins bit 0~9,13,14
14,15
11,17,18,22
28,38,41,48
GND
P
Ground
DVDD
HRST
1,25,39
13
P
3.3V core power
Hardware reset, low active
I
(pu)
AVDD
DM
19,24
20
P
3.3V analog power
USB D-
I/O
I/O
A
DP
21
USB D
RREF
X1
23
Reference R
12M crystal in
12M crystal out
Sensor clock
26
I
X2
27
I/O
I/O
CMS_CLK
35
I
(pd)
TEST
36
46
Test mode
VSYNC
I/O
Sensor Vsync
©2007 GenesysLogic, Inc. - All rights reserved.
Page 12
GL860A USB 2.0 UVC Camera Controller
HSYNC
NC
47
10
I/O
-
Sensor Hsync
No connection
Table 3.4 - 46-Pin LQFN Pin Descriptions
Pin Name
VDD
Pin#
Type
Description
12,16,37,40
P
I
1.8V power for crystal
Sensor data bit 1~9
CMS_DAT1~9 10,41~44,2~5
I/O
(pd)
6~9,29~34,
GPIO0~9,13,14
GPIO pins bit 0~9,13,14
14,15
11,17,18,22,
GND
28,38
P
Ground
DVDD
HRST
1,25,39
13
P
3.3V core power
Hardware reset, low active
I
(pu)
AVDD33
DM
19,24
20
P
3.3V analog power
USB D-
I/O
I/O
A
DP
21
USB D+
RREF
X1
23
Reference R
12M crystal in
12M crystal out
Sensor clock
26
I
X2
27
I/O
I/O
CMS_CLK
35
I
(pd)
TEST
36
Test mode
VSYNC
HSYNC
NC
45
46
10
I/O
I/O
-
Sensor Vsync
Sensor Hsync
No connection
Notation:
Type
O
Output
Input
Bi-directional
I
B
B/I
B/O
P
Bi-directional, default input
Bi-directional, default output
Power / Ground
A
Analog
pu
pd
odpu
Internal pull up
Internal pull down
Open drain with internal pull up
©2007 GenesysLogic, Inc. - All rights reserved.
Page 13
GL860A USB 2.0 UVC Camera Controller
CHAPTER 4 REGISTERS
4.1 Registers Base Address
Table 4.1 - Base Address for Registers
Mnemonic
GP1_DAT
GP1_INTPOL
GP1_INTEN
GP1_INT
ROMFLG
GP1_OE
Offset
00h
01h
02h
03h
04h
06h
07h
08h
09h
0Ah
0Dh
0Eh
0Fh
10h
11h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
Description
Default
--
GPIO[7:0] data
Interrupt polarity for GPIO[7:0]
Interrupt enable for GPIO[7:0]
Interrupt indication for GPIO[7:0]
Reserved for internal use.
Output enable for GPIO[7:0]
GPIO[14:8] data
8’h00
8’hFF
8’h00
8’hFF
8’h00
--
GP2_DAT
GP2_INTPOL
GP2_INTEN
GP2_INTEN
GP2_OE
Interrupt polarity for GPIO[14:8]
Interrupt enable for GPIO[14:8]
Interrupt indication for GPIO[14:8]
Output enable for GPIO[14:8]
Global control register
Interrupt mask for each sub-module
Sensor clock control
8’h00
8’hFF
8’h00
8’h00
8’hFC
8’h00
8’h80
8’h00
8’h04
8’h00
8’h00
8’h00
8’h00
8’h0C
--
GCTL
INT_MASK
CLKCTL
CPURST
CPU reset register
DEVCTL
UEVT1
USB Device control
USB interrupt flag #1
UEVT2
USB interrupt flag #2
UEVT1EN
UEVT2EN
UTMCTL
UTMDATL
UTMDATH
DEVADR
MISC
USB interrupt #1 enable
USB interrupt #2 enable
UTMI control
UTMI data low byte
UTMI data high byte
--
USB device address
8’h00
8’h10
8’h00
8’h00
8’h00
8’h40
8’h00
8’h00
8’h00
Miscellaneous register
Endpoint control 1
EPCTL1
EPCTL2
Endpoint control 2
EPCTL3
Endpoint control 3
EP0CTL
Endpoint 0 control
RX0CNT
FF0BUF
Endpoint 0 receive length
Endpoint 0 FIFO data
Endpoint 1 FIFO data
FF1BUF
©2007 GenesysLogic, Inc. - All rights reserved.
Page 14
GL860A USB 2.0 UVC Camera Controller
FF2BUF
51h
52h
53h
54h
55h
56h
57h
5Fh
60h
61h
62h
63h
C0h
C1h
Endpoint 2 FIFO data
Endpoint 3 FIFO data
Endpoint1,2 control 1
Endpoint1,2 control 2
Endpoint1,2 control 3
Endpoint3 control
8’h00
8’h00
8’h00
8’h00
8’h00
8’h00
FF3BUF
EP12CTL1
EP12CTL2
EP12CTL3
EP3CTL
RX2CNT
WAKEN
Endpoint 2 receive length
Wakeup source enable
Head function control 1
Head function control 2
Head 0 data
8’h00
8’h00
8’h00
8’h00
8’h00
8’h00
8’h00
8’h03
HEADCTL1
HEADCTL2
HEAD0
HEAD1
Head 1 data
SEN_CTL
MCK_SAMP
Sensor control
Master clock selection / Select of sampling phase
CLKRG_
CLKFG
C2h
Falling/rising edge for MCLK
8’h00
HV_CC
RHNL
C3h
C4h
Clock counter for Hsync/Vsync output
8’h00
8’h00
Pixel number for rising edge of Hsync output
RHNH_
FHNH
C5h
Pixel number for rising/falling of Hsync output
8’h00
FHNL
C6h
C7h
Pixel number for falling edge of Hsync output
Pixel number for rising edge of Vsync output
8’h00
8’h00
RVPNL
RVPNH_
RVLNH
C8h
Pixel number for rising/falling of Vsync output
8’h00
RVLNL
FVPNL
C9h
Pixel number for falling edge of Vsync output
Line number for rising edge of Vsync output
8’h00
8’h00
CAh
FVPNH_
FVLNH
CBh
Line number for rising/falling of Vsync output
8’h00
FVLNL
MPNL
CCh
CDh
Line number for falling edge of Vsync output
Maximum pixel number
8’h00
8’h00
MPNH_
MLNH
CEh
Maximum pixel/line number
8’h00
MLNL
CFh
D0h
Maximum line number
8’h00
8’h00
SALNL
Start line number of active window
SALNH_
EALNH
D1h
Start/end line number of active window
8’h00
EALNL
SAPNL
D2h
D3h
End line number of active window
Start pixel number of active window
8’h00
8’h00
SAPNH_
EAPNH
D4h
Start/end pixel number of active window
8’h00
EAPNL
D5h
D6h
End pixel number of active window
Sensor interrupt
8’h00
8’h00
SENINT
©2007 GenesysLogic, Inc. - All rights reserved.
Page 15
GL860A USB 2.0 UVC Camera Controller
SENINT_EN
SUB_SAMP
D7h
D8h
Sensor interrupt enable
Sub-sampling mode
8’h00
8’h00
Notation:
R/W
Read / Write
R/O
Read Only
W/O
Write Only
R/W1C
R/W/C
Read / Write “1” to Clear
Read / Write and hardware automatic Clear
©2007 GenesysLogic, Inc. - All rights reserved.
Page 16
GL860A USB 2.0 UVC Camera Controller
4.2 Registers Descriptions
4.2.1 Global Control Register Part
Offset 00h – GP1_DAT
GPIO7
R/W
GPIO6
R/W
GPIO5
R/W
GPIO4
R/W
GPIO3
R/W
GPIO2
R/W
GPIO1
R/W
GPIO0
R/W
7-0 GPIO[7:0]
GPIO7~0 data.
GPIO7~0O write.
GPIO7~0I read.
0
1
Offset 01h – GP1_INTPOL ………………………………………..…………… Default value = 8’h00
GPIO7
R/W
GPIO6
R/W
GPIO5
R/W
GPIO4
R/W
GPIO3
R/W
GPIO2
R/W
GPIO1
R/W
GPIO0
R/W
7-0 GPIO[7:0]
GPIO7~0 interrupt polarity.
0
1
H2L
L2H
Offset 02h – GP1_INTEN ………………………………………..…………… Default value = 8’hFF
GPIO7
R/W
GPIO6
R/W
GPIO5
R/W
GPIO4
R/W
GPIO3
R/W
GPIO2
R/W
GPIO1
R/W
GPIO0
R/W
7-0 GPIO[7:0]
0
Unmask int
Mask int
1
Offset 03h – GP1_INT ………………………………………………………… Default value = 8’h00
GPIO7
W1C
GPIO6
W1C
GPIO5
W1C
GPIO4
W1C
GPIO3
W1C
GPIO2
W1C
GPIO1
W1C
GPIO0
W1C
7-0 GPIO[7:0]
GPIO7~0 interrupt indication.
Offset 04h – ROMFLG ……..………………………………………………… Default value = 8’hFF
ROMFLG7 ROMFLG6 ROMFLG5 ROMFLG4 ROMFLG3 ROMFLG2 ROMFLG1 ROMFLG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 ROMFLG[7:0] Reserved for internal use.
©2007 GenesysLogic, Inc. - All rights reserved.
Page 17
GL860A USB 2.0 UVC Camera Controller
Offset 06h – GP1_OE ……..….…………………………………..…………… Default value = 8’h00
GPIO7
R/W
GPIO6
R/W
GPIO5
R/W
GPIO4
R/W
GPIO3
R/W
GPIO2
R/W
GPIO1
R/W
GPIO0
R/W
7-0 GPIO[7:0]
GPIO7~0 control.
0
Input
Output
1
Offset 07h – GP2_DAT
--
--
GPIO14
R/W
GPIO13
R/W
GPIO12
R/W
GPIO11
R/W
GPIO10
R/W
GPIO9
R/W
GPIO8
R/W
7
RESERVED
-
6-0 GPIO[14:8]
GPIO14~8 data.
0
1
GPIO14~8O write.
GPIO14~8I read.
Offset 08h – GP2_INTPOL ………………………………………..…………… Default value = 8’h00
--
--
GPIO14
R/W
GPIO13
R/W
EAPN11
R/W
SAPN11
R/W
GPIO10
R/W
GPIO9
R/W
GPIO8
R/W
7
RESERVED
-
6-5 GPIO[14:13]
GPIO14~13 interrupt polarity.
0
1
H2L
L2H
4
3
EAPN11
SAPN11
Pixel number of end active window
Pixel number of start active window
GPIO10~8 interrupt polarity.
2-0 GPIO[10:8]
0
1
H2L
L2H
Offset 09h – GP2_INTEN ………………………………………..…………… Default value = 8’hFF
--
--
GPIO14
R/W
GPIO13
R/W
GPIO12
R/W
GPIO11
R/W
GPIO10
R/W
GPIO9
R/W
GPIO8
R/W
7
RESERVED
-
6-0 GPIO[14:8]
0
1
Unmask int
Mask int
Offset 0Ah – GP2_INT ………………………………………………………… Default value = 8’h00
--
--
GPIO14
W1C
GPIO13
W1C
GPIO12
W1C
GPIO11
W1C
GPIO10
W1C
GPIO9
W1C
GPIO8
W1C
©2007 GenesysLogic, Inc. - All rights reserved.
Page 18
GL860A USB 2.0 UVC Camera Controller
7
RESERVED
-
6-0 GPIO[14:8]
GPIO14~8 interrupt indication.
Offset 0Dh – GP2_OE ……..….…………………………………..…………… Default value = 8’h00
--
--
GPIO14
R/W
GPIO13
R/W
GPIO12
R/W
GPIO11
R/W
GPIO10
R/W
GPIO9
R/W
GPIO8
R/W
7
RESERVED
-
6-0 GPIO[14:8]
GPIO14~8 control.
0
1
Input
Output
Offset 0Eh – GCTL ………………………………………………..…………… Default value = 8’hFC
SEN_CLKEN
R/W
--
--
--
--
--
--
--
--
--
--
SEN_EN
R/W
--
--
7-3 RESERVED
-
2
SEN_EN
Register enable to sensor interface.
0
1
Default/Reset state
Enable
1
0
RESERVED
-
SEN_CLKEN
0
1
Stop clock to sensor interface
Enable clock to sensor interface
Offset 0Fh – INT_MASK …………………………………………..…………… Default value = 8’h00
PIE_INTM
ASK
SEN_INTM
ASK
--
--
--
--
--
--
--
--
--
--
--
--
R/W
R/W
7-3 RESERVED
-
2
PIE_INTMASK
0
1
Mask of SIE_INT
Unmask of SIE_INT
1
0
RESERVED
-
SEN_INTMASK
0
1
Mask of SEN_INT
Unmask of SEN_INT
Offset 10h – CLKCTL ………………………………………………..………… Default value = 8’h80
SEN_CLKC SEN_CLKC SEN_CLKC SEN_CLKC SEN_CLKC
TL1
--
--
--
--
TL4
TL3
TL2
TL0
R/W
R/W
R/W
R/W
R/W
7-6 RESERVED
-
4
SEN_CLKCTL4 Operating clock of sensor interface is 48M
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
3
2
1
0
SEN_CLKCTL3 Operating clock of sensor interface is 7.5M
SEN_CLKCTL2 Operating clock of sensor interface is 15M
SEN_CLKCTL1 Operating clock of sensor interface is 30M
SEN_CLKCTL0 Operating clock of sensor interface is 60M
Offset 11h – CPURST ………………..……………………………..………… Default value = 8’h00
CPU2SEN_
RST
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W
7-1 RESERVED
-
0
CPU2SEN_RST
0
1
Unreset
Reset SEN_TOP
4.2.2 USB Register Part
Offset 40h – DEVCTL1 …………………………………………..…………… Default value = 8’h04
CHIRP_DEN
R/W
HS_SUSPD
R/W/C
TSTPKEN TSTPKRST
R/W/C W/O
--
--
DISGLUSB DIS_SUS
R/W R/W
PWRDN
R/W/C
7
HS_SUSPD
High Speed Suspend
This bit can be set/cleared by uC. When chip is in high speed mode and suspends
event is detected, uC can set HS_SUS and PWRDN bits to enter suspend mode.
This bit will be cleared automatically when end of resume signaling (K to SE0)
is detected.
6
5
4
CHIRP_DEN Set this bit will enable HS-KJKJKJ chirp detection. After correct HS chirp
sequence is detected, CHIRP_DET bit in USBEVT1 will be set.
TSTPKEN
Enable Endpoint 1 data packet transmission without receiving IN token.
This bit is cleared by hardware when TSTPKTX interrupt is set.
TSTPKRST
Reset Read Pointer of TX FIFO0.
Note: Write pointer & FIFO data keep unchanged.
3
2
RESERVED
DISGLUSB
-
When this bit is set to ‘1’, D+ pin will be left floating so that no connect will be
detected on the host side.
1
0
DIS_SUS
Disable suspend detection
PWRDN
`
Power down mode
If USB suspend is detected, firmware can set PWRDN to put the controller into
power down mode. Power down mode stops oscillator and freezes at known
states, and no more command can be executed. Hardware will automatically
clear PWRDN upon hardware reset or interrupted event.
Offset 41h – UEVT1 ………………………………………………..…………… Default value = 8’h00
CHIRP_DET
R/W1C
SOF
URST
WAKEUP RESUME
R/W1C R/W1C
SUSPD
R/W1C
EP0TX
R/W1C
EP0RX
R/W1C
R/W1C
R/W1C
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
7
6
5
SOF
SOF token packet received event
CHIRP_DET Chirp sequence “K-J-K-J-K-J” detected.
SRST
USB Reset (SE0 for 3ms) is detected.
After receiving this event, uC should begin the HS detection handshake.
4
3
2
1
0
WAKEUP
RESUME
SUSPD
Remote-wakeup event is detected during suspend state
USB resume detected
USB suspend detected
EP0TX
Endpoint 0 transmits a data packet completely.
Endpoint 0 receives a data packet.
EP0RX
Offset 42h – UEVT2 ………………………………………………..…………… Default value = 8’h00
SETUP
R/W1C
TSTPKTX EP2NAK
R/W1C R/W1C
EP1NAK
R/W1C
EP0NAK
R/W1C
EP3TX
R/W1C
EP2RX
R/W1C
EP1TX
R/W1C
7
SETUP
Device received a setup packet.
Test Packet is sent complete.
6
TSTPKTX
5-3 EPnNAK
Endpoint receiving or transmitting NAK flag. (n=2~0)
Endpoint 3 transmission done event
2
1
0
EP3TX
EP2RX
EP1TX
Endpoint 2 receive done event.
Endpoint 1 transmission done event.
Offset 43h – UEVT1EN …………………………………………..…………… Default value = 8’h00
SOFEN CHIRPDEN URSTEN WKUPEN
R/W R/W R/W R/W
RSMEN
R/W
SUSEN
R/W
EP0TXEN EP0RXEN
R/W R/W
7-0
These are the interrupt enable bits for USB event interrupt #1 to uC.
(Mask bits of USBEVT1)
Offset 44h – UEVT2EN …………………………………………..…………… Default value = 8’h00
TSTPKTXEN
R/W
SETUPEN
R/W
EP2NAKEN EP1NAKEN EP0NAKEN EP3TXEN EP2RXEN EP1TXEN
R/W R/W R/W R/W R/W R/W
7-0
These are the interrupt enable bits for USB event interrupt #2 to uC.
(Mask bits of USBEVT1)
Offset 45h – UTMCTL …………………………………………..…………… Default value = 8’h0C
TXVLDH/
RXVLDH
TXVLD/
RXACTV
VMI
R/O
VPI
R/O
OPMOD1 OPMOD0
R/W R/W
FSPEED
R/W
HSTERM
R/W
R/W
R/W
Write
Read
To generate HS Chirp, set to 8’b0010_0111.
To generate FS Remote-Wake-Up, set to 8’b0010_1111.
RXACTV/RXVLDH will reflect the real-time status of the UTM interface.
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
Offset 46h – UTMDATL
UTMD7
R/W
UTMD6
R/W
UTMD5
R/W
UTMD4
R/W
UTMD3
R/W
UTMD2
R/W
UTMD1
R/W
UTMD0
R/W
Offset 47h – UTMDATH
UTMD15 UTMD14 UTMD13 UTMD12 UTMD11 UTMD10
R/W R/W R/W R/W R/W R/W
UTMD9
R/W
UTMD8
R/W
UTMDATL/UTMDATH are used to set/read data to/from UTM interface.
Write
Set the output data on UTM interface.
To issue chirp or remote-wake-up, these 2 registers should set to 4’h0000.
Read
Reflect the real-time status of the UTM data bus.
Offset 48h – DEVADR ………..…………………………………..…………… Default value = 8’h00
--
--
DEVADR6 DEVADR5 DEVADR4 DEVADR3 DEVADR2 DEVADR1 DEVADR0
R/W R/W R/W R/W R/W R/W R/W
7
RESERVED
-
6-0
This register is used to store USB device address.
Offset 49h – MISC …….…………………………………………..…………… Default value = 8’h00
SUSPD
R/O
ADDR
R/O
DEFAULT POWER
R/O R/O
--
--
--
--
SF
SUS_DIS
R/W
R/W
7
SUSPD
Device is in the suspend state.
Device is in the address state.
Device is in the default state.
Device is in the powered state.
-
6
5
4
ADDR
DEFAULT
POWER
3-2 RESERVED
1
SF
Short frame mode, using in suspend detection.
0
1
Normal mode, needs 3ms bus idle to enter suspend mode
Short frame mode, needs only 200us to enter suspend mode
0
SUS_DIS
Disable suspend detection.
Offset 4Ah – EPCTL1 …….…………………………………………..………… Default value = 8’h00
EP1ISOEN DISNYET TATODEN EP0TEST BULK_RST EP3EN
EP2EN
R/W
EP1EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
EP1ISOEN
0
1
Endpoint 1 is BULK IN mode.
Endpoint 1 is ISO IN mode.
6
5
4
DISNYET
TATODEN
EP0TEST
Disable USB NYET response, instead of ACK response.
Turn around time out detect enable.
0
Normal mode, Endpoint 0 doesn’t response to bulk IN/OUT packet.
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
1
Test mode, Endpoint 0 can response all packet.
3
BULK_RST
EP1 bulk mode initial reset
2-0 EPnEN
Endpoint 1, 2, 3 TX/RX enable. (n=3~1)
After device is configured, EPTX1EN, EPTX2EN,EP3TXEN, EPRX1EN,
EPRX2EN,EP3RXEN write 1 to decide Endpoint 1,2,3 IN or OUT. Before
endpoint is enabled, it won’t response to any USB transaction.
Offset 4Bh – EPCTL2 …….…………………………………………..………… Default value = 8’h00
--
--
EP3TGRST EP2TGRST EP1TGRST
W/O W/O W/O
--
--
EP3STL
R/W
EP2STL
R/W
EP1STL
R/W
7
RESERVED
6-4 EPnTGRST
RESERVED
2-0 EPnSTL
-
Endpoint toggle reset. (n=3~1)
3
-
Endpoint stall. (n=3~1)
Offset 4Ch – EPCTL3 …….…………………………………………..………… Default value = 8’h00
EP3TOG
R/O
EP2TOG
R/O
EP1TOG TX3FFPOP FF3RST RX0FFPSH TX0FFPOP FF0RST
R/O R/W R/W R/W R/W R/W
7-5 EPnTOG
Toggle indication of DATA packet. (n=3~1)
uC pop endpoint 3 TXFIFO enable.
4
3
2
1
0
TX3FFPOP
FF3RST
Reset endpoint 3 FIFO read/write pointer. Data in FIFO remain unchanged.
uC push endpoint 0 RXFIFO enable
RX0FFPSH
TX0FFPOP
FF0RST
uC pop endpoint 0 TXFIFO enable.
Reset endpoint 0 TXFIFO read/write pointer. Data in FIFO remain unchanged.
Offset 4Dh – EPCTL3 …….…………………………………………..………… Default value = 8’h00
RX0DIS RXSETUP RXOUT
RXSEQ EP0RXSTL EP0TXSTL TX0OE
R/W R/W R/W R/W/C
TX0SEQ
R/W
R/W
R/O
R/O
7
RX0DIS
Disable receiving capability on endpoint 0
Upon successfully receiving a data packet on endpoint 0, hardware will automatically
set this bit to ‘1’. At this time, no more OUT data on endpoint 0 can be accepted,
hardware will respond with NAK. Note, for SETUP transaction, hardware will
always accept and respond with ACK.
0
1
Endp0 FIFO is available for data receiving.
Endp0 FIFO is not available
6
5
4
RXSETUP
RXOUT
RXSEQ
Endpoint 0 received token is SETUP.
Endpoint 0 received token is OUT.
Endpoint 0 received data toggle.
0
1
The received data is DATA0
The received data is DATA1
3
EP0RXSTL
Endpoint 0 receiving stall.
Endpoint 0 will respond with a STALL to a valid OUT transaction. This bit will
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
be cleared by SETUP transaction automatically.
Endpoint 0 transmitting stall.
2
EP0TXSTL
Endpoint 0 will respond with a STALL to a valid IN transaction. This bit will be
cleared by SETUP transaction automatically.
1
0
TX0OE
Ready to transmit control data.
TX0SEQ
Endpoint 0 transmission data toggle.
0
1
TX DATA0
TX DATA1
Offset 4Eh – RX0CNT ………………………………………………..………… Default value = 8’h00
CTLRD
R/W
RX0CNT6 RX0CNT5 RX0CNT4 RX0CNT3 RX0CNT2 RX0CNT1 RX0CNT0
R/O R/O R/O R/O R/O R/O R/O
7
CTLRD
Control pipe(Endpoint 0) control to prevent response of bulk packet.
0
1
Host send OUT packet right after SETUP package. (Has a IN packet status)
Host send IN packet right after SETUP package. (Has a OUT packet status)
6-0 RX0CNT[6:0] The received DATA length of endpoint 0.
Offset 4Fh – FF0BUF ………………………………………………..………… Default value = 8’h00
FF0DAT7 FF0DAT6 FF0DAT5 FF0DAT4 FF0DAT3 FF0DAT2 FF0DAT1 FF0DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF0DAT[7:0] Data entry for endpoint 0 FIFO.
Writing this register will push data into endpoint 0 TXFIFO, and reading will
pop data from endpoint 0 RXFIFO.
Offset 50h – FF1BUF ………………………………………………..………… Default value = 8’h00
FF1DAT7 FF1DAT6 FF1DAT5 FF1DAT4 FF1DAT3 FF1DAT2 FF1DAT1 FF1DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF1DAT[7:0] Data entry for endpoint 1 FIFO.
Writing this register will push data into endpoint 1 TXFIFO, and reading will
pop data from endpoint 1 RXFIFO.
Offset 51h – FF2BUF ………………………………………………..………… Default value = 8’h00
FF2DAT7 FF2DAT6 FF2DAT5 FF2DAT4 FF2DAT3 FF2DAT2 FF2DAT1 FF2DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF2DAT[7:0] Data entry for endpoint 2 FIFO.
Writing this register will push data into endpoint 2 TXFIFO, and reading will
pop data from endpoint 2 RXFIFO.
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GL860A USB 2.0 UVC Camera Controller
Offset 52h – FF3BUF ………………………………………………..………… Default value = 8’h00
FF3DAT7 FF3DAT6 FF3DAT5 FF3DAT4 FF3DAT3 FF3DAT2 FF3DAT1 FF3DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF3DAT[7:0] Data entry for endpoint 3 FIFO.
Writing this register will push data into endpoint 3 TXFIFO, and reading will
pop data from endpoint 3 RXFIFO.
Offset 53h – EP12CTL1 ……………………………………………..………… Default value = 8’h00
--
--
--
--
--
--
--
--
TXASEL2 TXASEL1 TXASEL0
R/W R/W R/W
--
--
7-3 RESERVED
-
2-0 TXASEL[2:0] 001 TXAFFSEL1 set 1
010 TXAFFSEL2 set 1
011 TXAFFSEL3 set 1
100 TXAFFSEL4 set 1
101 TXAFFSEL5 set 1
110 TXAFFSEL0 set 1
In normal operation, bulk FIFO is pushed/popped by DTV/SEN engine or USB SIE engine.
But use the register, we can push/pop bulk FIFO by uC.
uC accessing ISO/Bulk IN FIFO:
Set TXFFPSH=1, and use TXAFFSEL to select DATAA FIFO, or use TXBFFSEL to select DATA
B FIFO. Then write data to FF1BUF to begin pushing FIFO.
To pop data from FIFO, just set TXFFPSH = 0, set TXBFFSEL or TXAFFSEL to select DATA
A/DATA B FIFO, and read data from FF1BUF to begin popping FIFO.
After pop/push is complete, uC must clear all FIFO select and control setting on FFCTL.
Offset 54h – EP12CTL2 …….…………………………………………..……… Default value = 8’h00
--
--
--
--
DTXEN
R/W
TXFMOD TXFFRST RXFFRST TXFFPSH RXFFPSH
R/W R/W R/W R/W R/W
7-6 RESERVED
-
5
4
3
2
1
0
DTXEN
Firmware set ENDP1 TX mode.
TXFMOD
TXFFRST
RXFFRST
TXFFPSH
RXFFPSH
Firmware test EP1 FIFO, read/write byte mode.
Reset TXFIFO, cleared by hardware itself.
Reset RXFIFO, cleared by hardware itself.
Push indication for TX FIFO
Push indication for RX FIFO
Offset 55h – EP12CTL2 …….…………………………………………..……… Default value = 8’h00
ANK1_EN
R/W
--
--
--
--
--
--
--
--
ANAKEP2 EP2NAK
R/W R/W
EP1NAK
R/W
7
ANK1_EN
Force NAK of endpoint 1.
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
6-3 RESERVED
-
2
ANAKEP2
Automatic NAK of endpoint 2, after receiving a data packet.
(Bit FNAKEP2 would be set to 1, after receiving a data packet.).
Force NAK of endpoint 2.
1
0
EP2NAL
EP1NAK
Force NAK of endpoint 1.
Offset 56h – EP3CTL ………..…………………………………………..……… Default value = 8’h00
TXOE3
R/W/C
TX3CNT6 TX3CNT5 TX3CNT4 TX3CNT3 TX3CNT2 TX3CNT1 TX3CNT0
R/O R/O R/O R/O R/O R/O R/O
7
TXOE3
Ready to transmit endpoint 3 data
6-0 TX3CNT[6:0] The transmit DATA length of endpoint 3
Offset 57h – RX2CNT ……..…………………………………………..……… Default value = 8’h00
RX2DIS RX2CNT6 RX2CNT5 RX2CNT4 RX2CNT3 RX2CNT2 RX2CNT1 RX2CNT0
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
7
RX2DIS
Disable receiving capability on endpoint 2
Upon successfully receiving a data packet on endpoint 2, hardware will automatically set
this bit to ‘1’. At this time, no more OUT data on endpoint 2 can be accepted, hardware
will respond with NAK.
0
1
Endp2 FIFO is available for data receiving.
Endp2 FIFO is not available
6-0 RX2CNT[6:0] The received DATA length of endpoint 2
Offset 5Fh – WAKEN ……...…………………………………………..……… Default value = 8’h00
--
--
RAMDIS3 RAMDIS2 RAMDIS1
R/W R/W R/W
--
--
GP4EN
R/W
GP3EN
R/W
GP2EN
R/W
Enable falling edge event on corresponding pins as remote wakeup source.
7
6
5
4
3
2
1
0
RESERVED
RAMDIS3
RAMDIS2
RAMDIS1
RESERVED
GP4EN
-
Endp3 RAM disable.
Endp2 RAM disable.
Endp1 RAM disable.
-
Falling edge event on GPIO4 wakeup enable.
Falling edge event on GPIO3 wakeup enable.
Falling edge event on GPIO2 wakeup enable
GP3EN
GP2EN
Offset 60h – HEADCTL1 ……...………………………………………..……… Default value = 8’h00
--
--
--
--
--
--
--
--
--
--
--
--
FRAM_EN HEAD_EN
R/W R/W
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
7-2 RESERVED
-
1
0
FRAM_EN
HEAD_EN
Set 1 to enable, header function..
Set 1 to add Header for each frame, Set 0 to add Header for each SOF.
Offset 61h – HEADCTL2 ……...………………………………………..……… Default value = 8’h00
--
--
--
--
--
--
--
--
HEADCNT0 HEADCNT0 HEADCNT0 HEADCNT0
R/W R/W R/W R/W
7-4 RESERVED
-
3-0 HEADCNT[3:0] Select header byte count from 0~8.
Offset 62h – HEAD0 ……………………………………………………..……… Default value = 8’h00
H0DAT7
R/W
H0DAT6
R/W
H0DAT5
R/W
H0DAT4
R/W
H0DAT3
R/W
H0DAT2
R/W
H0DAT1
R/W
H0DAT0
R/W
7-0 H0DAT[7:0]
Head data 0.
Offset 63h – HEAD1 ……………………………………………………..……… Default value = 8’h00
H1DAT7
R/W
H1DAT6
R/W
H1DAT5
R/W
H1DAT4
R/W
H1DAT3
R/W
H1DAT2
R/W
H1DAT1
R/W
H1DAT0
R/W
7-0 H1DAT[7:0]
Head data 1.
4.2.3 Sensor Register Part
Offset C0h – SENCTL ………………………………………..……..………… Default value = 8’h00
INCTST EDGESEL CLKOE
VSATV
R/W
HSATV
R/W
HVOE
R/W
--
--
BITMODE
R/W
R/W
R/W
R/W
7
6
INCTST
EDGESEL
0
1
No incremental data on CMSDAT[9:0]
Incremental data on CMSDAT[9:0] for debugging
Rising/Falling edge of PIX_CLK selection
0
1
The same with the PIX_CLK
Inverse with the PIX_CLK
5
4
3
2
CLKOE
VSATV
HSATV
HVOE
MAS_CLK output selection
0
1
Input clock (PIX_CLK)
Output clock (MAS_CLK)
Select of timing to reset internal line count when VSYNC is coming from sensor.
0
1
Falling edge
Rising edge
Select of timing to reset internal pixel count when HSYNC is coming from sensor.
0
1
Falling edge
Rising edge
HSYNC/VSYNC output enable
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
0
1
Output
Input
1
0
RESERVED
BITMODE
-
Pixel data bit number.
0
1
8bit pixel date
10bit pixel date (In this mode, 10 bit data will be transferred to USB by
continuous two byte. The first byte is MSB 8 bit, and the next byte is LSB2
bit and 6’b0.)
Offset C1h – MCK_SAMP ………………………………………...…………… Default value = 8’h03
SAMP4
R/W
SAMP3
R/W
SAMP2
R/W
SAMP1
R/W
SAMP0
R/W
MCK2
R/W
MCK1
R/W
MCK0
R/W
7-3 SAMP[4:0]
2-0 MCK[2:0]
Sampling phase of data bus.
Selection of master clock to sensor (MCLK)
000 MCLK is 60MHz
001 MCLK is 30MHz
010 MCLK is 20MHz
011 MCLK is 15MHz
100 MCLK is 12MHz
101 MCLK is 10MHz
110 MCLK is 8.57MHz
111 MCLK is 7.5MHz
Address
Data
0x10
0x01
0xC1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CLOCK
60MHz
30
20
15
12
10
8.57
7.5
Address
Data
0x10
0x02
0xC1
0x00
0x01
0x02
0x03
0x04
0x05
CLOCK
30MHz
15
10
7.5
6
5
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
0x06
0x07
4.2857
3.75
Address
Data
0x10
0x04
0xC1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CLOCK
15MHz
7.5
5
3.75
3
2.5
2.1429
1.875
Address
Data
0x10
0x08
0xC1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CLOCK
7.5MHz
3.75
2.5
1.875
1.5
1.25
1.0714
0.9375
Address
Data
0x10
0x10
0xC1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CLOCK
48MHz
24
16
12
9.6
8
6.8571
6
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
Offset C2h – CLKRG_CLK ……………………………………..…………… Default value = 8’h00
CLKFG2
R/W
CLKFG1
R/W
CLKFG0
R/W
CLKRG2 CLKRG1 CLKRG0
R/W R/W R/W
--
--
--
--
5-3 CLKFG[2:0]
Falling edge of MCLK.
Rising edge of MCLK.
2-0 CLKRG[2:0]
Offset C3h – HV_CC ……………………………………………..…………… Default value = 8’h00
VCC2
R/W
VCC1
R/W
VCC0
R/W
HCC2
R/W
HCC1
R/W
HCC0
R/W
--
--
--
--
5-3 VCC[2:0]
2-0 HCC[2:0]
Phase of output VSYNC.
Phase of output HSYNC.
Offset C4h – RHNL …………….….…………………………………..……… Default value = 8’h00
RHN7
R/W
RHN6
R/W
RHN5
R/W
RHN4
R/W
RHN3
R/W
RHN2
R/W
RHN1
R/W
RHN0
R/W
Offset C5h – RHNH_FHNH ……….…………………………………..……… Default value = 8’h00
--
--
--
--
FHN10
R/W
FHN9
R/W
FHN8
R/W
RHN10
R/W
RHN9
R/W
RHN8
R/W
RHN[10:0]
Pixel number of the rising edge of HSYNC
Offset C6h – FHNL ……….……………………………..……………..……… Default value = 8’h00
FHN7
R/W
FHN6
R/W
FHN5
R/W
FHN4
R/W
FHN3
R/W
FHN2
R/W
FHN1
R/W
FHN0
R/W
FHN[10:0]
Pixel number of falling edge of HSYNC
Offset C7h – RVPNL …………….….…………………………………..……… Default value = 8’h00
RVPN7
R/W
RVPN6
R/W
RVPN5
R/W
RVPN4
R/W
RVPN3
R/W
RVPN2
R/W
RVPN1
R/W
RVPN0
R/W
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
Offset C8h – RVPNH_RVI ……….…………………………………..……… Default value = 8’h00
--
--
--
--
RVLN10
R/W
RVLN9
R/W
RVLN8
R/W
RVPN10
R/W
RVPN9
R/W
RVPN8
R/W
RVPN[10:0] Number of the rising pixel number
Offset C9h – RVLNL ……….…..………………………..……………..……… Default value = 8’h00
RVLN7
R/W
RVLN6
R/W
RVLN5
R/W
RVLN4
R/W
RVLN3
R/W
RVLN2
R/W
RVLN1
R/W
RVLN0
R/W
RVLN[10:0] Line number for Rising edge of VSYNC line number
Offset CAh – FVPNL …………….….…………………………………..……… Default value = 8’h00
FVPN7
R/W
FVPN6
R/W
FVPN5
R/W
FVPN4
R/W
FVPN3
R/W
FVPN2
R/W
FVPN1
R/W
FVPN0
R/W
Offset CBh – FVPNH_FVLNH …….…………………………………..……… Default value = 8’h00
--
--
--
--
FVLN10
R/W
FVLN9
R/W
FVLN8
R/W
FVPN10
R/W
FVPN9
R/W
FVPN8
R/W
FVPN[10:0]
Pixel number for falling edge of VSYNC
Offset CCh – FVLNL ……….…..………………………..……………..……… Default value = 8’h00
FVLN7
R/W
FVLN6
R/W
FVLN5
R/W
FVLN4
R/W
FVLN3
R/W
FVLN2
R/W
FVLN1
R/W
FVLN0
R/W
FVLN[7:0]
Line number for falling edge of VSYNC
Offset CDh – MPNL …………….….…………………………………..……… Default value = 8’h00
MPN7
R/W
MPN6
R/W
MPN5
R/W
MPN4
R/W
MPN3
R/W
MPN2
R/W
MPN1
R/W
MPN0
R/W
Offset CEh – MPNH_MLNH …….………………..…………………..……… Default value = 8’h00
MLN10
R/W
MLN9
R/W
MLN8
R/W
MPN10
R/W
MPN9
R/W
MPN8
R/W
--
--
--
--
MPN[10:0]
MLN[10:0]
Pixel number for maximum window
Line number for maximum window
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
Offset CFh – MLNL …….….…..………………………..……………..……… Default value = 8’h00
MLN7
R/W
MLN6
R/W
MLN5
R/W
MLN4
R/W
MLN3
R/W
MLN2
R/W
MLN1
R/W
MLN0
R/W
Offset D0h – SALNL …………….…..…………………………………..……… Default value = 8’h00
SALN7
R/W
SALN6
R/W
SALN5
R/W
SALN4
R/W
SALN3
R/W
SALN2
R/W
SALN1
R/W
SALN0
R/W
SALN[10:0]
Line number of start active window
EALN[10:0] Line number of end active window
Offset D1h – SALNH_EALNH ……………………..…………………..……… Default value = 8’h00
--
--
--
--
EALN10
R/W
EALN9
R/W
EALN8
R/W
SALN10
R/W
SALN9
R/W
SALN8
R/W
Offset D2h – EALNL …….….…..…………..…………..……………..……… Default value = 8’h00
EALN7
R/W
EALN6
R/W
EALN5
R/W
EALN4
R/W
EALN3
R/W
EALN2
R/W
EALN1
R/W
EALN0
R/W
Offset D3h – SAPNL …………...…..…………………………………..……… Default value = 8’h00
SAPN7
R/W
SAPN6
R/W
SAPN5
R/W
SAPN4
R/W
SAPN3
R/W
SAPN2
R/W
SAPN1
R/W
SAPN0
R/W
SAPN[10:0]
EAPN[10:0]
Pixel number of start active window
Pixel number of end active window
Offset D4h – SAPNH_EAPNH ……………………..…………………..……… Default value = 8’h00
--
--
--
--
EAPN10
R/W
EAPN9
R/W
EAPN8
R/W
SAPN10
R/W
SAPN9
R/W
SAPN8
R/W
Offset D5h – EAPNL …….….…..…………....…………..……………..……… Default value = 8’h00
EAPN7
R/W
EAPN6
R/W
EAPN5
R/W
EAPN4
R/W
EAPN3
R/W
EAPN2
R/W
EAPN1
R/W
EAPN0
R/W
©2007 GenesysLogic, Inc. - All rights reserved.
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GL860A USB 2.0 UVC Camera Controller
Offset D6h – SENINT ….….…..…………....…………..……………..……… Default value = 8’h00
--
--
--
--
--
--
--
--
--
--
--
--
--
--
EOFINT
R/W1C
7-1 RESERVED
-
0
EOFINT
EOF (end of frame)
Indicate EOF
Offset D7h – SENINT_EN ….…..…………....…………..……………..……… Default value = 8’h00
EOFINT_EN
R/W1C
--
--
--
--
--
--
--
--
--
--
--
--
--
--
7-1 RESERVED
-
0
EOFINT_EN
0
1
Disable EOFINT
Enable EOFINT
Offset D8h – SUB_SAMP ……..…………....…………..……………..……… Default value = 8’h00
PSH_MODE PSH_MODE PCLK_CNT1 PCLK_CNT0 SUB_SAMP4 SUB_SAMP2
--
--
--
--
R/W
R/W
R/W
R/W
R/W
R/W
6-7 RESERVED
-
5-4 PSH_MODE[1:0] “2” SEN2FF_PSH will separate 2 SEN_CLK60
“1” SEN2FF_PSH will separate 1 SEN_CLK60
“0” SEN2FF_PSH will continue
3-2 PCLK_CNT[1:0] 00 Incoming sensor data rate is the same as MCLK
01 Incoming sensor data rate is 1/2 times of MCLK
10 Incoming sensor data rate is 1/3 times of MCLK
11 Incoming sensor data rate is 1/4 times of MCLK
1
0
SUB_SAMP4
SUB_SAMP2
0
Unchanged
1
Frame size will reduce to 1/16. Pixel number which are sampled on horizontal
and vertical direction separately reduce to 1/4 times. For example, a 640x480
image will be 160x120 if this bit is set.
0
1
Unchanged
Frame size will reduce to 1/4. Pixel number which are sampled on horizontal
and vertical direction separately reduce to 1/2 times. For example, a 320x240
image will be 160x120 if this bit is set.
©2007 GenesysLogic, Inc. - All rights reserved.
Page 33
GL860A USB 2.0 UVC Camera Controller
CHAPTER 5 FUNCTIONAL DESCRIPTION
5.1 Function Block
CCD/CMOS
Sensor I/F
USB 2.0
PHY
TXFIFO
PIE
CPU
8052
Figure 5.1 - Block Diagram
CCD Module/CMOS Sensor Interface
ꢀ
GL860A can link with popular CMOS sensor on market for PC camera application. GL860A can be
configured by different sensor requirement. If sensor is acting as master, GL860A can accept
HSYNC/VSYNC from sensor. If GL860A is configured as a master HSYNC/VSYNC will be provided
by GL860A to sensor. GL860A keep the most flexibility to fit most of the sensors. The detail of
configuration needs to refer to GL860A Application Note. For most sensors no matter of YUV format or
RGB format, they can be easily transferred image data to PC by GL860A.
ꢀ
ꢀ
TXFIFO
GL860A build in 6K byte internal buffer for USB high bandwidth application. This 6K internal buffer
can be used as transmitted buffer of isochronous pipe or bulk pipe. In USB specification, the highest
bandwidth of isochronous pipe is 24M byte/second, that can be easily derived to maximum frame rate
depending on configuration. For example, frame rate can be easily achieved to 30 frames per second if
image size is 640 x 480 if raw data output and sensor clock is 15M.
PIE
PIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with
CPU to play the role of the chip’s kernel. The main functions of PIE include the state machine of USB
protocol flow, CRC check, PID error check, and timeout check. Unlike USB1.1, bit stuffing/de-stuffing
is implemented in UTMI, not in PIE.
ꢀ
ꢀ
USB 2.0 PHY (UTMI )
UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI
specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI
encoding/decoding, Bit stuffing /de-stuffing, supporting USB2.0 test modes, and serial/parallel conversion.
CPU
CPU is the micro-processor unit of GL860A. It is an 8-bit 8052 processor with 8K ROM and 256 bytes
RAM. It operates at 15Mhz clock to decode the USB command issued from host and then prepares the
data to respond to the host. In addition,
C can handle GPIO (general purpose I/O) settings and
reading content of EEPROM to support high flexibility for customers of different configurations of chip.
These configurations include self/bus power mode setting, individual/gang mode setting, downstream
port number setting, device removable/non-removable setting, and PID/VID setting.
©2007 GenesysLogic, Inc. - All rights reserved.
Page 34
GL860A USB 2.0 UVC Camera Controller
5.2 Operation Mode
For customized firmware, flash memory can use as external program memory of CPU. This is for customer to
develop their firmware. This is only available for 100-pin package type.
5.2.1 with Flash Memory
ꢀ
ꢀ
ꢀ
ꢀ
Only available in 100-pin QFP package
Force EXTCPU = 0
GPIO9 pull down
GPIO13/GPIO14 used as serial bus to configure sensor
5.2.2 without Flash Memory
ꢀ
ꢀ
ꢀ
If 100 pin, set EXTCPU = 0
GPIO9 pull down
GPIO13/GPIO14 are used as serial bus to configure sensor
©2007 GenesysLogic, Inc. - All rights reserved.
Page 35
GL860A USB 2.0 UVC Camera Controller
CHAPTER 6 ELECTRICAL CHARACTERISTICS
6.1 Maximum Ratings
Table 6.1 - Maximum Ratings
Parameter
Symbol
Min.
3.0
0
Max.
3.6
Unit
V
VIN
TA
3.3V Input Voltage
Ambient Temperature under bias
+100
oC
FOSC Frequency
12 MHz 500ppm
6.2 DC Characteristics
Table 6.2 - DC Characteristics Except USB Signals
Symbol
Parameter
Min.
Typ.
Max.
Unit
PD
VDD
VIL
VIH
Power Dissipation
-
3
-
-
3.6
0.9
-
mA
V
Power Supply Voltage
3.3
LOW level input voltage
HIGH level input voltage
-
-
V
2.0
1.36
1.36
-
-
1.48
1.48
-
V
VTLH LOW to HIGH threshold voltage
VTHL HIGH to LOW threshold voltage
1.62
1.62
0.4
-
V
V
VOL
VOH
LOW level output voltage when IOL=8mA
HIGH level output voltage when IOH=8mA
V
2.4
-
V
Leakage current for pads with internal pull up or pull
down resistor
IOLK
-
-
-
µA
RDN
RUP
Pad internal pull down resister
Pad internal pull up resister
-
-
-
-
-
-
©2007 GenesysLogic, Inc. - All rights reserved.
Page 36
GL860A USB 2.0 UVC Camera Controller
CHAPTER 7 PACKAGE DIMENSION
Figure 7.1 - GL860A 48 Pin LQFP Package
©2007 GenesysLogic, Inc. - All rights reserved.
Page 37
GL860A USB 2.0 UVC Camera Controller
Internal No.
Green Package
Code No.
Date Code
Lot Code
Figure 7.2 - GL860A 48 Pin LQFN Package
©2007 GenesysLogic, Inc. - All rights reserved.
Page 38
GL860A USB 2.0 UVC Camera Controller
Internal No.
Green Package
Code No.
Date Code
Lot Code
Figure 7.3 - GL860A 46 Pin LQFN Package
©2007 GenesysLogic, Inc. - All rights reserved.
Page 39
GL860A USB 2.0 UVC Camera Controller
CHAPTER 8 ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number
GL860A-MNGXX
GL860A-PNGXX
GL860A-PMGXX
Package
Green
Version
XX
Status
48-pin LQFP
48-pin LQFN
46-pin LQFN
Green Package
Green Package
Green Package
Available
Available
Available
XX
XX
©2007 GenesysLogic, Inc. - All rights reserved.
Page 40
GL860A USB 2.0 UVC Camera Controller
Appendix A. Application circuit
The schematic below represents a very basic example to the controller and is subject to variations depending
on application intentions.
©2007 GenesysLogic, Inc. - All rights reserved.
Page 41
GL860A USB 2.0 UVC Camera Controller
©2007 GenesysLogic, Inc. - All rights reserved.
Page 42
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