GPCE001A-NnnV-C [GENERALPLUS]
16-bit Sound Controller with 256K x 16 Flash Memory;
| 型号： | GPCE001A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-bit Sound Controller with 256K x 16 Flash Memory |
| 文件： | 总25页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-bit Sound Controller with
256K x 16 Flash Memory
Oct 01, 2013
Version 1.7
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE001A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. APPLICATION FIELD.................................................................................................................................................................................. 3
3. FEATURES.................................................................................................................................................................................................. 3
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 7
5.2. PIN MAP ............................................................................................................................................................................................... 8
6. FUNCTIONAL DESCRIPTION .................................................................................................................................................................... 9
6.1. CPU ..................................................................................................................................................................................................... 9
6.2. MEMORY ............................................................................................................................................................................................... 9
6.3. PLL, CLOCK, POWER SAVING MODE..................................................................................................................................................... 10
6.4. POWER SAVING MODE ......................................................................................................................................................................... 10
6.5. CPU HALT MODE................................................................................................................................................................................. 10
6.6. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET........................................................................................................................... 10
6.7. INTERRUPT...........................................................................................................................................................................................11
6.8. I/O.......................................................................................................................................................................................................11
6.9. TIMER/COUNTER ................................................................................................................................................................................. 13
6.10.SLEEP MODE, WAKEUP, HALT MODE, AND WATCHDOG ........................................................................................................................... 14
6.11.ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 14
6.12.16 BITS DAC AUDIO DRIVER ................................................................................................................................................................ 14
6.13.SERIAL INTERFACE I/O (SIO)................................................................................................................................................................ 14
6.14.SPI..................................................................................................................................................................................................... 15
6.15.AUDIO ALGORITHM............................................................................................................................................................................... 15
6.16.SECURITY FUNCTION ........................................................................................................................................................................... 15
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 16
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 16
7.2. DC CHARACTERISTICS (VDD25=2.5V, VDD = 3.3V, VDDIO = 5V, TA = 25℃)....................................................................................... 16
7.3. ADC CHARACTERISTICS (AVDD = 3.3V, TA = 25℃).............................................................................................................................. 17
7.4. DAC CHARACTERISTICS (AVDD = 3.3V, TA = 25℃).............................................................................................................................. 18
8. APPLICATION CIRCUITS......................................................................................................................................................................... 19
8.1. APPLICATION CIRCUIT 1 (WITH CRYSTAL) .............................................................................................................................................. 19
8.2. APPLICATION CIRCUIT (WITH R-OSCILLATOR)......................................................................................................................................... 20
8.3. APPLICATION CIRCUIT 2 (WITH R-OSCILLATOR)...................................................................................................................................... 20
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 22
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 22
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 22
10.DISCLAIMER............................................................................................................................................................................................. 24
11. REVISION HISTORY ................................................................................................................................................................................. 25
© Generalplus Technology Inc.
Proprietary & Confidential
2
Oct 01, 2013
Version: 1.7
GPCE001A
16-bit SOUND CONTROLLER
WITH 256K x 16 FLASH MEMORY
1. GENERAL DESCRIPTION
3. FEATURES
The GPCE001A, a 16-bit architecture product, equips the newest
16-bit microprocessor, μ’nSP™ ISA 1.3 developed by Sunplus
Technology. This high processing speed ensures the μ’nSP™
ISA 1.3 is capable of handling sophisticated digital signal
processes (DSP) easily and rapidly. Therefore, the GPCE001A is
especially targeted to the areas of DSP and Speech/Audio
encode/decode. The wide range of CPU speed, from 0.1875MHz
to 48MHz, makes the GPCE001A easily to be applied in varieties
16-bit μ’nSP™ ISA 1.3 microprocessor
CPU clock: 0.1875MHz - 48MHz@6MHz crystal
256K-word flash memory and 256-word information block
2K-word CPU working SRAM
Chip operating voltage: 2.7V - 3.6V
IO operating voltage: 2.7V - 5.5V
Total of 32 programmable IO including IOA(8) & IOB(16) &
IOC(8)
of applications.
The memory capacity contains 256K-word
Crystal Resonator & R-oscillator
FLASH, and 2K-word working SRAM as well. Other features
include 32 programmable multi-functional I/Os, three 16-bit
timers/counters, 32768Hz Real Time Clock, Low Voltage
Reset/Detection, eight channels of 12-bit ADC (one channel built-in
MIC amplifier with Auto Gain Controller), one 16-bit DAC output
and two PWM IOs. A power saving mode, halt mode, is designed
to only stop CPU clock. To save even more power, a sleep mode
is featured to deactivate all of clocks. These two modes can be
awakened from the interrupt source triggers.
Standby mode (Clock Stop mode) for power savings
Halt mode (only CPU clock stop) for power savings
Three 16-bit timers/counters
One 16-bit DAC output
Wakeup source from IOA key, TIMER/RTC
32768Hz Real Time Clock (RTC)
Eight channels of 12-bit AD converter
ADC external top reference voltage
One Generalplus Serial interface I/O
One SPI serial interface I/O
Built-in microphone amplifier and AGC function
Low voltage reset and low voltage detection
Watchdog enable
2. APPLICATION FIELD
Intelligent interactive talking toys
Advanced educational toys
General speech synthesizer
Long duration audio products
ICE function for development and download into flash memory
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Oct 01, 2013
Version: 1.7
GPCE001A
4. BLOCK DIAGRAM
© Generalplus Technology Inc.
Proprietary & Confidential
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Oct 01, 2013
Version: 1.7
GPCE001A
5. SIGNAL DESCRIPTIONS
LQFP 128
PIN No.
Mnemonic
PIN No.
Type
Description
PORT A, Port B, Port C
IOA [15:8]
103,105
97,87,104-99
I/O
IOA [15:8]: bi-directional I/O ports.
107-112
113 - 128
65 - 72
93
It can be programmed to wakeup-able I/O pins.
IOB [15:0]: bi-directional I/O ports.
IOC [7:0]: bi-directional I/O ports.
-
IOB [15:0]
IOC [7:0]
NC
120-105
72-65
N/A
I/O
I/O
Power & GND
VDDIO_1
VSSIO_1
VDDIO_2
VSSIO_2
VDDIO_3
VSSIO_3
VDDIO_4,
VDDIO_5
VSSIO_4,
VSSIO_5
VDD25_1
VSS25_1
VDD25_2
VSS25_2
NC
73
74
76
75
129
130
16
17
14
15
38
41
39
40
43
42
56
55
52
54
36
73
74
76
75
121
122
3
P
G
P
G
P
G
P
Positive power supply for IOC
Ground reference for IOC
Positive power supply
Ground reference
Positive power supply for IOA , IOB
Ground reference for IOA , IOB
Positive power supply
4
1
G
Ground reference
2
15
18
16
17
N/A
N/A
47
46
43
45
13
P
G
P
Positive power supply for core
Ground reference for core
Positive power supply for oscillator and PLL
G
Ground reference for oscillator and PLL
-
-
NC
AVDD_1
AVSS_1
AVDD_2
AVSS_2
VDD
P
G
P
G
P
Positive power supply for analog circuit including ADC & MIC
Ground reference for analog circuit including ADC & MIC
Positive power supply for analog circuit including DAC
Ground reference for analog circuit including DAC
Positive power for regulator and ICESCK, ICESDA, ICEEN, RESETB,
TEST, TEST2.
VDD25O
37
14
P
Regulator output for connections to VDD25_1 and VDD25_2.
CLK SYSTEM/ ICE INTERFACE
ICEEN
ICESDA
ICESCK
XI
30
29
28
35
34
7
6
I
IO
I
ICE (low)/Free run (high) selection pin (floating as H)
ICE Serial DATA
5
ICE Clock
12
11
I
Oscillator Crystal input
XO / ROSC
O
Oscillator Crystal output/ ROSC-input at ROSC mode
OPTION (pin option in both ROM-less and real chip)
TEST
32
33
9
I
I
TEST Mode selection pin
TEST Mode for flash
TEST2
10
OPTION (mask option in real chip)
RI_XO
94
78
I
I
ROSC/Crystal selection pin (No connect as crystal OSC, tie VSS as
ROSC)
WDGE
0(info)
N/A
Mask option (Flash Information Block) (1: enable watch dog 0: disable)
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Version: 1.7
GPCE001A
LQFP 128
PIN No.
Mnemonic
LVR_EN
PIN No.
Type
Description
0(info)
N/A
I
Mask option (Flash Information Block) (1: enable low voltage reset 0:
disable)
-
NC
47-49
N/A
DAC
DAC1
DAC_EN
50
95
41
79
O
I
Audio DAC1 output
DAC enable signal with pull high. We strongly recommend connecting it
with power(ex. VDDIO)
ADC
MICIP
63
62
61
60
59
58
57
64
53
54
53
52
51
50
49
48
55
44
I
I
MIC amplifier input positive (Internal Floating)
MIC amplifier input negative (Internal Floating)
MIC amplifier output
MICIN
MICO
O
I
OPI
Audio amplifier negative input
AGC
IO
O
I
AGC by pass filter
V_MIC
AVREF_TOP
AVREF_MID
AVREF_DAC
Other Signal
RESETB
VPP
MIC power output switch to AVDD
AVREF_TOP input
O
O
AVREF_TOP/2 output with buffer (ADC maximum value voltage)
AVREF_DA reference pin
31
104
8
I
System reset pin low active (internal 47Kohms pull high resistor)
N/A
N/A
N/A
N/A
N/A
P
Flash VPP
NC
1-13,18-27
44-46,47-49
77-92
-
-
-
-
NC
NC
NC
131-136
Total: 136 pins for chip, 128 pins for LQFP 128 package.
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Version: 1.7
GPCE001A
5.1. PAD Assignment
This IC substrate should be connected to VSS
Note1: To ensure the IC functions properly, please bond all VDD and VSS pins.
Note2: The 0.1uF capacitor between VDD and VSS should be placed to IC as close as possible.
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Version: 1.7
GPCE001A
5.2. PIN Map
© Generalplus Technology Inc.
Proprietary & Confidential
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Oct 01, 2013
Version: 1.7
GPCE001A
6. FUNCTIONAL DESCRIPTION
6.1. CPU
6.2.2. Flash memory
The GPCE001A is equipped with a 16-bit μ’nSP® (read as
“micro-n-SP”) designed by SUNPLUS. Thirteen registers are
available in μ’nSP®: R1 ~ R4 (General-purpose registers), SR1 ~
SR4 (Secondary Bank Registers), PC (Program Counter), SP
(Stack Pointer), Base Pointer (BP), SR (Segment Register) and FR
(Flag Register). It provides interrupts, including fifteen FIQs (Fast
Interrupt Request) and sixteen IRQs (Interrupt Request), plus one
software-interrupt, BREAK.
Flash memory size is 256K words and its address is mapped from
$04000 to $043FFF. This flash memory is a high-speed memory,
with 50ns access time, containing 256 words information block
ranged from $2700 through $27ff as well as containing option
information for GPCE001A. The option in information block is
described below.
OPTION_SECURITY:
OPTION_WDOG_EN:
OPTION_PARA_WP:
enable or disable ICE read.
enable or disable Watchdog reset.
enable or disable flash write function in
Moreover,
a
high performance hardware multiplier with the
address range from $C000 through $FFFF.
capability of FIR filter calculation is also built-in to reduce the
software multiplication loading.
OPTION_MAIN_WP:
enable or disable flash write function in
address range from $10000 through $43FFF.
6.2. Memory
6.2.1. SRAM
Writing option into flash information block is done by IDE tool.
The amount of SRAM is 2K-word (including Stack) ranged from
$0000 through $07FF with two CPU-clock cycles access speed.
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Oct 01, 2013
Version: 1.7
GPCE001A
6.3. PLL, Clock, Power saving Mode
6.3.1. PLL (Phase Lock Loop)
6.5. CPU Halt Mode
The GPCE001A features a CPU halt mode for power savings. In
this mode, the CPU clock is turned off.
The purpose of PLL is to provide stable output frequency which
takes the base frequency (from crystal) for reference. The PLL
frequency gain (output frequency/input frequency) ranges from 4 to
15. Suppose base frequency is 6 MHz and PLL frequency gain
selects 8, the output frequency of PLL is 48 MHz.
6.6. Low Voltage Detection and Low Voltage Reset
6.6.1. Low Voltage Detection (LVD)
The Low Voltage Detect (LVD) reports the circumstance of present
voltage. There are four LVD levels to be selected: 2.6V, 2.8V,
3.0v and 3.2V. Those levels can be programmed via P_LVD_Ctrl.
As an example, suppose LVD is given to 2.8V. When the voltage
drops below 2.8V, the b12 of P_LVD_Ctrl is read as HIGH. In
such state, program can be designed to react this condition.
6.3.1.1. System clock
Basically, the system clock is provided by PLL and determined by
programming the P_SystemClock (W). The default PLL clock
(PLL) pumps to 6*FOSC, that is 36MHZ using 6MHZ crystal and
CPU clock is 4.5MHZ (with default value: PLL/8).
6.6.2. Low voltage reset
6.3.1.2. 32768Hz RTC
In addition to the LVD, the GPCE001A provides another important
feature, Low Voltage Reset (LVR). With the LVR function, a reset
signal is generated to reset system when the operating voltage
drops below 2.4V for 4 consecutive PLL system clock cycles.
Without LVR, the CPU becomes unstable and malfunctions when
the operating voltage drops below 2.4V. Using LVR, it will reset all
functions to the initial operational (stable) states when the voltage
drops below 2.4V. A LVR timing diagram is given as follows.
The Real Time Clock (RTC) is normally used in watch, clock or
other timing-based applications.
A 2Hz-RTC (0.5 seconds)
function is available in GPCE001A. The RTC counts the time as
well as to wake CPU up whenever RTC occurs. Time can be
traced by the numbers of RTC occurrence.
In addition,
GPCE001A supports 32768Hz oscillator in strong mode and weak
mode for power savings. In strong mode, 32768Hz OSC circuit in
GPCE001A always runs at the highest power consumption. On
the other hand, 32768Hz OSC in GPCE001A circuit run less power
consumption in weak mode, but it must use a high-standard
32768Hz external crystal such as SEIKO SSP_T6 or Microcrystal
CC5V-T1A.
PLL
VDD
2.4V
Tw
Tvdd
6.4. Power Saving Mode
RESET
The GPCE001A features a power savings mode (or called standby
mode) for low power applications. To enter standby mode, the
desired key wakeup port (IOA[15:8]) must be configured to input
first. And read the P_IOA_Data to latch the IOA state before
entering the standby mode. Also remember to enable the
corresponding interrupt source(s) for wakeup. After that, stop the
CPU clock by writing $5555 into P_SystemSleep(W) to enter
standby mode. In such mode, SRAM and I/Os remain in the
previous states until CPU being awakened. The wakeup sources
in GPCE001A include KEY wake up (IOA15 - 8), RTC wakeup, and
IRQ1 - IRQ7. After GPCE001A is awakened, CPU will continue to
execute the program from the location it slept. Programmer can
also enable or disable the 32768Hz RTC when CPU is in standby
mode.
Treset
Tw=PLL x 4 cycle
LVR @ Tvdd > Tw
Treset = PLL x 512 PLL cycle
6.6.3. Watchdog reset
The GPCE001A provides another important feature, watchdog
reset. With the watchdog function, a reset signal is generated to
reset system when watchdog counter is overflow and the option of
OPTION_WDOG_EN is enabled.
The purpose of watchdog is to monitor whether the system
operates normally. Within a certain period, watchdog register
must be cleared. If it is not cleared, CPU assumes the program
has been running in an abnormal condition. As a result, the CPU
will reset the system to the initial state and start running the
program all over again.
© Generalplus Technology Inc.
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Version: 1.7
GPCE001A
6.6.4. Soft reset protection
6.8. I/O
Software reset. Writes $5555 into P_System_Reset will reset the
whole system like hardware reset(pull low RESETB pin), except a
flag will set on in P_System_LVD_Ctrl(R/W).
Three I/O ports are built in GPCE001A - PortA, PortB, PortC. The
PortA is an general purpose I/O with programmable wakeup
capability, i.e. IOA[15:8] is the key wakeup port. User can latch
data on P_IOA_Data and enable the key wakeup function.
Wakeup is triggered when the PortA state is different from latched
data. Furthermore, the I/O ports can be operated at 5V level,
higher than the CPU core which is a 2.5V level system. Suppose
system operating voltage is running at 2.7V, VDDIO (power for I/O)
operates from 2.7V to 5.5V. In such condition, the I/O pad is
capable of operating from 0V to VDDIO. The following diagram is
an I/O schematic. Although data can be written into the same
register through Port_Data and Port_Buffer, they can be read from
different places, Buffer(R) and Data(R).
6.6.5. Stack access protection
GPCE001A will be reset when stack operation (example push or
pop) of CPU accesses the SRAM that is not in the defined range.
The defined stack range uses stack top (P_Stack_Top) and bottom
(P_Stack_Bottom) control register.
6.7. Interrupt
The GPCE001A has 16 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. An IRQ can be interrupted by a
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any
other interrupt sources.
Buffer(R)
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
Pin pad
Timer A
Timer B
Timer C
SPI
IRQ0_TMA/FIQ_TMA
IRQ1_TMB/FIQ_TMB
IRQ2_TMC/FIQ_TMC
IRQ3_SPI/FIQ_SPI
1(High)
Control
logic
2
3
4
Data(R)
SIO
IRQ3_SI/O
5
Key wakeup
EXT1
IRQ5_KEY/FIQ_KEY
IRQ5_EXT1/FIQ_EXT1
IRQ5_EXT2/FIQ_EXT2
IRQ6_4KHz/FIQ_4KHz
IRQ6_2KHz/FIQ_2KHz
IRQ6_512Hz/FIQ_512Hz
IRQ7_64Hz/FIQ_64Hz
IRQ7_16Hz_FIQ_16Hz
IRQ7_2Hz/FIQ_2Hz
6
In addition to a general purpose I/O port function, PortA/B/C also
shares/carries some special functions. A summary of PortA/B/C
special functions is listed as follows:
7
EXT2
8
9
4096Hz
2048Hz
512Hz
64Hz
10
11
12
16Hz
13
2Hz
14(Low)
Port
Special Function
APWMO1
Function Description
IOA8
TimerA PWM output
BPWMO1
TimerB PWM output
IOA9
IOA10
IOA11
IOA12
IOA13
IROUT
IR Output
Work with IOA11 by adding a RC circuit between them to get an OSC to EXT2
Feedback Output2
interrupts.
Feedback Input2
EXT2
-
External interrupt source 2 (negative edge triggered)
Work with IOA13 by adding a RC circuit between them to get an OSC to EXT1
Feedback Output1
interrupts.
Feedback Input1
EXT1
-
External interrupt source 1 (negative edge triggered)
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GPCE001A
Port
Special Function
Function Description
IOA14
IOA15
IOB6
RTCO
RTCI
APWMO2
BPWMO2
SDA
Real time clock output
Real time clock input
TimerA PWM output
TimerB PWM output
Serial interface data
Serial interface clock
SPI chip select
IOB7
IOB10
IOB11
IOB12
IOB13
IOB14
SCK
CS
CK
SPI clock
DI
SPI data input
IOB15
DO
SPI data output
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADC Channel 0
ADC Channel 1
ADC Channel 2
ADC Channel 3
ADC Channel 4
ADC Channel 5
ADC Channel 6
ADC Channel 7
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GPCE001A
Refer to the above table, the configuration of IOA10, IOA11, IOA12,
IOA13 involves feedback function that an OSC frequency can be
obtained from EXT1 (EXT2) by simply adding a RC circuit between
IOA10 (IOA12) and IOA11 (IOA13).
Input 1 and 2 provides varieties of speeds to TimerA / CounterA -
“1” representing pass signal (not gating), and “0” meaning timer
deactivated. For instance, if Input 1 =”1”, the clock is depending
on Input 2. If Input 1 =”0”, the TimerA is deactivated. The
EXT1/EXT2 is the external clock source.
6.9. Timer/Counter
TMXSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Input 1
‘0’
Input 2
‘0’
GPCE001A provides three 16-bit timers/counters - TimerA, TimerB
and TimerC, or so called universal counters. The clock source of
Timer A/B/C are from clock source Input1 and clock source Input2
(as following table) which perform AND operation to form varieties
of combinations. When timer overflows, a timeout signal (TAOUT)
is sent to CPU interrupt module to generate a timer interrupt signal.
In addition, Timer A/B/C hardware interrupt events can be used to
latch the DAC audio output and trigger ADC conversion.
‘1’
‘1’
FRTC / EXT1
FPLL
EXT2
EXT2
64Hz
16Hz
2Hz
‘1’
EXT2
EXT2
EXT2
EXT2
Example to Timer A, sending a write signal into TMA_CNT, the
value of TMA_DATA (value=N) will reload into TMA_CNT and set
an appropriated clock source. Timer will up-count from N, N+1,
N+2… 0XFFFF. An INT signal is generated at the moment of
timer rolling over from “0xFFFF” to “0x0000”, and an INT signal is
processed by INT controller immediately. At the same time, N will
be reloaded into TMA_CNT and start counting again.
FRTC / EXT1
FRTC / EXT1
FRTC / EXT1
FRTC / EXT1
FPLL
64Hz
16Hz
2Hz
‘1’
64Hz
16Hz
2Hz
‘1’
FPLL
FPLL
FPLL
In Timer A, the clock Input 1 is a high frequency source and clock
Input 2 is a low frequency clock source. The combination of clock
TimerA_Timeout
Tapwmo
Tduty
APWMO
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GPCE001A
Wakeup Source
6.9.1. IO PWM
FIQ source
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
Two IO PWMs which duty is selected from 1/16 to 14/16.
Example in the above figure is a 3/16-duration cycle. The
APWMO waveform is made by selecting a pulse width through
P_APWM_Ctrl. As a result, each 16 cycles will generate a pulse
width defined in control port. These PWM signals can be applied
for controlling the speed of motor or other devices.
EXT1/EXT2/KEY
RTC
6.9.2. Timebase
Timebase, generated by 32768Hz crystal oscillator, is
a
6.11. ADC (Analog to Digital Converter) / DAC
combination of frequency selection. Furthermore, timebase
The GPCE001A has eight channels of 12-bit A/D (Analog to Digital
Converter). The function of an A/D converter is to convert analog
quality signal, e.g. a voltage into a digital word or input source, can
be eight channels line-in from IOC[7:0] or one channel microphone
input through amplifier and AGC controller. The MIC amplifier
circuit is capable of reducing common mode noise by transmitting
signals through MIC fully differential Input. Moreover, an external
resistor can be applied to adjust microphone gain and time of AGC
operating. The ADC needs to select source of line-in before
converting.
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (IRQ6, IRQ7) for Real-Time-Clock.
6.10. Sleep mode, Wakeup, Halt mode, and Watchdog
6.10.1. Sleep and Wakeup modes
1) Sleep: After power-on reset, IC starts running until a sleep
command is issued. When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
2) Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The
FIQ/IRQ signal makes CPU complete the wakeup
6.12. 16-bit DAC Audio Driver
The GPCE001A provide one 16-bit DAC for audio output.
process and initialization.
The CPU wakeup
6.13. Serial Interface I/O (SIO)
source is given in the following table.
3) Halt mode: Halt mode is for power saving. In this mode, CPU
clock is turned off.
Serial interface I/O offers
a one-bit serial interface that
communicates with other devices. This serial interface is capable
of transmitting or receiving data via two I/O pins, IOB11 (SCK) and
IOB10 (SDA).
SIO Write Mode :
SCK
SDA
Ax
Ax-1
A0
Dx
Dx-1
D0
Dx
Dx-1
D0
START
Read/Write bit waveform = 0
STOP
SIO Read Mode :
SCK
Ax
Ax-1
A0
Dx
Dx-1
D0
Dx
Dx-1
D0
SDA
START
Read/Write bit waveform = 1
STOP
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GPCE001A
6.14. SPI
A Serial Peripheral Interface (SPI) controller is built in GPCE001A
to facilitate communicating with other devices and components.
There are four control signals on SPI - SPICS (IOB12), SPICK
(IOB13), SDI (IOB14), and SDO (IOB15).
SPICK(POL=0)
SPICK(POL=1)
SDO
SDI
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SPICS
6.15. Audio Algorithm
6.16. Security Function
The following speech types can be used in GPCE001A: PCM, LOG
PCM, SACM_S200 SACM_S480, SACM_S530, SACM_S720,
SACM_A1600, SACM_A1601, SACM_A3200, SACM_A3600,
SACM_DVR1600 (Digital Voice Recorder), and SACM_DVR4800.
Security function is able to protect code been read or written.
When program is downloaded into flash memory, program can be
read/write protected by IDE tools for security purpose. By writing
security enable option, the IDE function will be disabled except the
flash mass erase function in ICE mode. After Mass erase the
flash, the security option will be enabled again, to enable the
security option cannot limit CPU to read flash content in free run
mode.
For melody synthesis, the GPCE001A provides a SACM_MS01
(FM synthesizer) and SACM_MS02 wave-table synthesizer.
© Generalplus Technology Inc.
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Version: 1.7
GPCE001A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Min.
Max.
Unit
Regulator Supply Voltage
IO PAD Supply Voltage
Analog Supply Voltage
Core Supply Voltage
VDD
VDDIO
AVDD
VDD25
VIN
-0.3
-0.3
-0.3
-0.3
-0.3
2K
4.0
V
V
6.0
4.0
V
3.0
V
Input Voltage Range
VDDIO + 0.5
V
ESD Protection(HBM)
Operating Temperature Range
Storage Temperature Range
VESD
-
V
TA
0
+60
+150
℃
℃
TSTO
-50
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
7.2. DC Characteristics (VDD25=2.5V, VDD = 3.3V, VDDIO = 5V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
2.7
2.7
2.7
2.4
Typ.
5.0
3.3
3.3
2.5
Max.
5.5
Operating Voltage (IO)
VDDIO
VDD
V
V
V
V
IO VDD
Operating Voltage (Regulator)
Operating Voltage (Analog)
Operating Voltage (Core)
3.6
3.3V for regulator power
3.3V for analog power
2.5V for core power
VDD = 3.0V,
AVDD
VDD25
3.6
2.7
Regulator Max Output Current
I(VDD25O)
-
-
60
-
mA
VDD25O= 2.5V, (Regulator output)
PLL = 48MHz,
AD, DAC disable, no loading ;
VDD25 = 2.5V; VDD =3.3V;
VDDIO = 5.5V
Operating Current
IOP
-
40
mA
Standby Current
Input High Level
Input Low Level
ISTB
VIH
VIL
-
10
-
30
μA
V
Disable 32KHz crystal
-
0.7 VDDIO
-
-
-
0.3 VDDIO
V
-
VOH = 0.9 × VDDIO
VOL = 0.1 × VDDIO
IO Output High Current
IO Output Low Current
IOH
-
-6.0
-
mA
IOL
-
-
-
-
12.0
90
-
-
-
-
mA
KΩ
KΩ
KΩ
Input Pull-Low Resistor
(IOA [8:13], IOB)
RPL1
RPL2
RPH
VIN = VDDIO
VIN = VDDIO
VIN = VSS
Input Pull-Low Resistor
(IOA [14,15], IOC)
410
130
Input Pull-High Resistor
(IOA, IOB, IOC)
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GPCE001A
7.2.1. R-OSC Frequency VS Resistor
7.2.1.1. VDD25=2.5V, VDD = 3.3V, VDDIO = 5V, TA = 25℃
Operating Current(AD,ADC off,VDD=3.3v)
Rosc Freq VS. Resistor
40
30
20
10
0
Rosc=47K
12
10
8
6
4
2
0
0
20
40
60
PLL(MHz)
0
25
50
75
100 125 150 175
Rosc(Kohm)
7.2.1.2. Operation current (VDD25=2.5V, VDD = 3.3V,
VDDIO = 5V, TA = 25℃)
Operating Current(AD,ADC off,VDD=3.3v)
40
Crytal=6M
30
20
10
0
0
20
40
60
PLL(MHz)
7.3. ADC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
Max.
ADC Line_In Input Voltage Range from IOC[7:0]
ADC Microphone Input Voltage Range
External ADC Top Voltage
VINL (Note 1)
VINM
AVSS-0.3
-
AVDD+0.3
V
AVSS-0.3
-
-
AVDD+0.3
V
VEXTREF (Note 2)
RESO
2.0
AVDD+0.3
V
bits
Resolution of ADC
-
-
-
-
-
-
-
-
-
12
Signal-to-Noise Plus Distortion of ADC from Line in
Effective Number of Bit
SINAD (Note 4)
ENOB (Note 5)
INL
60
9.6
±3.0
±1.0
12
-
-
dB
-
bits
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
No Missing Code
-
LSB (Note 3)
LSB
DNL (Note 6)
-
-
Bits
Max ADC Clock
3.375
150K
MHz
Hz
AD Conversion Rate
FCONV
-
Note1: Internal protection diodes clamp the analog input to AVDD and AVSS. These diodes allow the analog input to swing from (AVSS-0.3V) to (AVDD+0.3V)
without causing damage to the devices.
Note2: The ADC performance is limited by the system’s noise level, so the GPCE001A just guarantee with the 8-bit accuracy when AVREF_TOP is 2V.
Note3: LSB means Least Significant Bit. With VINL=3V, 1LSB=3V/2^12= 0.732 mV.
Note4: The SINAD testing condition at VINLp-p=3.1V, FCONV = 48KHz, Fin=0.997KHz Sine waves at AVDD=3.3V from the IOC [7:0] input.
Note5: ENOB=(SINAD-1.76)/6.02.
Note6: The ADC of GPCE001A can guarantee no missing code.
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GPCE001A
7.4. DAC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Typ.
16
Characteristics
Resolution of DAC
Symbol
Unit
Min.
Max.
RESO
-
-
-
-
-
-
-
-
bit
dB
Signal to Noise Ratio of DAC
Dynamic Range
Sample Rate
SNR
-
90
DR
FS
-
85
dB
-
200K
-60
-
Hz
THD+N at FS
FOUT=0.997KHz
RL
-
125
-
db
Output Loading
Output Range
chm
AVDD
Input=Full Scale
60%
Note1: The THD+N testing condition at AVDD=3.3, Fs=48KHz, Fin=0.997KHz input at RL=125 ohm
7.4.1. Pull High Resister and VDDIO
7.4.3. I/O Output High Current IOH and VOH
RPH Test
IOH Test
350
300
250
200
150
100
50
8
other I/O port
6
PB[13,14]
4
2
0
0
2
3
4
5
6
2
3
4
5
6
VDDIO(V)
VDD(V)
7.4.4. I/O Output Low Current IOL and VOL
7.4.2. Pull Low Resister and VDDIO
RPL Test
IOL Test(@VOL=1v)
0
500
PB[13,14]
-5
-10
-15
-20
-25
PA[14,15];PC[7:0]
250
other I/O rtport
other I/O port
0
2
3
4
5
6
2
3
4
5
6
VDDIO(V)
VDDIO(V)
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GPCE001A
8. APPLICATION CIRCUITS
8.1. Application Circuit 1 (with Crystal)
6MHz
12-20 p*
12-20 p*
VMIC
1K
XI
XO
VDD5
RESETB
220
0.1
RESET
3K
8
7
0.22
0.22
100
0.1
MICP
MICN
MIC
0.22
5
1K
1
2
DAC1
Speaker1
4
3K
3
0.1
GPY0030A
6
10 K
0.22
MICO
OPI
0.1
5.1K
33
DAC_EN
VDD25_2
VDD
5000p
AGC
4.7
470K
100
100
0.1
0.1
VSS25_2
VDD25_1
AVDD (3.3V)
0.1
AVREF_TOP
GPCE001A
47
VSS25_1
VDD25O
VDD25
AVREF_DAC
0.1
33
AVDD
VDDIO_5
VDD
AVDD_1
100
100
0.1
VSSIO_5
VDDIO_4
100
0.1
0.1
33
33
33
33
VDD
VDD
VDD
VDD
AVSS_1
AVDD_2
AVDD
100
0.1
VSSIO _4
VDD IO_3
100
100
0.1
0.1
AVSS_2
VDD
VSSIO_3
VDDIO_2
VDD
100
VDD5
0.1
VSS IO_2
VDDIO_1
VSS25_1
VDD33
2
3
GPY0029B
100
0.1
VSSIO_1
1
IOA[15:8]
IOB[15:0]
IOA[15:8]
IOB[15:0]
IOC[7:0]
IOC[7:0]
GPCE001A Application Circuit audio amplifier, for 3-battery use only)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE001A
8.2. Application Circuit (with R-oscillator)
VDD25
51K
1K
XO
VDD
100
33
VMIC
RESETB
220
0.1
RESET
3K
8
7
0.22
0.22
0.1
MICP
MICN
MIC
0.22
5
1K
1
2
DAC1
Speaker1
4
3K
3
0.1
GPY0030A
6
10K
0.22
5.1K
MICO
OPI
0.1
33
DAC_EN
RI_XO
VDD
5000p
AGC
4.7
470K
VDD25_2
100
100
0.1
0.1
AVDD (3.3V)
0.1
AVREF_TOP
VSS25_2
VDD25_1
GPCE001A
47
VSS25 _1
VDD25O
AVREF_DAC
VDD
25
0.1
33
33
33
33
AVDD
100
VDDIO_5
VDD
VDD
VDD
VDD
AVDD _1
100
100
0.1
VSSIO_5
VDDIO_4
0.1
0.1
AVSS_1
AVDD_2
AVDD
100
0.1
0.1
VSSIO_4
VDDIO_3
100
100
AVSS_2
VDD
VSSIO_3
VDDIO_2
VDD
100
0.1
0.1
VSSIO_2
VDDIO_1
VSS25_1
33
VDD
100
0.1
VSSIO_1
IOA[15:8]
IOB[15:0]
IOA[15:8]
IOB[15:0]
IOC[7:0]
IOC[7:0]
GPCE001A Application Circuit audio amplifier, for 2-battery use only)
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Version: 1.7
GPCE001A
Application Circuit 2 (with R-oscillator)
VDD25
51K
1K
XO
VDD5
VMIC
ET
RES
B
220
0.1
RESET
3K
8
7
0.22
0.22
100
0.1
MICP
MICN
MIC
0.22
5
1K
1
2
DAC1
Speaker1
4
3K
3
0.1
GPY0030A
6
10K
0.22
MICO
OPI
0.1
5.1K
VDD5(5V)
DAC_EN
RI_XO
5000p
AGC
4.7
470K
VDD25_2
100
0.1
0.1
AVDD (3.3V)
0.1
VSS25_2
VDD25_1
AVREF_TOP
GPCE001A
47
100
VSS25_1
VDD25O
VDD25
AVREF_DAC
0.1
AVDD
100
VDDIO_5
VDD5(5V)
VDD5(5V)
AVDD_1
100
100
0.1
VSSIO_5
VDDIO_4
0.1
0.1
AVSS_1
AVDD_2
AVDD
100
0.1
VSS IO_4
VDDIO_3
VDD5(5V)
VDD5(5V)
100
100
0.1
0.1
AVSS_2
VDD
VSS IO_3
VDDIO_2
VDD
100
VDD 5
0.1
VSSIO_2
VDDIO_1
VSS25_1
2
3
VDD33
VDD5(5V)
GPY0029B
1
100
0.1
VSSIO_1
IOA[15:8]
IOB[15:0]
IOC[7:0]
IOA[15:8]
IOB[15:0]
IOC[7:0]
GPCE001A Application Circuit audio amplifier, for 3-battery use only)
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Version: 1.7
GPCE001A
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
GPCE001A-NnnV-C
Package Type
Chip form
GPCE001A-NnnV-QL09x
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 0 - 9, serial number).
9.2. Package Information
9.2.1. LQFP 128 outline dimensions
Dimension in inch
Symbol
Min.
Typ.
Max.
1.60
0.15
1.45
0.23
0.20
A
A1
A2
b
-
-
0.05
1.35
0.13
0.09
-
1.40
0.16
c
-
D
16.00 BSC.
14.00 BSC.
16.00 BSC.
D1
E
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Version: 1.7
GPCE001A
Dimension in inch
Typ.
Symbol
Min.
Max.
E1
e
14.00 BSC.
0.40 BSC.
0.60
L
0.45
0.75
L1
θ
1.00 REF
3.5∘
0∘
7∘
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Version: 1.7
GPCE001A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms
of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the
specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information
in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
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Version: 1.7
GPCE001A
11. REVISION HISTORY
Date
Revision #
Description
Page
Oct. 01, 2013
May 09, 2011
1.7
1.6
Add COMAIR logo to the cover page
Rename one NC pin to DAC_EN and modify related application circuit.
5,6,7,8,
19,20,21
Sep. 15, 2009
Jan. 12, 2009
1.5
1.4
Modify 7.2 DC Characteristics.
16
1. Modify “SIGNAL DESCRIPTIONS” in section 5.
2. Modify “Application Circuit2” in section 8.3.
5
21
Sep. 09, 2008
Jul. 04, 2007
1.3
1.2
Modify section 8. APPLICATION CIRCUITS.
19-21
1. Modify the “SIGNAL DESCRIPTIONS” in section 5.
2. Modify the “PAD Assignment” in section 9.1.
3. Add the “Package Information” in section 9.3.
5
21
22
Jan. 05, 2007
Oct. 05, 2006
1.1
1.0
Rename to match the real body function.
Original
1
22
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