MBM29LV160T-80PFTY [FUJITSU]
16M (2M xⅴ 8/1M x 16) BIT; 16M ( 2M xⅴ 8 / 1M ×16 )位型号: | MBM29LV160T-80PFTY |
厂家: | FUJITSU |
描述: | 16M (2M xⅴ 8/1M x 16) BIT |
文件: | 总60页 (文件大小:732K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20846-4E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
-80/-90/-12
-80/-90/-12
/MBM29LV160B
MBM29LV160T
■ FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
46-pin SON (Package suffix: PN)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector Protect command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)
■ PACKAGE
48-pin plastic TSOP (I)
46-pin plastic SON
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(LCC-46P-M02)
48-pin plastic CSOP
48-pin plastic FBGA
(BGA-48P-M03)
(BGA-48P-M13)
(LCC-48P-M03)
2
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ GENERAL DESCRIPTION
The MBM29LV160T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29LV160T/B is offered in a 48-pin TSOP (I), 46-pin SON, 48-pin CSOP and 48-ball
FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply.
12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed
in standard EPROM programmers.
The standard MBM29LV160T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV160T/B is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160T/B is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a
time using the EPROM programming mechanism of hot electron injection.
3
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.
• One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
Sector
SA0
Sector Size
(× 8) Address Range
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1F7FFFH
1F8000H to 1F9FFFH
1FA000H to 1FBFFFH
1FC000H to 1FFFFFH
(× 16) Address Range
00000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to AFFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FBFFFH
FC000H to FCFFFH
FD000H to FDFFFH
FE000H to FFFFFH
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
32 Kbytes or 16 Kwords
8 Kbytes or 4 Kwords
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
8 Kbytes or 4 Kwords
16 Kbytes or 8 Kwords
MBM29LV160T Top Boot Sector Architecture
4
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Sector
SA0
Sector Size
(× 8) Address Range
00000H to 03FFFH
04000H to 05FFFH
06000H to 07FFFH
08000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1FFFFFH
(× 16) Address Range
00000H to 01FFFH
02000H to 02FFFH
03000H to 03FFFH
04000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to AFFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FFFFFH
16 Kbytes or 8 Kwords
8 Kbytes or 4 Kwords
SA1
SA2
8 Kbytes or 4 Kwords
SA3
32 Kbytes or 16 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
64 Kbytes or 32 Kwords
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
MBM29LV160B Bottom Boot Sector Architecture
5
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ PRODUCT LINE UP
Part No.
MBM29LV160T/160B
+0.3 V
–0.3 V
-80
—
—
—
VCC = 3.3 V
Ordering Part No.
+0.6 V
–0.3 V
-90
-12
VCC = 3.0 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
80
80
30
90
90
35
120
120
50
■ BLOCK DIAGRAM
DQ0 to DQ15
RY/BY
Buffer
RY/BY
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
WE
State
Control
BYTE
RESET
Command
Register
Program Voltage
Generator
Chip Enable
STB
Data Latch
Output Enable
Logic
CE
OE
Y-Gating
Y-Decoder
STB
Timer for
Program/Erase
Address
Latch
Low VCC Detector
X-Decoder
Cell Matrix
A0 to A19
A-1
6
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ CONNECTION DIAGRAMS
TSOP(I)
A15
A14
A16
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
BYTE
VSS
2
A13
3
A12
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
4
A11
5
A10
6
A9
7
A8
8
A19
9
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A17
A7
A6
A5
A4
A3
VSS
A2
CE
A1
A0
FPT-48P-M19
(Marking Side)
A1
A2
A0
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CE
A3
VSS
OE
A4
A5
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
A6
A7
A17
A18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
A19
Reverse Pinout
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
A8
8
A9
7
A10
6
A11
5
A12
4
A13
3
A14
BYTE
A16
2
A15
1
FPT-48P-M20
(TOP VIEW)
A13
A14
A15
A12
A11
A10
A9
1
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
A3
A2
A1
A4
A5
A6
A7
A17
A18
(Marking Side)
2
3
4
5
6
7
A8
8
A19
WE
RESET
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
RY/BY
N.C.
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A0
SON-46
DQ14
DQ7
A16
BYTE
VSS
DQ15/A-1
CE
VSS
OE
LCC-46P-M02
(Continued)
7
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
(TOP VIEW)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0
A1
A2
CE
3
VSS
OE
A3
4
A4
5
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
A5
6
A6
7
A7
8
A17
9
A18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RY/BY
N.C.
N.C.
RESET
WE
N.C.
A19
CSOP-48
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
A8
A9
A10
A11
A12
A13
BYTE
A16
A14
A15
LCC-48P-M03
FBGA
(TOP VIEW)
Marking side
A1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
D5
E5
F5
G5
H5
A6
B1
C1
D1
E1
F1
G1
H1
B6
C6
D6
E6
F6
G6
H6
(BGA-48P-M03)
(BGA-48P-M13)
A1
B1
C1
D1
E1
F1
G1
H1
A3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A3
RY/BY
N.C.
A18
A4
B4
C4
D4
E4
F4
G4
H4
WE
A5
A9
A6
B6
C6
D6
E6
F6
G6
H6
A13
A4
A17
B3
C3
D3
E3
F3
G3
H3
RESET B5
A8
A12
A2
A6
N.C.
A19
C5
D5
E5
F5
G5
H5
A10
A14
A1
A5
N.C.
DQ2
A11
A15
A0
DQ0
DQ8
DQ9
DQ1
DQ5
DQ12
VCC
DQ7
DQ14
DQ13
DQ6
A16
CE
OE
VSS
DQ10
DQ11
DQ3
BYTE
DQ15/A-1
VSS
DQ4
8
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ LOGIC SYMBOL
Table 1 MBM29LV160T/B Pin Configuration
Pin
Function
Address Inputs
A-1, A0 to A19
DQ0 to DQ15
A-1
20
Data Inputs/Outputs
A0 to A19
16 or 8
CE
OE
Chip Enable
DQ0 to DQ15
Output Enable
Write Enable
CE
OE
WE
WE
Ready/Busy Output
RY/BY
RY/BY
RESET
BYTE
N.C.
RESET
BYTE
Hardware Reset Pin/
Temporary Sector Unprotection
Selects 8-bit or 16-bit mode
Pin Not Connected Internally
Device Ground
VSS
VCC
Device Power Supply
9
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 2 MBM29LV160T/B User Bus Operation (BYTE = VIH)
DQ0 to DQ15
Code
Code
DOUT
Operation
Auto-Select Manufacture Code (1)
Auto-Select Device Code (1)
Read (3)
CE
L
OE
L
WE
H
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
RESET
H
H
H
H
H
H
H
H
VID
L
L
L
H
H
A0
X
L
L
L
L
H
A1
X
A6
X
X
A6
L
Standby
H
L
X
X
HIGH-Z
HIGH-Z
DIN
Output Disable
H
H
VID
L
H
X
X
X
Write (Program/Erase)
Enable Sector Protection (2), (4)
Verify Sector Protection (2), (4)
Temporary Sector Unprotection (5)
Reset (Hardware)/Standby
L
L
A0
L
A1
H
H
X
A9
VID
VID
X
L
X
L
H
X
X
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
Table 3 MBM29LV160T/B User Bus Operation (BYTE = VIL)
DQ15
Operation
CE OE WE
A0
A1
A6
A9
DQ0 to DQ7
RESET
/A-1
Auto-Select Manufacture Code (1)
Auto-Select Device Code (1)
Read (3)
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
L
H
A0
X
X
A0
L
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
H
H
H
H
H
H
H
H
VID
L
L
L
A-1
X
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
HIGH-Z
HIGH-Z
DIN
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection (2), (4)
Verify Sector Protection (2), (4)
Temporary Sector Unprotection (5)
Reset (Hardware)/Standby
A-1
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
Legend: L = VIL, H = VIH, X = VIL or VIH.
= pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 7.
2. Refer to the section on Sector Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ±10%
5. It is also used for the extended sector protection.
10
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29LV160
T
-80
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PN
=46-Pin Small Outline Nonleaded
Package (SON)
PCV = 48-Pin C- leaded Small Outline
Package (CSOP)
PBT = 48-Pin Fine Pitch Ball Grid Array
Package (FBGA:BGA-48P-M03)
PBT- SF2= 48-Pin Fine Pitch Ball Grid Array
Package (FBGA:BGA-48P-M13)
SPEED OPTION
See Product Selector Guide
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV160
16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Write, and Erase
11
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV160T/B has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC - tOE time.) See Figure 5.1 for timing specifications.
Standby Mode
There are two ways to implement the standby mode on the MBM29LV160T/B devices. One is by using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from
either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V
(CE = “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is
taken high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode, the outputs are in the high-impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV160T/B data. This mode can be used effectively with an application requesting low power consumption
such as handy terminals.
To activate this mode, MBM29LV160T/B automatically switches itself to low power mode when addresses remain
stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the current
consumed is typically 1 µA (CMOS Level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to
be in a high-impedance state.
Autoselect
The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command may also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range
of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Table 2 or Table 3.)
12
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV160T/B is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 7, Command Definitions.
Byte 0 (A0 = VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code.
For the MBM29LV160T/B these two bytes are given in the Table 4.2. All identifiers for manufactures and device
will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing
the Autoselect, A1 must be VIL. (See Tables 2 or 3.) For device indentification in word mode (BYTE = VIH), DQ9
and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’.
If BYTE = VIL (for byte mode), the device code is C4H (for top boot block) or 49H (for bottom boot block). If BYTE
= VIH (for word mode), the device code is 22C4H (for top boot block) or 2249H (for bottom boot block).
In order to determine which sectors are write protected, A1 must be at VIH while running through the sector
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1).
Table 4.1 MBM29LV160T/B Sector Protection Verify Autoselect Code
Code
Type
Manufacture’s Code
A12 to A18
A6
A1
A0
A-1*1
(HEX)
X
VIL
VIL
VIL
VIL
VIL
X
04H
Byte
Word
Byte
C4H
MBM29LV160T
MBM29LV160B
X
X
VIL
VIL
VIH
22C4H
49H
Device Code
VIL
X
VIL
VIL
VIL
VIH
VIH
VIL
Word
2249H
Sector
Addresses
Sector Protection
VIL
01H*2
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 4.2 Expanded Autoselect Code Table
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
Manufacture’s Code
04H A-1/0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
(B)
C4H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29LV160T
(W) 22C4H
0
0
1
0
0
0
1
0
Device
Code
(B)
49H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29LV160B
(W)
2249H
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Sector Protection
01H A-1/0
(B): Byte mode
(W): Word mode
13
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 5 Sector Address Tables (MBM29LV160T)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range (× 16) Address Range
Address
SA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1F7FFFH
1F8000H to 1F9FFFH
1FA000H to 1FBFFFH
1FC000H to 1FFFFFH
00000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to AFFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FBFFFH
FC000H to FCFFFH
FD000H to FDFFFH
FE000H to FEFFFH
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
1
1
0
1
1
1
X
14
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 6 Sector Address Tables (MBM29LV160B)
Sector
Address
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range (× 16) Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
00000H to 03FFFH
04000H to 05FFFH
06000H to 07FFFH
08000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 1FFFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1FFFFFH
00000H to 01FFFH
02000H to 02FFFH
03000H to 03FFFH
04000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to 8FFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FFFFFH
SA2
0
1
1
SA3
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
15
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Write
Device erasure and programming are accomplished via the command register. The command register is written
by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or
WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.
Standard microprocessor write timings are used. See Figures 6 to 8.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29LV160T/B features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to
the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual
sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated
with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 16
and 24 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)
while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the
device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and
A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes. A-1 requires to VIL in byte mode.
ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing
a read operation at the address location XX02H, where the higher order addresses pins (A19, A18, A17, A16, A15,
A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See
Tables 4.1 and 4.2 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV160T/B devices in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12
V). Duringthismode, formerlyprotectedsectorscanbeprogrammedorerasedbyselectingthesectoraddresses.
Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.
(See Figures 18 and 25.)
16
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 7 MBM29LV160T/B Standard Command Definitions
Second
Bus
Fourth Bus
Read/Write
Cycle
Command
Sequence
First Bus
Third Bus
Fifth Bus
Sixth Bus
Bus
Write Write Cycle
Write Cycle
Write Cycle Write Cycle
Write Cycle
Cycles
Req'd
(Notes 1, 2, 3, 5)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Word
/Byte
Read/Reset
(Note 6)
1
3
XXXH F0H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Word
Byte
555H
AAH
2AAH
555H
2AAH
555H
2AAH
555H
AAAH
555H
AAAH
555H
Read/Reset
(Note 6)
55H
F0H RA
RD
AAAH
Word
Byte
555H
AAH
Autoselect
3
4
6
6
55H
55H
55H
55H
90H
—
—
—
—
—
—
—
—
—
—
AAAH
Byte/Word
Program
Word
555H
AAH
A0H PA
PD
Byte
AAAH
555H
AAAH
(Notes 3, 4)
Word
Byte
Word
Byte
555H
AAH
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
80H
2AAH
555H
2AAH
555H
555H
AAH
Chip Erase
AAH
AAH
55H
55H
10H
30H
AAAH
AAAH
555H
AAH
555H
80H
Sector Erase
(Note 3)
SA
AAAH
AAAH
Sector Erase
Suspend
Word
/Byte
1
1
XXXH B0H
XXXH 30H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Word
/Byte
Sector Erase
Resume
Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Tables 2 and 3.
3. RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA =Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.
5. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A-1 to A10
6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
17
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 8 MBM29LV160T/B Extended Command Definitions
Bus
Write
First Bus
Second Bus
Write Cycle
Third Bus
Fourth Bus
Read Cycle
Command
Sequence
Write Cycle
Write Cycle
Cycles
Req'd
Addr
Data
Addr
2AAH
555H
Data
Addr
Data
Addr
Data
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555H
AAAH
XXXH
XXXH
XXXH
XXXH
55H
555H
Set to Fast
3
2
2
2
4
AAH
55H
20H
—
—
Mode
AAAH
Fast Program *1
A0H
90H
98H
60H
PA
PD
F0H *4
—
—
—
—
—
—
—
—
—
XXXH
XXXH
Reset from Fast
Mode *1
Query
—
—
—
—
—
Command *2
AAH
Extended Sector
Protect *3
XXXH
SPA
60H
SPA
40H
SPA
SD
SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector
addresses.
*1. This command is valid while fast mode.
*2. Addresses from system set to A0 to A6. The other addresses are “Don’t care”.
*3. This command is valid while VID = RESET.
*4. The data" OOH" is also acceptable.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device remains enabled for reads until the command
register contents are altered.
Thedevicewillautomaticallypower-upintheRead/Resetstate. Inthiscase, acommandsequenceisnotrequired
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters. (See Figure 5.1.)
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
18
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A
read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the device code (MBM29LV160T = C4H and
MBM29LV160B = 49H for ×8 mode; MBM29LV160T = 22C4H and MBM29LV160B = 2249H for ×16 mode). (See
Tables 4.1 and 4.2.)
All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit.
The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).
Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce
a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
Word/Byte Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 20 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode.
(See Figure 8.)
Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
19
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
= 30H) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase
command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is
followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50 µs time-out window the timer is reset. Monitor DQ3 to determine if the sector
erase timer window is still open. (See section DQ3, Sector Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case,
restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for
Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 34).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations. (See Figure 8.)
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase
Time] × Number of Sector Erase.
Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when
writing the Erase Suspend or Erase Resume commands.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
20
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6)
which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29LV160T/B has Fast Mode function. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register.
(Refer to the Figure 26 Extended algorithm.) The VCC active current is required even CE = VIH during Fast
Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 26 Extended algorithm.)
(3) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-
compatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. Following the
command write, a read cycle from specific address retrives device information. Please note that output data
of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate
operation, it is necessary to write the read/reset command sequence into the register.
(4) Extended Sector Protect
In addition to normal sector protection, the MBM29LV160T/B has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only
RESET pinrequiresVID forsectorprotectioninthismode. TheextendedsectorprotectrequiresVID onRESET
pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command
register. Then, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0)
should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write
extended sector protect command (60H). A sector is typically protected in 150 µs. To verify programming of
the protection circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) =
(0, 1, 0) should be set and write a command (40H). Following the command write, a logical “1” at device
output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please
repeat to write extended sector protect command (60H) again. To terminate the operation, it is necessary
to set RESET pin to VIH.
21
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Write Operation Status
Table 9 Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded/Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
In
Erase
Progress
Erase Suspend Read
Suspend
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
(Note 1)
1
(Note 2)
Embedded Program Algorithm
Embedded/Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
Exceeded
Time
N/A
Limits
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle
1
0
N/A
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
DQ7
Data Polling
The MBM29LV160T/B device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 22.
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV160T/B data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm
or sector erase time-out.
See Figure 9 for the Data Polling timing specifications and diagrams.
22
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
DQ6
Toggle Bit I
TheMBM29LV160T/Balsofeaturethe“ToggleBitI”asamethodtoindicatetothehostsystemthattheEmbedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
200 µs and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See Figure 10 and Figure 23 for the Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in Tables 2 and 3.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the
second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
23
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
DQ2
Toggle Bit II
This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at DQ2.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 10 and Figure 19.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
Table 10 Toggle Bit Status
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle
Erase Suspend Read
(Erase Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ7
Toggle (Note 1)
1 (Note 2)
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
RY/BY
Ready/Busy Pin
The MBM29LV160T/B provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29LV160T/B is placed in an Erase Suspend
mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram. The RY/BY pin is
pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
24
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
RESET
Hardware Reset Pin
The MBM29LV160T/B device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
device requires an additional tRH before it allows read access. When the RESET pin is low, the device will be in
the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
thattheRY/BYoutputsignalshouldbeignoredduringtheRESETpulse. RefertoFigure12forthetimingdiagram.
Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
Word/Byte Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160T/B device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0 to
DQ15. Whenthispinisdrivenlow, thedeviceoperatesinbyte(8-bit)mode. Underthismode, DQ15/A-1 pinbecomes
the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit
operation and hence commands are written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Refer to Figures
13 and 14 for the timing diagrams.
Data Protection
The MBM29LV160T/B is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
Handling of SON Package
The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.
25
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Table 11 Common Flash Memory Interface Code
DQ0 to DQ15
DQ0 to DQ15
Description
A0 to A6
Description
A0 to A6
Query-unique ASCII string
“QRY”
10h
11h
12h
0051h
0052h
0059h
Erase Block Region 1
Information
2Dh
2Eh
2Fh
30h
0000h
0000h
0040h
0000h
Primary OEM Command Set
2h: AMD/FJ standard type
13h
14h
0002h
0000h
Erase Block Region 2
Information
31h
32h
33h
34h
0001h
0000h
0020h
0000h
Address for Primary
Extended Table
15h
16h
0040h
0000h
Alternate OEM Command
Set (00h = not applicable)
17h
18h
0000h
0000h
Erase Block Region 3
Information
35h
36h
37h
38h
0000h
0000h
0080h
0000h
Address for Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
VCC Min. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Bh
0027h
Erase Block Region 4
Information
39h
3Ah
3Bh
3Ch
001Eh
0000h
0000h
0001h
VCC Max. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Ch
0036h
VPP Min. voltage
VPP Max. voltage
1Dh
1Eh
1Fh
0000h
0000h
0004h
Query-unique ASCII string
“PRI”
40h
41h
42h
0050h
0052h
0049h
Typical timeout per single
byte/word write 2N µs
Major version number, ASCII
Minor version number, ASCII
43h
44h
45h
0031h
0030h
0000h
Typical timeout for Min. size
20h
21h
22h
23h
24h
25h
26h
27h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
0015h
buffer write 2N µs
Address Sensitive Unlock
0 = Required
1 = Not Required
Typical timeout per individual
block erase 2N ms
Erase Suspend
46h
47h
48h
0002h
0001h
0001h
Typical timeout for full chip
erase 2N ms
0 = Not Supported
1 = To Read Only
2 = To Read & Write
Max. timeout for byte/word
write 2N times typical
Sector Protect
Max. timeout for buffer write
2N times typical
0 = Not Supported
X = Number of sectors in per
group
Max. timeout per individual
block erase 2N times typical
Sector Temporary Unprotect
00 = Not Supported
01 = Supported
Max. timeout for full chip
erase 2N times typical
Device Size = 2N byte
Reserve
49h
4Ah
4Bh
4Ch
XXXXh
XXXXh
XXXXh
XXXXh
Flash Device Interface
description
28h
29h
0002h
0000h
Max. number of byte in
multi-byte write = 2N
2Ah
2Bh
0000h
0000h
Number of Erase Block
Regions within device
2Ch
0004h
26
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..................................................................................................–55°C to +125°C
Ambient Temperature with Power Applied ..................................................................–40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, and RESET (Note 1)............–0.5 V to +VCC +0.5 V
VCC (Note 1) ................................................................................................................–0.5 V to +5.5 V
A9, OE, and RESET (Note 2) ......................................................................................–0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC
+0.5 V. During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Ambient Temperature (TA)
MBM29LV160T/B-80.................................................................................–20°C to +70°C
MBM29LV160T/B-90/-12...........................................................................–40°C to +85°C
VCC Supply Voltages
MBM29LV160T/B-80.................................................................................+3.0 V to +3.6 V
MBM29LV160T/B-90/-12...........................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is quaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
27
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ MAXIMUM OVERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
28
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
A9, OE, RESET Inputs Leakage VCC = VCC Max.,
ILIT
—
—
35
µA
Current
A9, OE, RESET = 12.5 V
Byte
Word
Byte
Word
30
35
15
17
35
CE = VIL, OE = VIH
f = 10 MHz
mA
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH
f = 5 MHz
—
mA
ICC2
ICC3
ICC4
VCC Active Current (Note 2)
VCC Current (Standby)
CE = VIL, OE = VIH
—
—
mA
µA
VCC = VCC Max., CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
5
5
VCC = VCC Max.,
RESET = VSS ±0.3 V
VCC Current (Standby, RESET)
—
—
µA
µA
VCC = VCC Max., CE = VSS ±0.3 V,
RESET = VCC ±0.3 V,
VIN = VCC ±0.3 V or VSS ±0.3 V
VCC Current
(Automatic Sleep Mode) (Note 3)
ICC5
5
VIL
VIH
Input Low Level
Input High Level
—
—
–0.5
2.0
0.6
V
V
VCC + 0.3
Voltage for Autoselect,Sector
Protection, and Temporary
Sector Unprotection
VID
—
11.5
12.5
V
(A9, OE, RESET) (Note 4)
VOL
VOH1
VOH2
VLKO
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
IOL = 4.0 mA, VCC = VCC Min.
IOH = –2.0 mA, VCC = VCC Min.
IOH = –100 µA
—
2.4
0.45
—
V
V
V
V
VCC – 0.4
2.3
—
—
2.5
Notes: 1. The lCC current listed includes both the DC operating current and the frequency dependent component.
2. lCC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. (VID – VCC) do not exceed 9 V.
29
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
-80
(Note)
-90
(Note)
-12
(Note)
Description
Test Setup
Unit
JEDEC Standard
tAVAV
tAVQV
tRC
Read Cycle Time
—
Min.
Max.
80
80
90
90
120
120
ns
ns
CE = VIL
OE = VIL
tACC
Address to Output Delay
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output HIGH-Z
Output Enable to Output HIGH-Z
OE = VIL Max.
80
30
25
25
90
35
30
30
120
50
ns
ns
ns
ns
—
—
—
Max.
Max.
Max.
30
30
Output Hold Time From Address,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
—
Min.
Max.
Max.
0
20
5
0
20
5
0
20
5
ns
µs
ns
tREADY
RESET Pin Low to Read Mode
tELFL
tELFH
—
CE or BYTE Switching Low or High
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV160T/B-80/-90)
1 TTL gate and 100 pF (MBM29LV160T/B-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV160T/B-80/-90)
CL = 100 pF including jig capacitance (MBM29LV160T/B-12)
Figure 4 Test Conditions
30
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
• Write (Erase/Program) Operations
Parameter Symbols
JEDEC Standard
MBM29LV160T/B
Description
Unit
-80
-90
90
0
-12
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
—
tWC
tAS
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
80
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
45
35
0
45
45
0
50
50
0
tDS
tDH
tOES
Output Enable Setup Time
0
0
0
Read
0
0
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
0
10
0
10
0
tGHWL
tGHEL
tGHWL
tGHEL
Read Recover Time Before Write
Read Recover Time Before Write
(OE High to CE Low)
Min.
0
0
0
ns
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tCS
tWS
tCH
CE Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
WE Setup Time
CE Hold Time
0
0
0
tWH
tWP
tCP
WE Hold Time
0
0
0
Write Pulse Width
CE Pulse Width
Write Pulse Width High
CE Pulse Width High
35
35
25
25
8
45
45
25
25
8
50
50
30
30
8
tWPH
tCPH
Byte
tWHWH1
tWHWH1
Programming Operation
Typ.
µs
Word
16
1
16
1
16
1
tWHWH2
—
tWHWH2
tEOE
Sector Erase Operation (Note 1)
Typ.
Max.
Min.
Min.
Min.
Min.
Min.
Min.
sec
ns
µs
µs
µs
µs
µs
ns
Delay Time from Embedded Output Enable
VCC Setup Time
30
50
4
35
50
4
50
50
4
—
tVCS
—
tVLHT
tWPP
tOESP
tCSP
Voltage Transition Time (Note 2)
Write Pulse Width (Note 2)
—
100
4
100
4
100
4
—
OE Setup Time to WE Active (Note 2)
CE Setup Time to WE Active (Note 2)
Recover Time From RY/BY
—
4
4
4
—
tRB
0
0
0
(Continued)
31
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
Parameter Symbols
JEDEC Standard
MBM29LV160T/B
Description
Unit
-80
-90
200
90
-12
—
—
—
—
—
—
tRH
tBUSY
tFLQZ
tFHQV
tVIDR
tRP
RESET Hold Time Before Read
Program/Erase Valid to RY/BY Delay
BYTE Switching Low to Output HIGH-Z
BYTE Switching High to Output Active
Rise Time to VID (Note 2)
Min.
Max.
Max.
Min.
Min.
Min.
200
90
200
90
ns
ns
ns
ns
ns
ns
30
35
50
30
35
50
500
500
500
500
500
500
RESET Pulse Width
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
32
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Change
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
tRC
Addresses
Addresses Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tCE
tOH
HIGH-Z
HIGH-Z
Outputs
Output Valid
Figure 5.1 AC Waveforms for Read Operations
33
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
tRC
Addresses
Addresses Stable
tACC
tRH
RESET
Outputs
tOH
HIGH-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
34
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
3rd Bus Cycle
Data Polling
555H
tWC
PA
PA
Addresses
tRC
tAS
tAH
CE
tCH
tCS
tCE
OE
tOE
tWP
tWPH
tGHWL
tWHWH1
WE
tDF
tOH
tDS
tDH
PD
DOUT
DOUT
A0H
DQ7
Data
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at word address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
35
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
3rd Bus Cycle
555H
Data Polling
PA
PA
Addresses
tWC
tAH
tAS
WE
tWS
tWH
OE
CE
tCP
tCPH
tWHWH1
tGHEL
tDS
tDH
PD
DOUT
DQ7
A0H
Data
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at word address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
36
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
2AAH
555H
555H
SA*
2AAH
Addresses
555H
tWC
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30H for Sector Erase
10H
AAH
AAH
55H
80H
55H
Data
VCC
tVCS
* : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAAH (Byte) for Chip
Erase.
2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8 AC Waveforms for Chip/Sector Erase Operations
37
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Valid Data
Data
Data
DQ7
DQ7
tWHWH1 or 2
DQ0 to DQ6
Valid Data
DQ0 to DQ6 = Output Flag
DQ0 to DQ6
(tEOE)
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
tDH
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
DQ6 = Toggle
DQ6 = Toggle
Data
DQ6
tOE
* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)
Figure 10 AC Waveforms for Taggle Bit I during Embedded Algorithm Operations
38
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 11 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
tRB
RY/BY
tREADY
Figure 12 RESET, RY/BY Timing Diagram
39
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
CE
OE
BYTE
DQ0 to DQ14
DQ0 to DQ7
tFHQV
DQ0 to DQ14
tELFH
DQ15
DQ15/A-1
A-1
Figure 13 Timing Diagram for Word Mode Configuration
CE
OE
BYTE
tELFL
DQ0 to DQ14
DQ0 to DQ14
DQ0 to DQ7
DQ15/A-1
DQ15
A-1
tFLQZ
Figure 14 Timing Diagram for Byte Mode Configuration
40
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
CE
The falling edge of the last WE signal
WE
Input
Valid
BYTE
tSET
(tAS)
tHOLD
(tAH)
Figure 15 BYTE Timing Diagram for Write Operations
41
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
A19, A18, A17
A16, A15, A14
A13, A12
SAX
SAY
A0
A1
A6
12 V
3 V
A9
tVLHT
12 V
3 V
OE
tVLHT
tVLHT
tWPP
WE
CE
tVLHT
tOESP
tCSP
01H
Data
VCC
tVCS
tOE
SAX = Sector Address for initial sector
SAY = Sector Address for next sector
Note: A-1 is VIL on byte mode.
Figure 16
AC Waveforms for Sector Protection Timing Diagram
42
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
VCC
tVCS
tVLHT
RESET
Add
tVIDR
SPAX
SPAX
SPAY
A0
A1
A6
CE
TIME-OUT
OE
WE
Data
60H
60H
40H
01H
60H
tOE
SPAX
SPAY
TIME-OUT : Time-out Window = 150 µs (min)
: Sector Address to be protected
: Next Sector Address to be protected
Figure 17 Extended Sector Protection Timing Diagram
43
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
VCC
tVIDR
tVCS
tVLHT
VID
3 V
3 V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection period
RY/BY
Figure 18 Temporary Sector Unprotection Timing Diagram
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 19 DQ2 vs. DQ6
44
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
EMBEDDED PROGRAM TM ALGORITHM
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
No
Verify Byte
?
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Figure 20 Embedded ProgramTM Algorithm
45
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
EMBEDDED PROGRAM TM ALGORITHM
Start
Write Erase Command
Sequece
(See Below)
Data Polling or Toggle Bit
from Device
No
Data = FFH
?
Yes
Erasure Completed
Individual Sector/Multiple Sector*
Chip Erase Command Sequence*
Erase Command Sequence
(Address/Command):
(Address/Command):
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
* : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Figure 21 Embedded EraseTM Algorithm
46
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
VA =Address for programming
=Any of the sector addresses
Start
within the sector being erased
during sector erase or multiple
erases operation.
Read Byte
=Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
operation.
(DQ0 to DQ7)
Addr. = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = VA
Yes
DQ7 = Data?
*
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 22 Data Polling Algorithm
47
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Start
Read
(DQ0 to DQ7)
Addr. = “H” or “L”
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = “H” or “L”
No
DQ6 = Toggle
? *
Yes
Fail
Pass
* : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1”.
Figure 23 Toggle Bit Algorithm
48
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Start
Setup Sector Addr.
(A19, A18, A17, A16,
A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID
A6 = CE = VIL, RESET = VIH
A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
( A1 = VIH, A0 = VIL,
Addr. = SA, A6 = VIL)*
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector?
No
Remove VID from A9
Device Failed
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
Figure 24 Sector Protection Algorithm
49
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 25 Temporary Sector Unprotection Algorithm
50
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
FAST MODE ALGORITHM
Start
555H/AAH
2AAH/55H
Set Fast Mode
555H/20H
XXXXH/A0H
In Fast Program
Program Address/Program Data
Data Polling Device
No
Verify Byte?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
XXXXH/90H
XXXXH/F0H
Reset Fast Mode
* : The sequence is applied for ×16 mode.
* : The addresses differ from ×8 mode.
Figure 26 Embedded Programming Algorithm for Fast Mode
51
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
No
Extended Sector
Protect Entry?
Temporary Sector Unprotect
Mode
Yes
To Setup Sector Protect
Write XXXH/60H
PLSCNT = 1
To Sector Protect
Write 60H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Time out 150 µs
To Verify Sector Protect
Write 40H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Increment PLSCNT
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
Setup Next Sector Address
No
Data = 01H?
Yes
PLSCNT = 25?
Yes
Yes
Protect Other Sector
?
Remove VID from RESET
Write Reset Command
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Figure 27 Extended Sector Protect Algorithm
52
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
sec
µs
Comments
Min.
Typ.
Max.
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
Byte Programming Time
Word Programming Time
—
—
8
300
360
Excludes system-level
overhead
16
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
16.8
—
50
—
sec
100,000
cycles
—
■ TSOP (I) PIN CAPACITANCE
Parameter
Parameter Description
Symbol
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
7.5
8
9.5
10
13
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
10
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ SON PIN CAPACITANCE
Parameter
Parameter Description
Symbol
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
7.5
8
9.5
10
13
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
10
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ FBGA PIN CAPACITANCE
Parameter
Parameter Description
Symbol
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
7.5
8
9.5
10
13
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
10
Note: Test conditions TA = 25°C, f = 1.0 MHz
53
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
■ PACKAGE DIMENSIONS
48-pin plastic TSOP (I)
(FPT-48P-M19)
*: Resin protruction. (Each side: 0.15(.006) Max)
LEAD No.
1
48
Details of "A" part
0.15(.006)
MAX
INDEX
0.35(.014)
MAX
"A"
0.15(.006)
0.25(.010)
24
25
20.00±0.20
(.787±.008)
* 12.00±0.20
(.472±.008)
*18.40±0.20
(.724±.008)
11.50REF
(.460)
1.10−+00..1050
.043−+..000024
(MOUNTING
HEIGHT)
0.50(.0197)
TYP
0.05(0.02)MIN
STAND OFF
0.10(.004)
0.15±0.05
(.006±.002)
0.20±0.10
(.008±.004)
M
0.10(.004)
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
C
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions in mm (inches)
(Continued)
54
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
*: Resin protrusion. (Each side: 0.15(.006) Max)
48-pin plastic TSOP (I)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
0.25(.010)
24
25
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
0.20±0.10
(.008±.004)
M
0.10(.004)
0.50(.0197)
TYP
0.05(0.02)MIN
STAND OFF
0.10(.004)
1.10−+00..1050
*18.40±0.20
(.724±.008)
11.50(.460)REF
* 12.00±0.20(.472±.008)
.043−+..000024
(MOUNTING
HEIGHT)
20.00±0.20
(.787±.008)
C
Dimensions in mm (inches)
(Continued)
1996 FUJITSU LIMITED F48030S-2C-2
55
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
Note 1) Resin residue for * marked dimensions is 0.15 max on a single side.
46-pin plastic SON
Note 2) Die pad geometry may change with the models.
(LCC-46P-M02)
*12.00±0.10(.472±.004)
0.75(.030)MAX
0.50(.020)TYP
(TOTAL HEIGHT)
"A"
46
24
10.10±0.20
(.398±.008)
10.00±0.10
(.394±.004)
1
23
INDEX
M
0.05(.002)
Details of "B" part
0.10(.004)TYP
Details of "A" part
*0.50(.020)TYP
"B"
0.05(.002)
0.50(.020)TYP
0.32±0.05
0(0)MIN
(STAND OFF)
(.013±.002)
C
1997 FUJITSU LIMITED C46002S-4C-3
Dimensions in mm (inches)
(Continued)
56
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
48-pin plastic CSOP
(LCC-48P-M03)
"A"
48
25
10.00±0.20
(.394±.008)
9.50±0.10
(.374±.004)
INDEX
0.05 –+00.05
INDEX
.002 –+..0002
(Stand off)
1
24
LEAD No.
0.22±0.035
(.009±.001)
0.95±0.05(.037±.002)
(Mounting height)
10.00±0.10(.394±.004)
Details of "A" part
0°~10°
0.65(.026)
1.15(.045)
0.40(.016)
TYP
0.08(.003)
9.20(.362)REF
Dimensions in mm (inches)
(Continued)
C
1998 FUJITSU LIMITED C48056S-1C-1
57
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
48-pin plastic FBGA
(BGA-48P-M03)
Note: The actual shape of corners may differ from the dimension.
5.60(.221)
0.80(.031)NOM
9.00±0.20(.354±.008)
1.20(.047)MAX
(Mounting height)
0.35±0.10(.014±.004)
(Stand off)
6
5
4
3
2
1
0.80(.031)
NOM
4.00(.157)
8.00±0.20
(.315±.008)
INDEX
H
G
F
E
D
C
B
A
Ø0.40±0.10
(.016±.004)
M
Ø0.08(.003)
0.10(.004)
C
1997 FUJITSU LIMITED B48003S-1C-2
Dimensions in mm (inches)
(Continued)
58
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
(Continued)
48-pin plastic FBGA
Note: The actual shape of corners may differ from the dimension.
(BGA-48P-M13)
9.00±0.20(.354±.008)
1.05 +–00..1105 .041 –+..000046
(Mounting height)
5.60(.221)
0.80(.031)TYP
0.38±0.10(.015±.004)
(Stand off)
6
5
4
3
2
1
8.00±0.20
(.315±.008)
4.00(.157)
INDEX
H
G
F
E
D
C
B
A
C0.25(.010)
48-Ø0.45±0.10
(48-.018±.004)
M
Ø0.08(.003)
0.10(.004)
Dimensions in mm (inches)
C
1998 FUJITSU LIMITED B480013S-1C-1
59
MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
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FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inhereut chance inherently
a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9904
FUJITSU LIMITED Printed in Japan
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