MBM29LV080A-90PTN_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20870-5E

FLASH MEMORY

CMOS

8M (1M × 8) BIT

MBM29LV080A^-70/90/12

■ DESCRIPTION

The MBM29LV080A is a 16 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each. The 1 M bytes

of data is divided into 32 sectors of 64 K bytes of flexible erase capability. The 8 bits of data will appear on

DQ0 toDQ7. TheMBM29LV080Aisofferedina40-pinTSOP(I)package. Thedeviceisdesignedtobeprogrammed

in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV080A offers access times of 70 ns and 120 ns, allowing operation of high-speed micro-

processors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable

(WE), and output enable (OE) controls.

(Continued)

■ PRODUCT LINE UP

MBM29LV080A

-70

-90

-12

+0.3 V

–0.3 V

+0.6 V

3.0 V

–0.3 V

Power Supply Voltage V^CC(V)

3.3 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

70

90

35

120

50

70

30

■ PACKAGES

40-pin plastic TSOP (I)

Marking Side

(FPT-40P-M06)

(FPT-40P-M07)

MBM29LV080A-70/90/12

(Continued)

The MBM29LV080A is pin and command set compatible with JEDEC standard E²PROMs. Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an

internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the device is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV080A is programmed by executing the program command sequence. This will invoke the Embed-

ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and

verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase

is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm

which is an internal algorithm that automatically preprograms the array if it is not already programmed before

executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies

proper cell margins.

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV080A is erased when shipped from the factory.

Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of

time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally resets to the read mode.

The MBM29LV080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded

Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the

read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during

the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read

mode and will have erroneous data stored in the address locations being programmed or erased. These locations

need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up

firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29LV080A memory electrically erases all bits within

a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using

the EPROM programming mechanism of hot electron injection.

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MBM29LV080A-70/90/12

■ FEATURES

• Address specification is not necessary during command sequence

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Compatible with JEDEC-standard world-wide pinouts

40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)

• Minimum 100,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

16 sectors of 64 K bytes each

Any combination of sectors can be concurrently erased. MBM29LV080A also supports full chip erase.

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TM* Algorithms

Automatically programs and verifies data at specified address

• Data polling and toggle bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Low V^CCwrite inhibit ≤ 2.5 V

• Hardware RESET pin

Resets internal state machine to the read mode

• Erase suspend/resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector protection set function by extended sector protect command

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin

*: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

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MBM29LV080A-70/90/12

■ PIN ASSIGNMENTS

TSOP (I)

1

A16

A15

A14

A13

A12

A11

A9

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17

2

VSS

N.C.

A19

(Marking Side)

3

4

5

A10

6

DQ7

DQ6

DQ5

DQ4

VCC

N.C.

DQ3

DQ2

DQ1

DQ0

OE

7

8

A8

9

WE

RESET

N.C.

RY/BY

A18

A7

10

11

12

13

14

15

16

17

18

19

20

Normal Bend

A6

A5

A4

A3

VSS

CE

A0

A2

A1

FPT-40P-M06

20

19

18

17

16

15

14

13

12

11

10

9

A1

A2

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

A0

(Marking Side)

Reverse Bend

CE

A3

VSS

OE

A4

A5

DQ0

DQ1

DQ2

DQ3

N.C.

VCC

DQ4

DQ5

DQ6

DQ7

A10

A6

A7

A18

RY/BY

N.C.

RESET

WE

A8

8

7

A9

6

A11

A12

A13

A14

A15

A16

5

4

A19

3

N.C.

VSS

A17

2

1

FPT-40P-M07

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MBM29LV080A-70/90/12

■ PIN DESCRIPTIONS

Pin Name

A⁰to A¹⁹

DQ⁰to DQ⁷

CE

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

WE

Write Enable

RY/BY

RESET

V^SS

Ready/Busy Output

Hardware Reset Pin/Temporary Sector Unprotection

Device Ground

V^CC

Device Power Supply

Pin Not Connected Internally

N.C.

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MBM29LV080A-70/90/12

■ BLOCK DIAGRAM

DQ0 to DQ7

RY/BY

Buffer

RY/BY

VCC

VSS

Erase Voltage

Generator

Input/Output

Buffers

WE

State

Control

RESET

Command

Register

Program Voltage

Generator

STB

Chip Enabl

Output Enable

Logic

Data Latch

CE

OE

Y-Decoder

Y-Gating

STB

Time for

Program/Erase

Address

Latch

Low VCC Detector

Cell Matrix

X-Decoder

A0 to A19

■ LOGIC SYMBOL

20

A0 to A19

8

DQ0 to DQ7

CE

OE

WE

RY/BY

RESET

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MBM29LV080A-70/90/12

■ DEVICE BUS OPERATIONS

Table 1 User Bus Operation

Operation

Auto-Select Manufacture Code *¹

Auto-Select Device Code *¹

Read*²

CE

OE WE

A⁰

L

A¹

L

A⁶

L

A⁹

VID

A9

X

A¹⁰DQ⁰to DQ⁷RESET

L

H

L

X

L

H

X

H

L

Code

DOUT

High-Z

DIN

H

VID

L

H

A0

X

L

A1

X

A6

X

A6

L

A10

X

Standby

X

H

VID

L

Output Disable

X

Write (Program/Erase)

Enable Sector Protection *^3,*⁴

Verify Sector Protection *^3,*⁴

Temporary Sector Unprotection *⁵

Reset (Hardware)/Standby

A⁰

L

A1

H

X

A9

VID

X

A10

X

H

X

L

Code

X

High-Z

Legend: L = V^IL, H = VIH, X = VIL or VIH.

= pulse input. See “■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics” for voltage levels.

*1 : Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 3.

*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*3 : Refer to the section on Sector Protection.

*4 : V^CC= 3.3 V ±10%

*5 : It is also used for the extended sector protection.

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MBM29LV080A-70/90/12

Table 2 Standard Command Definitions

Second

Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Third Bus

Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Command

Sequence

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset*

1

3

XXXh F0h

—

XXXh AAh XXXh 55h XXXh F0h

XXXh AAh XXXh 55h XXXh 90h

XXXh AAh XXXh 55h XXXh A0h

RA

RD

Autoselect

3

4

6

—

Byte Program

Chip Erase

Sector Erase

PA

PD

XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h XXXh 10h

XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h

SA

—

30h

—

Sector Erase

Suspend

1

XXXh B0h

XXXh 30h

—

Sector Erase

Resume

—

*: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Notes: • Address bit = X = “H” or “L”.

• Bus operations are defined in “Table 1 User Bus Operation”.

• RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA = Address of the sector to be erased. The combination of A19, A18, A17, and A16 will uniquely select

any sector.

• RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

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MBM29LV080A-70/90/12

Table 3 Extended Command Definitions

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read Cycle

Command

Sequence

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Fast Mode Set

3

2

XXXh

AAh

A0h

90h

XXXh

PA

55h

PD

XXXh

—

20h

—

Fast Program *¹

Fast Mode Reset *¹

XXXh F0h *³

—

Extended Sector

Protection *²

4

XXXh

60h

SPA 60h

SPA

40h

SPA

SD

SPA:Sector address to be protected. Set sector address (SA) and (A¹⁰, A6, A1, A0) = (0, 0, 1, 0).

SD: Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected

sector addresses.

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET=VID.

*3: The data “00h” is also acceptable.

Table 4.1 Sector Protection Verify Autoselect Code

Type

Manufacture’s Code

Device Code

A¹⁶to A¹⁹

A¹⁰

V^IL

A⁶

VIL

A¹

VIL

A⁰

VIL

VIH

Code (HEX)

04h

X

38h

Sector

Addresses

Sector Protection

VIL

VIH

VIL

01h*

*: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.

Table 4.2 Expanded Autoselect Code

Type

Manufacture’s Code

Device Code

Code

04h

DQ⁷

0

DQ⁶

0

DQ⁵

0

DQ⁴

0

DQ³

0

DQ²

1

DQ¹

DQ⁰

0

38h

0

1

0

Sector Protection

01h

0

1

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MBM29LV080A-70/90/12

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• Sixteen 64 K byte sectors

• Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15).

• Individual-sector or multiple-sector erase capability

• Sector protection is user-definable.

FFFFFh

64 Kbytes

EFFFFh

64 Kbytes

DFFFFh

64 Kbytes

CFFFFh

64 Kbytes

BFFFFh

64 Kbytes

AFFFFh

64 Kbytes

9FFFFh

64 Kbytes

8FFFFh

64 Kbytes

7FFFFh

64 Kbytes

6FFFFh

64 Kbytes

5FFFFh

64 Kbytes

4FFFFh

64 Kbytes

3FFFFh

64 Kbytes

2FFFFh

64 Kbytes

1FFFFh

64 Kbytes

0FFFFh

64 Kbytes

00000h

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MBM29LV080A-70/90/12

Table 5 Sector Address

A¹⁷

Sector

Address

A¹⁹

A¹⁸

A¹⁶

Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

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MBM29LV080A^-70/90/12

■ FUNCTIONAL DESCRIPTION

Read Mode

The MBM29LV080A has two control functions which must be satisfied in order to obtain data at the outputs. CE

is the power control and should be used for a device selection. OE is the output control and should be used to

gate data to the output pins if a device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC - tCE time.) See “Figure 5.1 Read Operation Timing Diagram” for

timing specifications.

Standby Mode

There are two ways to implement the standby mode on the MBM29LV080A device, one using both the CE and

RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.

Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC

Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from

either of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE

= “H” or “L”). Under this condition the current is consumed is less than 5 µA Max. Once the RESET pin is taken

high, the device requires tRH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV080A

data.

Thismodecanbeusedeffectivelywithanapplicationrequestedlowpowerconsumptionsuchashandyterminals.

To activate this mode, MBM29LV080A automatically switches itself to low power mode when MBM29LV080A

addresses remain stably during access time of 150 ns. It is not necessary to control CE, WE, and OE on the

mode. Under the mode, the current consumed is typically 1 µA (CMOS level).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Output Disable

With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the device to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the device.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All

addresses are DON’T CARES except A0, A1, A6, and A10. (See “Table 4.1 Sector Protection Verify Autoselect

Code”.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29LV080A is erased or programmed in a system without access to high voltage on the A⁹pin. The command

sequence is illustrated in Table 2. (Refer to Autoselect Command section.)

Byte 0 (A⁰= VIL) represents the manufacture’s code (Fujitsu = 04h) and byte 1 (A0 = VIH) represents the device

identifier code MBM29LV080A = 38h. All identifiers for manufactures and device will exhibit odd parity with DQ7

defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be

VIL. (See “Table 4.1 Sector Protection Verify Autoselect Code” and “Table 4.2 Expanded Autoselect Code”.)

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MBM29LV080A-70/90/12

In order to determine which sectors are write protected, A¹must be at VIH while running through the sector

addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1).

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Timing Diagram for specific timing parameters.

Sector Protection

The MBM29LV080A features hardware sector protection. This feature will disable both program and erase

operations in any number of sectors (0 through 15). The sector protection feature is enabled using programming

equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, (suggest

VID = 11.5 V), CE = VIL, A0 = A6 = VIL, and A1 = VIH. The sector addresses (A19, A18, A17,and A16) should be set to

the sector to be protected. Table 5 define the sector address for each of the sixteen (16) individual sectors.

Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the

rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 13 and 21

for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17,and A16) while (A10, A6, A1,

A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices

will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A6, and A10 are

DON’T CARES. Address locations with A¹= VIL are reserved for Autoselect manufacturer and device codes.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing

a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17,and A16). are

the sector address will produce a logical “1” at DQ0 for a protected sector. See “Table 4.1 Sector Protection Verify

Autoselect Code” and “Table 4.2 Expanded Autoselect Code” for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29LV080A device in order

to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V).

During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.

Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.

See “Figure 15 Temporary Sector Unprotection Timing Diagram” and “Figure 22 Temporary Sector Unprotection

Algorithm”.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to

read mode. “Table 3 Extended Command Definitions” defines the valid register command sequences. Note that

the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the sector Erase operation

is in progress. Moreover, both Read/Reset commands are functionally equivalent, resetting the device to the

read mode. Please note that commands are always written at DQ⁰to DQ7 bits are ignored.

Read/Reset Command

The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

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MBM29LV080A-70/90/12

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-

istics and the specific timing parameters.(See “Figure 5.1 Read Operation Timing Diagram” and “Figure 5.2

Hardware Reset/Read Operation Timing Diagram”.)

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the device resides in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-

lowing the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address X001h returns the device code (MBM29LV080A = 38h). (See “Table 4.1 Sector Protection

Verify Autoselect Code” and “Table 4.2 Expanded Autoselect Code”.)

All manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.

Sector state (protection or unprotection) will be informed address X0002h.

Scanning the sector addresses (A¹⁹, A18, A17, A16) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce a logical “1” at

device output DQ0 for a protected sector. The programming verification should be perform margin mode on the

protected sector. (See “■ DEVICE BUS OPERATIONS”.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-

quence.

Byte Programming

The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two

“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are

latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of

CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide

further controls or timings. The device will automatically provide adequate internally generated program pulses

and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the device returns to the read mode and addresses are no longer latched. (See “Table 7 Toggle

Bit Status” and “Table 6 Hardware Sequence Flags”.) Therefore, the device requires that a valid address to the

device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at

the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-

gramming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device (exceed timing limits), or result

in an apparent success according to the data polling algorithm but a read from read/reset mode will show that

the data is still “0”. Only erase operations can convert “0”s to “1”s.

“Figure 17 Embedded Program^TMAlgorithm” illustrates the Embedded Program^TMAlgorithm using typical com-

mand strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Chip Erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase. The system is not required to provide any controls or timings during these

operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ7 is “1” (See “Write Operation Status”.) at which time the device returns to read the mode.

14

MBM29LV080A-70/90/12

“Figure 18 Embedded Erase^TMAlgorithm” illustrates the Embedded Erase^TMAlgorithm using typical command

strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of WE, while the command

(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last Sector

Erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on “Table 3 Extended

Command Definitions”. This sequence is followed with writes of the Sector Erase command to addresses in

other sectors desired to be concurrently erased. The time between writes must be less than 50 µs, otherwise

that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled

during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command

is written. A time-out of 50 µs from the rising edge of the last WE will initiate the execution of the Sector Erase

command(s). If another falling edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor

DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any

command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the

read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt

the data in that sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the

“Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any

sequence and with any number of sectors (0 to 15).

Sector erase does not require the user to program the devices prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the

remaining unselected sectors are not affected. The system is not required to provide any controls or timings

during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ7 is “1” (See the section on “Write Operation

Status”) at which time the device returns to the read mode. Data polling must be performed at an address within

any of the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector

Erase Time] × Number of Sector Erase.

“Figure 18 Embedded Erase^TMAlgorithm” illustrates the Embedded Erase^TMAlgorithm using typical command

strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command

during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the

erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when

writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/

BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of

the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on “DQ2”.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, pro-

15

MBM29LV080A-70/90/12

gramming in this mode is the same as programming in the regular Program mode except that the data must be

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6)

which is the same as the regular Program operation. Note that DQ7 must be read from the Program address

while DQ6 can be read from any address.

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Extended Command

(1) Fast Mode

MBM29LV080A has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the

standard program command sequence by writing Fast mode command into the command register. In this mode,

the required bus cycle for programming is two cycles instead of four bus cycles in normal command. (Do not

write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this

mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to “Figure 23

Extended Sector Protection Algorithm”.) The V^CCactive current is required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program Setup command (A0h) and data write cycles (PA/PD). (Refer to “Figure

23 Extended Sector Protection Algorithm”.)

(3) Extended Sector Protection

In addition to normal sector protection, the MBM29LV080A has Extended Sector Protection as extended function.

This function enables to protect sector by forcing V^IDon RESET pin and write a command sequence. Unlike

conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin

requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this

condition, the operation is initiated by writing the Setup command (60h) into the command register. Then, the

sector addresses pins (A19, A18, A17, and A16) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be set to the sector to be

protected (recommend to set VIL for the other addresses pins), and write extended sector protect command

(60h). A sector is typically protected in 250 µs. To verify programming of the protection circuitry, the sector

addresses pins (A19, A18, A17, and A16) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be set and write a command

(40h). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the

read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60h)

again. To terminate the operation, it is necessary to set RESET pin to VIH.

16

MBM29LV080A^-70/90/12

Write Operation Status

Table 6 Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded/Erase Algorithm

Toggle

0

1

Toggle

Erase Suspend Read

(Erase Suspended Sector)

1

0

Data

0

Data

0

Toggle

Data

1*²

In Progress

Erase

Erase Suspend Read

Suspend

Data

DQ⁷

Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle*¹

Embedded Program Algorithm

DQ⁷

0

Toggle

1

0

1

Exceeded Embedded/Erase Algorithm

N/A

Time Limits

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ7

Toggle

1

0

N/A

*1: Performing successive read operations from any address will cause DQ⁶to toggle.

*2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

Notes : • DQ0 and DQ1 are reserve pins for future use.

• DQ4 is Fujitsu internal use only.

DQ⁷

Data Polling

The MBM29LV080A device features Data Polling as a method to indicate to the host that the Embedded Algo-

rithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device

will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart

for Data Polling (DQ7) is shown in “Figure 19 Data Polling Algorithm”.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is

close to being completed, the MBM29LV080A data pins (DQ⁷) may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of

time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation

and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will

be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-

rithm, or sector erase time-out. (See “Table 7 Toggle Bit Status”.)

See “Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram” for the Data Polling timing

specifications and diagrams.

17

MBM29LV080A^-70/90/12

DQ⁶

Toggle Bit I

The MBM29LV080A also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 50 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ6 to toggle.

See “Figure 10 Toggle Bit 1 during Embedded Algorithm Operation Timing Diagram” and “Figure 20 Toggle Bit

Algorithm” for the Toggle Bit I timing specifications and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately

2 mA). The OE and WE pins will control the output disable functions as described in “■ DEVICE BUS OPER-

ATIONS”.

The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the

DQ5 bit will indicate a “1” . Please note that this is not a device failure condition since the device was incorrectly

used. If this occurs, reset the device with command sequence.

DQ³

Sector Erase Timer

After completion of the initial sector erase command sequence, the sector erase time-out begins. DQ³will remain

low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase command

sequence.

If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to

determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle

has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is

completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional Sector

Erase commands. To insure the command has been accepted, the system software should check the status of

DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status

check, the command may not have been accepted.

See “Table 6 Hardware Sequence Flags”.

DQ²

Toggle Bit II

This Toggle Bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

18

MBM29LV080A-70/90/12

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles

while DQ6 does not.) See also the below Table 7 and “Figure 16 DQ2 vs. DQ6”.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the devices are in the

erase mode, DQ2 toggles if this bit is read from the erasing sector.

Table 7 Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Erase-Suspend Read

1

Toggle

1*²

(Erase-Suspended Sector)*¹

Erase-Suspend Program

DQ7

Toggle*¹

*1: Performing successive read operations from any address will cause DQ⁶to toggle.

*2: Reading the address being programmed while in the erase-suspend program mode will indicate logic “1” at the

DQ²bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

RY/BY

Ready/Busy Pin

The MBM29LV080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with

either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase

operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands

with the exception of the Erase Suspend command. If the MBM29LV080A is placed in an Erase Suspend mode,

the RY/BY output will be high, by means of connecting with a pull up resistor to VCC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. See “Figure 11 RY/BY Timing Diagram during Program/Erase Opera-

tions” and “Figure 12 RESET, RY/BY Timing Diagram” for a detailed timing diagram. The RY/BY pin is pulled

high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

RESET

Hardware Reset Pin

The MBM29LV080A device may be reset by driving the RESETpin to VIL. The RESET pin has a pulse requirement

and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation

in the process of being executed will be terminated and the internal state machine will be reset to the read mode

tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes into high, the devices require

an additional tRH before it will allow read access. When the RESET pin is low, the device will be in the standby

mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during

a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY

output signal should be ignored during the RESET pulse. See “Figure 12 RESET, RY/BY Timing Diagram” for

the timing diagram. Refer to “Figure 15 Temporary Sector Unprotection Timing Diagram” for additional function-

ality.

If hardware reset occurs during Embedded Erase Algorithm, there is the possibility that the erasing sector(s)

cannot be used.

19

MBM29LV080A-70/90/12

Data Protection

The MBM29LV080A is designed to offer protection against accidental erasure or programming caused by spu-

rious system level signals that may exist during power transitions. During power up the device automatically

resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will be reset to the Read mode. Subsequent writes will be ignored

until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically

correct to prevent unintentional writes when VCC is above 2.3 V.

If Embedded Erase Algorithm is interrupted, there is the possibility that the erasing sector(s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

20

MBM29LV080A-70/90/12

■ ABSOLUTE MAXIMUM RATINGS

Rating

Unit

Parameter

Symbol

Conditions

Min.

Max.

Storage Temperature

Tstg

T^A

–55

+125

°C

Ambient Temperature with

Power Applied

–40

+85

Voltage with respect to

Ground All pins except A⁹,

OE, RESET *¹

VIN, VOUT

–0.5

VCC+0.5

V

Power Supply Voltage *¹

A9, OE, and RESET *²

VCC

VIN

–0.5

+5.5

V

+13.0

*1 : Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC

+ 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.

*2 : Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET

pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply

voltage (VIN − VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V

which may overshoot to 14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Value

Parameter

Ambient Temperature

Power Supply Voltage

Symbol

T^A

Conditions

Unit

Min.

–40

Max.

+85

°C

V

MBM29LV080A-70

MBM29LV080A-90/12

+3.0

+2.7

+3.6

V^CC

V

Note : Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

21

MBM29LV080A-70/90/12

■ MAXIMUM OVERSHOOT / UNDERSHOOT

20 ns

+0.6 V

−0.5 V

−2.0 V

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

V^CC+2.0 V

VCC +0.5 V

+2.0 V

20 ns

Figure 2 Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

V^CC+0.5 V

20 ns

Note : This waveform is applied for A9, OE and RESET.

Figure 3 Maximum Overshoot Waveform 2

22

MBM29LV080A-70/90/12

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Parameter

Symbol

Condition

Unit

Min.

–1.0

Max.

+1.0

Input Leakage Current

Output Leakage Current

ILI

VIN = VSS to VCC, VCC = VCC Max.

VOUT = VSS to VCC, VCC = VCC Max.

µA

I^LO

A9, OE, RESET Inputs Leakage

Current

VCC = VCC Max.,

A9, OE, RESET = 12.5 V

ILIT

—

35

µA

CE = VIL, OE = VIH, f = 10 MHz

CE = VIL, OE = VIH, f = 5 MHz

CE = VIL, OE = VIH

—

22

12

35

mA

V^CCActive Current*¹

ICC1

VCC Active Current *²

V^CCCurrent (Standby)

ICC2

ICC3

VCC = VCC Max., CE = VCC ±0.3 V,

RESET = VCC ±0.3 V

—

5

µA

V^CCCurrent during Reset

(Standby, RESET)

VCC = VCC Max.,

RESET = VSS ±0.3 V

ICC4

ICC5

VCC = VCC Max.,

V^CCCurrent

(Automatic Sleep Mode) *³

RESET = VCC ±0.3 V,

CE = VSS ±0.3 V, VIN = VCC ±0.3 V

or VSS ±0.3 V

—

5

µA

Input Low Level

Input High Level

VIL

VIH

—

–0.5

2.0

0.6

V

VCC + 0.3

Voltage for Autoselect,

Sector Protection and Temporary

Sector Unprotection

(A⁹, OE, RESET) *^4,*⁵

VID

—

11.5

12.5

V

Output Low Voltage Level

Output High Voltage Level

Low VCC Lock-Out Voltage

V^OL

V^OH1

VOH2

VLKO

IOL = 4.0 mA, VCC = VCC Min.

IOH = –2.0 mA, VCC = VCC Min.

IOH = –100 µA

—

2.4

0.45

—

V

VCC – 0.4

2.3

—

2.5

*1 : The lCC current listed includes both the DC operating current and the frequency dependent component.

*2 : lCC active while Embedded Erase or Embedded Program is in progress.

*3 : Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4 : This voltage is for Sector Protection operation.

*5 : (V^ID- VCC) do not exceed 9 V.

23

MBM29LV080A-70/90/12

2. AC Characteristics

• Read Only Operations Characteristics

Value

90

Symbol

Unit

Test

Setup

Parameter

70

12

JEDEC Standard

Min. Max. Min. Max. Min. Max.

Read Cycle Time

t^AVAV

tRC

—

70

—

90

—

120

—

ns

CE = VIL

OE = VIL

Address to Output Delay

tAVQV

tACC

—

70

—

90

—

120 ns

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

tEHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

—

70

30

25

—

90

35

30

—

50

30

ns

Output Hold Time From Address,

CE or OE, Whichever Occurs First

tAXQX

tOH

—

0

—

0

—

0

—

ns

RESET Pin Low to Read Mode

—

tREADY

—

20

—

20

—

20

µs

Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV080A-70)

1 TTL gate and 100 pF (MBM29LV080A-90/12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

3.3 V

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diodes = IN3064

or Equivalent

Notes: CL = 30 pF including jig capacitance (MBM29LV080A-70)

CL = 100 pF including jig capacitance (MBM29LV080A-90/12)

Figure 4 Test Conditions

24

MBM29LV080A-70/90/12

• Write (Erase/Program) Operations Characteristics

MBM29LV080A

Symbol

Parameter

70

90

12

Unit

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

JEDEC Standard

Write Cycle Time

tAVAV

tAVWL

t^WLAX

t^DVWH

tWHDX

—

tWC

tAS

70

0

90

0

120

0

ns

Address Setup Time

Address Hold Time

Data Setup Time

tAH

45

35

0

45

0

50

0

tDS

Data Hold Time

tDH

t^OES

Output Enable Setup Time

0

Read

0

Output Enable

—

t^OEH

Toggle and Data

Polling

Hold Time

10

0

10

0

10

0

ns

Read Recover Time Before Write

(OE High to WE Low)

tGHWL

tGHEL

tGHWL

tGHEL

Read Recover Time Before Write

(OE High to CE Low)

0

CE Setup Time

tELWL

tWLEL

tCS

tWS

0

ns

µs

s

WE Setup Time

CE Hold Time

tWHEH

tEHWH

tWLWH

tELEH

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

CE Pulse Width

tWP

35

25

45

25

50

30

tCP

Write Pulse Width High

CE Pulse Width High

Programming Operation

Sector Erase Operation *¹

tWHWL

tEHEL

tWPH

tCPH

tWHWH1

tWHWH2

t^WHWH1

tWHWH2

8

1

8

1

8

1

Delay Time from Embedded Out-

put Enable

—

tEOE

30

35

50

ns

V^CCSetup Time

—

tVCS

tVLHT

tWPP

tOESP

tCSP

tRB

50

4

50

4

50

4

µs

ns

Voltage Transition Time *²

Write Pulse Width*²

100

4

100

4

100

4

OE Setup Time to WE Active*²

CE Setup Time to WE Active*²

Recover Time From RY/BY

RESET Hold Time Before Read

4

0

tRH

200

(Continued)

25

MBM29LV080A-70/90/12

(Continued)

MBM29LV080A

90

Symbol

JEDEC Standard

Parameter

70

12

Unit

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Program/Erase Valid to RY/BY

Delay

—

tBUSY

90 90 90

ns

Rise Time to VID *²

—

tVIDR

tRP

500

ns

RESET Pulse Width

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Protection operation.

26

MBM29LV080A-70/90/12

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

“H” or “L”:

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-Z

“Off” State

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs

Output Valid

Figure 5.1 Read Operation Timing Diagram

27

MBM29LV080A-70/90/12

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tCE

tRH

RESET

Outputs

tOH

High-Z

Output Valid

Figure 5.2 Hardware Reset/Read Operation Timing Diagram

28

MBM29LV080A-70/90/12

Data Polling

3rd Bus Cycle

XXXh

Address

PA

tWC

tRC

tAS

tAH

CE

tCH

tCS

tCE

OE

tWP

tWPH

tOE

tGHWL

tWHWH1

WE

tDF

tOH

tDS

tDH

A0h

PD

DQ 7

DOUT

Data

Notes: • PA is an address of the memory location to be programmed.

• PD is data to be programmed at the byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Figure 6 Alternate WE Controlled Program Operation Timing Diagram

29

MBM29LV080A-70/90/12

3rd Bus Cycle

Data Polling

Address

WE

PA

XXXh

tWC

tAS

tAH

tWS

tWH

OE

CE

tCP

tCPH

tWHWH1

tGHEL

tDS

tDH

A0h

PD

DQ 7

DOUT

Data

Notes: • PA is an address of the memory location to be programmed.

• PD is data to be programmed at the byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Figure 7 Alternate CE Controlled Program Operation Timing Diagram

30

MBM29LV080A-70/90/12

XXXh

Address

XXXh

tWC

XXXh

SA*

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDH

tDS

30h for Sector Erase

10h

AAh

55h

80h

AAh

55h

Data

tVCS

VCC

*: SA is the sector address for Sector Erase. Addresses = XXXh for Chip Erase.

Figure 8 Chip/Sector Erase Operation Timing Diagram

31

MBM29LV080A-70/90/12

CE

tCH

tOE

tDF

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ

Valid Data⁰

Data

DQ6 to DQ0

RY/BY

DQ6 to DQ0 = Output Flag

tEOE

tBUSY

*: DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

CE

tOEH

WE

OE

tOES

tOEH

*

tDH

DQ6 =

Stop Toggling

DQ0 to DQ7

Data Valid

Data

DQ6 = Toggle

DQ⁶

tOE

*: DQ6 stops toggling. (The device has completed the Embedded operation.)

Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram

32

MBM29LV080A-70/90/12

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

Figure 11 RY/BY Timing Diagram during Program/Erase Operations

WE

RESET

tRP

tRB

RY/BY

tREADY

Figure 12 RESET, RY/BY Timing Diagram

33

MBM29LV080A-70/90/12

A¹⁹, A18

A17, A16

SAX

SAY

A10, A6, A0

A1

VID

VIH

A9

tVLHT

VID

V^IH

OE

tOESP

tVLHT

tWPP

tVLHT

WE

tCSP

CE

Data

V^CC

01h

tVLHT

tOE

SAX: Sector Address to be protected

SAY: Next Sector Address to be protected

Figure 13 Sector Protection Timing Diagram

34

MBM29LV080A-70/90/12

VCC

tVCS

tVLHT

RESET

Address

tVIDR

SPAX

SPAY

A10, A6, A0

A¹

CE

OE

TIME-OUT

WE

Data

60h

40h

01h

60h

tOE

SPAX: Sector Address to be protected

SPAY: Next Sector Address to be protected

TIME-OUT: Time-Out window = 250 µs (Min.)

Figure 14 Extended Sector Protection Timing Diagram

35

MBM29LV080A-70/90/12

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Figure 15 Temporary Sector Unprotection Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ6

DQ2

Toggle

DQ2 and DQ6

with OE or CE

Note: DQ2 is read from the erase-suspended sector.

Figure 16 DQ²vs. DQ⁶

36

MBM29LV080A-70/90/12

■ FLOW CHART

EMBEDDED ALGORITHM

Start

Write Program Command

Sequence

(See below)

Data Polling

Embeded

Program

Algorithm

in progress

No

Verify Data

?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence (Address/Command):

XXXh/AAh

XXXh/55h

XXXh/A0h

Program Address/Program Data

Figure 17 Embedded Program^TMAlgorithm

37

MBM29LV080A-70/90/12

EMBEDDED ALGORITHM

Start

Write Erase Command

Sequence

(See below)

Data Polling

Embeded

Program

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

XXXh/AAh

XXXh/55h

XXXh/80h

XXXh/AAh

XXXh/55h

XXXh/10h

XXXh/AAh

XXXh/55h

XXXh/80h

XXXh/AAh

XXXh/55h

Sector Address/30h

Additional sector

erase commands

are optional.

Sector Address/30h

Figure 18 Embedded Erase^TMAlgorithm

38

MBM29LV080A-70/90/12

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

erases operation.

Start

Read Byte

(DQ7 to DQ0)

Addr. = VA

= Any of the sector addresses

within the sector not being

protected during sector erase or

multiple sector erases

Yes

operation.

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

*: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 19 Data Polling Algorithm

39

MBM29LV080A-70/90/12

Start

Read DQ7 to DQ0

*1

Read DQ7 to DQ0

No

Toggle Bit

= Toggle

?

Yes

No

DQ5 = 1?

Yes

*1, *2

Read DQ7 to DQ0

Twice

No

Toggle Bit

= Toggle

?

Yes

Program/Erase

Operation Not

Complete. Write

Reset Command

Program/Erase

Operation Complete.

*1: Reset toggle bit twice to determine whether or not it is toggle.

*2: Recheck toggle bit because it may stop toggle as DQ5 changes to “1”.

Figure 20 Toggle Bit Algorithm

40

MBM29LV080A-70/90/12

Start

Setup Sector Addr.

(A19, A18, A17, A16)

PLSCNT = 1

OE = VID, A9 = VID,

A6 = CE = VIL, RESET = VIH

A0 = VIL, A1 = VIH

Activate WE Pulse

Time out 100 µs

Increment PLSCNT

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector

(A1 = VIH, A0 = VIL,

Addr. = SA, A6 = VIL)

No

PLSCNT = 25?

Yes

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector?

No

Device Failed

Remove VID from A9

Write Reset Command

Sector Protection

Completed

Figure 21 Sector Protection Algorithm

41

MBM29LV080A-70/90/12

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotection Completed

*2

*1: All protected sectors are unprotected.

*2: All previously protected sectors are protected once again.

Figure 22 Temporary Sector Unprotection Algorithm

42

MBM29LV080A-70/90/12

Start

RESET = VID

Wait to 4 µs

Device is Operating in

Temporary Secto

Unprotection Mode

No

Extended Sector

Protection Entry?

Yes

To Setup Sector Protection

Write XXXh/60h

PLSCNT = 1

To Sector Protection

Write 60h to Sector Address

(A0 = VIL, A1 = VIH, A6 = VIL)

Time out 250 µs

Increment PLSCNT

To Verify Sector Protection

Write 40h to Sector Address

(A0 = VIL, A1 = VIH, A6 = VIL)

Setup Next Sector Address

Read from Sector Address

(A0 = VIL, A1 = VIH, A6 = VIL)

No

PLSCNT = 25

Yes

?

Data = 01h?

Yes

Protect Other Sector

?

Remove VID from RESET

Write Reset Command

No

Device Failed

Remove VID from RESET

Write Reset Command

Sector Protection

Completed

Figure 23 Extended Sector Protection Algorithm

43

MBM29LV080A-70/90/12

FAST MODE ALGORITHM

Start

XXXh/AAh

XXXh/55h

XXXh/20h

XXXh/A0h

Set Fast Mode

Program Address/Program Data

Data Polling

In Fast Program

No

Verify Data?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Reset Fast Mode

Figure 24 Embedded Program^TMAlgorithm for Fast Mode

44

MBM29LV080A-70/90/12

■ ERASE AND PROGRAMMING PERFORMANCE

Limit

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Excludes system-level

overhead

Byte Programming Time

—

8

300

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

8.4

—

25

—

s

100,000

cycle

—

■ TSOP (I) PIN CAPACITANCE

Value

Unit

Parameter

Symbol

Test Setup

Typ.

Max.

Input Capacitance

C^IN

VIN = 0

7

8

10

pF

Output Capacitance

C^OUT

CIN2

VOUT = 0

VIN = 0

Control Pin Capacitance

10

12.5

Note: Test conditions TA = 25°C, f = 1.0 MHz

45

MBM29LV080A-70/90/12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29LV080

A

-70

PTN

PACKAGE TYPE

PTN = 40-pin Thin Small Outline Package

(TSOP (I)) Normal Bend

PTR = 40-pin Thin Small Outline Package

(TSOP (I)) Reverse Bend

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

DEVICE NUMBER/DESCRIPTION

MBM29LV080

8Mega-bit (1M × 8-Bit) CMOS Flash Memory

3.0 V-only Read, Program, and Erase

Part number

Package

Remarks

MBM29LV080A-70PTV

MBM29LV080A-90PTV

MBM29LV080A-12PTV

40-pin plastic TSOP(I)

(FPT-40P-M06)

Normal Bend

MBM29LV080A-70PTR

MBM29LV080A-90PTR

MBM29LV080A-12PTR

40-pin plastic TSOP(I)

(FPT-40P-M07)

Reverse Bend

46

MBM29LV080A-70/90/12

■ PACKAGE DIMENSIONS

40-pin plastic TSOP(I)

(FPT-40P-M06)

Details of "A" part

LEAD No.

1

40

0.15(.006)

MAX

0.35(.014)

MAX

INDEX

"A"

0.15(.006)

0.25(.010)

20

21

0.15±0.05

(.006±.002)

0.05(.002)MIN

(STAND OFF)

20.00±0.20

(.787±.008)

18.40±0.20

(.724±.008)

10.00±0.20

(.394±.008)

1.10 –⁺0⁰.^.0¹5⁰

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

(Mounting height)

0.50(.0197)

TYP

0.10(.004)

9.50(.374)

REF.

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.20±0.10

(.008±.004)

M

0.10(.004)

C

Dimensions in mm (inches).

2000 FUJITSU LIMITED F40007S-1C-2

40-pin plastic TSOP(I)

(FPT-40P-M07)

LEAD No.

1

40

Details of "A" part

0.15(.006)

MAX

0.35(.014)

INDEX

MAX

"A"

0.15(.006)

0.25(.010)

20

21

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

9.50(.374)

REF.

0.05(.002)MIN

(STAND OFF)

0.15±0.05

(.006±.002)

0.50(.0197)

TYP

0.10(.004)

1.10 –⁺0⁰.^.0¹5⁰

(Mounting height)

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

18.40±0.20

(.724±.008)

10.00±0.20

(.394±.008)

20.00±0.20

(.787±.008)

C

Dimensions in mm (inches).

2000 FUJITSU LIMITED F40008S-1C-2

47

MBM29LV080A-70/90/12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Marketing Division

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The products described in this document are designed, and

manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use,

and household use, but are not designed, developed and

manufactured as contemplated (1) for use accompanying fatal risks

or dangers that, unless extremely high safety is secured, could have

a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

http://www.fujitsu-fme.com/

Asia Pacific

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0107

FUJITSU LIMITED Printed in Japan


型号：	MBM29LV080A-90PTN
厂家：	FUJITSU
描述：	Flash, 1MX8, 90ns, PDSO40, PLASTIC, TSOP1-40 光电二极管
文件：	总48页 (文件大小：396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29LV080A-90PTN [FUJITSU]

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