MBM29LV080A-70 [FUJITSU]
8M (1M x 8) BIT; 8M （ 1M ×8 ）位
| 型号： | MBM29LV080A-70 |
| 厂家： | 
FUJITSU |
| 描述： | 8M (1M x 8) BIT |
| 文件： | 总49页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20870-4E
FLASH MEMORY
CMOS
8M (1M × 8) BIT
MBM29LV080A-70/-90/-12
■ FEATURES
• Address specification is not necessary during command sequence
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
• Minimum 100,000 program/erase cycles
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29LV080A
+0.3 V
–0.3 V
VCC = 3.3 V
-70
—
—
—
Ordering Part No.
+0.6 V
–0.3 V
VCC = 3.0 V
-90
-12
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
70
70
30
90
90
35
120
120
50
■ PACKAGE
40-pin plastic TSOP (I)
40-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-40P-M06)
(FPT-40P-M07)
MBM29LV080A-70/-90/-12
(Continued)
• High performance
70 ns maximum access time
• Sector erase architecture
16 sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM* Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector protect command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MBM29LV080A-70/-90/-12
■ GENERAL DESCRIPTION
The MBM29LV080A is a 16M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each. The 1M bytes
of data is divided into 32 sectors of 64K bytes of flexible erase capability. The 8 bits of data will appear on DQ0
to DQ7. The MBM29LV080A is offered in a 40-pin TSOP (I) package. The device is designed to be programmed
in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV080A offers access times of 70 ns and 120 ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV080A is pin and command set compatible with JEDEC standard E2PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV080A is programmed by executing the program command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and
verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase
is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV080A is erased when shipped from the factory.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV080A memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using
the EPROM programming mechanism of hot electron injection.
3
MBM29LV080A-70/-90/-12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• Sixteen 64K byte sectors
• Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15).
• Individual-sector or multiple-sector erase capability
• Sector protection is user-definable.
FFFFFH
64 Kbytes
EFFFFH
64 Kbytes
DFFFFH
64 Kbytes
CFFFFH
64 Kbytes
BFFFFH
64 Kbytes
AFFFFH
64 Kbytes
9FFFFH
64 Kbytes
8FFFFH
64 Kbytes
7FFFFH
64 Kbytes
6FFFFH
64 Kbytes
5FFFFH
64 Kbytes
4FFFFH
64 Kbytes
3FFFFH
64 Kbytes
2FFFFH
64 Kbytes
1FFFFH
64 Kbytes
0FFFFH
64 Kbytes
00000H
4
MBM29LV080A-70/-90/-12
■ BLOCK DIAGRAM
DQ0 to DQ7
RY/BY
Buffer
RY/BY
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
RESET
Command
Register
Program Voltage
Generator
STB
Chip Enabl
Output Enable
Logic
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
Time for
Program/Erase
Address
Latch
Low VCC Detector
Cell Matrix
X-Decoder
A0 to A19
5
MBM29LV080A-70/-90/-12
■ CONNECTION DIAGRAMS
TSOP (I)
1
A16
A15
A14
A13
A12
A11
A9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
2
VSS
N.C.
A19
(Marking Side)
3
4
5
A10
6
DQ7
DQ6
DQ5
DQ4
VCC
VCC
N.C.
DQ3
DQ2
DQ1
DQ0
OE
7
8
A8
9
WE
RESET
N.C.
RY/BY
A18
A7
10
11
12
13
14
15
16
17
18
19
20
MBM29LV080A
A6
A5
A4
A3
VSS
CE
A0
A2
A1
FPT-40P-M06
20
19
18
17
16
15
14
13
12
11
10
9
A1
A2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A0
(Marking Side)
MBM29LV080A
CE
A3
VSS
OE
A4
A5
DQ0
DQ1
DQ2
DQ3
N.C.
VCC
VCC
DQ4
DQ5
DQ6
DQ7
A10
A6
A7
A18
RY/BY
N.C.
RESET
WE
A8
8
7
A9
6
A11
A12
A13
A14
A15
A16
5
4
A19
3
N.C.
VSS
A17
2
1
FPT-40P-M07
6
MBM29LV080A-70/-90/-12
■ LOGIC SYMBOL
Table 1 MBM29LV080A Pin Configuration
Pin
Function
Address Inputs
A0 to A19
DQ0 to DQ7
20
Data Inputs/Outputs
A0 to A19
8
CE
OE
Chip Enable
DQ0 to DQ7
Output Enable
Write Enable
CE
OE
WE
WE
RY/BY
RESET
Ready/Busy Output
RY/BY
RESET
N.C.
VSS
Hardware Reset Pin/
Temporary Sector Unprotection
Pin Not Connected Internally
Device Ground
Device Power Supply
VCC
Table 2 MBM29LV080A User Bus Operation
Operation
Auto-Select Manufacture Code (1)
Auto-Select Device Code (1)
Read (2)
CE
L
OE WE
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
A10 DQ0 to DQ7 RESET
L
L
H
H
H
X
H
L
L
L
Code
Code
DOUT
H
H
H
H
H
H
H
H
VID
L
L
H
A0
X
L
L
L
L
A1
X
A6
X
X
A6
L
A10
X
Standby
H
L
X
H
H
VID
L
HIGH-Z
HIGH-Z
DIN
Output Disable
X
X
X
X
Write (Program/Erase)
Enable Sector Protection (3), (4)
Verify Sector Protection (3), (4)
Temporary Sector Unprotection (5)
Reset (Hardware)/Standby
L
A0
L
A1
H
H
X
A9
VID
VID
X
A10
X
L
X
L
H
X
X
L
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
Legend: L = VIL, H = VIH, X = VIL or VIH.
= pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 6.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Refer to the section on Sector Protection.
4. VCC = 3.3 V ±10%
5. It is also used for the extended sector protection.
7
MBM29LV080A-70/-90/-12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV080A has two control functions which must be satisfied in order to obtain data at the outputs. CE
is the power control and should be used for a device selection. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC - tCE time.) See Figure 5.1 for timing specifications.
Standby Mode
There are two ways to implement the standby mode on the MBM29LV080A device, one using both the CE and
RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from
either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV080A
data.
Thismodecanbeusedeffectivelywithanapplicationrequestedlowpowerconsumptionsuchashandyterminals.
To activate this mode, MBM29LV080A automatically switchs itself to low power mode when MBM29LV080A
addresses remain stably during access time of 150 ns. It is not necessary to control CE, WE, and OE on the
mode. Under the mode, the current consumed is typically 1 µA (CMOS level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, A6, and A10. (See Table 3.1.)
8
MBM29LV080A-70/-90/-12
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV080A is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table 6. (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacture’s code (Fujitsu = 04H) and byte 1 (A0 = VIH) represents the device
identifier code MBM29LV080A = 38H. All identifiers for manufactures and device will exhibit odd parity with DQ7
defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be
VIL. (See Tables 3.1 and 3.2.)
In order to determine which sectors are write protected, A1 must be at VIH while running through the sector
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1).
Table 3.1 MBM29LV080A Sector Protection Verify Autoselect Code
Type
A16 to A19
A10
VIL
VIL
A6
VIL
VIL
A1
VIL
VIL
A0
VIL
VIH
Code (HEX)
04H
Manufacture’s Code
X
X
Device Code
MBM29LV080A
38H
Sector
Addresses
Sector Protection
VIL
VIL
VIH
VIL
01H*
*: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 3.2 Expanded Autoselect Code Table
Type
Code
04H
38H
01H
DQ7
0
DQ6
0
DQ5
0
DQ4
0
DQ3
0
DQ2
1
DQ1
DQ0
0
Manufacture’s Code
0
0
0
Device Code
MBM29LV080A
0
0
1
1
1
0
0
Sector Protection
0
0
0
0
0
0
1
9
MBM29LV080A-70/-90/-12
Table 4 Sector Address Tables
Sector
Address
A19
A18
A17
A16
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
10
MBM29LV080A-70/-90/-12
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29LV080A features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 15). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, A0 = A6 = VIL, and A1 = VIH. The sector addresses (A19, A18, A17,and A16) should be set to
the sector to be protected. Tables 4 and 5 define the sector address for each of the sixteen (16) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 13 and 21
for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17,and A16) while (A10, A6, A1,
A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices
will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A6, and A10 are
DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A19, A18, A17,and A16). are
the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 3.1 and 3.2 for Autoselect
codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV080A device in order
to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V).
During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.
Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.
See figure 15 and 22.
11
MBM29LV080A-70/-90/-12
Table 5 MBM29LV080A Standard Command Definitions
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Bus
Write
Cycles
Req'd
Command
Sequence
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
(Notes 1, 2, 3)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
(Note 5)
1
XXXH F0H
XXXH AAH XXXH 55H XXXH F0H RA
XXXH AAH XXXH 55H XXXH 90H
XXXH AAH XXXH 55H XXXH A0H PA
—
—
—
—
—
—
—
—
—
—
Read/Reset
(Note 5)
3
3
4
6
6
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
Autoselect
—
Byte Program
(Notes 3, 4)
PD
Chip Erase
XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H XXXH 10H
Sector Erase
(Note 3)
XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H
SA
30H
Sector Erase
Suspend
1
1
XXXH B0H
XXXH 30H
Sector Erase
Resume
Notes: 1. Address bit = X = “H” or “L”.
2. Bus operations are defined in Table 2.
3. RA=Address of the memory location to be read.
PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA=Address of the sector to be erased. The combination of A19, A18, A17, and A16 will
uniquely select any sector.
4. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE.
5. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the sector Erase operation is in progress. Moreover, both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ0 to DQ7 bits are ignored.
12
MBM29LV080A-70/-90/-12
Table 6 MBM29LV080A Extended Command Definitions
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read Cycle
Command
Sequence
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Fast Mode Set
3
2
2
XXXH
XXXH
XXXH
AAH
A0H
90H
XXXH
PA
55H
PD
XXXH
—
20H
—
—
—
—
—
—
—
Fast Program *1
Fast Mode Reset *1
XXXH F0H *3
—
—
Extended Sector
Protection *2
4
XXXH
60H
SPA 60H
SPA
40H
SPA
SD
SPA:Sector address to be protected. Set sector address (SA) and (A10, A6, A1, A0) = (0, 0, 1, 0).
SD: Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected
sector addresses.
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET=VID.
*3: The data "00H" is also acceptable.
Read/Reset Command
The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-
istics and Waveforms for the specific timing parameters.(See Figures 5.1 and 5.2.)
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM pro-
grammers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-
lowing the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address X001H returns the device code (MBM29LV080A = 38H). (See Tables 3.1 and 3.2.)
All manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.
Sector state (protection or unprotection) will be informed address X0002H.
Scanning the sector addresses (A19, A18, A17, A16) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce a logical “1” at
device output DQ0 for a protected sector. The programming verification should be perform margin mode on the
protected sector. (See Table 2.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-
quence.
13
MBM29LV080A-70/-90/-12
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bitatwhichtimethedevicereturnstothereadmodeandaddressesarenolongerlatched. (SeeTable8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-
gramming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device (exceed timing limits), or result
in an apparent success according to the data polling algorithm but a read from read/reset mode will show that
the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Chip Erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last Sector
Erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs, otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the
sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector
Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous
command string. Resetting the devices once execution has begun will corrupt the data in that sector. In that
case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section
14
MBM29LV080A-70/-90/-12
for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 15).
Sector erase does not require the user to program the devices prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase
Time] × Number of Sector Erase.
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when
writing the Erase Suspend or Erase Resume commands.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-
mand sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, pro-
gramming in this mode is the same as programming in the regular Program mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6)
which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
15
MBM29LV080A-70/-90/-12
Extended Command
(1) Fast Mode
MBM29LV080A has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the
standard program command sequence by writing Fast mode command into the command register. In this mode,
the required bus cycle for programming is two cycles instead of four bus cycles in normal command. (Do not
write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this
mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 23
Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program Setup command (A0H) and data write cycles (PA/PD). (Refer to the
Figure 23 Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29LV080A has Extended Sector Protection as extended function.
This function enable to protect sector by forcing VID on RESET pin and write a command sequence. Unlike
conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin
requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this
condition, the operation is initated by writing the Setup command (60H) into the command register. Then, the
sector addresses pins (A19, A18, A17, and A16) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be set to the sector to be
protected (recommend to set VIL for the other addresses pins), and write extended sector protect command
(60H). A sector is typically protected in 250 µs. To verify programming of the protection cicuitry, the sector
addresses pins (A19, A18, A17, and A16) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be set and write a command
(40H). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the
read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60H)
again. To terminate the opetation, it is necessary to set RESET pin to VIH.
16
MBM29LV080A-70/-90/-12
Write Operation Status
Table 7 Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded/Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
In Progress
Erase
Erase Suspend Read
Suspend
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
(Note 1)
1
(Note 2)
Embedded Program Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
Exceeded Embedded/Erase Algorithm
N/A
Time Limits
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle
1
0
N/A
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
“1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
17
MBM29LV080A-70/-90/-12
DQ7
Data Polling
The MBM29LV080A device features Data Polling as a method to indicate to the host that the Embedded Algo-
rithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device
will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 19.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV080A data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, or sector erase time-out. (See Table 8.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29LV080A also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 50 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See Figure 10 and Figure 20 for the Toggle Bit I timing specifications and diagrams.
18
MBM29LV080A-70/-90/-12
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the
DQ5 bit will indicate a “1” Please note that this is not a device failure condition since the device was incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial Sector Erase command sequence the sector erase time-out will begin. DQ3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional Sector Erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the
second status check, the command may not have been accepted.
See Table 8: Hardware Sequence Flags.
DQ2
Toggle Bit II
This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles
while DQ6 does not.) See also above Table 9 and Figure 16.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the devices are in the
erase mode, DQ2 toggles if this bit is read from the erasing sector.
19
MBM29LV080A-70/-90/-12
Table 8 Toggle Bit Status
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ7
Toggle (Note 1)
1 (Note 2)
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
RY/BY
Ready/Busy Pin
The MBM29LV080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29LV080A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull up resistor to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram. The RY/BY pin is
pulled high in stadby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset Pin
The MBM29LV080A device may be reset by driving the RESETpin to VIL. The RESET pin has a pulse requirement
and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation
in the process of being executed will be terminated and the internal state machine will be reset to the read mode
tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices requires an
additional tRH before it will allow read access. When the RESET pin is low, the device will be in the standby mode
for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a
program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY
output signal should be ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Tem-
porary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
20
MBM29LV080A-70/-90/-12
Data Protection
The MBM29LV080A is designed to offer protection against accidental erasure or programming caused by spu-
rious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the Read mode. Subsequent writes will be ignored
until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
21
MBM29LV080A-70/-90/-12
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Conditions
Unit
Min.
Max.
Storage Temperature
Tstg
TA
–55
+125
°C
°C
Ambient Temperature with
Power Applied
–40
+85
Voltage with respect to
Ground All pins except A9,
OE, RESET (Note 1)
VIN, VOUT
–0.5
VCC+0.5
V
Power Supply Voltage
(Note 1)
VCC
–0.5
–0.5
+5.5
V
V
A9, OE, and RESET
(Note 2)
VIN
+13.0
Notes: 1. Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may
undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC
+ 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and
RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input
and supply voltage (VIN − VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and RESET
pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Value
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
Conditions
Unit
Min.
–40
Max.
+85
°C
V
MBM29DL16XTE/BE-70
+3.0
+2.7
+3.6
+3.6
VCC
MBM29DL16XTE/BE-90/12
V
Operating ranges define those limits between which the functionality of the device is quaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
22
MBM29LV080A-70/-90/-12
■ MAXIMUM OVERSHOOT / UNDERSHOOT
20 ns
20 ns
+0.6 V
−0.5 V
−2.0 V
20 ns
Figure 1 Maximum Undershoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2 Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
Figure 3 Maximum Overshoot Waveform 2
23
MBM29LV080A-70/-90/-12
■ DC CHARACTERISTICS
Parameter
Parameter Description
Symbol
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
A9, OE, RESET Inputs Leakage VCC = VCC Max.,
ILIT
—
35
µA
Current
A9, OE, RESET = 12.5 V
CE = VIL, OE = VIH, f = 10 MHz
CE = VIL, OE = VIH, f = 5 MHz
CE = VIL, OE = VIH
—
—
—
22
12
35
mA
mA
mA
ICC1
VCC Active Current (Note 1)
ICC2
VCC Active Current (Note 2)
VCC Current (Standby)
VCC = VCC Max., CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
ICC3
—
—
5
5
µA
µA
VCC Current during Reset
(Standby, RESET)
VCC = VCC Max.,
RESET = VSS ±0.3 V
ICC4
VCC = VCC Max.,
VCC Current
RESET = VCC ±0.3 V,
ICC5
—
5
µA
(Automatic Sleep Mode) (Note 3) CE = VSS ±0.3 V, VIN = VCC ±0.3 V
or VSS ±0.3 V
VIL
Input Low Level
Input High Level
—
—
–0.5
2.0
0.6
V
V
VIH
VCC + 0.3
Voltage for Autoselect,
Sector Protection and Temporary
Sector Unprotection
VID
—
11.5
12.5
V
(A9, OE, RESET) (Note 4, 5)
VOL
VOH1
VOH2
VLKO
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
IOL = 4.0 mA, VCC = VCC Min.
IOH = –2.0 mA, VCC = VCC Min.
IOH = –100 µA
—
2.4
0.45
—
V
V
V
V
VCC – 0.4
2.3
—
—
2.5
Notes: 1. The lCC current listed includes both the DC operating current and the frequency dependent component.
2. lCC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. This voltage is for Sector Protection operation.
5. (VID - VCC) do not exceed 9 V.
24
MBM29LV080A-70/-90/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
-70
(Note)
-90
(Note)
-12
(Note)
Description
Test Setup
Unit
JEDEC Standard
tAVAV
tRC
Read Cycle Time
—
Min.
Max.
70
70
90
90
120
120
ns
ns
CE = VIL
OE = VIL
tAVQV
tACC
Address to Output Delay
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output HIGH-Z
Output Enable to Output HIGH-Z
OE = VIL Max.
70
30
25
25
90
35
30
30
120
50
ns
ns
ns
ns
—
—
—
Max.
Max.
Max.
30
30
Output Hold Time From Address,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
Min.
0
0
0
ns
tREADY
RESET Pin Low to Read Mode
Max.
20
20
20
µs
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV080A-70)
1 TTL gate and 100 pF (MBM29LV080A-90/-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV080A-70)
CL = 100 pF including jig capacitance (MBM29LV080A-90/-12)
Figure 4 Test Conditions
25
MBM29LV080A-70/-90/-12
• Write (Erase/Program) Operations
Parameter Symbols
MBM29LV080A
Description
Unit
JEDEC Standard
-70
70
0
-90
90
0
-12
120
0
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
—
tWC
tAS
Write Cycle Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAH
45
35
0
45
45
0
50
50
0
tDS
tDH
tOES
Data Hold Time
Output Enable Setup Time
0
0
0
Read
0
0
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
10
10
Read Recover Time Before Write
(OE High to WE Low)
tGHWL
tGHWL
tGHEL
Min.
Min.
0
0
0
0
0
0
ns
ns
Read Recover Time Before Write
(OE High to CE Low)
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
—
tCS
tWS
CE Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
Typ.
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
WE Setup Time
tCH
CE Hold Time
0
0
0
tWH
WE Hold Time
0
0
0
tWP
Write Pulse Width
CE Pulse Width
35
35
25
25
8
45
45
25
25
8
50
50
30
30
8
tCP
tWPH
tCPH
tWHWH1
tWHWH2
tEOE
tVCS
tVLHT
tWPP
tOESP
tCSP
tRB
Write Pulse Width High
CE Pulse Width High
Programming Operation
Sector Erase Operation (Note 1)
1
1
1
Delay Time from Embedded Output Enable Max.
30
50
4
35
50
4
50
50
4
ns
µs
µs
µs
µs
µs
ns
ns
—
VCC Setup Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
—
Voltage Transition Time (Note 2)
Write Pulse Width (Note 2)
—
100
4
100
4
100
4
—
OE Setup Time to WE Active (Note 2)
CE Setup Time to WE Active (Note 2)
Recover Time From RY/BY
RESET Hold Time Before Read
—
4
4
4
—
0
0
0
—
tRH
200
200
200
(Continued)
26
MBM29LV080A-70/-90/-12
(Continued)
Parameter Symbols
MBM29LV080A
Unit
Description
JEDEC Standard
-70
90
-90
-12
—
—
—
tBUSY
tVIDR
tRP
Program/Erase Valid to RY/BY Delay
Rise Time to VID (Note 2)
RESET Pulse Width
Max.
Min.
Min.
90
90
ns
ns
ns
500
500
500
500
500
500
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
27
MBM29LV080A-70/-90/-12
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Change
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
tRC
Addresses
Addresses Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tOH
tCE
High-Z
High-Z
Outputs
Output Valid
Figure 5.1 AC Waveforms for Read Operations
28
MBM29LV080A-70/-90/-12
tRC
Addresses
Addresses Stable
tACC
tRH
RESET
Outputs
tOH
High-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
29
MBM29LV080A-70/-90/-12
Data Polling
3rd Bus Cycle
Addresses
XXXH
tWC
PA
PA
tRC
tAS
tAH
CE
tCH
tCS
tCE
OE
tWP
tWPH
tOE
tGHWL
tWHWH1
WE
tDF
tOH
tDS
tDH
A0H
PD
DQ 7
DOUT
DOUT
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
30
MBM29LV080A-70/-90/-12
3rd Bus Cycle
Data Polling
PA
Addresses
PA
XXXH
tWC
tAS
tAH
WE
tWS
tWH
OE
CE
tCP
tCPH
tWHWH1
tGHEL
tDS
tDH
A0H
PD
DQ 7
DOUT
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
31
MBM29LV080A-70/-90/-12
XXXH
XXXH
XXXH
Addresses
XXXH
tWC
XXXH
SA*
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDH
tDS
30H for Sector Erase
10H
AAH
55H
80H
AAH
55H
Data
tVCS
VCC
*: SA is the sector address for Sector Erase. Addresses = XXXH for Chip Erase.
Figure 8 AC Waveforms for Chip/Sector Erase Operations
32
MBM29LV080A-70/-90/-12
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
High-Z
DQ0 to DQ
Valid Data6
DQ0 to DQ6
DQ0 to DQ6 = Output Flag
tEOE
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
OE
tOES
tOEH
*
tDH
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
Data
DQ6 = Toggle
DQ6 = Toggle
DQ6
tOE
*: DQ6 stops toggling. (The device has completed the Embedded operation.)
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
33
MBM29LV080A-70/-90/-12
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 11 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
tRB
RY/BY
tREADY
Figure 12 RESET, RY/BY Timing Diagram
34
MBM29LV080A-70/-90/-12
A19, A18
A17, A16
SAX
SAY
A0
A1
A6, A10
12 V
3 V
A9
tVLHT
12
3 V
OE
WE
CE
tOESP
tVLHT
tVLHT
tVLHT
tWPP
tCSP
Data
VCC
01H
tVLHT
tOE
SAX: Sector Address for initial sector
SAY : Sector Address for next sector
Figure 13 AC Waveforms for Sector Protection Timing Diagram
35
MBM29LV080A-70/-90/-12
VCC
tVCS
tVLHT
RESET
Add
tVIDR
SPAX
SPAX
SPAY
A0
A1
A6, A10
CE
OE
TIME-OUT
WE
Data
60H
60H
40H
01H
60H
tOE
SPAX: Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (min.)
Figure 14 Extended Sector Protection Timing Diagram
36
MBM29LV080A-70/-90/-12
VCC
tVIDR
tVCS
tVLHT
VID
3 V
3 V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
Figure 15 Temporary Sector Unprotection Timing Diagram
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 16 DQ2 vs. DQ6
37
MBM29LV080A-70/-90/-12
■ FLOW CHART
EMBEDDED ALGORITHM
Start
Write Program Command
Sequence
(See below)
Data Polling
Embeded
Program
Algorithm
in progress
No
Verify Data
?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command):
XXXH/AAH
XXXH/55H
XXXH/A0H
Program Address/Program Data
Figure 17 Embedded ProgramTM Algorithm
38
MBM29LV080A-70/-90/-12
EMBEDDED ALGORITHM
Start
Write Erase Command
Sequence
(See below)
Data Polling
Embeded
Program
Algorithm
in progress
No
Data = FFH
?
Yes
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
XXXH/AAH
XXXH/AAH
XXXH/55H
XXXH/55H
XXXH/80H
XXXH/AAH
XXXH/55H
XXXH/10H
XXXH/80H
XXXH/AAH
XXXH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Figure 18 Embedded EraseTM Algorithm
39
MBM29LV080A-70/-90/-12
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
= Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
Yes
operation.
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
DQ7 = Data?
*
No
Fail
Pass
*: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 19 Data Polling Algorithm
40
MBM29LV080A-70/-90/-12
Start
Read DQ7 to DQ0
*1
Read DQ7 to DQ0
No
Toggle Bit
= Toggle
?
Yes
No
DQ5 = 1?
Yes
*1, *2
Read DQ7 to DQ0
Twice
No
Toggle Bit
= Toggle
?
Yes
Program/Erase
Operation Not
Complete. Write
Reset Command
Program/Erase
Operation Complete.
*1: Reset toggle bit twice to determine whether or not it is toggle.
*2: Recheck toggle bit because it may stop toggle as DQ5 changes to “1”.
Figure 20 Toggle Bit Algorithm
41
MBM29LV080A-70/-90/-12
Start
Setup Sector Addr.
(A19, A18, A17, A16)
PLSCNT = 1
OE = VID, A9 = VID,
A6 = CE = VIL, RESET = VIH
A0 = VIL, A1 = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
(A1 = VIH, A0 = VIL,
Addr. = SA, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
Figure 21 Sector Protection Algorithm
42
MBM29LV080A-70/-90/-12
Start
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
*2
*1: All protected sectors are unprotected.
*2: All previously protected sectors are protected once again.
Figure 22 Temporary Sector Unprotection Algorithm
43
MBM29LV080A-70/-90/-12
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Secto
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write 60H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Wait to 250 µs
Increment PLSCNT
To Verify Sector Protection
Write 40H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25
Yes
?
Data = 01H?
Yes
Yes
Protect Other Sector
?
Remove VID from RESET
Write Reset Command
No
Device Failed
Remove VID from RESET
Write Reset Command
Sector Protection
Completed
Figure 23 Extended Sector Protection Algorithm
44
MBM29LV080A-70/-90/-12
FAST MODE ALGORITHM
Start
XXXH/AAH
XXXH/55H
XXXH/20H
XXXH/A0H
Set Fast Mode
Program Address/Program Data
Data Polling Device
In Fast Program
No
Verify Data?
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
XXXH/90H
XXXH/F0H
Reset Fast Mode
Figure 24 Embedded ProgramTM Algorithm for Fast Mode
45
MBM29LV080A-70/-90/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
s
Excludes system-level
overhead
Byte Programming Time
—
8
300
µs
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
8.4
—
25
—
s
100,000
cycle
—
■ TSOP (I) PIN CAPACITANCE
Parameter
Parameter Description
Symbol
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
7
8
10
10
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
10
12.5
Note: Test conditions TA = 25°C, f = 1.0 MHz
46
MBM29LV080A-70/-90/-12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29LV080
A
-70
PTN
PACKAGE TYPE
PTN = 40-pin Thin Small Outline Package
(TSOP (I)) Standard Pinout
PTR = 40-pin Thin Small Outline Package
(TSOP (I)) Reverse Pinout
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
DEVICE NUMBER/DESCRIPTION
MBM29LV080
8Mega-bit (1M × 8-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
Part number
Package
Remarks
MBM29LV080A-70PTV
MBM29LV080A-90PTV
MBM29LV080A-12PTV
40-pin plastic TSOP(I)
(FPT-40P-M06)
Standard Pinout
MBM29LV080A-70PTR
MBM29LV080A-90PTR
MBM29LV080A-12PTR
40-pin plastic TSOP(I)
(FPT-40P-M07)
Reverse Pinout
47
MBM29LV080A-70/-90/-12
■ PACKAGE DIMENSIONS
40-pin plastic TSOP(I)
(FPT-40P-M06)
Details of "A" part
LEAD No.
1
40
0.15(.006)
MAX
0.35(.014)
MAX
INDEX
"A"
0.15(.006)
0.25(.010)
20
21
0.15±0.05
(.006±.002)
0.05(.002)MIN
(STAND OFF)
20.00±0.20
(.787±.008)
18.40±0.20
(.724±.008)
10.00±0.20
(.394±.008)
1.10 –+00..0150
.043 +–..000024
(Mounting height)
0.50(.0197)
TYP
0.10(.004)
9.50(.374)
REF.
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.20±0.10
(.008±.004)
M
0.10(.004)
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED F40007S-1C-1
40-pin plastic TSOP(I)
(FPT-40P-M07)
LEAD No.
1
40
Details of "A" part
0.15(.006)
MAX
0.35(.014)
INDEX
MAX
"A"
0.15(.006)
0.25(.010)
20
21
0.20±0.10
(.008±.004)
M
0.10(.004)
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
9.50(.374)
REF.
0.05(.002)MIN
(STAND OFF)
0.15±0.05
(.006±.002)
0.50(.0197)
TYP
0.10(.004)
1.10 –+00..0150
(Mounting height)
.043 +–..000024
18.40±0.20
(.724±.008)
10.00±0.20
(.394±.008)
20.00±0.20
(.787±.008)
C
Dimensions in mm (inches).
1994 FUJITSU LIMITED F40008S-1C-1
48
MBM29LV080A-70/-90/-12
FUJITSU LIMITED
For further information please contact:
Japan
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FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
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If any products described in this document represent goods or
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prior authorization by Japanese government should be required for
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F0008
FUJITSU LIMITED Printed in Japan
相关型号：
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