MB96F356AWBPMC-GSE2 [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB96F356AWBPMC-GSE2 |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总110页 (文件大小：3139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
FME-MB96350 rev 7
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96350 Series
MB96F353/F355
MB96F356
■ DESCRIPTION
MB96350 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
MB96350 Series
■ FEATURES
Feature
Description
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
CPU
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 56 MHz external clock
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
System clock
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
On-chip voltage regula-
tor
Low voltage reset
Code Security
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
Memory Patch Function
DMA
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
Timers
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
2
FME-MB96350 rev 7
MB96350 Series
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Up to 400 kbps
USART
I2C
• Master and Slave functionality, 7-bit and 10-bit addressing
• SAR-type
• 10-bit resolution
A/D converter
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Reload Timers
Free Running Timers
Input Capture Units
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of
peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
Programmable Pulse
Generator
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer underflow as clock input
• Can be triggered by software or reload timer
FME-MB96350 rev 7
3
MB96350 Series
Feature
Description
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
Real Time Clock
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
External Interrupts
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
Non Maskable Interrupt
• Pin shared with external interrupt 0.
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
External bus interface • Multiplexed address/data lines
• Wait state request
• External bus master possible
• Timing programmable
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
I/O Ports
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
• 64-pin plastic LQFP M23/M24
Packages
4
FME-MB96350 rev 7
MB96350 Series
Feature
Description
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
Flash Memory
• Data retention time: 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
FME-MB96350 rev 7
5
MB96350 Series
■ PRODUCT LINEUP
Features
MB96V300B
Evaluation sample
MB96(F)35x
Flash product: MB96F35x
Mask ROM product: MB9635x
Product type
Product options
YS
RS
YW
RW
AS
Low voltage reset persistently on / Single clock devices
Low voltage reset can be disabled / Single clock devices
Low voltage reset persistently on / Dual clock devices
NA
Low voltage reset can be disabled / Dual clock devices
No CAN / Low voltage reset can be disabled / Single clock devices
No CAN / Low voltage reset can be disabled / Dual clock devices
AW
Flash/
ROM
RAM
96KB
8KB
8KB
ROM/Flash
MB96F353R, MB96F353A
MB96F355R, MB96F355A
MB96F356Y, MB96F356R, MB96F356A
FPT-64P-M23/24
memory emulation
by external RAM,
92KB internal RAM
160KB
288KB
12KB
Package
BGA416
DMA
USART
I2C
16 channels
10 channels
2 channels
40 channels
4 channels
4 channels
1 channel
A/D Converter
15 channels
A/D Converter Reference
Voltage switch
yes
No
6 channels + 1
channel (for PPG)
16-bit Reload Timer
4 channels + 1 channel (for PPG)
16-bit Free-Running
Timer
4 channels
4 channels (2 channels with external clock input pin)
16-bit Output Compare
16-bit Input Capture
12 channels
12 channels
4 channels
6 channels (plus 2 channels for LIN USART)
16-bit Programmable
Pulse Generator
20 channels
20 channels
MB96F35xA: no
CAN Interface
5 channels
MB96F353R/F355R: 1 channel
MB96F356Y/R: 2 channels
External Interrupts
16 channels
13 channels
1 channel
Non-Maskable Interrupt
6
FME-MB96350 rev 7
MB96350 Series
Features
MB96V300B
MB96(F)35x
Real Time Clock
I/O Ports
1
136
49 for part number with suffix "W", 51 for part number with suffix "S"
External bus interface
Chip select
Yes
6 signals
2 channels
Yes
Clock output function
Low voltage reset
On-chip RC-oscillator
Yes
FME-MB96350 rev 7
7
MB96350 Series
■ BLOCK DIAGRAM
Block diagram of MB96(F)35x
AD00 ... AD15
CKOT0_R, CKOT1, CKOT1_R
A16 ... A21
ALE
CKOTX1
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
RDX
WR(L)X, WRHX
HRQ
HAKX
NMI_R
RDY
ECLK
CS0_R ... CS5_R
Clock &
Mode Controller
External Bus
Interface
Interrupt
Controller
Flash
Memory A
Memory Patch
Unit
16FX
CPU
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
VCC
VSS
C
SDA0
SCL0
I2C
1 ch.
TX1 *2, TX2 *3
RX1*2 , RX2 *3
CAN
Interface
2 ch.
AVCC
AVSS
AVRH
10-bit ADC
15 ch.
AN0 ... AN14
ADTG_R
TIN0_R, TIN2_R
TIN1, TIN3
TOT0_R, TOT2_R
TOT1, TOT3
SIN2, SIN2_R, SIN3, SIN7_R, SIN8_R
SOT2, SOT2_R, SOT3, SOT7_R, SOT8_R
SCK2, SCK2_R, SCK3, SCK7_R, SCK8_R
16-bit Reload
Timer
USART
4 ch.
4 ch.
TTG0, TTG1, TTG4 ... TTG9, TTG12 ... TTG15
TTG8_R ... TTG11_R, TTG16_R ... TTG19_R
PPG0 ... PPG7, PPG12 ... PPG15
16-bit PPG
20 ch.
FRCK0
I/O Timer 0
ICU 0/1
IN0 ... IN1
RLT6
PPG8_R ... PPG11_R, PPG16_R ... PPG19_R
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
FRCK1
IN4 ... IN7
OUT4 ... OUT7
Real Time
Clock
WOT
I/O Timer 2
ICU 9
INT8 ... INT15
INT0_R, INT2_R, INT4_R
INT7_R, INT9_R ... INT11_R
INT3_R1
External
Interrupt
I/O Timer 3
ICU 10
*1: X0A, X1A only available on devices with suffix “W”
*2: TX1, RX1 only available on MB96F356Y/R
*3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R
8
FME-MB96350 rev 7
MB96350 Series
■ PIN ASSIGNMENTS
Pin assignment of MB96(F)35x
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
P01_0/AD08/CKOT1/TIN1/TTG16_R
P00_7/AD07/INT15/PPG11_R
P00_6/AD06/INT14/PPG10_R
P00_5/AD05/INT13/SIN8_R/PPG9_R
P00_4/AD04/INT12/SOT8_R/PPG8_R
P00_3/AD03/INT11/SCK8_R/TTG11_R
P00_2/AD02/INT10/SIN7_R/TTG10_R
P00_1/AD01/INT9/SOT7_R/TTG9_R
P00_0/AD00/INT8/SCK7_R/TTG8_R
MD0
Vcc
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
P04_4/SDA0/FRCK0/TIN0_R
P04_5/SCL0/FRCK1/TIN2_R
LQFP - 64
P03_0/ALE/IN4/TTG4/TTG12/TOT0_R
P03_1/RDX/IN5/TTG5/TTG13/TOT2_R
*3
P03_2/WR(L)X/RX2/INT10_R
*3
P03_3/TX2/WRHX
Package code (mold)
FPT-64P-M23/M24
P03_4/HRQ/OUT4
P03_5/HAKX/OUT5
P03_6/RDY/OUT6
MD1
MD2
X1A/P04_1 *1
P03_7/ECLK/OUT7
P06_0/AN0/PPG0/CS0_R
P06_1/AN1/PPG1/CS1_R
AVcc
*1
X0A/P04_0
Vss
*2
P04_3/IN7/TX1/TTG7/TTG15
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
*2: TX1, RX1 only available on MB96F356Y/R
*3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R
(FPT-64P-M23/M24)
Remark:
MB96(F)35x products are pin-compatible to F2MC-16LX family MB90350 series.
FME-MB96350 rev 7
9
MB96350 Series
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 of 2)
Pin name
ADn
Feature
Description
External bus interface (multiplexed mode) address output and
data input/output
External bus
ADTG_R
ALE
ADC
External bus
External bus
ADC
Relocated A/D converter trigger input
External bus Address Latch Enable output
External bus address output
An
ANn
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
AVSS
ADC
A/D converter high reference voltage input
Analog circuits power supply
Supply
C
Voltage regulator
Clock output function
Clock output function
Clock output function
External bus
External bus
Free Running Timer
External bus
External bus
ICU
Internally regulated power supply stabilization capacitor pin
Clock Output function n output
CKOTn
CKOTn_R
CKOTXn
ECLK
CSn_R
FRCKn
HAKX
HRQ
Relocated Clock Output function n output
Clock Output function n inverted output
External bus clock output
Relocated External bus chip select n output
Free Running Timer n input
External bus Hold Acknowledge
External bus Hold Request
INn
Input Capture Unit n input
INTn
External Interrupt
External Interrupt
Core
External Interrupt n input
INTn_R
MDn
Relocated External Interrupt n input
Input pins for specifying the operating mode.
Relocated Non-Maskable Interrupt input
Output Compare Unit n waveform output
General purpose IO
NMI_R
OUTn
Pxx_n
PPGn
PPGn_R
RDX
External Interrupt
OCU
GPIO
PPG
Programmable Pulse Generator n output
Relocated Programmable Pulse Generator n output
External bus interface read strobe output
External bus interface external wait state request input
PPG
External bus
External bus
RDY
10
FME-MB96350 rev 7
MB96350 Series
Pin Function description (2 of 2)
Pin name
Feature
Description
RSTX
RXn
Core
CAN
Reset input
CAN interface n RX input
SCKn
SCKn_R
SCLn
SDAn
SINn
USART
USART
I2C
USART n serial clock input/output
Relocated USART n serial clock input/output
I2C interface n clock I/O input/output
I2C interface n serial data I/O input/output
USART n serial data input
I2C
USART
USART
USART
USART
Reload Timer
Reload Timer
Reload Timer
Reload Timer
PPG
SINn_R
SOTn
SOTn_R
TINn
Relocated USART n serial data input
USART n serial data output
Relocated USART n serial data output
Reload Timer n event input
TINn_R
TOTn
TOTn_R
TTGn
TTGn_R
TXn
Relocated Reload Timer n event input
Reload Timer n output
Relocated Reload Timer n output
Programmable Pulse Generator n trigger input
Relocated Programmable Pulse Generator n trigger input
CAN interface n TX output
PPG
CAN
VCC
Supply
Power supply
VSS
Supply
Power supply
WOT
RTC
Real Timer clock output
WRHX
WRLX/WRX
X0
External bus
External bus
Clock
External bus High byte write strobe output
External bus Low byte / Word write strobe output
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix "W")
Oscillator output
X1
Clock
X1A
Clock
Subclock Oscillator output (only for devices with suffix "W")
FME-MB96350 rev 7
11
MB96350 Series
■ PIN CIRCUIT TYPE
Pin circuit types
FPT-64P-M23/24
Circuit
Pin no.
type *1
1
2
Supply
G
I
3 to 15
16,17
18
H
Supply
B *2
19,20
19,20
21 to 23
24 to 44
45
H *3
C
H
E
46,47
48,49
50
A
Supply
F
51
H
52,53
54 to 61
62,63
64
N
H
I
Supply
*1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types
*2: Devices with suffix ”W”
*3: Devices without suffix ”W”
12
FME-MB96350 rev 7
MB96350 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
High-speed oscillation circuit:
• Programmable between oscillation mode (ex-
ternal crystal or resonator connected to X0/X1
pins) and Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
X1
R
0
1
Xout
MRFBE
FCI
R
X0
FCI or osc disable
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 MΩ. Feedback resistor is grounded in the
center when the oscillator is disabled
Xout
X1A
R
SRFBE
R
X0A
osc disable
C
E
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
R
Hysteresis
inputs
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
Hysteresis
inputs
FME-MB96350 rev 7
13
MB96350 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
G
• A/D converter ref+ (AVRH) power supply input
pin with protection circuit
ANE
AVR
• Flash devices do not have a protection circuit
against VCC for pin AVRH
ANE
H
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Nout
R
Note: MB96F353/F355:
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
14
FME-MB96350 rev 7
MB96350 Series
Type
Circuit
Remarks
I
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
Pull-up control
Pout
Nout
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
R
Note: MB96F353/F355:
Hysteresis input
Standby control
for input shutdown
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Hysteresis input
Automotive input
Standby control
for input shutdown
Standby control
for input shutdown
TTL input
Standby control
for input shutdown
Analog input
N
• CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Nout
*1: N-channel transistor has slew rate control ac-
cording to I2C spec, irrespective of usage
R
Hysteresis input
Standby control
for input shutdown
Note: MB96F353/F355:
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
FME-MB96350 rev 7
15
MB96350 Series
■ MEMORY MAP
MB96V300B
MB96(F)35x
FF:FFFFH
DE:0000H
USER ROM /
Emulation ROM
*4
External Bus
External Bus
External Bus
Boot-ROM
Reserved
10:0000H
0F:E000H
Boot-ROM
Reserved
0E:0000H
02:0000H
External RAM
Reserved
Internal RAM
RAMEND1*2
Internal RAM
bank 1
RAM availability de-
pending on the device
RAMSTART12
bank 1
01:0000H
00:8000H
Reserved
ROM/RAM MIRROR
ROM/RAM MIRROR
Internal RAM
bank 0
RAMSTART0*2
Internal RAM
bank 0
Reserved
External Bus end
*2
address
RAMSTART0*3
00:0C00H
External Bus
External Bus
Peripherals
Peripherals
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
GPR*1
DMA
GPR*1
DMA
External Bus
Peripheral
External Bus
Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the
following pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
16
FME-MB96350 rev 7
MB96350 Series
■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Bank 0
Bank 1 External Bus
Devices
RAMSTART0 RAMSTART1 RAMEND1
RAM size RAM size end address
MB96F353/F355 8KByte
MB96F356 12KByte
-
-
00:51FFH
00:51FFH
00:6240H
00:5240H
-
-
-
-
FME-MB96350 rev 7
17
MB96350 Series
■ USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F353
MB96F355
MB96F356
Flash size
96kByte
Flash size
160kByte
Flash size
288kByte
Alternative mode Flash memory
CPU address
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
S39 - 64K
S39 - 64K
S38 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
Flash A
External bus
External bus
External bus
E0:0000H
DF:FFFFH
Reserved
Reserved
Reserved
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Flash A
Reserved
Reserved
Reserved
DE:0000H
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
18
FME-MB96350 rev 7
MB96350 Series
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F35x
Pin number
Normal function
USART Number
LQFP-64
9
SIN2
SOT2
10
11
34
35
36
26
25
24
29
28
27
USART2
USART3
USART7
USART8
SCK2
SIN3
SOT3
SCK3
SIN7_R
SOT7_R
SCK7_R
SIN8_R
SOT8_R
SCK8_R
Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor
to support at least port P00_1 on pin 25.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
FME-MB96350 rev 7
19
MB96350 Series
■ I/O MAP
I/O map MB96(F)35x (1 of 28)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
Access
000000H
000001H
000002H
000003H
000004H
000005H
000006H
I/O Port P00 - Port Data Register
I/O Port P01 - Port Data Register
I/O Port P02 - Port Data Register
I/O Port P03 - Port Data Register
I/O Port P04 - Port Data Register
I/O Port P05 - Port Data Register
I/O Port P06 - Port Data Register
PDR00
PDR01
PDR02
PDR03
PDR04
PDR05
PDR06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000007H-
000017H
Reserved
-
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
00001FH
000020H
000021H
ADC0 - Control Status register Low
ADC0 - Control Status register High
ADC0 - Data Register Low
ADCSL
ADCSH
ADCRL
ADCRH
ADCS
ADCR
ADSR
R/W
R/W
R
ADC0 - Data Register High
R
ADC0 - Setting Register
R/W
R/W
R/W
-
ADC0 - Setting Register
ADC0 - Extended Configuration Register
Reserved
ADECR
FRT0 - Data register of free-running timer
FRT0 - Data register of free-running timer
TCDT0
TCCS0
R/W
R/W
FRT0 - Control status register of free-running timer
Low
000022H
000023H
TCCSL0
TCCSH0
R/W
R/W
FRT0 - Control status register of free-running timer
High
000024H
000025H
FRT1 - Data register of free-running timer
FRT1 - Data register of free-running timer
TCDT1
TCCS1
R/W
R/W
FRT1 - Control status register of free-running timer
Low
000026H
000027H
TCCSL1
TCCSH1
R/W
R/W
-
FRT1 - Control status register of free-running timer
High
000028H-
000033H
Reserved
20
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (2 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
000043H
000044H
000045H
OCU4 - Output Compare Control Status
OCU5 - Output Compare Control Status
OCU4 - Compare Register
OCS4
OCS5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
OCCP4
OCCP5
OCU4 - Compare Register
OCU5 - Compare Register
OCU5 - Compare Register
OCU6 - Output Compare Control Status
OCU7 - Output Compare Control Status
OCU6 - Compare Register
OCS6
OCS7
OCCP6
OCCP7
OCU6 - Compare Register
OCU7 - Compare Register
OCU7 - Compare Register
ICU0/ICU1 - Control Status Register
ICU0/ICU1 - Edge register
ICS01
ICE01
ICU0 - Capture Register Low
ICU0 - Capture Register High
ICU1 - Capture Register Low
ICU1 - Capture Register High
IPCPL0
IPCPH0
IPCPL1
IPCPH1
IPCP0
IPCP1
R
R
R
000046H -
00004BH
Reserved
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
ICU4/ICU5 - Control Status Register
ICU4/ICU5 - Edge register
ICS45
ICE45
R/W
R/W
R
ICU4 - Capture Register Low
ICU4 - Capture Register High
ICU5 - Capture Register Low
ICU5 - Capture Register High
ICU6/ICU7 - Control Status Register
ICU6/ICU7 - Edge register
IPCPL4
IPCPH4
IPCPL5
IPCPH5
ICS67
IPCP4
IPCP5
R
R
R
R/W
R/W
R
ICE67
ICU6 - Capture Register Low
ICU6 - Capture Register High
IPCPL6
IPCPH6
IPCP6
R
FME-MB96350 rev 7
21
MB96350 Series
I/O map MB96(F)35x (3 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000056H
000057H
000058H
ICU7 - Capture Register Low
IPCPL7
IPCPH7
ENIR0
IPCP7
R
R
ICU7 - Capture Register High
EXTINT0 - External Interrupt Enable Register
R/W
EXTINT0 - External Interrupt Interrupt request Reg-
ister
000059H
EIRR0
R/W
00005AH
00005BH
00005CH
EXTINT0 - External Interrupt Level Select Low
EXTINT0 - External Interrupt Level Select High
EXTINT1 - External Interrupt Enable Register
ELVRL0
ELVRH0
ENIR1
ELVR0
R/W
R/W
R/W
EXTINT1 - External Interrupt Interrupt request Reg-
ister
00005DH
EIRR1
R/W
00005EH
00005FH
000060H
000061H
000062H
000062H
000063H
000063H
000064H
000065H
000066H
000066H
000067H
000067H
000068H
000069H
00006AH
00006AH
00006BH
00006BH
00006CH
EXTINT1 - External Interrupt Level Select Low
EXTINT1 - External Interrupt Level Select High
RLT0 - Timer Control Status Register Low
RLT0 - Timer Control Status Register High
RLT0 - Reload Register - for writing
ELVRL1
ELVRH1
ELVR1
R/W
R/W
R/W
R/W
W
TMCSRL0
TMCSRH0
TMCSR0
TMRLR0
TMR0
RLT0 - Reload Register - for reading
RLT0 - Reload Register - for writing
R
W
RLT0 - Reload Register - for reading
RLT1 - Timer Control Status Register Low
RLT1 - Timer Control Status Register High
RLT1 - Reload Register - for writing
R
TMCSRL1
TMCSRH1
TMCSR1
R/W
R/W
W
TMRLR1
TMR1
RLT1 - Reload Register - for reading
RLT1 - Reload Register - for writing
R
W
RLT1 - Reload Register - for reading
RLT2 - Timer Control Status Register Low
RLT2 - Timer Control Status Register High
RLT2 - Reload Register - for writing
R
TMCSRL2
TMCSRH2
TMCSR2
R/W
R/W
W
TMRLR2
TMR2
RLT2 - Reload Register - for reading
RLT2 - Reload Register - for writing
R
W
RLT2 - Reload Register - for reading
RLT3 - Timer Control Status Register Low
R
TMCSRL3
TMCSR3
R/W
22
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (4 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00006DH
00006EH
00006EH
00006FH
00006FH
RLT3 - Timer Control Status Register High
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
TMCSRH3
R/W
W
TMRLR3
TMR3
R
W
R
RLT6 - Timer Control Status Register Low (dedic.
RLT for PPG)
000070H
000071H
000072H
000072H
000073H
000073H
TMCSRL6
TMCSRH6
TMCSR6
R/W
R/W
W
RLT6 - Timer Control Status Register High (dedic.
RLT for PPG)
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
TMRLR6
TMR6
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
R
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
W
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
R
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
PPG3-PPG0 - General Control register 1 Low
PPG3-PPG0 - General Control register 1 High
PPG3-PPG0 - General Control register 2 Low
PPG3-PPG0 - General Control register 2 High
PPG0 - Timer register
GCN1L0
GCN1H0
GCN2L0
GCN2H0
GCN10
GCN20
PTMR0
PCSR0
PDUT0
PCN0
R/W
R/W
R/W
R/W
R
PPG0 - Timer register
R
PPG0 - Period setting register
PPG0 - Period setting register
PPG0 - Duty cycle register
W
W
W
PPG0 - Duty cycle register
W
PPG0 - Control status register Low
PPG0 - Control status register High
PPG1 - Timer register
PCNL0
PCNH0
R/W
R/W
R
PTMR1
PCSR1
PPG1 - Timer register
R
PPG1 - Period setting register
W
FME-MB96350 rev 7
23
MB96350 Series
I/O map MB96(F)35x (5 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
000096H
000097H
000098H
000099H
00009AH
00009BH
00009CH
00009DH
00009EH
00009FH
0000A0H
PPG1 - Period setting register
PPG1 - Duty cycle register
W
W
PDUT1
PCN1
PPG1 - Duty cycle register
W
PPG1 - Control status register Low
PPG1 - Control status register High
PPG2 - Timer register
PCNL1
PCNH1
R/W
R/W
R
PTMR2
PCSR2
PDUT2
PCN2
PPG2 - Timer register
R
PPG2 - Period setting register
PPG2 - Period setting register
PPG2 - Duty cycle register
W
W
W
PPG2 - Duty cycle register
W
PPG2 - Control status register Low
PPG2 - Control status register High
PPG3 - Timer register
PCNL2
PCNH2
R/W
R/W
R
PTMR3
PCSR3
PDUT3
PCN3
PPG3 - Timer register
R
PPG3 - Period setting register
PPG3 - Period setting register
PPG3 - Duty cycle register
W
W
W
PPG3 - Duty cycle register
W
PPG3 - Control status register Low
PPG3 - Control status register High
PPG7-PPG4 - General Control register 1 Low
PPG7-PPG4 - General Control register 1 High
PPG7-PPG4 - General Control register 2 Low
PPG7-PPG4 - General Control register 2 High
PPG4 - Timer register
PCNL3
PCNH3
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN1L1
GCN1H1
GCN2L1
GCN2H1
GCN11
GCN21
PTMR4
PCSR4
PDUT4
PPG4 - Timer register
R
PPG4 - Period setting register
PPG4 - Period setting register
PPG4 - Duty cycle register
W
W
W
24
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (6 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000A1H
0000A2H
0000A3H
0000A4H
0000A5H
0000A6H
0000A7H
0000A8H
0000A9H
0000AAH
0000ABH
0000ACH
0000ADH
0000AEH
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
PPG4 - Duty cycle register
W
R/W
R/W
R
PPG4 - Control status register Low
PPG4 - Control status register High
PPG5 - Timer register
PCNL4
PCNH4
PCN4
PTMR5
PCSR5
PDUT5
PCN5
PPG5 - Timer register
R
PPG5 - Period setting register
PPG5 - Period setting register
PPG5 - Duty cycle register
W
W
W
PPG5 - Duty cycle register
W
PPG5 - Control status register Low
PPG5 - Control status register High
I2C0 - Bus Status Register
PCNL5
PCNH5
IBSR0
R/W
R/W
R
I2C0 - Bus Control Register
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C0 - Ten bit Slave address Register Low
I2C0 - Ten bit Slave address Register High
I2C0 - Ten bit Address mask Register Low
I2C0 - Ten bit Address mask Register High
I2C0 - Seven bit Slave address Register
I2C0 - Seven bit Address mask Register
I2C0 - Data Register
ITBA0
ITMK0
ISMK0
IDAR0
ICCR0
I2C0 - Clock Control Register
0000B6H-
0000D3H
Reserved
-
0000D4H
0000D5H
0000D6H
0000D6H
0000D7H
0000D8H
0000D9H
USART2 - Serial Mode Register
USART2 - Serial Control Register
USART2 - TX Register
SMR2
SCR2
TDR2
R/W
R/W
W
USART2 - RX Register
RDR2
SSR2
R
USART2 - Serial Status
R/W
R/W
R/W
USART2 - Control/Com. Register
USART2 - Ext. Status Register
ECCR2
ESCR2
FME-MB96350 rev 7
25
MB96350 Series
I/O map MB96(F)35x (7 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E0H
0000E0H
0000E1H
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
USART2 - Baud Rate Generator Register Low
USART2 - Baud Rate Generator Register High
USART2 - Extended Serial Interrupt Register
Reserved
BGRL2
BGRH2
ESIR2
BGR2
R/W
R/W
R/W
-
USART3 - Serial Mode Register
USART3 - Serial Control Register
USART3 - TX Register
SMR3
SCR3
R/W
R/W
W
TDR3
USART3 - RX Register
RDR3
R
USART3 - Serial Status
SSR3
R/W
R/W
R/W
R/W
R/W
R/W
USART3 - Control/Com. Register
USART3 - Ext. Status Register
ECCR3
ESCR3
BGRL3
BGRH3
ESIR3
USART3 - Baud Rate Generator Register Low
USART3 - Baud Rate Generator Register High
USART3 - Extended Serial Interrupt Register
BGR3
0000E7H-
0000EFH
Reserved
-
0000F0H-
0000FFH
External Bus area
EXTBUS0
R/W
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000108H
000109H
00010AH
00010BH
00010CH
DMA0 - Buffer address pointer low byte
DMA0 - Buffer address pointer middle byte
DMA0 - Buffer address pointer high byte
DMA0 - DMA control register
BAPL0
BAPM0
BAPH0
DMACS0
IOAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA0 - I/O register address pointer low byte
DMA0 - I/O register address pointer high byte
DMA0 - Data counter low byte
IOA0
IOAH0
DCTL0
DCTH0
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1
DCT0
DMA0 - Data counter high byte
DMA1 - Buffer address pointer low byte
DMA1 - Buffer address pointer middle byte
DMA1 - Buffer address pointer high byte
DMA1 - DMA control register
DMA1 - I/O register address pointer low byte
IOA1
26
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (8 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00010DH
00010EH
00010FH
000110H
000111H
000112H
000113H
000114H
000115H
000116H
000117H
000118H
000119H
00011AH
00011BH
00011CH
00011DH
00011EH
00011FH
DMA1 - I/O register address pointer high byte
DMA1 - Data counter low byte
IOAH1
DCTL1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DCT1
DMA1 - Data counter high byte
DMA2 - Buffer address pointer low byte
DMA2 - Buffer address pointer middle byte
DMA2 - Buffer address pointer high byte
DMA2 - DMA control register
DMA2 - I/O register address pointer low byte
DMA2 - I/O register address pointer high byte
DMA2 - Data counter low byte
IOA2
IOAH2
DCTL2
DCTH2
BAPL3
BAPM3
BAPH3
DMACS3
IOAL3
DCT2
DMA2 - Data counter high byte
DMA3 - Buffer address pointer low byte
DMA3 - Buffer address pointer middle byte
DMA3 - Buffer address pointer high byte
DMA3 - DMA control register
DMA3 - I/O register address pointer low byte
DMA3 - I/O register address pointer high byte
DMA3 - Data counter low byte
IOA3
IOAH3
DCTL3
DCTH3
DCT3
DMA3 - Data counter high byte
000120H-
00017FH
Reserved
-
000180H-
00037FH
CPU - General Purpose registers (RAM access)
GPR_RAM
R/W
000380H
000381H
000382H
000383H
DMA0 - Interrupt select
DMA1 - Interrupt select
DMA2 - Interrupt select
DMA3 - Interrupt select
DISEL0
DISEL1
DISEL2
DISEL3
R/W
R/W
R/W
R/W
000384H-
00038FH
Reserved
-
000390H
000391H
DMA - Status register low byte
DMA - Status register high byte
DSRL
DSRH
DSR
R/W
R/W
FME-MB96350 rev 7
27
MB96350 Series
I/O map MB96(F)35x (9 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000392H
000393H
000394H
000395H
DMA - Stop status register low byte
DMA - Stop status register high byte
DMA - Enable register low byte
DMA - Enable register high byte
DSSRL
DSSRH
DERL
DSSR
R/W
R/W
R/W
R/W
DER
DERH
000396H-
00039FH
Reserved
-
0003A0H
0003A1H
0003A2H
0003A3H
0003A4H
0003A5H
Interrupt level register
ILR
IDX
ICR
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt index register
Interrupt vector table base register Low
Interrupt vector table base register High
Delayed Interrupt register
TBRL
TBRH
DIRR
NMI
TBR
Non Maskable Interrupt register
0003A6H-
0003ABH
Reserved
-
0003ACH
0003ADH
0003AEH
0003AFH
0003B0H
0003B1H
0003B2H
0003B3H
0003B4H
0003B5H
0003B6H
0003B7H
0003B8H
0003B9H
0003BAH
0003BBH
0003BCH
EDSU communication interrupt selection Low
EDSU communication interrupt selection High
ROM mirror control register
EDSU2L
EDSU2H
ROMM
EDSU2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EDSU configuration register
EDSU
Memory patch control/status register ch 0/1
Memory patch control/status register ch 0/1
Memory patch control/status register ch 2/3
Memory patch control/status register ch 2/3
Memory patch control/status register ch 4/5
Memory patch control/status register ch 4/5
Memory patch control/status register ch 6/7
Memory patch control/status register ch 6/7
Memory Patch function - Patch address 0 low
Memory Patch function - Patch address 0 middle
Memory Patch function - Patch address 0 high
Memory Patch function - Patch address 1 low
Memory Patch function - Patch address 1 middle
PFCS0
PFCS1
PFCS2
PFCS3
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
28
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (10 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003BDH
0003BEH
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
0003D0H
0003D1H
0003D2H
0003D3H
0003D4H
0003D5H
0003D6H
0003D7H
0003D8H
0003D9H
0003DAH
Memory Patch function - Patch address 1 high
Memory Patch function - Patch address 2 low
Memory Patch function - Patch address 2 middle
Memory Patch function - Patch address 2 high
Memory Patch function - Patch address 3 low
Memory Patch function - Patch address 3 middle
Memory Patch function - Patch address 3 high
Memory Patch function - Patch address 4 low
Memory Patch function - Patch address 4 middle
Memory Patch function - Patch address 4 high
Memory Patch function - Patch address 5 low
Memory Patch function - Patch address 5 middle
Memory Patch function - Patch address 5 high
Memory Patch function - Patch address 6 low
Memory Patch function - Patch address 6 middle
Memory Patch function - Patch address 6 high
Memory Patch function - Patch address 7 low
Memory Patch function - Patch address 7 middle
Memory Patch function - Patch address 7 high
Memory Patch function - Patch data 0 Low
Memory Patch function - Patch data 0 High
Memory Patch function - Patch data 1 Low
Memory Patch function - Patch data 1 High
Memory Patch function - Patch data 2 Low
Memory Patch function - Patch data 2 High
Memory Patch function - Patch data 3 Low
Memory Patch function - Patch data 3 High
Memory Patch function - Patch data 4 Low
Memory Patch function - Patch data 4 High
Memory Patch function - Patch data 5 Low
PFAH1
PFAL2
PFAM2
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
PFAH4
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
PFDL0
PFDH0
PFDL1
PFDH1
PFDL2
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFD0
PFD1
PFD2
PFD3
PFD4
PFD5
FME-MB96350 rev 7
29
MB96350 Series
I/O map MB96(F)35x (11 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003DBH
0003DCH
0003DDH
0003DEH
0003DFH
Memory Patch function - Patch data 5 High
Memory Patch function - Patch data 6 Low
Memory Patch function - Patch data 6 High
Memory Patch function - Patch data 7 Low
Memory Patch function - Patch data 7 High
PFDH5
PFDL6
PFDH6
PFDL7
PFDH7
R/W
R/W
R/W
R/W
R/W
PFD6
PFD7
0003E0H-
0003F0H
Reserved
-
0003F1H
0003F2H
0003F3H
Memory Control Status Register A
MCSRA
MTCRAL
MTCRAH
R/W
R/W
R/W
Memory Timing Configuration Register A Low
Memory Timing Configuration Register A High
MTCRA
0003F4H-
0003F8H
Reserved
-
0003F9H
0003FAH
0003FBH
0003FCH
0003FDH
Flash Memory Write Control register 1
Flash Memory Write Control register 2
Flash Memory Write Control register 3
Flash Memory Write Control register 4
Flash Memory Write Control register 5
FMWC1
FMWC2
FMWC3
FMWC4
FMWC5
R/W
R/W
R/W
R/W
R/W
0003FEH-
0003FFH
Reserved
-
000400H
000401H
000402H
000403H
000404H
000405H
000406H
000407H
000408H
000409H
00040AH
Standby Mode control register
Clock select register
SMCR
CKSR
R/W
R/W
R/W
R
Clock Stabilization select register
Clock monitor register
CKSSR
CKMR
Clock Frequency control register Low
Clock Frequency control register High
PLL Control register Low
CKFCRL
CKFCRH
PLLCRL
PLLCRH
RCTCR
MCTCR
SCTCR
CKFCR
PLLCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLL Control register High
RC clock timer control register
Main clock timer control register
Sub clock timer control register
30
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (12 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
Reset cause and clock status register with clear
function
00040BH
RCCSRC
R
00040CH
00040DH
00040EH
00040FH
Reset configuration register
RCR
R/W
R
Reset cause and clock status register
Watch dog timer configuration register
Watch dog timer clear pattern register
RCCSR
WDTC
WDTCP
R/W
W
000410H-
000414H
Reserved
-
000415H
000416H
000417H
000418H
000419H
00041AH
00041BH
Clock output activation register
Clock output configuration register 0
Clock output configuration register 1
Clock Modulator control register
Reserved
COAR
COCR0
COCR1
CMCR
R/W
R/W
R/W
R/W
-
Clock Modulator Parameter register Low
Clock Modulator Parameter register High
CMPRL
CMPRH
CMPR
R/W
R/W
00041CH-
00042BH
Reserved
-
00042CH
00042DH
Voltage Regulator Control register
VRCR
CILCR
R/W
R/W
Clock Input and LVD Control Register
00042EH-
00042FH
Reserved
-
000430H
000431H
000432H
000433H
000434H
000435H
000436H
I/O Port P00 - Data Direction Register
I/O Port P01 - Data Direction Register
I/O Port P02 - Data Direction Register
I/O Port P03 - Data Direction Register
I/O Port P04 - Data Direction Register
I/O Port P05 - Data Direction Register
I/O Port P06 - Data Direction Register
DDR00
DDR01
DDR02
DDR03
DDR04
DDR05
DDR06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000437H-
000443H
Reserved
-
000444H
000445H
I/O Port P00 - Port Input Enable Register
I/O Port P01 - Port Input Enable Register
PIER00
PIER01
R/W
R/W
FME-MB96350 rev 7
31
MB96350 Series
I/O map MB96(F)35x (13 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000446H
000447H
000448H
000449H
00044AH
I/O Port P02 - Port Input Enable Register
I/O Port P03 - Port Input Enable Register
I/O Port P04 - Port Input Enable Register
I/O Port P05 - Port Input Enable Register
I/O Port P06 - Port Input Enable Register
PIER02
PIER03
PIER04
PIER05
PIER06
R/W
R/W
R/W
R/W
R/W
00044BH-
000457H
Reserved
-
000458H
000459H
00045AH
00045BH
00045CH
00045DH
00045EH
I/O Port P00 - Port Input Level Register
I/O Port P01 - Port Input Level Register
I/O Port P02 - Port Input Level Register
I/O Port P03 - Port Input Level Register
I/O Port P04 - Port Input Level Register
I/O Port P05 - Port Input Level Register
I/O Port P06 - Port Input Level Register
PILR00
PILR01
PILR02
PILR03
PILR04
PILR05
PILR06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00045FH-
00046BH
Reserved
-
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
I/O Port P00 - Extended Port Input Level Register
I/O Port P01 - Extended Port Input Level Register
I/O Port P02 - Extended Port Input Level Register
I/O Port P03 - Extended Port Input Level Register
I/O Port P04 - Extended Port Input Level Register
I/O Port P05 - Extended Port Input Level Register
I/O Port P06 - Extended Port Input Level Register
EPILR00
EPILR01
EPILR02
EPILR03
EPILR04
EPILR05
EPILR06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000473H-
00047FH
Reserved
-
000480H
000481H
000482H
000483H
000484H
000485H
I/O Port P00 - Port Output Drive Register
I/O Port P01 - Port Output Drive Register
I/O Port P02 - Port Output Drive Register
I/O Port P03 - Port Output Drive Register
I/O Port P04 - Port Output Drive Register
I/O Port P05 - Port Output Drive Register
PODR00
PODR01
PODR02
PODR03
PODR04
PODR05
R/W
R/W
R/W
R/W
R/W
R/W
32
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (14 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000486H
I/O Port P06 - Port Output Drive Register
Reserved
PODR06
R/W
-
000487H-
0004A7H
0004A8H
0004A9H
0004AAH
0004ABH
0004ACH
0004ADH
0004AEH
I/O Port P00 - Pull-Up resistor Control Register
I/O Port P01 - Pull-Up resistor Control Register
I/O Port P02 - Pull-Up resistor Control Register
I/O Port P03 - Pull-Up resistor Control Register
I/O Port P04 - Pull-Up resistor Control Register
I/O Port P05 - Pull-Up resistor Control Register
I/O Port P06 - Pull-Up resistor Control Register
PUCR00
PUCR01
PUCR02
PUCR03
PUCR04
PUCR05
PUCR06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0004AFH-
0004BBH
Reserved
-
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
0004C1H
0004C2H
I/O Port P00 - External Pin State Register
I/O Port P01 - External Pin State Register
I/O Port P02 - External Pin State Register
I/O Port P03 - External Pin State Register
I/O Port P04 - External Pin State Register
I/O Port P05 - External Pin State Register
I/O Port P06 - External Pin State Register
EPSR00
EPSR01
EPSR02
EPSR03
EPSR04
EPSR05
EPSR06
R
R
R
R
R
R
R
0004C3H-
0004CFH
Reserved
-
0004D0H
0004D1H
0004D2H
0004D3H
0004D4H
0004D5H
0004D6H
0004D7H
0004D8H
0004D9H
ADC analog input enable register 0
ADC analog input enable register 1
ADC analog input enable register 2
ADC analog input enable register 3
ADC analog input enable register 4
Reserved
ADER0
ADER1
ADER2
ADER3
ADER4
R/W
R/W
R/W
R/W
R/W
-
Peripheral Resource Relocation Register 0
Peripheral Resource Relocation Register 1
Peripheral Resource Relocation Register 2
Peripheral Resource Relocation Register 3
PRRR0
PRRR1
PRRR2
PRRR3
R/W
R/W
R/W
R/W
FME-MB96350 rev 7
33
MB96350 Series
I/O map MB96(F)35x (15 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0004DAH
0004DBH
0004DCH
0004DDH
0004DEH
0004DFH
0004E0H
0004E1H
0004E2H
0004E3H
0004E4H
0004E5H
0004E6H
0004E7H
0004E8H
0004E9H
0004EAH
0004EBH
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
Peripheral Resource Relocation Register 4
Peripheral Resource Relocation Register 5
Peripheral Resource Relocation Register 6
Peripheral Resource Relocation Register 7
Peripheral Resource Relocation Register 8
Peripheral Resource Relocation Register 9
RTC - Sub Second Register L
PRRR4
PRRR5
PRRR6
PRRR7
PRRR8
PRRR9
WTBRL0
WTBRH0
WTBR1
WTSR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
WTBR0
RTC - Sub Second Register M
RTC - Sub-Second Register H
RTC - Second Register
RTC - Minutes
WTMR
RTC - Hour
WTHR
RTC - Timer Control Extended Register
RTC - Clock select register
WTCER
WTCKSR
WTCRL
WTCRH
CUCR
RTC - Timer Control Register Low
RTC - Timer Control Register High
CAL - Calibration unit Control register
Reserved
WTCR
CAL - Duration Timer Data Register Low
CAL - Duration Timer Data Register High
CAL - Calibration Timer Register 2 Low
CAL - Calibration Timer Register 2 High
CAL - Calibration Timer Register 1 Low
CAL - Calibration Timer Register 1 High
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
CUTR2
CUTR1
R/W
R/W
R
R
R
R
0004F2H-
0004F9H
Reserved
-
R/W
-
0004FAH
RLT - Timer input select (for Cascading)
Reserved
TMISR
0004FBH-
0004FFH
000500H
000501H
FRT2 - Data register of free-running timer
FRT2 - Data register of free-running timer
TCDT2
R/W
R/W
34
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (16 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
R/W
FRT2 - Control status register of free-running timer
Low
000502H
000503H
TCCSL2
TCCSH2
TCCS2
FRT2 - Control status register of free-running timer
High
R/W
000504H
000505H
FRT3 - Data register of free-running timer
FRT3 - Data register of free-running timer
TCDT3
TCCS3
R/W
R/W
FRT3 - Control status register of free-running timer
Low
000506H
000507H
TCCSL3
TCCSH3
R/W
R/W
-
FRT3 - Control status register of free-running timer
High
000508H-
000513H
Reserved
000514H
000515H
000516H
000517H
000518H
000519H
00051AH
00051BH
00051CH
00051DH
00051EH
00051FH
ICU8/ICU9 - Control Status Register
ICU8/ICU9 - Edge Register
ICS89
ICE89
R/W
R/W
R
ICU8 - Capture Register Low
ICU8 - Capture Register High
ICU9 - Capture Register Low
ICU9 - Capture Register High
ICU10/ICU11 - Control Status Register
ICU10/ICU11 - Edge Register
ICU10 - Capture Register Low
ICU10 - Capture Register High
ICU11 - Capture Register Low
ICU11 - Capture Register High
IPCPL8
IPCPH8
IPCPL9
IPCPH9
ICS1011
ICE1011
IPCPL10
IPCPH10
IPCPL11
IPCPH11
IPCP8
IPCP9
R
R
R
R/W
R/W
R
IPCP10
IPCP11
R
R
R
000520H-
00053DH
Reserved
-
00053EH
00053FH
000540H
000540H
000541H
000542H
USART7 - Serial Mode Register
USART7 - Serial Control Register
USART7 - Serial TX Register
SMR7
SCR7
TDR7
RDR7
SSR7
ECCR7
R/W
R/W
W
USART7 - Serial RX Register
R
USART7 - Serial Status Register
USART7 - Ext. Control/Com. Register
R/W
R/W
FME-MB96350 rev 7
35
MB96350 Series
I/O map MB96(F)35x (17 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000543H
000544H
000545H
000546H
000547H
000548H
000549H
00054AH
00054AH
00054BH
00054CH
00054DH
00054EH
00054FH
000550H
USART7 - Ext. Status Com. Register
USART7 - Baud Rate Generator Register Low
USART7 - Baud Rate Generator Register High
USART7 - Extended Serial Interrupt Register
Reserved
ESCR7
BGRL7
BGRH7
ESIR7
R/W
R/W
R/W
R/W
-
BGR7
USART8 - Serial Mode Register
SMR8
SCR8
R/W
R/W
W
USART8 - Serial Control Register
USART8 - Serial TX Register
TDR8
USART8 - Serial RX Register
RDR8
R
USART8 - Serial Status Register
SSR8
R/W
R/W
R/W
R/W
R/W
R/W
USART8 - Ext. Control/Com. Register
USART8 - Ext. Status Com. Register
USART8 - Baud Rate Generator Register Low
USART8 - Baud Rate Generator Register High
USART8 - Extended Serial Interrupt Register
ECCR8
ESCR8
BGRL8
BGRH8
ESIR8
BGR8
000551H-
000563H
Reserved
-
000564H
000565H
000566H
000567H
000568H
000569H
00056AH
00056BH
00056CH
00056DH
00056EH
00056FH
000570H
PPG6 - Timer register
PTMR6
PCSR6
PDUT6
PCN6
R
R
PPG6 - Timer register
PPG6 - Period setting register
PPG6 - Period setting register
PPG6 - Duty cycle register
PPG6 - Duty cycle register
PPG6 - Control status register Low
PPG6 - Control status register High
PPG7 - Timer register
W
W
W
W
PCNL6
PCNH6
R/W
R/W
R
PTMR7
PCSR7
PDUT7
PPG7 - Timer register
R
PPG7 - Period setting register
PPG7 - Period setting register
PPG7 - Duty cycle register
W
W
W
36
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (18 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000571H
000572H
000573H
000574H
000575H
000576H
000577H
000578H
000579H
00057AH
00057BH
00057CH
00057DH
00057EH
00057FH
000580H
000581H
000582H
000583H
000584H
000585H
000586H
000587H
000588H
000589H
00058AH
00058BH
00058CH
00058DH
00058EH
PPG7 - Duty cycle register
W
R/W
R/W
R/W
R/W
R/W
R/W
R
PPG7 - Control status register Low
PPG7 - Control status register High
PPG11-PPG8 - General Control register 1 Low
PPG11-PPG8 - General Control register 1 High
PPG11-PPG8 - General Control register 2 Low
PPG11-PPG8 - General Control register 2 High
PPG8 - Timer register
PCNL7
PCNH7
PCN7
GCN12
GCN22
PTMR8
PCSR8
PDUT8
PCN8
GCN1L2
GCN1H2
GCN2L2
GCN2H2
PPG8 - Timer register
R
PPG8 - Period setting register
PPG8 - Period setting register
PPG8 - Duty cycle register
W
W
W
PPG8 - Duty cycle register
W
PPG8 - Control status register Low
PPG8 - Control status register High
PPG9 - Timer register
PCNL8
PCNH8
R/W
R/W
R
PTMR9
PCSR9
PDUT9
PCN9
PPG9 - Timer register
R
PPG9 - Period setting register
PPG9 - Period setting register
PPG9 - Duty cycle register
W
W
W
PPG9 - Duty cycle register
W
PPG9 - Control status register Low
PPG9 - Control status register High
PPG10 - Timer register
PCNL9
PCNH9
R/W
R/W
R
PTMR10
PCSR10
PDUT10
PCN10
PPG10 - Timer register
R
PPG10 - Period setting register
PPG10 - Period setting register
PPG10 - Duty cycle register
W
W
W
PPG10 - Duty cycle register
W
PPG10 - Control status register Low
PCNL10
R/W
FME-MB96350 rev 7
37
MB96350 Series
I/O map MB96(F)35x (19 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00058FH
000590H
000591H
000592H
000593H
000594H
000595H
000596H
000597H
000598H
000599H
00059AH
00059BH
00059CH
00059DH
00059EH
00059FH
0005A0H
0005A1H
0005A2H
0005A3H
0005A4H
0005A5H
0005A6H
0005A7H
0005A8H
0005A9H
0005AAH
0005ABH
0005ACH
PPG10 - Control status register High
PPG11 - Timer register
PCNH10
R/W
R
PTMR11
PCSR11
PDUT11
PCN11
PPG11 - Timer register
R
PPG11 - Period setting register
PPG11 - Period setting register
PPG11 - Duty cycle register
W
W
W
PPG11 - Duty cycle register
W
PPG11 - Control status register Low
PPG11 - Control status register High
PPG15-PPG12 - General Control register 1 Low
PPG15-PPG12 - General Control register 1 High
PPG15-PPG12 - General Control register 2 Low
PPG15-PPG12 - General Control register 2 High
PPG12 - Timer register
PCNL11
PCNH11
GCN1L3
GCN1H3
GCN2L3
GCN2H3
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN13
GCN23
PTMR12
PCSR12
PDUT12
PCN12
PPG12 - Timer register
R
PPG12 - Period setting register
PPG12 - Period setting register
PPG12 - Duty cycle register
W
W
W
PPG12 - Duty cycle register
W
PPG12 - Control status register Low
PPG12 - Control status register High
PPG13 - Timer register
PCNL12
PCNH12
R/W
R/W
R
PTMR13
PCSR13
PDUT13
PCN13
PPG13 - Timer register
R
PPG13 - Period setting register
PPG13 - Period setting register
PPG13 - Duty cycle register
W
W
W
PPG13 - Duty cycle register
W
PPG13 - Control status register Low
PPG13 - Control status register High
PPG14 - Timer register
PCNL13
PCNH13
R/W
R/W
R
PTMR14
38
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (20 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0005ADH
0005AEH
0005AFH
0005B0H
0005B1H
0005B2H
0005B3H
0005B4H
0005B5H
0005B6H
0005B7H
0005B8H
0005B9H
0005BAH
0005BBH
0005BCH
0005BDH
0005BEH
0005BFH
0005C0H
0005C1H
0005C2H
0005C3H
0005C4H
0005C5H
0005C6H
0005C7H
0005C8H
0005C9H
0005CAH
PPG14 - Timer register
R
W
PPG14 - Period setting register
PPG14 - Period setting register
PPG14 - Duty cycle register
PCSR14
PDUT14
PCN14
W
W
PPG14 - Duty cycle register
W
PPG14 - Control status register Low
PPG14 - Control status register High
PPG15 - Timer register
PCNL14
PCNH14
R/W
R/W
R
PTMR15
PCSR15
PDUT15
PCN15
PPG15 - Timer register
R
PPG15 - Period setting register
PPG15 - Period setting register
PPG15 - Duty cycle register
W
W
W
PPG15 - Duty cycle register
W
PPG15 - Control status register Low
PPG15 - Control status register High
PPG19-PPG16 - General Control register 1 Low
PPG19-PPG16 - General Control register 1 High
PPG19-PPG16 - General Control register 2 Low
PPG19-PPG16 - General Control register 2 High
PPG16 - Timer register
PCNL15
PCNH15
GCN1L4
GCN1H4
GCN2L4
GCN2H4
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN14
GCN24
PTMR16
PCSR16
PDUT16
PCN16
PPG16 - Timer register
R
PPG16 - Period setting register
PPG16 - Period setting register
PPG16 - Duty cycle register
W
W
W
PPG16 - Duty cycle register
W
PPG16 - Control status register Low
PPG16 - Control status register High
PPG17 - Timer register
PCNL16
PCNH16
R/W
R/W
R
PTMR17
PCSR17
PPG17 - Timer register
R
PPG17 - Period setting register
W
FME-MB96350 rev 7
39
MB96350 Series
I/O map MB96(F)35x (21 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0005CBH
0005CCH
0005CDH
0005CEH
0005CFH
0005D0H
0005D1H
0005D2H
0005D3H
0005D4H
0005D5H
0005D6H
0005D7H
0005D8H
0005D9H
0005DAH
0005DBH
0005DCH
0005DDH
0005DEH
0005DFH
PPG17 - Period setting register
PPG17 - Duty cycle register
PPG17 - Duty cycle register
PPG17 - Control status register Low
PPG17 - Control status register High
PPG18 - Timer register
W
W
PDUT17
PCN17
W
PCNL17
PCNH17
R/W
R/W
R
PTMR18
PCSR18
PDUT18
PCN18
PPG18 - Timer register
R
PPG18 - Period setting register
PPG18 - Period setting register
PPG18 - Duty cycle register
PPG18 - Duty cycle register
PPG18 - Control status register Low
PPG18 - Control status register High
PPG19 - Timer register
W
W
W
W
PCNL18
PCNH18
R/W
R/W
R
PTMR19
PCSR19
PDUT19
PCN19
PPG19 - Timer register
R
PPG19 - Period setting register
PPG19 - Period setting register
PPG19 - Duty cycle register
PPG19 - Duty cycle register
PPG19 - Control status register Low
PPG19 - Control status register High
W
W
W
W
PCNL19
PCNH19
R/W
R/W
0005E0H-
00065FH
Reserved
-
000660H
000661H
000662H
000663H
Peripheral Resource Relocation Register 10
Peripheral Resource Relocation Register 11
Peripheral Resource Relocation Register 12
Peripheral Resource Relocation Register 13
PRRR10
PRRR11
PRRR12
PRRR13
R/W
R/W
R/W
W
000664H-
0006DFH
Reserved
-
0006E0H
0006E1H
External Bus - Area configuration register 0 Low
External Bus - Area configuration register 0 High
EACL0
EACH0
EAC0
R/W
R/W
40
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (22 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0006E2H
0006E3H
0006E4H
0006E5H
0006E6H
0006E7H
0006E8H
0006E9H
0006EAH
0006EBH
0006ECH
0006EDH
0006EEH
0006EFH
0006F0H
0006F1H
0006F2H
0006F3H
0006F4H
0006F5H
External Bus - Area configuration register 1 Low
External Bus - Area configuration register 1 High
External Bus - Area configuration register 2 Low
External Bus - Area configuration register 2 High
External Bus - Area configuration register 3 Low
External Bus - Area configuration register 3 High
External Bus - Area configuration register 4 Low
External Bus - Area configuration register 4 High
External Bus - Area configuration register 5 Low
External Bus - Area configuration register 5 High
External Bus - Area select register 2
EACL1
EACH1
EACL2
EACH2
EACL3
EACH3
EACL4
EACH4
EACL5
EACH5
EAS2
EAC1
EAC2
EAC3
EAC4
EAC5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
External Bus - Area select register 3
EAS3
External Bus - Area select register 4
EAS4
External Bus - Area select register 5
EAS5
External Bus - Mode register
EBM
External Bus - Clock and Function register
External Bus - Address output enable register 0
External Bus - Address output enable register 1
External Bus - Address output enable register 2
External Bus - Control signal register
EBCF
EBAE0
EBAE1
EBAE2
EBCS
0006F6H-
0007FFH
Reserved
-
000800H
000801H
000802H
000803H
000804H
000805H
000806H
000807H
CAN1 - Control register Low
CTRLRL1
CTRLRH1
STATRL1
STATRH1
ERRCNTL1
ERRCNTH1
BTRL1
CTRLR1
STATR1
ERRCNT1
BTR1
R/W
R
CAN1 - Control register High (reserved)
CAN1 - Status register Low
R/W
R
CAN1 - Status register High (reserved)
CAN1 - Error Counter Low (Transmit)
CAN1 - Error Counter High (Receive)
CAN1 - Bit Timing Register Low
CAN1 - Bit Timing Register High
R
R
R/W
R/W
BTRH1
FME-MB96350 rev 7
41
MB96350 Series
I/O map MB96(F)35x (23 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000808H
000809H
00080AH
00080BH
00080CH
00080DH
CAN1 - Interrupt Register Low
INTRL1
INTRH1
INTR1
TESTR1
BRPER1
R
R
CAN1 - Interrupt Register High
CAN1 - Test Register Low
TESTRL1
TESTRH1
BRPERL1
BRPERH1
R/W
R
CAN1 - Test Register High (reserved)
CAN1 - BRP Extension register Low
CAN1 - BRP Extension register High (reserved)
R/W
R
00080EH-
00080FH
Reserved
-
000810H
000811H
000812H
CAN1 - IF1 Command request register Low
CAN1 - IF1 Command request register High
CAN1 - IF1 Command Mask register Low
IF1CREQL1
IF1CREQH1
IF1CMSKL1
IF1CREQ1
IF1CMSK1
R/W
R/W
R/W
CAN1 - IF1 Command Mask register High (re-
served)
000813H
IF1CMSKH1
R
000814H
000815H
000816H
000817H
000818H
000819H
00081AH
00081BH
00081CH
00081DH
00081EH
00081FH
000820H
000821H
000822H
000823H
000824H
000825H
CAN1 - IF1 Mask 1 Register Low
CAN1 - IF1 Mask 1 Register High
CAN1 - IF1 Mask 2 Register Low
CAN1 - IF1 Mask 2 Register High
CAN1 - IF1 Arbitration 1 Register Low
CAN1 - IF1 Arbitration 1 Register High
CAN1 - IF1 Arbitration 2 Register Low
CAN1 - IF1 Arbitration 2 Register High
CAN1 - IF1 Message Control Register Low
CAN1 - IF1 Message Control Register High
CAN1 - IF1 Data A1 Low
IF1MSK1L1
IF1MSK1H1
IF1MSK2L1
IF1MSK2H1
IF1ARB1L1
IF1ARB1H1
IF1ARB2L1
IF1ARB2H1
IF1MCTRL1
IF1MCTRH1
IF1DTA1L1
IF1DTA1H1
IF1DTA2L1
IF1DTA2H1
IF1DTB1L1
IF1DTB1H1
IF1DTB2L1
IF1DTB2H1
IF1MSK11
IF1MSK21
IF1ARB11
IF1ARB21
IF1MCTR1
IF1DTA11
IF1DTA21
IF1DTB11
IF1DTB21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN1 - IF1 Data A1 High
CAN1 - IF1 Data A2 Low
CAN1 - IF1 Data A2 High
CAN1 - IF1 Data B1 Low
CAN1 - IF1 Data B1 High
CAN1 - IF1 Data B2 Low
CAN1 - IF1 Data B2 High
42
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (24 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000826H-
Reserved
00083FH
-
000840H
000841H
000842H
CAN1 - IF2 Command request register Low
CAN1 - IF2 Command request register High
CAN1 - IF2 Command Mask register Low
IF2CREQL1
IF2CREQH1
IF2CMSKL1
IF2CREQ1
IF2CMSK1
R/W
R/W
R/W
CAN1 - IF2 Command Mask register High (re-
served)
000843H
IF2CMSKH1
R
000844H
000845H
000846H
000847H
000848H
000849H
00084AH
00084BH
00084CH
00084DH
00084EH
00084FH
000850H
000851H
000852H
000853H
000854H
000855H
CAN1 - IF2 Mask 1 Register Low
CAN1 - IF2 Mask 1 Register High
CAN1 - IF2 Mask 2 Register Low
CAN1 - IF2 Mask 2 Register High
CAN1 - IF2 Arbitration 1 Register Low
CAN1 - IF2 Arbitration 1 Register High
CAN1 - IF2 Arbitration 2 Register Low
CAN1 - IF2 Arbitration 2 Register High
CAN1 - IF2 Message Control Register Low
CAN1 - IF2 Message Control Register High
CAN1 - IF2 Data A1 Low
IF2MSK1L1
IF2MSK1H1
IF2MSK2L1
IF2MSK2H1
IF2ARB1L1
IF2ARB1H1
IF2ARB2L1
IF2ARB2H1
IF2MCTRL1
IF2MCTRH1
IF2DTA1L1
IF2DTA1H1
IF2DTA2L1
IF2DTA2H1
IF2DTB1L1
IF2DTB1H1
IF2DTB2L1
IF2DTB2H1
IF2MSK11
IF2MSK21
IF2ARB11
IF2ARB21
IF2MCTR1
IF2DTA11
IF2DTA21
IF2DTB11
IF2DTB21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN1 - IF2 Data A1 High
CAN1 - IF2 Data A2 Low
CAN1 - IF2 Data A2 High
CAN1 - IF2 Data B1 Low
CAN1 - IF2 Data B1 High
CAN1 - IF2 Data B2 Low
CAN1 - IF2 Data B2 High
000856H-
00087FH
Reserved
-
000880H
000881H
000882H
000883H
CAN1 - Transmission Request 1 Register Low
CAN1 - Transmission Request 1 Register High
CAN1 - Transmission Request 2 Register Low
CAN1 - Transmission Request 2 Register High
TREQR1L1
TREQR1H1
TREQR2L1
TREQR2H1
TREQR11
TREQR21
R
R
R
R
FME-MB96350 rev 7
43
MB96350 Series
I/O map MB96(F)35x (25 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000884H-
Reserved
00088FH
-
000890H
000891H
000892H
000893H
CAN1 - New Data 1 Register Low
CAN1 - New Data 1 Register High
CAN1 - New Data 2 Register Low
CAN1 - New Data 2 Register High
NEWDT1L1
NEWDT1H1
NEWDT2L1
NEWDT2H1
NEWDT11
NEWDT21
R
R
R
R
000894H-
00089FH
Reserved
-
0008A0H
0008A1H
0008A2H
0008A3H
CAN1 - Interrupt Pending 1 Register Low
CAN1 - Interrupt Pending 1 Register High
CAN1 - Interrupt Pending 2 Register Low
CAN1 - Interrupt Pending 2 Register High
INTPND1L1
INTPND1H1
INTPND2L1
INTPND2H1
INTPND11
INTPND21
R
R
R
R
0008A4H-
0008AFH
Reserved
-
0008B0H
0008B1H
0008B2H
0008B3H
CAN1 - Message Valid 1 Register Low
CAN1 - Message Valid 1 Register High
CAN1 - Message Valid 2 Register Low
CAN1 - Message Valid 2 Register High
MSGVAL1L1
MSGVAL1H1
MSGVAL2L1
MSGVAL2H1
MSGVAL11
MSGVAL21
R
R
R
R
0008B4H-
0008CDH
Reserved
-
R/W
-
0008CEH
CAN1 - Output enable register
Reserved
COER1
0008CFH-
0008FFH
000900H
000901H
000902H
000903H
000904H
000905H
000906H
000907H
000908H
CAN2 - Control register Low
CTRLRL2
CTRLRH2
STATRL2
STATRH2
ERRCNTL2
ERRCNTH2
BTRL2
CTRLR2
STATR2
ERRCNT2
BTR2
R/W
R
CAN2 - Control register High (reserved)
CAN2 - Status register Low
R/W
R
CAN2 - Status register High (reserved)
CAN2 - Error Counter Low (Transmit)
CAN2 - Error Counter High (Receive)
CAN2 - Bit Timing Register Low
CAN2 - Bit Timing Register High
CAN2 - Interrupt Register Low
R
R
R/W
R/W
R
BTRH2
INTRL2
INTR2
44
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (26 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000909H
00090AH
00090BH
00090CH
00090DH
CAN2 - Interrupt Register High
INTRH2
TESTRL2
TESTRH2
BRPERL2
BRPERH2
R
R/W
R
CAN2 - Test Register Low
TESTR2
BRPER2
CAN2 - Test Register High (reserved)
CAN2 - BRP Extension register Low
CAN2 - BRP Extension register High (reserved)
R/W
R
00090EH-
00090FH
Reserved
-
000910H
000911H
000912H
CAN2 - IF1 Command request register Low
CAN2 - IF1 Command request register High
CAN2 - IF1 Command Mask register Low
IF1CREQL2
IF1CREQH2
IF1CMSKL2
IF1CREQ2
IF1CMSK2
R/W
R/W
R/W
CAN2 - IF1 Command Mask register High (re-
served)
000913H
IF1CMSKH2
R
000914H
000915H
000916H
000917H
000918H
000919H
00091AH
00091BH
00091CH
00091DH
00091EH
00091FH
000920H
000921H
000922H
000923H
000924H
000925H
CAN2 - IF1 Mask 1 Register Low
CAN2 - IF1 Mask 1 Register High
CAN2 - IF1 Mask 2 Register Low
CAN2 - IF1 Mask 2 Register High
CAN2 - IF1 Arbitration 1 Register Low
CAN2 - IF1 Arbitration 1 Register High
CAN2 - IF1 Arbitration 2 Register Low
CAN2 - IF1 Arbitration 2 Register High
CAN2 - IF1 Message Control Register Low
CAN2 - IF1 Message Control Register High
CAN2 - IF1 Data A1 Low
IF1MSK1L2
IF1MSK1H2
IF1MSK2L2
IF1MSK2H2
IF1ARB1L2
IF1ARB1H2
IF1ARB2L2
IF1ARB2H2
IF1MCTRL2
IF1MCTRH2
IF1DTA1L2
IF1DTA1H2
IF1DTA2L2
IF1DTA2H2
IF1DTB1L2
IF1DTB1H2
IF1DTB2L2
IF1DTB2H2
IF1MSK12
IF1MSK22
IF1ARB12
IF1ARB22
IF1MCTR2
IF1DTA12
IF1DTA22
IF1DTB12
IF1DTB22
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN2 - IF1 Data A1 High
CAN2 - IF1 Data A2 Low
CAN2 - IF1 Data A2 High
CAN2 - IF1 Data B1 Low
CAN2 - IF1 Data B1 High
CAN2 - IF1 Data B2 Low
CAN2 - IF1 Data B2 High
FME-MB96350 rev 7
45
MB96350 Series
I/O map MB96(F)35x (27 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000926H-
Reserved
00093FH
-
000940H
000941H
000942H
CAN2 - IF2 Command request register Low
CAN2 - IF2 Command request register High
CAN2 - IF2 Command Mask register Low
IF2CREQL2
IF2CREQH2
IF2CMSKL2
IF2CREQ2
IF2CMSK2
R/W
R/W
R/W
CAN2 - IF2 Command Mask register High (re-
served)
000943H
IF2CMSKH2
R
000944H
000945H
000946H
000947H
000948H
000949H
00094AH
00094BH
00094CH
00094DH
00094EH
00094FH
000950H
000951H
000952H
000953H
000954H
000955H
CAN2 - IF2 Mask 1 Register Low
CAN2 - IF2 Mask 1 Register High
CAN2 - IF2 Mask 2 Register Low
CAN2 - IF2 Mask 2 Register High
CAN2 - IF2 Arbitration 1 Register Low
CAN2 - IF2 Arbitration 1 Register High
CAN2 - IF2 Arbitration 2 Register Low
CAN2 - IF2 Arbitration 2 Register High
CAN2 - IF2 Message Control Register Low
CAN2 - IF2 Message Control Register High
CAN2 - IF2 Data A1 Low
IF2MSK1L2
IF2MSK1H2
IF2MSK2L2
IF2MSK2H2
IF2ARB1L2
IF2ARB1H2
IF2ARB2L2
IF2ARB2H2
IF2MCTRL2
IF2MCTRH2
IF2DTA1L2
IF2DTA1H2
IF2DTA2L2
IF2DTA2H2
IF2DTB1L2
IF2DTB1H2
IF2DTB2L2
IF2DTB2H2
IF2MSK12
IF2MSK22
IF2ARB12
IF2ARB22
IF2MCTR2
IF2DTA12
IF2DTA22
IF2DTB12
IF2DTB22
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN2 - IF2 Data A1 High
CAN2 - IF2 Data A2 Low
CAN2 - IF2 Data A2 High
CAN2 - IF2 Data B1 Low
CAN2 - IF2 Data B1 High
CAN2 - IF2 Data B2 Low
CAN2 - IF2 Data B2 High
000956H-
00097FH
Reserved
-
000980H
000981H
000982H
000983H
CAN2 - Transmission Request 1 Register Low
CAN2 - Transmission Request 1 Register High
CAN2 - Transmission Request 2 Register Low
CAN2 - Transmission Request 2 Register High
TREQR1L2
TREQR1H2
TREQR2L2
TREQR2H2
TREQR12
TREQR22
R
R
R
R
46
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (28 of 28)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000984H-
Reserved
00098FH
-
000990H
000991H
000992H
000993H
CAN2 - New Data 1 Register Low
CAN2 - New Data 1 Register High
CAN2 - New Data 2 Register Low
CAN2 - New Data 2 Register High
NEWDT1L2
NEWDT1H2
NEWDT2L2
NEWDT2H2
NEWDT12
NEWDT22
R
R
R
R
000994H-
00099FH
Reserved
-
0009A0H
0009A1H
0009A2H
0009A3H
CAN2 - Interrupt Pending 1 Register Low
CAN2 - Interrupt Pending 1 Register High
CAN2 - Interrupt Pending 2 Register Low
CAN2 - Interrupt Pending 2 Register High
INTPND1L2
INTPND1H2
INTPND2L2
INTPND2H2
INTPND12
INTPND22
R
R
R
R
0009A4H-
0009AFH
Reserved
-
0009B0H
0009B1H
0009B2H
0009B3H
CAN2 - Message Valid 1 Register Low
CAN2 - Message Valid 1 Register High
CAN2 - Message Valid 2 Register Low
CAN2 - Message Valid 2 Register High
MSGVAL1L2
MSGVAL1H2
MSGVAL2L2
MSGVAL2H2
MSGVAL12
MSGVAL22
R
R
R
R
0009B4H-
0009CDH
Reserved
-
R/W
-
0009CEH
CAN2 - Output enable register
Reserved
COER2
0009CFH-
000BFFH
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved
address results in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
FME-MB96350 rev 7
47
MB96350 Series
■ INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)35x (1 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
0
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
-
-
1
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
INT9
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EXCEPTION
NMI
-
-
Non-Maskable Interrupt
DLY
12
13
14
15
16
17
Delayed Interrupt
RC Timer
RC_TIMER
MC_TIMER
SC_TIMER
PLL_UNLOCK
EXTINT0
Main Clock Timer
Sub Clock Timer
Reserved
External Interrupt 0
Reserved
EXTINT2
EXTINT3
EXTINT4
Yes
Yes
Yes
19
20
21
External Interrupt 2
External Interrupt 3
External Interrupt 4
Reserved
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
CAN1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
23
24
25
26
27
28
29
30
31
32
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
CAN Controller 1 (only MB96F356Y/R)
48
FME-MB96350 rev 7
MB96350 Series
Interrupt vector table MB96(F)35x (2 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
CAN Controller 2 (only MB96F356Y/R
and MB96F353R/F355R)
33
378H
CAN2
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
374H
370H
36CH
368H
364H
360
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
PPG16
PPG17
PPG18
PPG19
RLT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Programmable Pulse Generator 16
Programmable Pulse Generator 17
Programmable Pulse Generator 18
Programmable Pulse Generator 19
Reload Timer 0
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
Reserved
Reserved
ICU4
ICU5
ICU6
ICU7
Yes
Yes
Yes
Yes
63
64
65
66
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
FME-MB96350 rev 7
49
MB96350 Series
Interrupt vector table MB96(F)35x (3 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
2BCH
2B8H
2B4H
2B0H
2ACH
2A8H
2A4H
2A0H
29CH
298H
294H
290H
28CH
288H
Reserved
ICU9
Yes
Yes
68
69
Input Capture Unit 9
Input Capture Unit 10
Reserved
ICU10
OCU4
OCU5
OCU6
OCU7
Yes
Yes
Yes
Yes
71
72
73
74
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
Reserved
Reserved
FRT0
FRT1
Yes
Yes
Yes
Yes
No
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Free Running Timer 0
Free Running Timer 1
Free Running Timer 2
Free Running Timer 3
Real Timer Clock
Clock Calibration Unit
I2C interface
FRT2
FRT3
RTC0
CAL0
No
IIC0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
ADC0
LINR2
LINT2
LINR3
LINT3
LINR7
LINT7
LINR8
LINT8
FLASH_A
A/D Converter
LIN USART 2 RX
LIN USART 2 TX
LIN USART 3 RX
LIN USART 3 TX
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
Flash memory A (only Flash devices)
50
FME-MB96350 rev 7
MB96350 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Unused sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Serial communication
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC
Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
FME-MB96350 rev 7
51
MB96350 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
X0
X1
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6. Power supply pins (VCC/VSS
)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
52
FME-MB96350 rev 7
MB96350 Series
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
FME-MB96350 rev 7
53
MB96350 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
Power supply voltage
*1
AVCC
VCC = AVCC
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
AD Converter voltage references
VSS - 0.3 VSS + 6.0
V
*2
Input voltage
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
VI ≤ VCC + 0.3V
VO ≤ VCC + 0.3V *2
Output voltage
VO
Applicable to general purpose
I/O pins *3
Maximum Clamp Current
ICLAMP
-4.0
+4.0
mA
mA
Applicable to general purpose
I/O pins *3
Total Maximum Clamp Current
“L” level maximum output current
Σ|ICLAMP|
-
-
40
15
IOL1
mA Normal outputs with driving
strength set to 5mA
“L” level average output current
IOLAV1
-
5
mA Normal outputs with driving
strength set to 5mA
“L” level maximum overall output current
“L” level average overall output current
”H” level maximum output current
ΣIOL1
ΣIOLAV1
IOH1
-
-
-
100
50
mA Normal outputs
mA Normal outputs
-15
mA Normal outputs with driving
strength set to 5mA
”H” level average output current
IOHAV1
-
-5
mA Normal outputs with driving
strength set to 5mA
”H” level maximum overall output current
”H” level average overall output current
ΣIOH1
-
-
-
-
-
-100
-50
mA Normal outputs
mA Normal outputs
ΣIOHAV1
320*5
640*5
800*5
TA=105oC
TA=85oC
TA=75oC
mW
mW
mW
Permitted Power dissipation (Flash de-
vices) *4
PD
TA=125oC, no Flash program/
erase *6
400*5
560*5
-
-
mW
mW
TA=115oC, no Flash program/
erase *6
0
+70
MB96V300B
oC
oC
-40
-40
-55
+105
+125
+150
Operating ambient temperature
Storage temperature
TA
*6
TSTG
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
54
FME-MB96350 rev 7
MB96350 Series
*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating super-
sedes the VI rating. Input/output voltages of standard ports depend on VCC.
*3: • Applicable to all general purpose I/O pins (Pnn_m)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
FME-MB96350 rev 7
55
MB96350 Series
2. Recommended Operating Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
VCC
3.0
5.5
V
UseaX7Rceramiccapacitoror
Smoothing capacitor at C
pin
CS
3.5
4.7
15
µF a capacitor that has similar fre-
quency characteristics
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
56
FME-MB96350 rev 7
MB96350 Series
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
Input H voltage
CMOSHysteresis
0.8/0.2 input se-
lected
0.8
VCC
VCC +
0.3
-
V
0.7
VCC +
-
-
V
V
VCC ≥ 4.5V
CMOSHysteresis
0.7/0.3 input se-
lected
VCC
0.3
Port inputs
Pnn_m
0.74
VCC
VCC +
0.3
VCC < 4.5V
VIH
AUTOMOTIVE
Hysteresis input
selected
0.8
VCC +
-
-
-
-
V
V
V
VCC
0.3
TTL input select-
ed
VCC +
0.3
2.0
External clock in
“Fast Clock Input
mode”
0.8
VCC
VCC +
0.3
VIHX0F
X0
X0,X1,
External clock in
VCC +
0.3
2.5
VIHX0S
V
V
V
X0A,X1A “oscillation mode”
CMOS Hysteresis in-
put
0.8
VCC
VCC +
0.3
-
-
VIHR
VIHM
RSTX
-
-
VCC -
0.3
VCC +
0.3
MD2-MD0
Input L voltage
CMOSHysteresis
0.8/0.2 input se-
lected
VSS -
0.2
-
-
V
0.3
VCC
CMOSHysteresis
0.7/0.3 input se-
lected
VSS -
0.3
0.3
VCC
V
V
Port inputs
Pnn_m
VIL
VSS -
0.3
0.5
VCC
-
-
VCC ≥ 4.5V
AUTOMOTIVE
Hysteresis input
selected
VSS -
0.3
0.46
VCC
VCC < 4.5V
TTL input select-
ed
VSS -
-
-
-
0.8
V
V
0.3
External clock in
“Fast Clock Input
mode”
VSS -
0.3
0.2 VCC
VILX0F
VILX0S
X0
X0,X1,
External clock in
X0A,X1A “oscillation mode”
VSS -
0.3
0.4
V
V
V
CMOS Hysteresis in-
put
VSS -
0.3
-
-
0.2 VCC
VILR
VILM
RSTX
-
-
VSS -
0.3
VSS +
0.3
MD2-MD0
FME-MB96350 rev 7
57
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V ≤ VCC ≤ 5.5V
IOH = -2mA
Output H voltage
Driving strength set
to 2mA
(PODR:OD=1)
Normal
outputs
VCC -
0.5
-
-
VOH2
V
3.0V ≤ VCC < 4.5V
IOH = -1.6mA
4.5V ≤ VCC ≤ 5.5V
IOH = -5mA
Driving strength set
to 5mA
(PODR:OD=0)
Normal
outputs
VCC -
0.5
-
-
-
-
-
VOH5
VOH3
VOL2
VOL5
V
V
V
3.0V ≤ VCC < 4.5V
IOH = -3mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
3mA out-
puts
VCC -
0.5
-
I/O circuit type “N”
3.0V ≤ VCC < 4.5V
IOH = -2mA
4.5V ≤ VCC ≤ 5.5V
IOL = +2mA
Output L voltage
Driving strength set
to 2mA
(PODR:OD=1)
Normal
outputs
-
-
0.4
0.4
3.0V ≤ VCC < 4.5V
IOL = +1.6mA
4.5V ≤ VCC ≤ 5.5V
IOL = +5mA
Driving strength set
to 5mA
(PODR:OD=0)
Normal
outputs
V
V
3.0V ≤ VCC < 4.5V
IOL = +3mA
3.0V ≤ VCC ≤ 5.5V
IOL = +3mA
3mA out-
puts
-
-
-
0.4
+1
VOL3
IIL
I/O circuit type “N”
VSS < VI < VCC
-1
Input leak current
Pull-up resistance
Pnn_m
µA Single port pin
AVSS, AVRL < VI <
AVCC, AVRH
40
25
100
50
160
100
VCC = 3.3V 10%
VCC = 5.0V 10%
kΩ
kΩ
Pnn_m,
RSTX
RUP
58
FME-MB96350 rev 7
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
+25˚C 14.5 19.5
mA MB96F353/F355
+125˚C
+25˚C
16
15
23
20
1 Flash/ROM wait state
mA MB96F356
(CLKRC and CLKSC
stopped)
+125˚C 16.5 23.5
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
+25˚C
+125˚C
+25˚C
23
25
24
29
33
30
mA MB96F353/F355
mA MB96F356
2 Flash/ROM wait states
(CLKRC and CLKSC
stopped)
+125˚C
26
34
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
+25˚C
+125˚C
+25˚C
26
28
28
38
42
40
mA MB96F353/F355
mA MB96F356
Power supply cur-
rent in Run
modes*
ICCPLL
0 Flash/ROM wait states
(CLKRC and CLKSC
stopped)
+125˚C
30
44
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
+25˚C
+125˚C
+25˚C
40
42
41
51
55
52
mA MB96F353/F355
2 Flash/ROM wait states
mA MB96F356
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
43
56
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
+25˚C
+125˚C
+25˚C
43
45
44
56
60
58
mA MB96F353/F355
mA MB96F356
1 Flash/ROM wait state
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
46
62
FME-MB96350 rev 7
59
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
+25˚C
4
5
mA MB96F353/F355
mA MB96F356
+125˚C 4.7
+25˚C 4.2
+125˚C 4.9
+25˚C 2.5
+125˚C 3.2
+25˚C 2.7
8
ICCMAIN
1 Flash/ROM wait state
5.2
8.2
3.5
6.5
3.7
6.7
0.3
3.1
0.6
(CLKPLL, CLKSC and
CLKRC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
mA MB96F353/F355
mA MB96F356
ICCRCH
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped)
+125˚C 3.4
+25˚C 0.18
+125˚C 0.73
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
mA MB96F353/F355
+25˚C
0.4
1 Flash/ROM wait state
Power supply cur-
rent in Run
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
mA MB96F356
+125˚C 0.95
3.4
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
+25˚C 0.15 0.25
1 Flash/ROM wait state
MB96F353/F355/
F356
mA
+125˚C 0.7
3.05
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode, no Flash program-
ming/erasing allowed)
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
+25˚C
0.1
0.2
3
1 Flash/ROM wait state
MB96F353/F355/
F356
ICCSUB
mA
+125˚C 0.65
(CLKMC, CLKPLL and
CLKRCstopped, noFlash
programming/erasing al-
lowed)
60
FME-MB96350 rev 7
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
PLL Sleep mode with
CLKS1/2 = CLKP1 =
16MHz,
+25˚C
4
6
MB96F353/F355/
F356
mA
9
CLKP2 = 8MHz
+125˚C 4.7
(CLKRC and CLKSC
stopped)
PLL Sleep mode with
CLKS1/2 = CLKP1 =
32MHz,
+25˚C
7
8
9.5
MB96F353/F355/
F356
mA
CLKP2 = 16MHz
+125˚C
12.5
(CLKRC and CLKSC
stopped)
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
+25˚C
+125˚C
+25˚C
7
8
9
MB96F353/F355/
F356
mA
12
ICCSPLL
(CLKRC and CLKSC
stopped)
PLL Sleep mode with
CLKS1/2 = CLKP1=
11
14.5
56MHz, CLKP2 = 28MHz
MB96F353/F355/
F356
mA
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
+25˚C
12
12
17.5
Power supply cur-
rent in Sleep
modes*
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
15
MB96F353/F355/
F356
CLKP2 = 24MHz
mA
18
+125˚C
+25˚C
13
1
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
1.3
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
mA MB96F353/F355
mA MB96F356
+125˚C 1.6
+25˚C 1.3
4.1
1.8
4.6
1.1
3.9
1.4
4.2
ICCSMAIN
(CLKPLL, CLKSC and
CLKRC stopped)
+125˚C 1.9
+25˚C 0.55
+125˚C 1.15
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
mA MB96F353/F355
mA MB96F356
ICCSRCH
+25˚C
0.8
(CLKMC, CLKPLL and
CLKSC stopped)
+125˚C 1.4
FME-MB96350 rev 7
61
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
+25˚C 0.08
0.2
mA MB96F353/F355
mA MB96F356
+125˚C 0.59 2.95
SMCR:LPMSS = 0
+25˚C
0.3
0.5
3.3
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C 0.8
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
+25˚C 0.05 0.15
Power supply cur-
rent in Sleep
modes*
SMCR:LPMSS = 1
MB96F353/F355/
F356
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.56
2.9
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
+25˚C 0.04 0.12
MB96F353/F355/
F356
ICCSSUB
mA
+125˚C 0.54
2.9
(CLKMC, CLKPLL and
CLKRC stopped)
+25˚C
+125˚C 1.9
+25˚C 1.5
1.3
1.8
4.8
2
PLL Timer mode with
CLKMC = 4MHz, CLKPLL
= 48MHz
mA MB96F353/F355
mA MB96F356
ICCTPLL
(CLKRC and CLKSC
stopped)
+125˚C 2.1
+25˚C 0.11
+125˚C 0.63
+25˚C 0.35
+125˚C 0.85
5
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
0.2
3
mA MB96F353/F355
mA MB96F356
Power supply cur-
rent in Timer
modes*
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
0.5
3.3
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
+25˚C 0.08 0.15
SMCR:LPMSS = 1
MB96F353/F355/
F356
mA
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.6
2.9
62
FME-MB96350 rev 7
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
+25˚C
0.1
0.2
mA MB96F353/F355
mA MB96F356
+125˚C 0.63
+25˚C 0.35
+125˚C 0.85
3
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
0.5
3.3
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
+25˚C 0.07 0.15
SMCR:LPMSS = 1
MB96F353/F355/
F356
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.6
2.9
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
+25˚C 0.06 0.15
+125˚C 0.56 2.95
Power supply cur-
rent in Timer
modes*
mA MB96F353/F355
mA MB96F356
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C
0.3
0.45
3.2
+125˚C 0.8
+25˚C 0.03
ICCTRCL
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
0.1
MB96F353/F355/
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
F356
+125˚C 0.53 2.85
Sub Timer mode with
CLKSC = 32kHz
+25˚C 0.035 0.1
+125˚C 0.53 2.85
+25˚C 0.02 0.08
MB96F353/F355/
F356
ICCTSUB
mA
(CLKMC, CLKPLL and
CLKRC stopped)
VRCR:LPMB[2:0] = 110B
(Core voltage at 1.8V)
MB96F353/F355/
F356
mA
+125˚C 0.52
2.8
Power supply cur-
rent in Stop Mode
ICCH
+25˚C 0.015 0.06
VRCR:LPMB[2:0] = 000B
(Core voltage at 1.2V)
MB96F353/F355/
F356
mA
+125˚C 0.4
2.3
10
MB96F353/F355
+25˚C
+125˚C
+25˚C
5
7
µA
Power supply cur-
rentforactiveLow
Voltage detector
Must be added to all
current above
20
µA
Low voltage detector en-
abled (RCR:LVDE = 1)
ICCLVD
MB96F356
90
140
150
µA
Must be added to all
+125˚C 100
current above
FME-MB96350 rev 7
63
MB96350 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
Power supply cur-
rent for active
Clock modulator
Clock modulator enabled
(CMCR:PDX = 1)
Must be added to all
current above
ICCCLOMO
ICCFLASH
CIN
-
-
-
3
4.5
40
15
mA
mA
FlashWrite/Erase
current
Current for one Flash
module
Must be added to all
current above
15
5
Other than C, AVCC,
pF AVSS, AVRH, AVRL,
Input capacitance
-
VCC, VSS
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of
the Hardware Manual for further details about voltage regulator control.
64
FME-MB96350 rev 7
MB96350 Series
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
When using an opposite phase external
clock, PLL off
0
3.5
0
-
-
-
16
16
56
56
MHz
Clock frequency
fC
X0, X1
When using a crystal oscillator or oppo-
MHz
site phase external clock, PLL on
When using a single phase external
MHz
clockin“FastClockInputmode”, PLLoff
Clock frequency
Clock frequency
Clock frequency
fFCI
X0
When using a single phase external
MHz
3.5
32
0
-
clockin“FastClockInputmode”, PLLon
32.768
-
100 kHz When using an oscillation circuit
X0A, X1A
X0A
When using an opposite phase external
100 kHz
clock
fCL
When using a single phase external
clock
0
50
1
-
100
2
50
kHz
When using slow frequency of RC oscil-
lator
200 kHz
fCR
-
-
When using fast frequency of RC oscil-
lator
4
MHz
Applied after any reset and when acti-
vating the RC oscillator.
MB96F356: 64 cycles
RC clock stabili-
zation time
tRCSTAB
64 or 256 RC clock cycles
others: 256 cycles
PLL Clock fre-
quency
Permitted VCO output frequency of PLL
(CLKVCO)
fCLKVCO
TPSKEW
-
-
64
-
-
-
200 MHz
For CLKMC (PLL input clock) ≥ 4MHz,
ns jitter coming from external oscillator,
crystal or resonator is not covered
PLL Phase Jitter
5
Inputclockpulse
width
PWH, PWL
X0,X1
8
5
-
-
-
-
ns Duty ratio is about 30% to 70%
Inputclockpulse
width
PWHL, PWLL X0A,X1A
µs
FME-MB96350 rev 7
65
MB96350 Series
tCYL
VIH
VIL
X0
PWH
PWL
tCYLL
VIH
VIL
X0A
PWHL
PWLL
66
FME-MB96350 rev 7
MB96350 Series
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Parameter
Symbol
1.8V
1.9V
Unit
Remarks
Min
0
Max
92
Min
0
Max
96
Internal System clock fre-
quency (CLKS1 and
CLKS2)
fCLKS1, fCLKS2
MHz
MHz
Others than below
MB96F356
0
88
0
96
Internal CPU clock fre-
quency (CLKB), internal
peripheralclockfrequency
(CLKP1)
fCLKB, fCLKP1
fCLKP2
0
0
52
28
0
0
56
32
MHz
MHz
Internal peripheral clock
frequency (CLKP2)
FME-MB96350 rev 7
67
MB96350 Series
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Reset input time
Symbol
Pin
Unit
Remarks
Min
Typ
Max
tRSTL
RSTX
500
-
-
ns
tRSTL
RSTX
0.2 VCC
0.2 VCC
68
FME-MB96350 rev 7
MB96350 Series
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
0.05
1
Typ
Max
30
-
Power on rise time
Power off time
tR
Vcc
Vcc
-
-
ms
ms
tOFF
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3 V
Rising edge of 50 mV/ms
maximum is allowed
FME-MB96350 rev 7
69
MB96350 Series
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Used Pin input func-
Parameter Symbol
Pin
Condition
Unit
tion
Min
Max
INTn(_R)
NMI(_R)
Pnn_m
External Interrupt
NMI
200
⎯
ns
General Purpose IO
Reload Timer
TINn(_R)
TTGn(_R)
ADTG(_R)
Input pulse
width
tINH
tINL
⎯
PPG Trigger input
AD Converter Trigger
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)
⎯
ns
Free Running Timer
external clock
FRCKn(_R)
INn(_R)
Input Capture
Note : Relocated Resource Inputs have same characteristics
VIH
VIH
External Pin input
VIL
VIL
tINH
tINL
70
FME-MB96350 rev 7
MB96350 Series
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must then be increased by 10ns.
Basic Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
25
Max
⎯
tCYC
tCHCL
ECLK
ECLK
⎯
tCYC/2-5
tCYC/2-5
-20
tCYC/2+5
tCYC/2+5
20
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-20
20
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX, ECLK
⎯
⎯
ns
ns
-20
20
-20
20
-10
10
tCHLL
-10
10
ECLK → ALE time
ALE, ECLK
tCLLH
-10
10
tCLLL
-10
10
tCHAV
-15
15
A[23:16],
ECLK
⎯
⎯
ns
ns
tCLAV
-15
15
ECLK → address valid time
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-15
15
AD[15:0],
ECLK
-15
15
-10
10
RDX, WRX,
WRLX,WRHX,
ECLK
-10
10
ECLK → RDX /WRX time
⎯
ns
-10
10
-10
10
FME-MB96350 rev 7
71
MB96350 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
Max
⎯
tCYC
tCHCL
30
ECLK
ECLK
⎯
tCYC/2-8
tCYC/2-8
-25
tCYC/2+8
tCYC/2+8
25
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-25
25
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX, ECLK
⎯
⎯
ns
ns
-25
25
-25
25
-15
15
tCHLL
-15
15
ECLK → ALE time
ALE, ECLK
tCLLH
-15
15
tCLLL
-15
15
tCHAV
-20
20
A[23:16],
ECLK
⎯
⎯
ns
ns
tCLAV
-20
20
ECLK → address valid time
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-20
20
AD[15:0],
ECLK
-20
20
-15
15
RDX, WRX,
WRLX, WRHX,
ECLK
-15
15
ECLK → RDX /WRX time
⎯
ns
-15
15
-15
15
72
FME-MB96350 rev 7
MB96350 Series
tCYC
tCHCL
tCLCH
0.8*Vcc
ECLK
0.2*Vcc
tCLAV
tCHAV
A[23:16]
tCHCBL
tCLCBL
tCHCBH
tCLCBH
CSn
LBX UBX
tCHRWL
tCLRWL
tCHRWH
tCLRWH
RDX
WRX (WRLX, WRHX)
tCHLL
tCLLL
tCLLH
tCHLH
ALE
tCHADV
tCLADV
Address
AD[15:0]
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
73
MB96350 Series
Bus Timing (Read)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 5
tCYC − 5
ALE pulse width
EACL:STS=1
tLHLL ALE
⎯
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 5
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC − 15
3tCYC/2 − 15
2tCYC − 15
5tCYC/2 − 15
tCYC/2 − 15
tCYC − 15
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
⇒ ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE,AD[15:0]
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 15
EACL:STS=1 and
EACL:ACE=1
2tCYC − 15
tCYC/2 − 15
-15
⎯
⎯
⎯
EACL:STS=0
EACL:STS=1
EACL:ACE=0
ALE ↓
⇒ Address valid time
tLLAX ALE, AD[15:0]
tAVRL RDX, A[23:16]
ns
ns
3tCYC/2 − 15
5tCYC/2 − 15
tCYC − 15
2tCYC − 15
⎯
⎯
⎯
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
Valid address
⇒ RDX ↓ time
⎯
tADVRL RDX, AD[15:0]
ns
ns
⎯
3tCYC − 55
4tCYC − 55
5tCYC/2 − 55
7tCYC/2 − 55
⎯
A[23:16],
tAVDV
w/o cycle
extension
AD[15:0]
⎯
Valid address
⇒ Valid data input
⎯
w/o cycle
extension
tADVDV AD[15:0]
tRLRH RDX
ns
ns
⎯
w/o cycle
extension
RDX pulse width
⎯
3 tCYC/2 − 5
w/o cycle
extension
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
⎯
⎯
⎯
3 tCYC/2 − 50 ns
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
0
⎯
ns
74
FME-MB96350 rev 7
MB96350 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
A[23:16],
Conditions
Unit
Min
Max
Address valid ⇒ Data hold
tAXDX
⎯
0
⎯
ns
time
AD[15:0]
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 10
tCYC/2 − 10
⎯
⎯
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
ns
other ECL:STS,
EACL:ACE setting
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, ECLK
tCYC − 15
tCYC/2 − 15
tCYC/2 − 10
tCYC/2 − 10
− 10
⎯
⎯
Valid address
⇒ ECLK ↑ time
⎯
ns
ns
ns
ns
RDX ↓ ⇒ ECLK ↑ time
⎯
EACL:STS=0
EACL:STS=1
⎯
⎯
⎯
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
⎯
ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK
⎯
tCYC − 50
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 8
tCYC − 8
ALE pulse width
EACL:STS=1
tLHLL ALE
⎯
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 8
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC − 20
3tCYC/2 − 20
2tCYC − 20
5tCYC/2 − 20
tCYC/2 − 20
tCYC − 20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
⇒ ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE, AD[15:0]
tLLAX ALE, AD[15:0]
ns
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 20
EACL:STS=1 and
EACL:ACE=1
2tCYC − 20
tCYC/2 − 20
-20
⎯
⎯
⎯
EACL:STS=0
EACL:STS=1
ALE ↓
⇒ Address valid time
FME-MB96350 rev 7
75
MB96350 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
EACL:ACE=0
3tCYC/2 − 20
5tCYC/2 − 20
tCYC − 20
2tCYC − 20
⎯
⎯
tAVRL RDX, A[23:16]
tADVRL RDX, AD[15:0]
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
⎯
⎯
Valid address
⇒ RDX ↓ time
ns
ns
⎯
3tCYC − 60
4tCYC − 60
5tCYC/2 − 60
7tCYC/2 − 60
⎯
A[23:16],
tAVDV
w/o cycle
extension
AD[15:0]
⎯
Valid address
⇒ Valid data input
⎯
w/o cycle
extension
tADVDV AD[15:0]
tRLRH RDX
ns
ns
⎯
w/o cycle
extension
RDX pulse width
⎯
3tCYC/2 − 8
w/o cycle
extension
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
⎯
⎯
⎯
3tCYC/2 − 55 ns
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
tAXDX A[23:16]
0
⎯
⎯
ns
ns
Address valid ⇒ Data hold
⎯
0
time
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 15
tCYC/2 − 15
⎯
⎯
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
ns
other ECL:STS,
EACL:ACE setting
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, ECLK
tCYC − 20
tCYC/2 − 20
tCYC/2 − 15
tCYC/2 − 15
− 15
⎯
⎯
Valid address
⇒ ECLK ↑ time
⎯
ns
ns
ns
ns
RDX ↓ ⇒ ECLK ↑ time
⎯
EACL:STS=0
EACL:STS=1
⎯
⎯
⎯
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
⎯
ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK
⎯
tCYC − 55
76
FME-MB96350 rev 7
MB96350 Series
tAVCH
tCHDV
tRLCH
tADVCH
0.8*Vcc
ECLK
tAVLL
tLLAX
tADVLL
tRHLH
ALE
0.2*VCC
tLHLL
tAVRL
tADVRL
tRLRH
RDX
tLLRL
A[23:16]
tRLDV
tAXDX
tAVDV
tRHDX
tADVDV
VIH
VIL
VIH
VIL
AD[15:0]
Address
Read data
Refer to the Hardware Manual for detailed Timing Charts
.
Bus Timing (Write)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EACL:ACE=0
3tCYC/2 −
⎯
WRX, WRLX,
WRHX,
A[23:16]
15
tAVWL
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
5tCYC/2 −
⎯
⎯
⎯
⎯
Valid address
⇒ WRX ↓ time
15
tCYC − 15
2tCYC − 15
tCYC − 5
WRX, WRLX,
tADVWL WRHX,
ns
AD[15:0]
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
⎯
⎯
ns
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
⇒ WRX ↑ time
w/o cycle
extension
tCYC − 20
⎯
FME-MB96350 rev 7
77
MB96350 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
⎯
⎯
tCYC/2 − 15
tCYC/2 − 15
⎯
ns
⇒ Data hold time
WRX ↑
⇒ Address valid time
WRX, WRLX,
WRHX,
A[23:16]
tWHAX
⎯
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC − 10
tCYC − 10
⎯
⎯
WRX ↑ ⇒ ALE ↑ time
WRX, WRLX,
WRHX, ALE
tWHLH
tWLCH
ns
ns
ns
ns
EACL:STS setting
WRX ↓ ⇒ ECLK ↑
time
WRX, WRLX,
WRHX, ECLK
⎯
tCYC/2 − 10
⎯
⎯
3tCYC/2 −
EACL:ACE=0
15
CSn ⇒ WRX time
WRX ⇒ CSn time
WRX, WRLX,
WRHX, CSn
tCSLWL
5tCYC/2 −
EACL:ACE=1
⎯
15
WRX, WRLX,
WRHX, CSn
⎯
tWHCSH
tCYC/2 − 15
⎯
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EACL:ACE=0
3tCYC/2 −
⎯
WRX, WRLX,
WRHX,
A[23:16]
20
tAVWL
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
5tCYC/2 −
⎯
⎯
⎯
⎯
Valid address
⇒ WRX ↓ time
20
tCYC − 20
2tCYC − 20
tCYC − 8
WRX, WRLX,
tADVWL WRHX,
ns
AD[15:0]
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
⎯
⎯
ns
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
⇒ WRX ↑ time
w/o cycle
extension
tDVWH
tCYC − 25
tCYC/2 − 20
tCYC/2 − 20
⎯
⎯
⎯
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
tWHAX
⎯
⎯
ns
ns
⇒ Data hold time
WRX ↑
⇒ Address valid time
WRX, WRLX,
WRHX,
A[23:16]
78
FME-MB96350 rev 7
MB96350 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC − 15
tCYC − 15
⎯
WRX ↑ ⇒ ALE ↑ time
WRX, WRLX,
WRHX, ALE
tWHLH
tWLCH
ns
ns
ns
ns
⎯
⎯
EACL:STS setting
WRX ↓ ⇒ ECLK ↑
time
WRX, WRLX,
WRHX, ECLK
⎯
tCYC/2 − 15
⎯
3tCYC/2 −
EACL:ACE=0
20
CSn ⇒ WRX time
WRX ⇒ CSn time
WRX, WRLX,
WRHX, CSn
tCSLWL
tWHCSH
5tCYC/2 −
EACL:ACE=1
⎯
20
WRX, WRLX,
WRHX, CSn
⎯
tCYC/2 − 20
⎯
tWLCH
0.8*VCC
ECLK
tWHLH
ALE
.
tAVWL
tWLWH
tADVWL
WRX (WRLX, WRHX)
0.2*VCC
tCSLWL
tWHCSH
CSn
tWHAX
A[23:16]
tDVWH
tWHDX
AD[15:0]
Address
Write data
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
79
MB96350 Series
Ready Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Condition
Parameter
Symbol
Pin
Units
Remarks
Min
Max
⎯
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
35
0
ns
ns
⎯
⎯
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Parameter
Symbol
Pin
Units
Remarks
Condition
Min
45
0
Max
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
ns
ns
⎯
⎯
Note : If the RDY setup time is insufficient, use the auto-ready function.
0.8*VCC
ECLK
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
Refer to the Hardware Manual for detailed Timing Charts
Hold Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating ⇒ HAKX ↓ time
HAKX ↑ time ⇒ Pin valid time
tXHAL
HAKX
HAKX
tCYC − 20 tCYC + 20
tCYC − 20 tCYC + 20
ns
ns
⎯
tHAHV
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating ⇒ HAKX ↓ time
HAKX ↑ time ⇒ Pin valid time
tXHAL
tHAHV
HAKX
HAKX
tCYC − 25 tCYC + 25
tCYC − 25 tCYC + 25
ns
ns
⎯
80
FME-MB96350 rev 7
MB96350 Series
0.8*VCC
HAKX
0.2*VCC
tHAHV
tXHAL
High-Z
0.8*VCC
0.2*VCC
Each pin
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
81
MB96350 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must then be increased by 10ns.
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYCI
tSLOVI
SCKn
4 tCLKP1
⎯
4 tCLKP1
⎯
ns
ns
SCK ↓ → SOT delay
time
SCKn,
SOTn
-20
+20
⎯
-30
+30
⎯
SOT → SCK ↑ delay
time
SCKn,
SOTn
N*tCLKP1
- 20 *1
N*tCLKP1 -
30 *1
tOVSHI
tIVSHI
Internal Shift
Clock Mode
ns
ns
ns
ns
ns
ns
ns
ns
SCKn,
SINn
tCLKP1 +
45
tCLKP1 +
55
Valid SIN → SCK ↑
⎯
⎯
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tSHIXI
0
⎯
0
⎯
Serial clock “L” pulse
width
tCLKP1 +
10
tCLKP1 +
10
tSLSHE
tSHSLE
tSLOVE
tIVSHE
tSHIXE
SCKn
SCKn
⎯
⎯
Serial clock “H” pulse
width
tCLKP1 +
10
tCLKP1 +
10
⎯
⎯
SCK ↓ → SOT delay
time
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
⎯
⎯
External Shift
Clock Mode
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2+
Valid SIN → SCK ↑
⎯
⎯
⎯
⎯
10
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tCLKP1 +
10
tCLKP1 +
10
SCK fall time
SCK rise time
tFE
tRE
SCKn
SCKn
⎯
⎯
20
20
⎯
⎯
20
20
ns
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
4*tCLKP1
N
2
5*tCLKP1, 6*tCLKP1
7*tCLKP1, 8*tCLKP1
...
3
4
...
82
FME-MB96350 rev 7
MB96350 Series
tSCYCI
SCK for
0.8*VCC
ESCR:SCES = 0
0.2*VCC
0.2*VCC
0.8*VCC
SCK for
0.8*VCC
ESCR:SCES = 1
0.2*VCC
tOVSHI
tSLOVI
0.8*VCC
0.2*VCC
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
VIH
VIL
VIH
VIH
VIL
ESCR:SCES = 0
VIL
SCK for
VIH
VIH
ESCR:SCES = 1
VIL
VIL
tSLOVE
tFE
tRE
0.8*VCC
0.2*VCC
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
External Shift Clock Mode
FME-MB96350 rev 7
83
MB96350 Series
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)
Fast-mode*1
Standard-mode
Parameter
Symbol
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45
⎯
0.6
0
⎯
0.9
⎯
µs
µs
ns
µs
µs
Data hold time
SCL↓→SDA↓↑
Data set-up time
SDA↓↑→SCL↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL↑→SDA↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
Cb
tSP
20 + 0.1*Cb *2
250
400
n/a
20 + 0.1*Cb *2
250
400
ns
pF
ns
Capacitive load for each bus line
⎯
⎯
Pulse width of spikes which will be sup-
pressed by input noise filter
n/a
0
1*tCLKP1*3
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
SDA
t
BUS
tSUDAT
t
HDSTA
t
LOW
SCL
tHIGH
t
HDSTA
t
HDDAT
t
SUSTA
tSUSTO
• VOH = 0.7 * VCC
• VOL = 0.3 * VCC
• CMOS Hysteresis 0.7/0.3 input selected
84
FME-MB96350 rev 7
MB96350 Series
5. Analog Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
Typ
Max
10
3
-
-
-
-
-
-
-
-
-
-
-
-
-
bit
Total error
LSB
Nonlinearity error
2.5 LSB
Differentialnonlinearity
error
-
-
-
1.9 LSB
AVRL - AVRL+ AVRL +
1.5 LSB 0.5 LSB 2.5 LSB
Zero transition voltage
VOT
ANn
ANn
V
V
Full scale transition
voltage
AVRH - AVRH - AVRH+
3.5 LSB 1.5 LSB 0.5 LSB
VFST
1.0
2.0
0.5
1.2
-
-
-
-
16,500 µs
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
TA ≤ 105 ˚C,
Compare time
Sampling time
-
-
-
-
-
-
-
µs
µs
µs
-1
-
-
+1
µA AVSS, AVRL < VI <
Analog input leakage
current (during conver-
sion)
AVCC, AVRH
IAIN
ANn
105 ˚C < TA ≤ 125 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
-1.2
+1.2
Analog input voltage
range
VAIN
ANn
AVRL
-
-
AVRH
AVcc
V
V
0.75
AVcc
AVRH
AVRH
Reference voltage
range
0.25
AVCC
AVRL
IA
AVRL
AVcc
AVcc
AVSS
-
2.5
-
V
-
-
5
5
mA A/D Converter active
Power supply current
A/DConverternotop-
erated
IAH
µA
AVRH/
AVRL
IR
IRH
-
-
-
-
0.7
1
5
4
mA A/D Converter active
Reference voltage cur-
rent
AVRH/
AVRL
A/DConverternotop-
erated
-
-
µA
Offset between input
channels
ANn
LSB
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
FME-MB96350 rev 7
85
MB96350 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
N: A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
86
FME-MB96350 rev 7
MB96350 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
3FE
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FD
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Nonlinearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential nonlinearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
FME-MB96350 rev 7
87
MB96350 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal
sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and
the AVcc voltage level. The following replacement model can be used for the calculation:
MCU
Analog
input
Rext
RADC
Comparator
Source
Cext
CIN
CADC
Sampling switch
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
CIN: capacitance of MCU input pin: 15pF (max)
RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V
12kΩ (max) for 3.0V ≤ AVcc < 4.5V
CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement
model above can be used:
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this
case the internal sampling capacitance CADC will be charged out of this external capacitance.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input
leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total
leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL
cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
88
FME-MB96350 rev 7
MB96350 Series
6. Low Voltage Detector characteristics
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Value *1
Value *2
Parameter
Symbol
Unit
Remarks
Min
Max
Min
Max
After power-up or change
of detection level
Stabilization time TLVDSTAB
-
75
-
110
µs
CILCR:LVL[3:0]=”0000”
CILCR:LVL[3:0]=”0001”
CILCR:LVL[3:0]=”0010”
CILCR:LVL[3:0]=”0011”
CILCR:LVL[3:0]=”0100”
CILCR:LVL[3:0]=”0101”
CILCR:LVL[3:0]=”0110”
CILCR:LVL[3:0]=”0111”
CILCR:LVL[3:0]=”1000”
CILCR:LVL[3:0]=”1001”
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
VDL7
VDL8
VDL9
VDL10
VDL11
VDL12
VDL13
VDL14
VDL15
2.7
2.9
3.1
3.5
3.6
3.7
3.8
3.9
4.0
4.1
2.9
3.1
2.5
2.8
3
2.9
3.2
3.4
3.8
3.95
4.1
4.2
4.3
4.4
4.5
V
V
V
V
V
V
V
V
V
V
3.3
3.75
3.85
3.95
4.05
4.15
4.25
4.35
3.35
3.5
3.6
3.7
3.8
3.9
3.95
not used
not used
not used
2.6
not used
not used
not used
not used
not used
CILCR:LVL[3:0]=”1100”
3
V
not used
not used
not used
*1: valid for all devices except devices listed under “*2”
*2: valid for: MB96F353/F355
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
V
dV
dt
-----
µs
For correct detection, the slope of the voltage level must satisfy
≤ 0.004
.
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
“Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to
3.0V).
FME-MB96350 rev 7
89
MB96350 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Power Reset Extension Time
Low Voltage Reset Assertion
Normal Operation
90
FME-MB96350 rev 7
MB96350 Series
7. FLASH memory program/erase characteristics
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Sector erase time
Unit
Remarks
Min
Typ
Max
Without erasure pre-program-
ming time
-
0.9
3.6
s
s
Without erasure pre-program-
ming time (n is the number of
Flash sector of the device)
Chip erase time
-
-
n*0.9
23
n*3.6
370
Without overhead time for sub-
mitting write command
Word (16-bit width) programming time
us
Program/Erase cycle
10 000
20
-
-
-
-
cycle
year
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
FME-MB96350 rev 7
91
MB96350 Series
■ EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in differ-
ent operation modes.
Common condition for all operation modes:
•
V
= AV = 5.0V
CC CC
•
•
Main clock = 4MHz external clock
Sub clock = 32kHz external clock
Operation mode details:
Mode name
Details
PLL Run 56
PLL Run mode current I
with the following settings:
CCPLL
•
•
f
f
= f
= f
= f
= 56MHz
CLKP1
CLKS1
CLKS2
CLKB
= 28MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
2 Flash/ROM wait states (MTCRA=233A )
H
RC oscillator and Sub oscillator stopped
PLL Run 48
PLL Run mode current I
with the following settings:
CCPLL
•
•
•
f
f
f
= f
= 96MHz
CLKS2
CLKS1
= f
= 48MHz
CLKP1
CLKB
= 24MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
1 Flash/ROM wait states (MTCRA=6B09 )
H
RC oscillator and Sub oscillator stopped
PLL Run 24
PLL Run mode current I
with the following settings:
CCPLL
•
•
f
f
= f
= 48MHz
CLKS2
CLKS1
= f
= f
= 24MHz
CLKP2
CLKB
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
0 Flash/ROM wait states (MTCRA=2208 )
H
RC oscillator and Sub oscillator stopped
Main Run
Main Run mode current I
with the following settings:
CCMAIN
•
f
= f
= f
= f
= f
= 4MHz
CLKP2
CLKS1
CLKS2
CLKB
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, RC oscillator and Sub oscillator stopped
92
FME-MB96350 rev 7
MB96350 Series
Mode name
Details
RC Run 2M
RC Run mode current I
with the following settings:
CCRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = f = f = f = 2MHz
f
CLKS1
CLKS2
CLKB
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, Main oscillator and Sub oscillator stopped
RC Run 100k
RC Run mode current I
with the following settings:
CCRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = f = f = f = 100kHz
f
CLKS1
CLKS2
CLKB
CLKP1
CLKP2
•
•
Regulator in Low Power Mode A (SMCR:LPMS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, Main oscillator and Sub oscillator stopped
Sub Run
Sub Run mode current I
with the following settings:
CCSUB
•
f
= f
= f
= f
= f
= 32kHz
CLKP2
CLKS1
CLKS2
CLKB
CLKP1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, RC oscillator and Main oscillator stopped
PLL Sleep 56
PLL Sleep 48
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
f
f
= f
= f
= 56MHz
CLKP1
CLKS1
CLKS2
= 28MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
•
f
f
f
= f
= 96MHz
CLKS2
CLKS1
CLKP1
CLKP2
= 48MHz
= 24MHz
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
PLL Sleep 24
Main Sleep
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
f
f
= f
= f
= 48MHz
CLKS1
CLKS2
= 24MHz
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
RC oscillator and Sub oscillator stopped
Main Sleep mode current I
with the following settings:
CCSMAIN
•
f
= f
= f
= f
= 4MHz
CLKP2
CLKS1
CLKS2
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
PLL, RC oscillator and Sub oscillator stopped
FME-MB96350 rev 7
93
MB96350 Series
Mode name
Details
RC Sleep 2M
RC Sleep mode current I
with the following settings:
CCSRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = f = f = 2MHz
f
CLKS1
CLKS2
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
PLL, Main oscillator and Sub oscillator stopped
RC Sleep 100k RC Sleep mode current I
with the following settings:
CCSRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = f = f = 100kHz
f
CLKS1
CLKS2
CLKP1
CLKP2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
Sub Sleep
Sub Sleep mode current I
with the following settings:
CCSSUB
•
f
= f
= f
= f
= 32kHz
CLKP2
CLKS1
CLKS2
CLKP1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Main oscillator stopped
PLL Timer 48
Main Timer
RC Timer 2M
PLL Timer mode current I
with the following settings:
CCTPLL
•
f
= f
= 48MHz
CLKS2
CLKS1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
RC oscillator and Sub oscillator stopped
Main Timer mode current I
with the following settings:
CCTMAIN
•
f
= f
= 4MHz
CLKS2
CLKS1
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Sub oscillator stopped
RC Timer mode current I
with the following settings:
CCTRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = 2MHz
f
CLKS1
CLKS2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k RC Timer mode current I
with the following settings:
CCTRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = 100kHz
f
CLKS1
CLKS2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
Sub Timer
Sub Timer mode current I
with the following settings:
CCTSUB
•
f
= f
= 32kHz
CLKS2
CLKS1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Main oscillator stopped
94
FME-MB96350 rev 7
MB96350 Series
Mode name
Details
Stop 1.8V
Stop mode current I
with the following settings:
CCH
•
•
Regulator in Low Power Mode B (by hardware)
Core voltage at 1.8V (VRCR:LPMB[2:0] = 110 )
B
Stop 1.2V
Stop mode current I
with the following settings:
CCH
•
•
Regulator in Low Power Mode B (by hardware)
Core voltage at 1.2V (VRCR:LPMB[2:0] = 000 )
B
MB96F353/F355 PLL Run and Sleep mode currents
50
40
30
20
10
0
PLL Run 48
PLL Run 56
PLL Run 24
PLL Sleep 48
PLL Sleep 56
PLL Sleep 24
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96350 rev 7
95
MB96350 Series
MB96F353/F355 operation modes with medium currents
5
4
3
2
1
0
Main Run
RC Run 2M
PLL Timer 48
Main Sleep
RC Sleep 2M
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F353/F355 Low power mode currents
1
RC Run 100k
0.1
Sub Run
Main Timer
RC Timer 2M
RC Sleep 100k
Sub Sleep
Sub Timer
RC Timer 100k
0.01
Stop 1.8V
Stop 1.2V
0.001
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
96
FME-MB96350 rev 7
MB96350 Series
MB96F356 PLL Run and Sleep mode currents
50
40
30
20
10
0
PLL Run 48
PLL Run 56
PLL Run 24
PLL Sleep 48
PLL Sleep 56
PLL Sleep 24
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F356 operation modes with medium currents
5
4
3
2
1
0
Main Run
RC Run 2M
PLL Timer 48
Main Sleep
RC Sleep 2M
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96350 rev 7
97
MB96350 Series
MB96F356 Low power mode currents
1
RC Run 100k
0.1
Sub Run
Main Timer
RC Timer 2M
Sub Sleep
RC Sleep 100k
Sub Timer
RC Timer 100k
0.01
Stop 1.8V
Stop 1.2V
0.001
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
98
FME-MB96350 rev 7
MB96350 Series
2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL
Run mode at different frequencies and Flash timing settings.
Measurement conditions:
•
V
= AV = 5.0V
CC CC
•
•
Ta = 25˚C
f
f
f
f
= f
= f
= f
= f
or f
= 2*f
as described in diagram
CLKB
CLKS1
CLKS2
CLKP1
CLKP2
CLKB
CLKS1
•
•
•
•
CLKS1
CLKB
/2
CLKB
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 ) or 1.9V (VRCR:HPM[1:0] = 11 ) as described in diagram
B
B
•
•
Main clock = 4MHz external clock
Flash memory timing settings:
• MTCRA=2128 /2208 (0 Flash wait states, f
= 2*f
)
CLKB
H
H
CLKS1
• MTCRA=0239 /2129 (1 Flash wait state, f
= f
CLKB
)
H
H
CLKS1
• MTCRA=4C09 /6B09 (1 Flash wait state, f
= 2*f
)
CLKB
H
H
CLKS1
• MTCRA=233A (2 Flash wait states, f
= f
)
CLKB
H
CLKS1
•
Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash wait states: 0.5
• 1 Flash wait states: 0.33
• 2 Flash wait states: 0.25
MB96F353/F355 PLL Run mode currents
45
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
40
35
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
30
2 Flash wait states
(CLKS1=CLKB, 1.9V)
25
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
20
15
1 Flash wait state
(CLKS1=CLKB, 1.8V)
10
: Specified in "DC characteristics"
5
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
CLKB/CLKP1 (MHz)
FME-MB96350 rev 7
99
MB96350 Series
MB96F356 PLL Run mode currents
45
40
35
30
25
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.9V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
20
15
10
5
1 Flash wait state
(CLKS1=CLKB, 1.8V)
: Specified in "DC characteristics"
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
CLKB/CLKP1 (MHz)
100
FME-MB96350 rev 7
MB96350 Series
■ PACKAGE DIMENSION MB96(F)35x LQFP 64 - M23
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LFQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00
±
0.20(.551
±
.008)SQ
.004)SQ
*12.00
±
0.10(.472
±
0.145
±
0.055
(.0057
±
.0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 +0.20
–
0.10
.004
(Mounting height)
.059 +.008
–
0.25(.010)
INDEX
0~8˚
64
17
0.50
(.020
±
±
0.20
.008)
0.10
±
0.10
.004)
(.004
±
"A"
1
16
(Stand off)
0.60
±
0.15
(.024
±
.006)
0.65(.026)
0.32
(.013
±
±
0.05
.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
FME-MB96350 rev 7
101
MB96350 Series
■ PACKAGE DIMENSION MB96(F)35x LQFP 64 - M24
64-pin plastic LQFP
Lead pitch
0.50 mm
10.0 × 10.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32 g
Code
(Reference)
(FPT-64P-M24)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*
10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50±0.20
(.020±.008)
1
16
LEAD No.
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
2005 FUJITSU LIMITED F64036S-c-1-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
102
FME-MB96350 rev 7
MB96350 Series
■ ORDERING INFORMATION
MCU with CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F353RSB PMC-GSE2
MB96F353RWB PMC-GSE2
MB96F353RSB PMC1-GSE2
MB96F353RWB PMC1-GSE2
MB96F355RSB PMC-GSE2
MB96F355RWB PMC-GSE2
MB96F355RSB PMC1-GSE2
MB96F355RWB PMC1-GSE2
MB96F356YSB PMC-GSE2
MB96F356RSB PMC-GSE2
MB96F356YWB PMC-GSE2
MB96F356RWB PMC-GSE2
MB96F356YSB PMC1-GSE2
MB96F356RSB PMC1-GSE2
MB96F356YWB PMC1-GSE2
MB96F356RWB PMC1-GSE2
MB96V300BRB-ES
No
Yes
No
64 pins Plastic LQFP
(FPT-64P-M23)
Flash A (96KB)
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
No
No
64 pins Plastic LQFP
(FPT-64P-M23)
Yes
No
Flash A (160KB)
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
Yes
No
No
64 pins Plastic LQFP
(FPT-64P-M23)
Yes
Yes
No
Flash A (288KB)
Yes
No
No
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
Yes
No
416 pin Plastic BGA
(BGA-416P-M02)
Emulated by ext. RAM
Yes
No
(for evaluation)
FME-MB96350 rev 7
103
MB96350 Series
MCU without CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F353ASB PMC-GSE2
MB96F353AWB PMC-GSE2
MB96F353ASB PMC1-GSE2
MB96F353AWB PMC1-GSE2
MB96F355ASB PMC-GSE2
MB96F355AWB PMC-GSE2
MB96F355ASB PMC1-GSE2
MB96F355AWB PMC1-GSE2
MB96F356ASB PMC-GSE2
MB96F356AWB PMC-GSE2
MB96F356ASB PMC1-GSE2
MB96F356AWB PMC1-GSE2
No
Yes
No
64 pins Plastic LQFP
(FPT-64P-M23)
Flash A (96KB)
Flash A (160KB)
Flash A (288KB)
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
No
64 pins Plastic LQFP
(FPT-64P-M23)
Yes
No
No
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
No
64 pins Plastic LQFP
(FPT-64P-M23)
Yes
No
64 pins Plastic LQFP
(FPT-64P-M24)
Yes
This datasheet is also valid for the following outdated devices:
MB96F356YSA, MB96F356RSA, MB96F356YWA, MB96F356RWA, MB96F356ASA, MB96F356AWA,
MB96F353RSA, MB96F353RWA, MB96F355RSA, MB96F355RWA, MB96F353ASA, MB96F353AWA,
MB96F355ASA, MB96F355AWA.
104
FME-MB96350 rev 7
MB96350 Series
■ REVISION HISTORY
Revision
Date
Modification
Prelim 1
Prelim 2
Prelim 3
2007-05-03 Creation
2007-05-25 Electrical characteristics update
2007-11-27 Package description is removed from cover page.
Typos corrections in product lineup. Product option details added
Electrical characteristics update
Update of the block diagram
Update of the IO map
Pin circuit type, LVD characteristics and example characteristics chapters
added
Prelim 4
2007-12-20 Update of the block diagram: external bus address lines, clock output
function pins, AVRL removed from ADC block, relayout.
RAMSTART value is corrected
IO map regenerated
Memory map and Flash configuration reworked
Few typos corrected accross the document.
Flash bank renaming.
Ordering information: package type corrected.
IO circuit drawings modified.
Prelim 5
2008-02-04 • Reload Timer RLT 6 for PPGs added
• Block diagram corrected: ICU2 deleted, TTG2,3 deleted, TTG8,9 added
• Pin function description corrected with all existing pin types
• I/O circuit type diagrams corrected
• Memory map cleaned up
• "Flash sector configuration" replaced by corrected "User ROM Memory map
for Flash devices"
• Parallel Flash programming spec removed
• IO map table regenerated:
- Port register: Naming style corrected
- Memory control registers renamed (Main -> A)
- addresses after 000BFFh removed
• Handling devices: AD converter items added
• Absolute maximum ratings: Pd and Ta specified more precisely
• Run and Sleep mode currents: more conditions added (1WS settings)
• Run mode current spec in 48/24MHz mode corrected
• Maximum CLKS1 frequency corrected at 1.8V
• External bus timings: missing conditions added and readability improved
• Ordering information updated
• Typos and formatting corrected
FME-MB96350 rev 7
105
MB96350 Series
Revision
6
Date
Modification
2009-01-09 • Format adjusted to official Fujitsu Microelectronics datasheet standard
(mainly style changes and official notes and disclaimer added)
• Numbering of Electrical Characteristics subchapters automated
• CANless devices added (MB96F356A)
• I/O map: Added node about reserved registers
• Serial programming interface: Note about handshaking pins improved
• specified AD converter channel offset to 4LSB
• package code of MB96V300 corrected in ordering information
• Added voltage condition to pull-up resistance spec
• Ordering information: column “Flash/ROM” added, column “Remarks” re-
moved
• Official package dimension drawing with additional notes added
• Empty pages removed
• Handling devices: Notes added about Serial communication and about us-
ing ceramic resonators.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for
crystal oscillators. For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• MB96F353/F355 added (under development)
• Free running timer (I/O Timer) 2 and 3 added (without clock input pin)
• Input capture ICU9 and ICU10 added (without input pin, only for LIN USART)
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
• “Preliminary” watermark removed
106
FME-MB96350 rev 7
MB96350 Series
Revision
7
Date
Modification
2010-06-24 • AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above
105deg
• Low voltage detector: Detection levels of MB96F353/F355 updated
• Note added that PLL phase jitter spec does not include jitter coming from
Main clock
• Note added in DC characteristics how to select driving strength of ports
• I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and
Condition removed
• I/O Circuit type: Note added for type “N” (slew rate control according to I2C
spec)
• Example characteristics updated, new figures added showing dependency
of PLL Run mode current on frequency
• Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new
spec items in PLL Run/Sleep mode, small adjustment of most other values)
• Package dimension: Added the following sentence under the figure: “Please
confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/”
• AD converter: Impact of input pin capacitance and external capacitance
added to formula for calculation of the sampling time
• Added specification of RC clock stabilization time
• Ordering information updated: MB96F353/F355**A -> MB96F353/F355**B,
the device development is finished
• Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’
• Feature description PPG: ‘Reload timer overflow as clock input’ corrected
to ‘Reload timer underflow as clock input’
• ICCLVD specification updated, at 125deg typical value is 7uA and maximum
value is 20uA
• Companynameupdatedonthe coverpage:FujitsuMicroelectronicsLimited
-> Fujitsu Semiconductor Limited
FME-MB96350 rev 7
107
MB96350 Series
FME-MB96350 rev 7
MB96350 Series
FME-MB96350 rev 7
109
MB96350 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
110
FME-MB96350 rev 7
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