MB90F949_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13741-2E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90945 Series

MB90F946A/947A/F947/F947A/F949/F949A/

V390HA/V390HB

■ DESCRIPTION

The MB90945 series with one FULL-CAN* interface and FLASH ROM is especially designed for automotive HVAC

applications. Its main feature is the on board CAN* Interface, which conform to V2.0 Part A and Part B, while

supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN*

approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory

up to 384 K bytes. An internal voltage booster removes the necessity for a second programming voltage.

An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms

of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit features a 4-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate 16-bit

free running timers. Up to 3 UARTs, one Serial I/O and one I²C constitute additional functionality for communication

purposes.

* : Controller Area Network (CAN) - License of Robert Bosch GmbH

■ PACKAGE

100-pin Plastic QFP

(FPT-100P-M06)

MB90945 Series

■ FEATURES

• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time)

• New 0.35 µm CMOS Process Technology

• Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures

• One FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox

and FIFO buffering can be mixed)

• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)

• EI²OS - Automatic transfer function independant of CPU; 16 channels of intelligent I/O Services

• 18-bit Time-base counter

• Watchdog Timer

• 1 full duplex UART; support 10.4 KBaud (USA standard)

• up to 2 full duplex UARTs (LIN/SCI/SPI)

• 1 Serial I/O (SPI)

• 1 I²C interface

• A/D Converter : 15 channels analog inputs (Resolution 10-bit or 8-bit)

• 16-bit reload timer × 1channel

• ICU (Input capture) 16-bit × 6 channels

• OCU (Output compare) 16-bit × 4 channels

• 16-bit free running timer × 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5)

• 8/16-bit Programmable Pulse Generator 6 channels × 8/16-bit

• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different

addressing modes; barrel shift; variety of pointers)

• 4-byte instruction execution queue

• signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

• Program Patch Function (3 address match registers)

• Fast Interrupt processing

• Low Power Consumption mode

Sleep mode

Timebase timer mode

Stop mode

CPU intermittent mode

• Automotive input levels

• Package : 100-pin plastic QFP

2

MB90945 Series

■ PRODUCT LINEUP

Part Number

MB90F947, MB90F947A

MB90F949, MB90F949A

MB90V390HA

MB90V390HB

MB90947A

MB90F946A

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

System clock

ROM

Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL clock

multiplied by 6)

Boot-block

Flash memory

256 Kbytes: MB90F949

MB90F949A

128 Kbytes: MB90F947

MB90F947A

Boot-block

Flash memory

384 Kbytes

ROM memory

128 Kbytes

External

12 Kbytes: MB90F949

MB90F949A

6 Kbytes: MB90F947

MB90F947A

RAM

6 Kbytes

16 Kbytes

30 Kbytes

Yes

Emulator-specific

power supply^*1

⎯

0.35 µm CMOS with 0.35 µm CMOS with on-chip voltage regulator 0.35 µm CMOS with

on-chip voltage for internal power supply + Flash memory on-chip voltage

regulator for internal with on-chip charge pump for programming regulator for internal

power supply voltage power supply

Technology

3.5 V to 5.5 V : other than conditions listed below

4.0 V to 5.5 V : when writing to Flash

4.5 V to 5.5 V : if A/D Converter is used

Operating

voltage range

5 V 10%

Temperature range

Package

−40 °C to +105 °C

QFP-100P

⎯

PGA-299C

2 channels

1 channel

Full duplex double buffer

Supports asynchronous/synchronous (with start/stop bit) transfer

UART

Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock = 20 MHz

UART

(LIN/SCI/SPI)

1 channel

2 channels

1 channel

2 channels

1 channel

Transfer can be started from MSB or LSB

Serial I/O

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and negative-edge clock synchronization

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 20 MHz

I²C (400 Kbps)

1 channel

(Continued)

3

MB90945 Series

Part Number

MB90947A

Parameter

MB90F947, MB90F947A

MB90F949, MB90F949A

MB90V390HA

MB90V390HB

MB90F946A

10-bit or 8-bit resolution

A/D Converter

(15 input channels)

Conversion time : Min 4.9 µs includes sample time (per one channel, only at certain

machine clock frequencies)

1 channel

2 channels

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = System clock frequency)

Supports External Event Count function

16-bit Reload Timer

Signals an interrupt when overflowing

Supports Timer Clear when a match with Output Compare (ch0)

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = System clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5

16-bit

I/O Timer

(2 channels)

Rising edge, falling edge or rising & falling edge sensitive

Six 16-bit Capture registers

Signals an interrupt upon external event

16-bit

Input Capture

(6 channels)

ICU 3/5 inputs are

shared with OCU 6/7

outputs

⎯

4 channels

8 channels

Signals an interrupt when a match with 16-bit I/O Timer

Eight 16-bit compare registers.

A pair of compare registers can be used to generate an output signal.

16-bit

Output Compare

ICU 3/5 inputs are

shared with OCU 6/7

outputs

⎯

Supports 8-bit and 16-bit operation modes

Twelve 8-bit reload counters

8/16-bit

Twelve 8-bit reload registers for L pulse width

Twelve 8-bit reload registers for H pulse width

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler plus 8-bit reload counter

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 102.4 µs (fosc = 5 MHz)

(fsys = System clock frequency, fosc = Oscillation clock frequency)

Programmable

Pulse Generator

(6 channels)

1 channel

5 channels

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

CAN Interface

Flexible configuration of acceptance filtering :

Full-bit compare/Full-bit mask/Two partial bit masks

Supports up to 1 Mbps

MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time

(Continued)

4

MB90945 Series

Part Number

Parameter

MB90F947, MB90F947A

MB90F949, MB90F949A

MB90V390HA

MB90V390HB

MB90947A

MB90F946A

External Interrupt

(8 channels)

Can be programmed edge sensitive or level sensitive

Stepping motor

controller

⎯

2 channels

Watch Timer

⎯

1 channel

Sound generator

2 channels

(non-inverted and in-

verted)

Machine clock out-

put

⎯

Program patch

function

5 address match

registers

3 address match registers

Virtually all external pins can be used as general purpose I/O

All push-pull outputs

Bit-wise programmable as input/output or peripheral signal

I/O Ports

Port-wise program-

Automotive input level (P21/RX1, P42/SDA, P43/SCL have CMOS mable as Automotive

Schmitt input level)

(default) or CMOS

Schmitt input level

All ports except P80,

P81, PA0 to PA7,

P42, P43

I/O Ports with 4 mA

CMOS output

All ports except P42, P43

I/O Ports with 3 mA

CMOS output

P42, P43

I/O Ports with 30 mA

CMOS output with

slewrate control

P80, P81,

PA0 to PA7

⎯

Frequency and

Phase modulation mode phase

modulation mode

Phase modulation mode

Clock Modulator

MB90F947/F949/V390HA:

Do not use clock modulation and CAN at the

same time

Reduces EMI by modulating the PLL clock

2¹⁸oscillation cycles

(65.536 ms at 4 MHz

oscillation) +

oscillation time of os-

cillator*²

Start-up time at

power-on reset

3 × 2¹⁶oscillation cycles (49.152 ms at 4 MHz oscillation) + oscilla-

tion time of oscillator*²

(Continued)

5

MB90945 Series

(Continued)

Part Number

MB90947A

Parameter

MB90F947, MB90F947A

MB90F949, MB90F949A

MB90V390HA

MB90V390HB

MB90F946A

Supports automatic programming, Embedded

Algorithm^TM*³

Write/Erase/Erase-Suspend/Resume com-

mands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 20 years*⁴

Hard-wired reset vector available in order to

point to a fixed boot sector in Flash Memory

(address FFA000^H, mode data 00^H)

Boot block configuration

Flash

Memory

⎯

Erase can be performed on each block

Block protection with external programming

voltage

Write and erase at F^max= 20 MHz

*1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used.

Please refer to the Emulator hardware manual about details.

*2 : Oscillation time of the oscillator is the time that the amplitude reaches 90%.

*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

*4 : Data is based on reliability tests during process qualification (the value for T^A= + 85 °C is calculated via

the Arrenhius formula from data of accelerated measurements at elevated temperature) .

6

MB90945 Series

■ PIN ASSIGNMENTS

• MB90947A/F946A/F947/F947A/F949/F949A

(TOP VIEW)

P24/INT4

P25/INT5

P26/INT6

P27/INT7

P30

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P03/IN3

P02/IN2

P01/IN1

P00/IN0

P81

2

3

4

5

P31

6

P80

P32

7

PA7

P33

8

PA6

P34/SOT0

P35/SCK0

P36/SIN0

P37

9

PA5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PA4

PA3

PA2

P44

PA1

P45/ADTG

Vcc

PA0

Vss

Vcc

C

P96

P40

P92

P41

P91

P42/SDA

P43/SCL

P46/INT0

P47/INT1

P50/PPG10

PB0/PPG02/AN8

PB1/PPG03/AN9

PB2/PPG04/AN10

PB3/PPG05/AN11

PB4/SIN4/AN12

PB5/SCK4/AN13

P94/SCK3

P95/SOT3

P93/SIN3

P90

P57/PPG01

P56/PPG00

P55/PPG15

RST

MD0

MD1

MD2

(FPT-100P-M06)

7

MB90945 Series

• MB90V390HA/V390HB

(TOP VIEW)

P24/INT4

P25/INT5

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P03/IN3/OUT6

P02/IN2

2

P26/INT6

3

P01/IN1

P27/INT7

4

P00/IN0

P30/RX0

5

P81

P31/TX0

6

P80

P32/TIN1

7

PA7/PWM2M5

PA6/PWM2P5

PA5/PWM1M5

PA4PWM1P5

PA3/PWM2M4

PA2/PWM2P4

PA1/PWM1M4

PA0/PWM1P4

DVss

P33/TOT1

8

P34/SOT0

9

P35/SCK0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P36/SIN0

P37/SIN1

P44

P45/ADTG

Vcc

Vss

DVcc

C

P96/WOT

P92/SOT2

P91/SCK2

P94/SCK3

P95/SOT3

P93/SIN3

P90/SIN2

P57/PPG01/TX2

P56/PPG00/RX2

P55/PPG15

RST

P40/SCK1

P41/SOT1

P42/SDA

P43/SCL

P46/INT0

P47/INT1

P50/PPG10

PB0/PPG02/TX3/AN8

PB1/PPG03/RX3/AN9

PB2/PPG04/TX4/AN10

PB3/PPG05/RX4/AN11

PB4/SIN4/AN12

PB5/SCK4/AN13

MD0

MD1

MD2

(FPT-100P-M06)

As seen with QFP100 probe cable

8

MB90945 Series

■ PIN DESCRIPTION

Pin no.

92

Pin name

X1

Circuit type

Function

Pin for oscillation

Reset input

A

B

D

93

X0

54

RST

P00 to P05

IN0 to IN5

General purpose I/O

77 to 82

Inputs for the Input Captures 0-5

P06, P07

P10, P11

General purpose I/O

83 to 86

D

OUT0 to OUT3

P12, P13

P14

Outputs for the Output Compares

General purpose I/O

87, 88

89

D

General purpose I/O

TIN0

TIN0 input for the 16-bit Reload Timer 0

General purpose I/O

P15

94

95, 96

97

D

TOT0

P16, P17

P20

TOT0 output for the 16-bit Reload Timer 0

General purpose I/O

TX1

TX output for CAN Interface 1

General purpose I/O

P21

98

F

RX1

RX input for CAN Interface 1

General purpose I/O

P22 to P27

INT2 to INT7

P30 to P33

P34

99, 100

1 to 4

D

External interrupt inputs for INT2 to INT7

General purpose I/O

5 to 8

9

General purpose I/O

SOT0

P35

SOT output for UART0

General purpose I/O

10

11

D

SCK0

P36

SCK input/output for UART0

General purpose I/O

SIN0

SIN input for UART0

12

13

P37

D

General purpose I/O

P44

General purpose I/O

P45

General purpose I/O

14

18, 19

20

D

F

ADTG

P40, P41

P42

External trigger input of the A/D Converter

General purpose I/O

SDA

Serial data for I²C interface

(Continued)

9

MB90945 Series

Pin no.

Pin name

P43

Circuit type

Function

General purpose I/O

21

F

SCL

Serial clock for I²C interface

P46, P47

INT0, INT1

P50

General purpose I/O

22, 23

24

D

External interrupt inputs for INT0, INT1

General purpose I/O

PPG10

PB0 to PB3

Output for the PPG1

General purpose I/O

25 to 28 PPG02 to PPG05

E

Outputs for the PPG4, 6, 8, A

Inputs for the A/D Converter

General purpose I/O

AN8 to AN11

PB4

29

30

31

SIN4

AN12

SIN input for Serial I/O

Input for the A/D Converter

General purpose I/O

PB5

SCK4

SCK input/output for Serial I/O

Input for the A/D Converter

General purpose I/O

AN13

PB6

SOT4

SOT output for Serial I/O

Input for the A/D Converter

General purpose I/O

AN14

P60 to P67

AN0 to AN7

P51 to P54

PPG11 to PPG14

PB7

36 to 43

45 to 48

49

E

D

Inputs for the A/D Converter

General purpose I/O

Outputs for the PPG3, 5, 7, 9

General purpose I/O

FRCK0

P97

FRCK0 input for the 16-bit I/O Timer 0

General purpose I/O

50

FRCK1

P55

FRCK1 input for the 16-bit I/O Timer 1

General purpose I/O

55

PPG15

P56, P57

PPG00, PPG01

P90

Outputs for the PPGB

General purpose I/O

56, 57

Outputs for the PPG0, PPG2

General purpose I/O

58

59

D

SIN input for UART 2 (LIN/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

SIN2

P93

General purpose I/O

SIN3

SIN input for UART3 (LIN/SCI/SPI)

(Continued)

10

MB90945 Series

(Continued)

Pin no.

Pin name

P95

Circuit type

Function

General purpose I/O

60

61

D

SOT3

P94

SOT output for UART3 (LIN/SCI/SPI)

General purpose I/O

D

SCK3

P91

SCK input/output for UART3 (LIN/SCI/SPI)

General purpose I/O

62

63

SCK input/output for UART 2 (LIN/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

SCK2

P92

General purpose I/O

D

SOT output for UART 2 (LIN/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

SOT2

64

P96

D

H

General purpose I/O

General purpose I/O. For the EVA device, these pins are high

current outputs.

67 to 74

PA0 to PA7

General purpose I/O. For the EVA device, these pins are high

current outputs.

75, 76

P80, P81

H

32

33

34

35

AV^CC

AVRH

AVRL

AVss

⎯

Dedicated power supply pin (5 V) for the A/D converter

Dedicated pos. reference voltage pin for the A/D converter

Dedicated neg. reference voltage pin for the A/D converter

Dedicated power supply pin (0 V) for the A/D converter

These are input pins used to designate the operating mode. They

should be connected directly to V^CCor V^SS.

52, 53

51

MD1, MD0

MD2

C

G

This is an input pin used to designate the operating mode. It

should be connected directly to V^CCor V^SS.

15

65

90

These are power supply (5 V) input pins. For the EVA device, pin

65 is the DV^CCsupply pin for the high current outputs.

Vcc

⎯

16

44

66

91

These are power supply (0 V) input pins. For the EVA device, pin

66 is the DV^SSsupply pin for the high current outputs.

Vss

C

⎯

This is the power supply stabilization capacitor pin. It should be

connected to higher than or equal to 0.1 µF ceramic capacitor.

17

11

MB90945 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistor :

1 MΩ approx.

X1

Clock input

Pch

Nch

X0

A

Standby control signal

• CMOS Hysteresis input with pull-up

resistor :

50 kΩ approx.

VCC

R (pull-up)

R

B

C

CMOS Hysteresis

• EVA/ROM device :

CMOS Hysteresis input

• Flash device :

R

CMOS input.

• CMOS output (4 mA)

• Automotive Hysteresis input

V

CC

Pch

Nch

D

Automotive Hysteresis

R

(Continued)

12

MB90945 Series

(Continued)

Type

Circuit

Remarks

• CMOS output (4 mA)

• Automotive Hysteresis input

• Analog input

V

CC

Pch

Nch

E

Pch

Analog input

Nch

Automotive Hysteresis

R

• CMOS output

P42, P43 : 3mA

P21 : 4 mA

V

CC

Pch

• CMOS Hysteresis input

F

Nch

CMOS Hysteresis

R

• EVA/ROM device :

CMOS Hysteresis

CMOS Hysteresis input with pull-

down resistor : 50 kΩ approx.

• Flash device :

R

G

R (pull-down)

CMOS input without pull-down.

• EVA/ROM device :

CMOS high current output (30 mA)

with slewrate control

• Flash device :

V

CC

Pch

CMOS output (4 mA)

• Automotive Hysteresis input

H

Nch

Automotive Hysteresis

R

13

MB90945 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Stabilization of supply voltage

• Treatment of unused pins

• Using external clock

• Power supply pins (V^CC/V^SS)

• Pull-up/pull-down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter if A/D Converter is unused.

• Caution on Operations during PLL Clock Mode

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than V^CCor lower than V^SSis applied to an input or output pin.

• A voltage higher than the rated voltage is applied between V^CCand V^SS.

• The AV^CCpower supply is applied before the V^CCvoltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

In using the devices, take sufficient care to avoid exceeding maximum ratings.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

2. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the specified V^CCsupply

voltage operation range. Therefore, the V^CCsupply voltage should be stabilized.

For reference, the supply voltage should be controlled so that V^CCripple variations (peak-to-peak values) at

commercial frequencies (50 Hz to 60 Hz) fall below 10 % of the standard V^CCsupply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

3. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

4. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90945 Series

X0

X1

14

MB90945 Series

5. Power supply pins (V^CC/V^SS)

• If there are multiple V^CCand V^SSpins, from the point of view of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard for total output current, be sure to connect the V^CCand V^SSpins to the power supply

and ground externally.

• Connect V^CCand V^SSto the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

V^CCand V^SSin the vicinity of V^CCand V^SSpins of the device.

VCC

VSS

VCC

VSS

VCC

MB90945

Series

VCC

VSS

VCC

VSS

6. Pull-up/pull-down resistors

The MB90945 series does not support internal pull-up/pull-down resistors option. Use external components

where needed.

7. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits while you design

a printed circuit.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AV^CC, AVRH, AVRL) and analog inputs (AN0 to AN14)

after turning-on the digital power supply (V^CC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AV^CC(turning on/off the analog and digital power supplies simultaneously

is acceptable) .

9. Connection of Unused Pins of A/D Converter if A/D Converter is unused

Connect unused pins of A/D converter to AV^CC= V^CC, AV^SS= AVRH = AVRL = V^SS.

10. Notes on During Operation of PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

15

MB90945 Series

■ BLOCK DIAGRAMS

• MB90F946A

Clock

Controller

with Phase

Modulator

X0, X1

F²MC-16LX

CPU

RST

IO Timer 0

FRCK0

RAM

16 K bytes

Input

Capture

6 channels

IN5 to IN0

Flash

384 K bytes

Output

Compare

4 channels

OUT3 to OUT0

FRCK1

Prescaler

UART0

IO Timer 1

SOT0

SCK0

SIN0

8/16-bit

PPG

6 channels

PPG15 to PPG10

PPG05 to PPG00

Prescaler x2

RX1

TX1

CAN

Interface 1

SOT2/3

SCK2/3

SIN2/3

UART2/3

(LIN/SCI/

SPI)

External

Interrupt

INT7 to INT0

Prescaler

Serial I/O

SOT4

SCK4

SIN4

I²C

Interface

SDA

SCL

AVCC

16-bit

Reload Timer

1 channel

TIN0

AVSS

10-bit A/D

Converter

15 input

TOT0

AN [14:0]

AVRH

AVRL

ADTG

channel

16

MB90945 Series

• MB90947A

Clock

X0, X1

RST

F²MC-16LX

CPU

Controller

with Phase

Modulator

IO Timer 0

FRCK0

RAM

6 K bytes

Input

Capture

6 channels

IN5 to IN0

ROM

128 K bytes

Output

Compare

4 channels

OUT3 to OUT0

FRCK1

Prescaler

UART0

IO Timer 1

SOT0

SCK0

SIN0

8/16-bit

PPG

6 channels

PPG15 to PPG10

PPG05 to PPG00

Prescaler

RX1

TX1

CAN

Interface 1

SOT3

SCK3

SIN3

UART3

(LIN/SCI/

SPI)

External

Interrupt

INT7 to INT0

Prescaler

Serial I/O

SOT4

SCK4

SIN4

I²C

Interface

SDA

SCL

AVCC

16-bit

Reload Timer

1 channel

TIN0

AVSS

10-bit A/D

Converter

15 input

TOT0

AN [14:0]

AVRH

AVRL

ADTG

channel

17

MB90945 Series

• MB90F947, MB90F947A

Clock

Controller

with Phase

Modulator

X0, X1

F²MC-16LX

CPU

RST

IO Timer 0

FRCK0

RAM

6 K bytes

Input

Capture

6 channels

IN5 to IN0

Flash

128 K bytes

Output

Compare

4 channels

OUT3 to OUT0

FRCK1

Prescaler

UART0

IO Timer 1

SOT0

SCK0

SIN0

8/16-bit

PPG

6 channels

PPG15 to PPG10

PPG05 to PPG00

Prescaler

RX1

TX1

CAN

Interface 1

SOT3

SCK3

SIN3

UART3

(LIN/SCI/

SPI)

External

Interrupt

INT7 to INT0

Prescaler

Serial I/O

SOT4

SCK4

SIN4

I²C

Interface

SDA

SCL

AVCC

16-bit

Reload Timer

1 channel

TIN0

AVSS

10-bit A/D

Converter

15 input

TOT0

AN14 to AN0

AVRH

channel

AVRL

ADTG

18

MB90945 Series

• MB90F949, MB90F949A

Clock

X0, X1

RST

F²MC-16LX

CPU

Controller

with Phase

Modulator

IO Timer 0

FRCK0

RAM

12 K bytes

Input

Capture

6 channels

IN5 to IN0

Flash

256 K bytes

Output

Compare

4 channels

OUT3 to OUT0

FRCK1

Prescaler

UART0

IO Timer 1

SOT0

SCK0

SIN0

8/16-bit

PPG

6 channels

PPG15 to PPG10

PPG05 to PPG00

Prescaler

RX1

TX1

CAN

Interface 1

SOT3

SCK3

SIN3

UART3

(LIN/SCI/

SPI)

External

Interrupt

INT7 to INT0

Prescaler

Serial I/O

SOT4

SCK4

SIN4

I²C

Interface

SDA

SCL

AVCC

16-bit

Reload Timer

1 channel

TIN0

AVSS

10-bit A/D

Converter

15 input

TOT0

AN14 to AN0

AVRH

channel

AVRL

ADTG

19

MB90945 Series

■ MEMORY MAP

MB90F946A

MB90947A

MB90F947

MB90F947A

MB90F949

MB90F949A

MB90V390HA

MB90V390HB

FFFFFF^H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

FF0000^H

FEFFFF^H

FF0000^H

FEFFFF^H

FF0000^H

FEFFFF^H

FF0000^H

FEFFFF^H

FE0000^H

FDFFFF^H

FE0000^H

FDFFFF^H

FE0000^H

FDFFFF^H

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

FD0000^H

FCFFFF^H

FD0000^H

FCFFFF^H

FD0000^H

FC0000^H

FBFFFF^H

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

FB0000^H

FAFFFF^H

FB0000^H

FAFFFF^H

ROM (FA bank)

ROM (F9 bank)

FA0000^H

F9FFFF^H

FA0000^H

F9FFFF^H

F90000^H

8017FF^H

RAM 6 Kbytes

800000^H

00FFFF^H

008000^H

ROM (Image of

FF bank)

ROM (Image of

FF bank)

ROM (Image of

FF bank)

ROM (Image of

FF bank)

004000^H/

008000^H

004000^H/

008000^H

0070FF^H

RAM 12 Kbytes

Peripheral

0050FF^H

004100^H

003FFF^H

RAM 4 Kbytes

Peripheral

004100^H

003FFF^H

003500^H

Peripheral

003500^H

0030FF^H

003500^H

0030FF^H

003500^H

0030FF^H

RAM 12 Kbytes

Peripheral

RAM 12 Kbytes

Peripheral

0018FF^H

000100^H

RAM 12 Kbytes

Peripheral

RAM 6 Kbytes

Peripheral

000100^H

0000BF^H

000000^H

0000BF^H

000000^H

0000BF^H

000000^H

0000BF^H

000000^H

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000^Haccesses the value at FFC000^Hin ROM.

The ROM area in bank FF exceeds 32/48 K bytes, and its entire image cannot be shown in bank 00.

The image between FF4000^H/FF8000^Hand FFFFFF^His visible in bank 00, while the image between FF0000^H

and FF3FFF^H/FF7FFF^His visible only in bank FF.

20

MB90945 Series

■ I/O MAP

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

00^H

01^H

02^H

03^H

04^H

05^H

06^H

07^H

08^H

09^H

0A^H

0B^H

0C^H

0D^H

Port 0 data register

Port 1 data register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

Reserved

PDR8

PDR9

PDRA

PDRB

ADER0

ADER1

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

XXXXXXXX

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 8 data register

R/W

Port 8

Port 9

XXXXXXXX

11111111

Port 9 data register

Port A data register

Port A

Port B data register

Port B

Analog Input Enable 0

Analog Input Enable 1/ ADC Select

Port 6, A/D

Port B, A/D

01111111

Input Level Select Register

(MB90V390HA/MB90V390HB only)

0E^H

0F^H

ILSR

R/W

Ports

00000000

Input Level Select Register

(MB90V390HA/MB90V390HB only)

10^H

11^H

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

Reserved

DDR8

DDR9

DDRA

DDRB

Reserved

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

00000000

12^H

13^H

14^H

15^H

16^H

17^H

18^H

Port 8 direction register

Port 9 direction register

Port A direction register

Port B direction register

R/W

Port 8

Port 9

Port A

Port B

XXXXXX00

00000000

19^H

1A^H

1B^H

1C^Hto 1F^H

(Continued)

21

MB90945 Series

Abbrevia-

tion

Address

Register

Serial Mode Control 0

Access

Resource name

Initial value

20^H

21^H

UMC0

USR0

R/W

00000100

00010000

Status 0

UART0

UIDR0/

UODR0

22^H

Input/Output Data 0

Rate and Data 0

R/W

XXXXXXXX

0000000X

23^H

24^Hto 2B^H

2C^H

2D^H

2E^H

2F^H

30^H

URD0

Reserved

SMCS4

SDR4

Serial Mode Control 4

R/W

R

XXXX0000

00000010

XXXXXXXX

0 X 0 X 0000

00000000

XXXXXXXX

00000000

XXXXXXXX

000000XX

0X000XX1

0X000001

000000XX

Serial Mode Control 4

Serial I/O

Interface

Serial Data 4

Serial I/O Prescaler/Edge Selector 4

External Interrupt Enable

External Interrupt Request

External Interrupt Level

A/D Control Status 0

CDCR4

ENIR

31^H

EIRR

External Interrupt

A/D Converter

32^H

ELVR

33^H

ELVR

34^H

ADCS0

ADCS1

ADCR0

ADCR1

PPGC0

PPGC1

PPG01

Reserved

PPGC2

PPGC3

PPG23

Reserved

PPGC4

PPGC5

PPG45

Reserved

PPGC6

PPGC7

PPG67

Reserved

35^H

A/D Control Status 1

36^H

A/D Data 0

37^H

A/D Data 1

R/W

38^H

PPG0 operation mode control register

PPG1 operation mode control register

PPG0 and PPG1 clock select register

16-bit Programable

Pulse

39^H

Generator 0/1

3A^H

3B^H

3C^H

3D^H

3E^H

3F^H

40^H

PPG2 operation mode control register

PPG3 operation mode control register

PPG2 and PPG3 clock select register

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator 2/3

PPG4 operation mode control register

PPG5 operation mode control register

PPG4 and PPG5 clock select register

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

41^H

Generator 4/5

42^H

43^H

44^H

PPG6 operation mode control register

PPG7 operation mode control register

PPG6 and PPG7 clock select register

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

45^H

Generator 6/7

46^H

47^H

(Continued)

22

MB90945 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

48^H

49^H

PPG8 operation mode control register

PPG9 operation mode control register

PPG8 and PPG9 clock select register

PPGC8

PPGC9

PPG89

Reserved

PPGCA

PPGCB

PPGAB

Reserved

TMCSR0

Reserved

ICS01

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator 8/9

4A^H

4B^H

4C^H

4D^H

4E^H

4F^H

PPGA operation mode control register

PPGB operation mode control register

PPGA and PPGB clock select register

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator A/B

50^H

Timer Control Status 0

R/W

00000000

16-bit Reload Timer

0

51^H

XXXX0000

52^Hto 53^H

54^H

Input Capture Control Status 0/1

Input Capture Control Status 2/3

Input Capture Control Status 4/5

R/W

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

00000000

55^H

ICS23

56^H

ICS45

57^H

Reserved

OCS0

58^H

Output Compare Control Status 0

Output Compare Control Status 1

Output Compare Control Status 2

Output Compare Control Status 3

R/W

0000XX00

0XX00000

0000XX00

0XX00000

Output Compare 0/1

Output Compare 2/3

59^H

OCS1

5A^H

5B^H

OCS2

OCS3

5C^Hto

6E^H

Reserved

6F^H

ROM Mirror

ROMM

W

ROM Mirror

XXXXXXX1

70^Hto 7F^H

Reserved

80^Hto 8F^HReserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”

90^Hto 9D^H

9E^H

Reserved

PACSR0

DIRR

ROM Correction Control Status 0

Delayed Interrupt/release

R/W

ROM Correction 0

Delayed Interrupt

00000000

9F^H

XXXXXXX0

Low Power

Controller

A0^H

A1^H

Low-power Mode

Clock Selector

LPMCR

CKSCR

R/W

00011000

11111100

Low Power

Controller

A2^Hto A7^H

A8^H

Reserved

WDTC

Watchdog Control

R/W

Watchdog Timer

Timebase timer

XXXXX111

1XX00100

A9^H

Timebase timer Control

TBTC

AA^Hto

AD^H

Reserved

(Continued)

23

MB90945 Series

Abbrevia-

tion

Address

Register

Flash Control Status

Access

Resource name

Initial value

AE^H

FMCS

R/W

Flash memory

000X0000

(Flash devices only. Otherwise reserved)

AF^H

B0^H

B1^H

B2^H

B3^H

B4^H

B5^H

B6^H

B7^H

B8^H

B9^H

BA^H

BB^H

BC^H

BD^H

BE^H

BF^H

Reserved

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W

00000111

Interrupt controller

C0^Hto

FF^H

Reserved

(Continued)

24

MB90945 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3500^H

3501^H

3502^H

3503^H

3504^H

3505^H

3506^H

3507^H

3508^H

3509^H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

SMR3

R/W

XXXXXXXX

00000000

16-bit Programable

Pulse

Generator 0/1

16-bit Programable

Pulse

Generator 2/3

16-bit Programable

Pulse

350A^HReload L

350B^HReload H

350C^HReload L

350D^HReload H

350E^HReload L

350F^HReload H

Generator 4/5

16-bit Programable

Pulse

Generator 6/7

3510^H

3511^H

3512^H

3513^H

3514^H

3515^H

3516^H

3517^H

3518^H

3519^H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

16-bit Programable

Pulse

Generator 8/9

16-bit Programable

Pulse

Generator A/B

Serial Mode Register

Serial Control Register

SCR3

00000000

RDR3/

TDR3

351A^HReception/Transmission Data Register

R/W

00000000

351B^HSerial Status Register

SSR3

ECCR3

ESCR3

BGR03

BGR13

R/W

00001000

000000XX

00000100

00000000

UART3

351C^HExtended Communication Control Reg.

351D^HExtended Status/Control Register

351E^HBaud Rate Register 0

351F^HBaud Rate Register 1

00000000

(Continued)

25

MB90945 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3520^H

3521^H

3522^H

3523^H

3524^H

3525^H

3526^H

3527^H

3528^H

3529^H

Input Capture 0

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

IPCP0

IPCP1

IPCP2

IPCP3

IPCP4

IPCP5

TCDT0

TCCS0

OCCP0

OCCP1

OCCP2

OCCP3

R

XXXXXXXX

00000000

Input Capture 0/1

R

Input Capture 2/3

Input Capture 4/5

I/O Timer 0

R

352A^HInput Capture 5

352B^HInput Capture 5

352C^HTimer Data 0

352D^HTimer Data 0

352E^HTimer Control 0

352F^HTimer Control 0

R

R/W

00000000

0XXXXXXX

XXXXXXXX

3530^H

3531^H

3532^H

3533^H

3534^H

3535^H

3536^H

3537^H

Output Compare 0

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 0/1

Output Compare 2/3

3538^Hto

353B^H

Reserved

353C^HTimer Data 1

353D^HTimer Data 1

353E^HTimer Control 1

353F^HTimer Control 1

TCDT1

TCCS1

R/W

00000000

0XXXXXXX

I/O Timer 1

TMR0/

TMRLR0

3540^H

3541^H

Timer 0/Reload 0

R/W

XXXXXXXX

16-bit Reload

Timer 0

TMR0/

TMRLR0

3542^Hto

356D^H

Reserved

(Continued)

26

MB90945 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

356E^HCAN Direct Mode Register

CDMR

R/W

CAN clock sync

XXXXXXX0

356F^Hto

359F^H

Reserved

35A0^HI²C bus status register

35A1^HI²C bus control register

IBSR

IBCR

R

00000000

11111111

00111111

00000000

01111111

00000000

R/W

35A2^H

ITBAL

ITBAH

ITMKL

ITMKH

ISBA

I²C ten bit slave address register

35A3^H

35A4^H

I²C Interface

I²C ten bit address mask register

35A5^H

35A6^HI²C seven bit slave address register

35A7^HI²C seven bit address mask register

35A8^HI²C data register

ISMK

IDAR

35A9^Hto

35AA^H

Reserved

ICCR

35AB^HI²C clock control register

R/W

I²C Interface

00011111

35AC^Hto

35C8^H

Reserved

35C9^HInput Capture Edge 0/1

35CA^HInput Capture Edge 2/3

35CB^HInput Capture Edge 4/5

ICE01

ICE23

ICE45

R/W

R

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

XXXXX0XX

XXXXXXXX

XXXXX0XX

R/W

35CC^Hto

35CE^H

Reserved

PSCCR

PLL and Special Configuration Control

Register

35CF^H

W

PLL

XXXX0000

35D0^Hto

35D7^H

Reserved

35D8^HSerial Mode Register

35D9^HSerial Control Register

SMR2

SCR2

R/W

00000000

RDR2/

TDR2

UART2

35DA^HReception/Transmission Data Register

R/W

00000000

(MB90V390HA,

MB90V390HB and

MB90F946A only)

35DB^HSerial Status Register

SSR2

ECCR2

ESCR2

BGR02

R/W

00001000

000000XX

00000100

00000000

35DC^HExtended Communication Control Reg.

35DD^HExtended Status/Control Register

35DE^HBaud Rate Register 0

UART2

(MB90V390HA,

MB90V390HB and

MB90F946A only)

35DF^HBaud Rate Register 1

BGR12

R/W

00000000

27

MB90945 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

35E0^HROM Correction Address 0

35E1^HROM Correction Address 0

35E2^HROM Correction Address 0

35E3^HROM Correction Address 1

35E4^HROM Correction Address 1

35E5^HROM Correction Address 1

PADR0

PADR1

R/W

XXXXXXXX

Address Matching

Detection Function 0

XXXXXXXX

(Continued)

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

35E6^HROM Correction Address 2

35E7^HROM Correction Address 2

35E8^HROM Correction Address 2

PADR2

R/W

XXXXXXXX

Address Matching

Detection Function 0

35E9^Hto

37FF^H

Reserved

3800^Hto

38FF^H

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”

Reserved

3900^Hto

39FF^H

3A00^Hto

3FFF^H

_ : Unused bit

X : Unknown value

Note : Any write access to reserved addresses in I/O map should not be performed.

A read access to reserved address results in reading “X”.

28

MB90945 Series

■ CAN CONTROLLER

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each

message buffer as ID acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)

List of Control Registers (1)

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN1

000080^H

000081^H

000082^H

000083^H

000084^H

000085^H

000086^H

000087^H

000088^H

000089^H

00008A^H

00008B^H

00008C^H

00008D^H

00008E^H

00008F^H

Message buffer

valid register

00000000

Transmit request

register

00000000

Transmit cancel

register

00000000

Transmit

complete register

00000000

R/W

00000000

Receive complete register

RCR

Remote request receiving

register

00000000

RRTRR

ROVRR

RIER

Receive overrun

register

00000000

Receive interrupt enable

register

00000000

29

MB90945 Series

List of Control Registers (2)

Abbreviation

Address

Register

Access

R/W, R

R/W

Initial Value

CAN1

003900^H

003901^H

003902^H

003903^H

003904^H

003905^H

003906^H

003907^H

003908^H

003909^H

00390A^H

00390B^H

00390C^H

Control status

register

00XXX000

0XXXX0X1

CSR

LEIR

Last event

XXXXXXXX

000X0000

indicator register

Receive/transmit

error counter

00000000

RTEC

BTR

R

Bit timing

register

X1111111

11111111

R/W

XXXXXXXX

IDE register

IDER

TRTRR

R/W

Transmit RTR

register

00000000

R/W

Remote frame

receive waiting

register

XXXXXXXX

RFWTR

TIER

R/W

00390D^H

00390E^H

00390F^H

003910^H

003911^H

003912^H

003913^H

003914^H

003915^H

003916^H

003917^H

003918^H

003919^H

00391A^H

00391B^H

Transmit

00000000

interrupt enable register

XXXXXXXX

Acceptance mask select

register

AMSR

AMR0

AMR1

R/W

XXXXXXXX

Acceptance mask register 0

Acceptance mask register 1

XXXXXXXX

30

MB90945 Series

List of Message Buffers (ID Registers) (1)

Address

CAN1

Register

Abbreviation

Access

Initial Value

003800^H

to

00381F^H

XXXXXXXX

to

XXXXXXXX

General-

purpose RAM

⎯

R/W

003820^H

003821^H

003822^H

003823^H

003824^H

003825^H

003826^H

003827^H

003828^H

003829^H

00382A^H

00382B^H

00382C^H

00382D^H

00382E^H

00382F^H

003830^H

003831^H

003832^H

003833^H

003834^H

003835^H

003836^H

003837^H

003838^H

003839^H

00383A^H

00383B^H

00383C^H

00383D^H

00383E^H

00383F^H

XXXXXXXX

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

XXXXXXXX

R/W

XXXXXXXX

31

MB90945 Series

List of Message Buffers (ID Registers) (2)

Address

Register

Abbreviation

Access

Initial Value

CAN1

003840^H

003841^H

003842^H

003843^H

003844^H

003845^H

003846^H

003847^H

003848^H

003849^H

00384A^H

00384B^H

00384C^H

00384D^H

00384E^H

00384F^H

003850^H

003851^H

003852^H

003853^H

003854^H

003855^H

003856^H

003857^H

003858^H

003859^H

00385A^H

00385B^H

00385C^H

00385D^H

00385E^H

00385F^H

XXXXXXXX

ID register 8

IDR8

R/W

XXXXXXXX

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

XXXXXXXX

32

MB90945 Series

List of Message Buffers (DLC Registers and Data Registers) (1)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX

003860^H

003861^H

003862^H

003863^H

003864^H

003865^H

003866^H

003867^H

003868^H

003869^H

00386A^H

00386B^H

00386C^H

00386D^H

00386E^H

00386F^H

003870^H

003871^H

003872^H

003873^H

003874^H

003875^H

003876^H

003877^H

003878^H

003879^H

00387A^H

00387B^H

00387C^H

00387D^H

00387E^H

00387F^H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

33

MB90945 Series

List of Message Buffers (DLC Registers and Data Registers) (2)

Address

CAN1

Register

Abbreviation

Access

Initial Value

003880^H

to

XXXXXXXX

to

Data register 0 (8 bytes)

DTR0

R/W

003887^H

XXXXXXXX

003888^H

to

00388F^H

XXXXXXXX

to

XXXXXXXX

Data register 1 (8 bytes)

Data register 2 (8 bytes)

Data register 3 (8 bytes)

Data register 4 (8 bytes)

Data register 5 (8 bytes)

Data register 6 (8 bytes)

Data register 7 (8 bytes)

Data register 8 (8 bytes)

Data register 9 (8 bytes)

Data register 10 (8 bytes)

Data register 11 (8 bytes)

Data register 12 (8 bytes)

Data register 13 (8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

003890^H

to

003897^H

XXXXXXXX

to

XXXXXXXX

003898^H

to

00389F^H

XXXXXXXX

to

XXXXXXXX

0038A0^H

to

0038A7^H

XXXXXXXX

to

XXXXXXXX

0038A8^H

to

0038AF^H

XXXXXXXX

to

XXXXXXXX

0038B0^H

to

0038B7^H

XXXXXXXX

to

XXXXXXXX

0038B8^H

to

0038BF^H

XXXXXXXX

to

XXXXXXXX

0038C0^H

to

0038C7^H

XXXXXXXX

to

XXXXXXXX

0038C8^H

to

0038CF^H

XXXXXXXX

to

XXXXXXXX

0038D0^H

to

0038D7^H

XXXXXXXX

to

XXXXXXXX

0038D8^H

to

0038DF^H

XXXXXXXX

to

XXXXXXXX

0038E0^H

to

0038E7^H

XXXXXXXX

to

XXXXXXXX

0038E8^H

to

XXXXXXXX

to

0038EF^H

XXXXXXXX

34

MB90945 Series

List of Message Buffers (DLC Registers and Data Registers) (3)

Address

CAN1

Register

Abbreviation

Access

Initial Value

0038F0^H

to

XXXXXXXX

to

Data register 14 (8 bytes)

DTR14

R/W

0038F7^H

XXXXXXXX

0038F8^H

to

XXXXXXXX

to

Data register 15 (8 bytes)

DTR15

R/W

0038FF^H

XXXXXXXX

35

MB90945 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

Interrupt vector

Number Address

EI²OS

clear

register

Interrupt cause

Number

Address

Reset

N/A

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0^H

FFFFCC^H

FFFFC8^H

FFFFC4^H

FFFFC0^H

FFFFBC^H

FFFFB8^H

FFFFB4^H

FFFFB0^H

FFFFAC^H

FFFFA8^H

FFFFA4^H

FFFFA0^H

FFFF9C^H

FFFF98^H

FFFF94^H

FFFF90^H

FFFF8C^H

FFFF88^H

FFFF84^H

FFFF80^H

FFFF7C^H

FFFF78^H

FFFF74^H

FFFF70^H

FFFF6C^H

FFFF68^H

FFFF64^H

⎯

INT9 instruction

Exception

Timebase timer

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0^H

0000B1^H

0000B2^H

0000B3^H

0000B4^H

0000B5^H

0000B6^H

0000B7^H

0000B8^H

0000B9^H

0000BA^H

0000BB^H

0000BC^H

External Interrupt INT0 to INT7

Reserved

CAN 1 RX

N/A

CAN 1 TX/NS

PPG 0/1

PPG 2/3

PPG 4/5

PPG 6/7

PPG 8/9

PPG A/B

16-bit Reload Timer 0

Reserved

Input Capture 0/1

Output compare 0/1

Input Capture 2/3

Output Compare 2/3

Input Capture 4/5

I²C

A/D Converter

I/O Timer 0 / I/O Timer 1

Serial I/O

N/A

Reserved

UART 0 RX

UART 0 TX

Reserved

0000BD^H

Reserved

(Continued)

36

MB90945 Series

(Continued)

Interrupt control

Interrupt vector

EI²OS

clear

register

Interrupt cause

Number

#39

Address

FFFF60^H

FFFF5C^H

FFFF58^H

FFFF54^H

Number

Address

UART 2 RX / UART 3 RX

UART 2 TX / UART 3 TX

Flash memory

ICR14

ICR15

0000BE^H

#40

N/A

#41

0000BF^H

Delayed interrupt

#42

: The interrupt request flag is cleared by the EI²OS interrupt clear signal.

: The interrupt request flag is cleared by the EI²OS interrupt clear signal. A stop request is available.

: Unavailable

N/A : The interrupt request flag is not cleared by the EI²OS interrupt clear signal.

Notes : • For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request

flags are cleared by the EI²OS interrupt clear signal.

• At the end of EI²OS, the EI²OS clear signal will be asserted for all the interrupt flags assigned to the same

interrupt number. If one interrupt flag starts the EI²OS and in the meantime another interrupt flag is set

by hardware event, the later event is lost because the flag is cleared by the EI²OS clear signal caused

by the first event. So it is recommended not to use the EI²OS for this interrupt number.

• If EI²OS is enabled, EI²OS is initiated when one of the two interrupt signals in the same interrupt control

register (ICR) is asserted. This means that different interrupt sources share the same EI²OS Descriptor

which should be unique for each interrupt source. For this reason, when one interrupt source uses the

EI²OS, the other interrupt should be disabled.

37

MB90945 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

V^SS− 0.3 V^SS+ 6.0

V

AV^CC

V^CC= AV^CC*²

Power supply voltage*¹

AVRH,

AVRL

AV^CC≥ AVRH, AV^CC≥ AVRL,

AVRH ≥ AVRL

V^SS− 0.3 V^SS+ 6.0

V

Input voltage*¹

Output voltage*¹

V^I

V^O

V^SS− 0.3 V^SS+ 6.0

V

*3

Maximum Clamp Current

I^CLAMP

Σ|I^CLAMP|

I^OL1

−4.0

⎯

+4.0

40

mA *5

mA *4

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

15

I^OLAV1

ΣI^OL1

ΣI^OLAV1

I^OH1

4

100

50

−15

−4

I^OHAV1

ΣI^OH1

ΣI^OHAV

−100

−50

MB90947A/F947/F947A/F949/

F949A

⎯

500

Power consumption

P^D

mW

⎯

525

+105

+150

MB90F946A

Operating temperature

Storage temperature

T^A

−40

−55

°C

T^STG

*1 : This parameter is based on V^SS= AV^SS= 0 V.

*2 : Set AV^CCand V^CCto the same voltage. Make sure that AV^CCdoes not exceed V^CCand that the voltage at the

analog inputs does not exceed AV^CCwhen the power is switched on.

*3 : V^Iand V^Oshould not exceed V^CC+ 0.3 V. V^Ishould not exceed the specified ratings. However if the maximum

current to/from a input is limited by some means with external components, the I^CLAMPrating supercedes the

V^Irating.

*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7

*5 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

38

MB90945 Series

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits :

• Input/output equivalent circuits

Protective diode

V^CC

Limiting

Pch

resistance

+B input (0 V to 16 V)

Nch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

39

MB90945 Series

2. Recommended Conditions

(V^SS= AV^SS= 0 V)

Remarks

Value

Typ

Parameter

Symbol

Unit

Min

Max

Other than when writing to Flash

memory and when using the A/D

converter

3.5

5.0

5.5

V

V^CC,

AV^CC

Power supply voltage

4.0

4.5

2.0

0.1

−40

5.0

⎯

5.5

V

When writing to Flash memory

When using the A/D converter

Retain RAM data in stop mode

*

5.5

V

Smoothing capacitor

C^S

T^A

⎯

1.0

µF

°C

Operating temperature

⎯

+105

* : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the V^CCpin, use a bypass

capacitor that has a larger capacity than that of C^S. Refer to the following figure for connection of smoothing

capacitor C^S.

• C Pin Connection Diagram

C

CS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

40

MB90945 Series

3. DC Characteristics

(T^A= −40 °C to +105 °C, V^CC= 5.0 V 10%, V^SS= AV^SS= 0 V)

Value

Sym-

Parameter

bol

Condition

Unit

Remarks

Min

Typ

Max

Port inputs except

ports P21/RX1,

P42/SDA, P43/SCL

V^IHA

⎯

0.8 V^CC

⎯

V^CC+ 0.3

V

Port inputs P21/

RX1, P42/SDA,

P43/SCL

Input “H”

V^IHS

⎯

0.7 V^CC

⎯

V^CC+ 0.3

V

voltage

RST input pin

(CMOS Hysteresis)

V^IHR

V^IHM

⎯

0.8 V^CC

⎯

V^CC+ 0.3

V

V^CC− 0.3

MD input pin

Port inputs except

ports P21/RX1,

P42/SDA, P43/SCL

V^ILA

⎯

V^SS− 0.3

⎯

0.5 V^CC

0.3 V^CC

V

Port inputs P21/

RX1, P42/SDA,

P43/SCL

Input “L”

V^ILS

voltage

RST input pin

(CMOS Hysteresis)

V^ILR

V^ILM

⎯

V^SS− 0.3

V^CC− 0.5

⎯

0.2 V^CC

V^SS+ 0.3

⎯

V

MD input pin

Output “H”

voltage

Normal

outputs

V^CC= 4.5 V,

I^OH1= −4.0 mA

V^OH

V^OHI

V^OL

V^OLI

I^IL

Output “H”

voltage

I²C

V^CC= 4.5 V,

I^OH1= −3.0 mA

V^CC− 0.5

⎯

0.4

1

V

outputs

Output “L”

voltage

Normal

outputs

V^CC= 4.5 V,

I^OL1= 4.0 mA

⎯

−1

Output “L”

voltage

I²C

V^CC= 4.5 V,

I^OL1= 3.0 mA

V

outputs

Input leak

current

V^CC= 5.5 V,

V^SS< V^I< V^CC

⎯

µA

(Continued)

41

MB90945 Series

(Continued)

(T^A= −40 °C to +105 °C, V^CC= 5.0 V 10%, V^SS= AV^SS= 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Pull-down

resistance

only ROM

devices

R^DOWN

MD2

⎯

25

50

100 kOhm

MB90947A

mA MB90F947/A

MB90F949/A

V^CC= 5.0 V,

Internal frequency :

24 MHz,

⎯

60

65

50

75

85

65

At normal operation.

mA MB90F946A

MB90947A

mA MB90F947/A

MB90F949/A

V^CC= 5.0 V,

Internal frequency :

20 MHz,

At normal operation.

⎯

55

65

75

80

mA MB90F946A

I^CC

V^CC= 5.0 V,

Internal frequency :

20 MHz,

MB90F947/A

mA

MB90F949/A

⎯

70

75

90

85

95

mA MB90F946A

At writing FLASH memory.

V^CC= 5.0 V,

Internal frequency :

20 MHz,

MB90F947/A

mA

MB90F949/A

mA MB90F946A

At erasing FLASH memory.

Power supply

current*

V^CC

MB90947A

mA MB90F947/A

MB90F949/A

V^CC= 5.0 V,

Internal frequency :

24 MHz,

⎯

25

28

35

40

I^CCS

At Sleep mode.

mA MB90F946A

MB90947A

V^CC= 5.0 V,

Internal frequency :

2 MHz,

MB90F946A

MB90F947/A

I^CTS

⎯

0.3

5

0.6

7

mA

At Main Timebase timer mode

MB90F949/A

V^CC= 5.0 V,

Internal frequency :

24 MHz,

At PLL Timebase timer mode,

external frequency = 4 MHz

MB90947A

MB90F946A

mA

I^CTSPLL6

MB90F947/A

MB90F949/A

MB90947A

V^CC= 5.0 V,

At Stop mode,

TA = +25°C

MB90F946A

µA

I^CCH

5

100

MB90F947/A

MB90F949/A

OtherthanC,

AV^CC, AV^SS,

AVRH,

Input capacity

CIN

⎯

5

15

pF

AVRL, V^CC,

V^SS

* : The power supply current is measured with an external clock.

42

MB90945 Series

4. AC Characteristics

(1) Clock Timing

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5 V, V^SS= AV^SS= 0 V)

Value

Sym-

bol

Parameter

Max

CS2 = 0 CS2 = 1

Unit

Remarks

Min Typ

× 1/2 (When PLL stops)

When using an oscillation circuit

3

⎯

8

MHz

4

⎯

8

⎯

8

MHz PLL × 1 When using an oscillation circuit

MHz PLL × 2 When using an oscillation circuit

MHz PLL × 3 When using an oscillation circuit

MHz PLL × 4 When using an oscillation circuit

MHz PLL × 6 When using an oscillation circuit

X0, X1

6.67

5

⎯

6

⎯

4

Clock

frequency

f^C

× 1/2 (When PLL stops)

3

⎯

12

MHz

When using an external circuit

4

⎯

12

10

⎯

12

⎯

6

MHz PLL × 1 When using an external circuit

MHz PLL × 2 When using an external circuit

MHz PLL × 3 When using an external circuit

MHz PLL × 4 When using an external circuit

MHz PLL × 6 When using an external circuit

ns When using an oscillation circuit

X0

6.67

5

⎯

4

X0, X1 125

X0, X1 83.33

333

Clock

cycle time

t^CYL

ns When using an external clock

Input clock

pulse width

P^WH,

P^WL

X0

20

⎯

ns Duty ratio is about 30% to 70%.

Input clock

rise and fall

time

t^CR,

t^CF

X0

⎯

5

ns When using external clock

1.5

24

20

MHz Except programming or erasing Flash memory.

Machine clock

frequency

When programming or erasing Flash memory.

MHz Be sure that the maximum momentary

frequency F^maxdoes not exceed 20MHz.

fCP

⎯

41.67

50

⎯

666

ns Except programming or erasing Flash memory.

ns When programming or erasing Flash memory.

Machine clock

cycle time

t^CP

• Clock Timing

t

CYL

0.8 VCC

0.2 VCC

X0

P

WH

PWL

t

CF

tCR

43

MB90945 Series

• Guaranteed PLL operation range

Guaranteed operation range

Guaranteed PLL operation range (CS2=1)

5.5

4.5

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range (CS2=0)

1.5

4

8

20

24

Machine clock fCP (MHz)

Guaranteed operation range of MB90F947/MB90F949

• CS2 (bit 0 in PSCCR register) = 0

Guaranteed oscilation frequency range

×4 (CS=011)

×3 (CS=010)

×2 (CS=001)

20

16

12

×1*¹(CS=000)

×1/2 (PLL off)

8

6

4

1.5

3

4

6

8

10

12

External clock fC (MHz)*²

• CS2 (bit 0 in PSCCR register) = 1

Guaranteed oscilation frequency range

×6 (CS=110)

×4 (CS=101)

×2 (CS=100)

24

16

8

6

×1/2 (PLL off)

1.5

3

4

6

8

10

12

External clock fC

(MHz)*²

*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz.

*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz

External clock frequency and Machine clock frequency

44

MB90945 Series

(2) Reset Standby Input

Parameter Symbol

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5 V, V^SS= AV^SS= 0.0 V)

Value

Unit

Remarks

Min

Max

16 t^CP*¹

⎯

ns

µs

Under normal operation

In Stop mode

Reset input

t^RSTL

Oscillation time of oscillator*²

RST

⎯

time

+ 100 + 16 t^CP*¹

100

In Timebase timer mode

*1 : “t^CP” represents one cycle time of the machine clock.

No reset can fully initialize the Flash memory if it is performing the automatic algorithm.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystaloscillator, the oscillation time is betweenseveralms and totens of ms. InFAR / ceramic oscillators,

the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation :

tRSTL

RST

0.2 VCC

In Stop mode :

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

16 tCP

Oscillation time

of oscillator

Oscillation stabilization

waiting time

+100 µs

Instruction execution

Internal reset

45

MB90945 Series

(3) Power On Reset

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5 V, V^SS= AV^SS= 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t^R

V^CC

ms

⎯

t^OFF

⎯

ms Due to repetitive operation

tR

2.7 V

VCC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

Holds RAM data

3 V

VSS

46

MB90945 Series

(4) UART0, SIO Timing

Parameter

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5 V, V^SS= AV^SS= 0.0 V)

Value

Max

Sym-

bol

Re-

marks

Condition

Unit

Min

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SCK0, SCK4

8 t^CP

⎯

ns

SCK0, SCK4,

SOT0, SOT4

SCK ↓ → SOT delay time

−80

100

60

+80

Internal clock

operation output

pins are

SCK0, SCK4,

SIN0, SIN4

Valid SIN → SCK ↑

⎯

ns

CL = 80 pF + 1 TTL.

SCK0, SCK4,

SIN0, SIN4

SCK ↑ → Valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK0, SCK4

4 t^CP

⎯

ns

SCK0, SCK4, External clock

SOT0, SOT4 operation output

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

⎯

60

150

⎯

ns

pins are

CL = 80 pF + 1 TTL.

SCK0, SCK4,

SIN0, SIN4

SCK0, SCK4,

SIN0, SIN4

SCK ↑ → Valid SIN hold time t^SHIX

⎯

Notes : • AC characteristics in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

47

MB90945 Series

• Internal Shift Clock Mode

t

SCYC

2.4 V

SCK

SOT

0.8 V

t

SLOV

2.4 V

0.8 V

t

IVSH

t

SHIX

V

IH

IL

V

IH

IL

SIN

V

• External Shift Clock Mode

t

SLSH

t

SHSL

V

IH

VIH

SCK

SOT

V

IL

VIL

t

SLOV

2.4 V

0.8 V

t

IVSH

t

SHIX

V

IH

IL

V

IH

IL

SIN

V

48

MB90945 Series

(5) UART2/3 Timing

• Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5 V, V^SS= AV^SS= 0V)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYCSCK2,SCK3

5 t^CP

⎯

ns

SCK2,SCK3

t^SLOVI

SCK ↓ → SOT delay time

−50

t^CP+ 80

0

+50

⎯

Internal clock

operation output

pins are

SOT2,SOT3

SCK2,SCK3

t^IVSHI

Valid SIN → SCK ↑

ns

SIN2,SIN3

CL = 80 pF + 1 TTL.

SCK2,SCK3

t^SHIXI

SCK ↑ → Valid SIN hold time

⎯

SIN2,SIN3

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK2,SCK3

t^CP+ 10

3 t^CP− t^R

⎯

ns

SCK2,SCK3

SOT2,SOT3

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOVE

t^IVSHE

⎯

30

2 t^CP+ 60 ns

External clock

SCK2,SCK3 operation output

SIN2,SIN3 pins are

⎯

ns

CL = 80 pF + 1 TTL.

SCK2,SCK3

SIN2,SIN3

SCK ↑ → Valid SIN hold time t^SHIXE

t^CP+ 30

SCK fall time

SCK rise time

t^F

SCK2,SCK3

⎯

10

ns

t^R

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

• Internal Shift Clock Mode

t

SCYC

2.4 V

SCK

SOT

0.8 V

t

SLOVI

2.4 V

0.8 V

t

IVSHI

t

SHIXI

V

IH

IL

V

IH

IL

SIN

V

49

MB90945 Series

• External Shift Clock Mode

tSLSH

tSHSL

VIH

tR

VIH

SCK

VIL

tSLOVE

tF

2.4 V

0.8 V

SOT

SIN

tIVSHE

tSHIXE

VIH

VIL

VIH

VIL

• Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0V)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYCSCK2,SCK3

5 t^CP

⎯

ns

SCK2,SCK3

t^SHOVI

SCK ↑ → SOT delay time

−50

t^CP+ 80

0

+50

⎯

Internal clock

operation output

pins are

SOT2,SOT3

SCK2,SCK3

t^IVSLI

Valid SIN → SCK ↓

ns

SIN2,SIN3

CL = 80 pF + 1 TTL.

SCK2,SCK3

t^SLIXI

SCK ↓ → Valid SIN hold time

⎯

SIN2,SIN3

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK2,SCK3

3 t^CP− t^R

t^CP+ 10

⎯

ns

SCK2,SCK3

SOT2,SOT3

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

t^SHOVE

t^IVSLE

⎯

30

2 t^CP+ 60 ns

External clock

SCK2,SCK3 operation output

SIN2,SIN3 pins are

⎯

ns

CL = 80 pF + 1 TTL.

SCK2,SCK3

SIN2,SIN3

SCK ↓ → Valid SIN hold time t^SLIXE

t^CP+ 30

SCK fall time

SCK rise time

t^F

SCK2,SCK3

⎯

10

ns

t^R

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

50

MB90945 Series

• Internal Shift Clock Mode

t

SCYC

2.4 V

SCK

0.8 V

t

SHOVI

2.4 V

0.8 V

SOT

SIN

t

IVSLI

t

SLIXI

V

IH

IL

V

IH

IL

• External Shift Clock Mode

t

SHSL

t

SLSH

VIH

V

IH

SCK

VIL

V

IL

t

SHOVE

t

R

t

F

2.4 V

0.8 V

SOT

SIN

t

IVSLE

t

SLIXE

V

IH

IL

V

IH

IL

51

MB90945 Series

• Bit setting : ESCR : SCES = 0, ECCR : SCDE = 1

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Max

Serial clock cycle time

t^SCYCSCK2,SCK3

5 t^CP

⎯

ns

SCK2,SCK3

t^SHOVI

SCK ↑ → SOT delay time

−50

+50

⎯

SOT2,SOT3

Internal clock

operation output

pins are

SCK2,SCK3

t^IVSLI

Valid SIN → SCK ↓

t^CP+ 80

ns

SIN2,SIN3

SCK2,SCK3

t^SLIXI

CL = 80 pF + 1 TTL.

SCK ↓ → Valid SIN hold time

SOT → SCK ↓ delay time

0

⎯

SIN2,SIN3

SCK2,SCK3

tSOVLI

3 t^CP−

70

⎯

SOT2,SOT3

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

t

SCYC

2.4 V

SCK

SOT

0.8 V

t

SHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

t

IVSLI

tSLIXI

V

IH

IL

V

IH

IL

SIN

52

MB90945 Series

• Bit setting : ESCR : SCES = 1, ECCR : SCDE = 1

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Max

Serial clock cycle time

t^SCYCSCK2,SCK3

5 t^CP

⎯

ns

SCK2,SCK3

t^SLOVI

SCK ↓ → SOT delay time

−50

t^CP+ 80

0

+50

⎯

SOT2,SOT3

Internal clock

operation output

pins are

SCK2,SCK3

t^IVSHI

Valid SIN → SCK ↑

ns

SIN2,SIN3

SCK2,SCK3

SIN2,SIN3

CL = 80 pF + 1 TTL.

SCK ↑ → Valid SIN hold time t^SHIXI

SOT → SCK ↑ delay time

⎯

SCK2,SCK3

SOT2,SOT3

3 t^CP−

70

tSOVHI

⎯

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

tSCYC

2.4 V

SCK

SOT

0.8 V

tSLOVI

tSOVHI

2.4 V

0.8 V

2.4 V

0.8 V

tIVSHI

tSHIXI

VIH

VIL

VIH

VIL

SIN

53

MB90945 Series

(6) Trigger Input Timing

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

200

Max

⎯

INT0 to INT7

ADTG

ns

t^TRGH

t^TRGL

Input pulse width

⎯

t^CP+ 200

⎯

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

• Trigger Input Timing

VIH

VIL

tTRGH

tTRGL

(7) Timer Related Resource Input Timing

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

t^TIWH

t^TIWL

TIN0,

IN0 to IN5

Input pulse width

⎯

4 t^CP

⎯

ns

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for t^CP.

• Timer Input Timing

VIH

VIL

tTIWH

tTIWL

54

MB90945 Series

(8) I²C Timing

(T^A= −40 °C to +105 °C, V^CC= 3.5V to 5.5V, V^SS= AV^SS= 0.0 V)

Fast-mode^*4

Standard-mode

Parameter

Symbol Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

0

100

0

400

kHz

Hold time (repeated) START condition

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

0.6

⎯

µs

“L” width of SCL clock

“H” width of SCL clock

t^LOW

t^HIGH

4.7

4.0

⎯

1.3

0.6

⎯

µs

Set-up time for a repeated START condition

SCL ↑ → SDA ↓

t^SUSTA

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

ns

µs

R = 1.3 kΩ,

C = 50 pF*¹

Data hold time

SCL ↑ → SDA ↓↑

t^HDDAT

Data set-up time

SDA ↓↑ → SCL ↑

t^SUDAT

t^SUSTO

t^BUS

250

4.0

4.7

100

0.6

1.3

Set-up time for STOP condition

SCL ↑ → SDA ↑

⎯

Bus free time between STOP and START

condition

⎯

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HDDATonly has to be met if the devie does not stretch the “L” width (t^LOW) of the SCL signal.

*3 : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

t^SUDAT≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

• I²C Timing

SDA

t

BUS

t

SUDAT

t

LOW

t

HDSTA

SCL

t

SUSTO

t

HDSTA

t

HDDAT

t

HIGH

tSUSTA

55

MB90945 Series

5. A/D Converter

(TA

= −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, V^CC= AV^CC= 5.0 V 10%, V^SS= AV^SS= 0 V)

Value

Parameter

Resolution

Symbol

Unit

Remarks

Min

⎯

Typ

Max

10

⎯

bit

Total error

⎯

3.0

2.5

LSB

Nonlinearity error

⎯

Differential

nonlinearity error

⎯

1.9

LSB

Zero reading voltage

V^OT

V^FST

AN0 to AN14 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB

AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Full scale reading

voltage

Compare time

Sampling time

⎯

3.3

1.6

66 t^CP

32 t^CP

16500

µs

∞

Analog port input

current

I^AIN

AN0 to AN14

−0.3

⎯

+0.3

µA

Analog input voltage

range

V^AIN

AVRL

AVRH

V

AVRH

AVRL

AV^CC

AVRL + 2.7

⎯

AV^CC

V

Reference voltage

range

⎯

0

AVRH − 2.7

I^A

I^AH

I^R

⎯

3.5

⎯

7.5

5

mA

µA

Power supply current

AV^CC

*

AVRH

165

⎯

250

5

Reference voltage

current

I^RH

Offset between input

channels

⎯

AN0 to AN14

⎯

4

LSB

* : When not operating A/D converter, this is the current (V^CC= AV^CC= AVRH = 5.0 V) .

Terminology

Conversion error

: Absolute maximum conversion deviation with respect to the theoretical conversion

line.

Nonlinearity

: Relative maximum conversion deviation with respect to the theoretical conversion

line conncecting to the device unigque zero reading voltage and full scale reading

voltage.

Differential nonlinearity

Zero reading voltage

: Max conversion deviation in any two adjacent reading voltages with respect to the

theoretical LSB conversion step.

: Input voltage which results in the minimum conversion value.

Full scale reading voltage : Input voltage which results in the maximum conversion value.

Notes : • t^CPis the machine clock cycle time (Unit : ns) . Refer to “4. AC Characteristics (1) Clock timing” rating

for t^CP.

• The accuracy gets worse as |AVRH − AVRL| becomes smaller.

56

MB90945 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Linear error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential linear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

error

value.

Total error

: Difference between an actual value and an ideal value. A total error includes zero transition

error, full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AVRL

1 LSB (Ideal value) =

[V]

1024

V^OT(Ideal value) = AVRL + 0.5 LSB [V]

V^FST(Ideal value) = AVRH − 1.5 LSB [V]

V^NT: A voltage at which digital output transitions from (N − 1) to N.

(Continued)

57

MB90945 Series

(Continued)

Linear error

Differential linear error

Ideal

characteristics

3FFH

Actual conversion

characteristics

3FEH

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT}

3FDH

V^FST(actual

measurement

value)

N

VNT (actual

measurement value)

004H

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

003H

002H

001H

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V^OT(actual measurement value)

Analog input

AVRL

AVRH

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + V^OT}

[LSB]

Linear error of digital output N =

1 LSB

V (^N+1) ^T− V^NT

−1 LSB [LSB]

1 LSB

Differential linear error of digital output N =

1 LSB =

V^FST− V^OT

[V]

1022

V^OT: Voltage at which digital output transits from “000^H” to “001^H.”

V^FST: Voltage at which digital output transits from “3FE^H” to “3FF^H.”

58

MB90945 Series

7. Notes on A/D Converter Section

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

C

MB90F946A/947A/

Note : The values are reference values.

F947/F947A/F949/ 2.4 kΩ (Max) 36.4 pF (Max)

F949A

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between the external impedance and minimum sampling time

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

MB90F947

MB90F949

MB90F947

MB90F949

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

4

0

5

10

15

20

25

30

35

0

1

2

3

5

6

7

8

Minimum sampling time [µs]

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About the error

The accuracy gets worse as |AVRH − AVRL| becomes smaller.

59

MB90945 Series

8. Flash Memory Program/Erase Characteristics

Value

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Excludes programming

prior to erasure

Sector erase time

⎯

1

5

7

15

s

MB90F947, Excludes pro-

gramming prior to erasure

⎯

T^A= +25 °C

V^CC= 5.0 V

Chip erase time

MB90F949, Excludes pro-

gramming prior to erasure

Word (16-bit width)

programming time

Except for the overhead

time of the system

⎯

10,000

20

16

⎯

3,600

⎯

µs

Program/Erase cycle

⎯

cycle

Year

Flash Data Retention

Time

Average

T^A= +85 °C

⎯

*

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

60

MB90945 Series

■ EXAMPLE CHARACTERISTICS

•MB90F947

I^CCS- VCC

I^CC- VCC

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

60

30

25

20

15

10

5

50

f = 24 MHz

f = 20 MHz

40

30

20

10

0

f = 24 MHz

f = 16 MHz

f = 12 MHz

f = 20 MHz

f = 16 MHz

f = 10 MHz

f = 8 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

f = 4 MHz

f = 2 MHz

0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

2.0

3.0

4.0

5.0

6.0

7.0

VCC [V]

I^CTSPLL6- VCC

I^CTS- VCC

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

10

9

8

7

6

5

4

3

2

1

0

500

450

400

350

300

250

200

150

100

50

f = 2 MHz

f = 24 MHz

0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

2.0

3.0

4.0

5.0

6.0

7.0

VCC [V]

(Continued)

61

MB90945 Series

(Continued)

I^CCH- VCC

TA = +25 ˚C, at stop

10

9

8

7

6

5

4

3

2

1

0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

62

MB90945 Series

•MB90F949

ICC - VCC

I^CCS- VCC

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

60

50

40

30

20

10

30

25

20

15

10

5

f = 24 MHz

f = 20 MHz

f = 24 MHz

f = 20 MHz

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

f = 4 MHz

f = 2 MHz

0

2.0

3.0

4.0

5.0

6.0

7.0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

VCC [V]

I^CTS- VCC

I^CTSPLL6- VCC

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

500

450

400

350

300

250

200

150

100

50

10

9

8

7

6

5

4

3

2

1

0

f = 2 MHz

f = 24 MHz

0

2.0

3.0

4.0

5.0

6.0

7.0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

VCC [V]

(Continued)

63

MB90945 Series

(Continued)

I^CCH- VCC

TA = +25 ˚C, at stop

10

9

8

7

6

5

4

3

2

1

0

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

64

MB90945 Series

•I/O Characteristic

(V^CC−V^OH) − I^OH

V^OL− I^OL

T^A= +25 °C, V^CC= 4.5 V

1000

900

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

8

9

10

0

1

2

3

4

5

6

7

8

9

10

2

3

4

5

6

7

0

1

I^OH(mA)

I^OL(mA)

Automotive V^IN− V^CC

CMOS V^IN− V^CC

CAN RX pin, I²C pin

T^A= +25 °C

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

VIHA

VILA

V

IHS

ILS

V

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VCC (V)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

CC (V)

V

65

MB90945 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

100-pin Plastic QFP

(FPT-100P-M06)

MB90F946APF

MB90947APF

100-pin Plastic QFP

(FPT-100P-M06)

It is recommended to use MB90F947A,

because MB90F947 does not support

clock modulation and CAN at the same

time

100-pin Plastic QFP

(FPT-100P-M06)

MB90F947PF

MB90F947APF

MB90F949PF

100-pin Plastic QFP

(FPT-100P-M06)

It is recommended to use MB90F949A,

because MB90F949 does not support

clock modulation and CAN at the same

time

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic QFP

(FPT-100P-M06)

MB90F949APF

MB90V390HACR

MB90V390HBCR

299-pin Ceramic PGA

(PGA-299C-A01)

For evaluation

It is recommended to use MB90V390HB

299-pin Ceramic PGA

(PGA-299C-A01)

For evaluation

66

MB90945 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 –⁺.^.0⁰0¹8⁴

(Mounting height)

0~8˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

C

2002 FUJITSU LIMITED F100008S-c-5-5

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

67

MB90945 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0507


型号：	MB90F949
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总68页 (文件大小：704K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F949 [FUJITSU]

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