MB90591G_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-13704-6E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90590G Series

MB90591G/F591G/594G/F594G/V590G

■ DESCRIPTION

The MB90590G series with two FULL-CAN interfaces and FLASH ROM is especially designed for automotive

and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and

Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full

CAN approach.

The instruction set of F²MC-16LX CPU core inherits an AT architecture of the F²MC* family with additional

instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc-

tions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing

long word data.

The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial

interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller,

and sound generator.

* : F²MC is the abbreviation of Fujitsu Flexible Microcontroller.

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

2008.9

MB90590G Series

■ FEATURES

• Clock

Embedded PLL clock multiplication circuit

Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation

(at oscillation of 4 MHz, 4 MHz to 16 MHz).

Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,

V^CCof 5.0 V)

• Instruction set to optimize controller applications

Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types)

Enhanced signed multiplication/division instruction and RETI instruction functions

Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C language) and multi-task operations

Adoption of system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed : 4-byte instruction queue

• Enhanced interrupt function : 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI²OS) : Up to 10 channels

• Embedded ROM size and types

Mask ROM : 256 Kbytes/384 Kbytes

Flash ROM : 256 Kbytes/384 Kbytes

Embedded RAM size : 6 Kbytes/8 Kbytes

• Flash ROM

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory

Erase can be performed on each block

Block protection with external programming voltage

• Low-power consumption (stand-by) mode

Sleep mode (mode in which CPU operating clock is stopped)

Stop mode (mode in which oscillation is stopped)

CPU intermittent operation mode

Watch mode

Hardware stand-by mode

• Process

0.5µm CMOS technology

• I/O port

General-purpose I/O ports : 78 ports

• Timer

Watchdog timer : 1 channel

8/16-bit PPG timer : 8/16-bit × 6 channels

16-bit re-load timer : 2 channels

2

DS07-13704-6E

MB90590G Series

• 16-bit I/O timer

16-bit free-run timer : 1 channel

Input capture : 6 channels

Output compare : 6 channels

• Extended I/O serial interface : 1 channel

• UART (3 channels)

With full-duplex double buffer (8-bit length)

Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

• Stepping motor controller (4 channels)

• External interrupt circuit (8 channels)

A module for starting an extended intelligent I/O service (EI²OS) and generating an external interrupt which

is triggered by an external input.

• Delayed interrupt generation module

Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)

8/10-bit resolution can be selectively used.

Starting by an external trigger input.

• FULL-CAN interfaces : 2

Conforming to Version 2.0 Part A and Part B

Flexible message buffering (mailbox and FIFO buffering can be mixed)

• Sound generator

• 18-bit Time-base counter

• Watch timer : 1 channel

• External bus interface : Maximum address space 16 Mbytes

DS07-13704-6E

3

MB90590G Series

■ PRODUCT LINEUP

Features

Classification

MB90591G/594G

MB90F591G/F594G

MB90V590G

Mask ROM product

384/256 Kbytes

8/6 Kbytes

Flash ROM product

Evaluation product

384/256 Kbytes

Boot block

Hard-wired reset vector

ROM size

RAM size

None

8/6 Kbytes

8 Kbytes

None

Emulator-specific power

supply *¹

⎯

The number of instructions : 340

Instruction bit length : 8 bits, 16 bits

Instruction length : 1 byte to 7 bytes

Data bit length : 1 bit, 8 bits, 16 bits

CPU functions

Minimum execution time : 62.5 ns (at machine clock frequency of 16 MHz)

Interrupt processing time : 1.5 µs

(at machine clock frequency of 16 MHz, minimum value)

Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps)

Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500

/500000 bps at machine clock frequency of 16 MHz)

Transmission can be performed by bi-directional serial transmission or by master/

slave connection.

UART (3 channels)

8/10-bit A/D converter

Conversion precision : 8/10-bit can be selectively used.

Number of inputs : 8

One-shot conversion mode (converts selected channel once only)

Scan conversion mode (converts two or more successive channels and can program

up to 8 channels)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

Number of channels : 6 (8/16-bit × 6 channels)

PPG operation of 8-bit or 16-bit

8/16-bit PPG timers

(6 channels)

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, 128µs

(at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation

clock frequency)

Number of channels : 2

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = System clock frequency)

Supports External Event Count function

16-bit Reload timer

16-bit

Number of channels : 6 (8/16-bit × 6 channels)

16-bit

I/O

Output compares Pin input factor : A match signal of compare register

Number of channels : 6

Rewriting a register value upon a pin input (rising, falling, or both edges)

timer

Input captures

(Continued)

4

DS07-13704-6E

MB90590G Series

(Continued)

Features

MB90591G/594G

MB90F591G/F594G

MB90V590G

Number of channels : 2

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare / Full bit mask / Two partial bit masks

Supports up to 1Mbps

CAN bit timing setting :

^{MB90(F)59xG : TSEG2}≥ RSJW

Stepping motor controller Four high current outputs for each channel

(4 channels)

Synchronized two 8-bit PWM’s for each channel

Number of inputs : 8

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit

8-bit PWM signal is mixed with tone frequency from 8-bit reload counter

PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz)

Tone frequency : PWM frequency / 2 / (reload value + 1)

Sound generator

Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock

frequency of 16 MHz)

LSB first/MSB first

Extended I/O serial

interface

Directly operates with the system clock

Read/Write accessible Second/Minute/Hour registers

Watch timer

Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Watchdog timer

Supports automatic programming, Embedded Algorithm and

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Hard-wired reset vector available in order to point to a fixed boot sector in Flash

Memory

Flash Memory

Boot block configuration

Erase can be performed on each block

Block protection with external programming voltage

Flash Writer from Minato Electronics Inc.

Low-power consumption

(stand-by) mode

Sleep/stop/CPU intermittent operation/watch timer/hardware stand-by

CMOS

Process

Power supply voltage for

operation*²

5 V 10 % (MB90V590G, MB90F594G, MB90594G)

5 V 5 % (MB90F591G, MB90591G)

Package

QFP-100

PGA-256

*1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.

*2 : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

DS07-13704-6E

5

MB90590G Series

■ PIN ASSIGNMENT

(Top view)

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P20

P95/INT3

P94/INT2

P93/INT1

2

P21

3

P22

4

P23

RST

5

P24/INT4

P92/INT0

P25/INT5

P26/INT6

P27/INT7

P30

6

P91/RX0

7

P90/TX0

8

DV^SS

9

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DVCC

P31

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Vss

P32

P33

P34/SOT0

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DV^SS

P35/SCK0

P36/SIN0

P37/SIN1

P40/SCK1

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DVCC

P41/SOT1

P42/SOT2

P43/SCK2

P44/SIN2

Vcc

P45/SCIN3

P46/SCK3

P47/SOT3

C

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DV^SS

P50/PPG0

P51/PPG1

P52/PPG2

HST

MD2

(FPT-100P-M06)

6

DS07-13704-6E

MB90590G Series

■ PIN DESCRIPTION

No.

82

83

77

52

Pin name

X0

Circuit type

Function

A

Oscillator pin

X1

RST

B

C

Reset input

HST

Hardware standby input

General purpose I/O

Inputs for the Input Captures

P00 to P05

IN0 to IN5

85 to 90

D

P06, P07,

P10 to P13

General purpose I/O

91 to 96

D

Outputs for the Output Compares.

OUT0 to OUT5

To enable the signal outputs, the corresponding bits of the Port Direc-

tion registers should be set to “1”.

P14

RX1

P15

General purpose I/O

97

98

D

RX input for CAN Interface 1

General purpose I/O

TX output for CAN Interface 1.

To enable the signal output, the corresponding bit of the Port Direction

register should be set to “1”.

TX1

P16

General purpose I/O

SGO output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction

register should be set to “1”.

99

D

SGO

P17

General purpose I/O

SGA output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction

register should be set to “1”.

100

SGA

1 to 4

5 to 8

P20 to P23

P24 to P27

INT4 to INT7

P30, P31

P32, P33

P34

D

General purpose I/O

External interrupt input for INT4 to INT7

General purpose I/O

9, 10

D

12, 13

General purpose I/O

SOT output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction

register should be set to “1”.

14

15

D

SOT0

P35

General purpose I/O

SCK input/output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction

register should be set to “1”.

SCK0

(Continued)

DS07-13704-6E

7

MB90590G Series

No.

Pin name

P36

Circuit type

Function

General purpose I/O

SIN input for UART 0

General purpose I/O

SIN input for UART 1

General purpose I/O

SCK input/output for UART 1

General purpose I/O

SOT output for UART 1

General purpose I/O

SOT output for UART 2

General purpose I/O

SCK input/output for UART 2

General purpose I/O

SIN input for UART 2

General purpose I/O

SIN input for the Serial I/O

General purpose I/O

16

D

SIN0

P37

17

18

19

20

21

22

24

25

26

D

SIN1

P40

SCK1

P41

SOT1

P42

SOT2

P43

SCK2

P44

SIN2

P45

SIN3

P46

SCK3

P47

SCK input/output for the Serial I/O

General purpose I/O

SOT3

P50 to P55

SOT output for the Serial I/O

General purpose I/O

PPG0 to

PPG5,

ADTG

Outputs for the Programmable Pulse Generators.

Pin number 33 is also shared with ADTG input for the external trigger

of the A/D Converter.

28 to 33

D

P60 to P63

AN0 to AN3

P64 to P67

AN4 to AN7

P56

General purpose I/O

38 to 41

43 to 46

47

E

D

Inputs for the A/D Converter

General purpose I/O

Inputs for the A/D Converter

General purpose I/O

TIN

TIN input for the 16-bit Reload Timers

General purpose I/O

P57

TOT output for the 16-bit Reload Timers and WOT output for the

Watch Timer. Only one of three output enable flags in these periph-

eral blocks can be set at a time. Otherwise the output signal has no

meaning.

48

D

TOT/WOT

(Continued)

8

DS07-13704-6E

MB90590G Series

No.

Pin name

Circuit type

Function

P70 to P73

General purpose I/O

PWM1P0,

PWM1M0,

PWM2P0,

PWM2M0

54 to 57

F

Output for Stepping Motor Controller channel 0.

General purpose I/O

P74 to P77

PWM1P1,

PWM1M1,

PWM2P1,

PWM2M1

59 to 62

64 to 67

69 to 72

F

Output for Stepping Motor Controller channel 1.

General purpose I/O

P80 to P83

PWM1P2,

PWM1M2,

PWM2P2,

PWM2M2

Output for Stepping Motor Controller channel 2.

General purpose I/O

P84 to P87

PWM1P3,

PWM1M3,

PWM2P3,

PWM2M3

Output for Stepping Motor Controller channel 3.

P90

TX0

P91

RX0

P92

INT0

P93

INT1

P94

INT2

P95

INT3

General purpose I/O

74

75

76

78

79

80

D

TX output for CAN Interface 0

General purpose I/O

RX input for CAN Interface 0

General purpose I/O

External interrupt input for INT0

General purpose I/O

External interrupt input for INT1

General purpose I/O

External interrupt input for INT2

General purpose I/O

External interrupt input for INT3

Dedicated power supply pins for the high current output buffers

(Pin No. 54 to 72)

58, 68

DV^CC

DV^SS

⎯

Dedicated ground pins for the high current output buffers

(Pin No. 54 to 72)

53, 63, 73

Power supply for analog circuit pin

When turning this power supply on or off, always be sure to first apply

electric potential equal to or greater than AV^CCto VCC.

Power

supply

34

37

AV^CC

AV^SS

Power

supply

Ground level for analog circuit

(Continued)

DS07-13704-6E

9

MB90590G Series

(Continued)

No.

Pin name

Circuit type

Function

Reference voltage input pin for analog circuit

When turning this power supply on or off, always be sure to first apply

electric potential equal to or greater than AVRH to AV^CC.

Power

supply

35

AVRH

Power

supply

36

49, 50

51

AVRL

MD0, MD1

MD2

Reference voltage input pin for analog circuit

Operating mode selection input pins

Connect directly to V^CCor VSS.

C

G

Operating mode selection input pin

Connect directly to V^CCor VSS.

This is the power supply stabilization capacitor pin. It should be con-

nected externally to an 0.1 µF ceramic capacitor.

27

C

⎯

Power

supply

23, 84

11,42,81

V^CC

Power supply (5.0 V) input pin for digital circuit

Power supply (GND) input pin for digital circuit

Power

supply

VSS

10

DS07-13704-6E

MB90590G Series

■ I/O CIRCUIT TYPE

Circuit Type

Circuit

Remarks

• Oscillation feedback resistor :

1 MΩ approx.

X1

Clock

Input

X0

A

HARD,SOFT

STANDBY

CONTROL

• Hysteresis input with pull-up resistor :

50 kΩ approx.

R (pull-up)

R

B

C

HYS

• Hysteresis input

R

• CMOS output

• Hysteresis input

VCC

P-ch

N-ch

D

R

HYS

(Continued)

DS07-13704-6E

11

MB90590G Series

(Continued)

Circuit Type

Circuit

Vcc

P-ch

Remarks

• CMOS output

• Hysteresis input

• Analog input

N-ch

E

P-ch

Analog input

HYS

N-ch

R

• CMOS high current output

• Hysteresis input

P-ch

High current

N-ch

F

HYS

R

• Hysteresis input with pull-down resistor :

50 kΩ approx.

• Flash version does not have pull-down

R

resistor.

R(pull-down)

G

12

DS07-13704-6E

MB90590G Series

■ HANDLING DEVICES

(1) Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between Vcc and Vss.

• The AVcc power supply is applied before the Vcc voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

(2) Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be

more than 2 kΩ.

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

(3) Using external clock

To use external clock, drive X0 pin only and leave X1 pin unconnected.

Below is a diagram of how to use external clock.

MB90590G Series

X0

X1

Using external clock

DS07-13704-6E

13

MB90590G Series

(4)Power supply pins (Vcc/Vss)

In products with multiple V^CCor VSS pins, pins with the same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a

ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused

by the rise in the ground level, and to conform to the total current rating.

Make sure to connect V^CCand VSS pins via lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 µF between V^CCand VSS pin near the device.

Vcc

Vss

Vcc

Vss

Vcc

MB90590G

Series

Vcc

Vss

Vcc

Vss

(5) Pull-up/down resistors

The MB90590G Series does not support internal pull-up/down resistors. Use external components where need-

ed.

(6) Crystal Oscillator Circuit

Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the

shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure

that lines of oscillation circuits do not cross the lines of other circuits.

A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation

is highly recommended.

(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AV^CC, AVRH, AVRL) and analog inputs (AN0 to AN7) after

turning-on the digital power supply (V^CC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

(8) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV^CC= VCC, AVSS = AVRH = VSS.

14

DS07-13704-6E

MB90590G Series

(9) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(10) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

⁵⁰µs or more (0.2 V to 2.7 V).

(11) Indeterminate outputs from ports 0 and 1 (without MB90F591G/591G, MB90F594G)

During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the

outputs from ports 0 and 1 become following state.

• If RST pin is “H”, the outputs become indeterminate.

• If RST pin is “L”, the outputs become high-impedance.

Pay attention to the port output timing shown as follow.

Oscillation setting time^*2

RST pin is “H”

Power-on reset^*1

Vcc (Power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

Period of indeterminated

*1 : Power-on reset time : "Period of clock frequency" × 2¹⁷(Clock frequency of 16 MHz : 8.19 ms)

^{*2 : Oscillation setting time : "Period of clock frequency"}× 2¹⁸(Clock frequency of 16 MHz : 16.38ms)

Oscillation setting time^∗2

RST pin is “L”

Power-on reset^∗1

Vcc (Power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

High-impedance

^{*1 : Power-on reset time : "Period of clock frequency"}× 2¹⁷(Clock frequency of 16 MHz : 8.19 ms)

^{*2 : Oscillation setting time : "Period of clock frequency"}× 2¹⁸(Clock frequency of 16 MHz : 16.38ms)

DS07-13704-6E

15

MB90590G Series

(12) Initialization

The device contains internal registers which are initialized only by a power-on reset. To initialize these registers,

please turn on the power again.

(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre-

sponding bank register (DTB, ADB, USB, SSB) is set in “00 ^H”.

If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00 ^H”, the remainder

by the execution result of the instruction is not stored in the register of the instruction operand.

(14) Using REALOS

The use of EI²OS is not possible with the REALOS real time operating system.

(15) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-

running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or

the clock input is stopped. Performance of this operation, however, cannot be guaranteed.

16

DS07-13704-6E

MB90590G Series

■ BLOCK DIAGRAM

X0,X1

Clock

F²MC-16LX

CPU

RST

HST

Controller

16-bit

Free-run Timer

RAM 6/8 K

16-bit Input

Capture

6ch

IN0 to IN5

ROM/Flash

256 K/384 K

16-bit Output

Compare

6ch

OUT0 to OUT5

Prescaler × 3

UART 3ch

Prescaler

8/16-bit

PPG

6ch

SOT0 to SOT2

SCK0 to SCK2

SIN0 to SIN2

PPG0 to PPG5

RX0, RX1

TX0, TX1

CAN

2ch

SOT3

SCK3

SIN3

Serial I/O

PWM1M0 to PWM1M3

PWM1P0 to PWM1P3

PWM2M0 to PWM2M3

AVCC

AVSS

SMC

4ch

PWM2P0 to PWM2P3

DVCC

10-bit ADC

8ch

AN0 to AN7

AVRH

DVSS

AVRL

ADTG

External

Interrupt

INT0 to INT7

Circuit 8ch

TIN

16-bit Reload

Timer 2ch

TOT/WOT

Sound

SGO

SGA

Generator

Watch

Timer

DS07-13704-6E

17

MB90590G Series

■ MEMORY SPACE

The memory space of the MB90590/590G Series is shown below

MB90591G/

F591G

MB90V590G

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

MB90594G/F594G

FFFFFF^H

FF0000H

FEFFFFH

FE0000H

FDFFFF^H

FD0000H

FCFFFF^H

FC0000H

FBFFFFH

FB0000H

FAFFFF^H

FA0000H

F9FFFFH

F90000H

FFFFFF^H

FF0000H

FEFFFF^H

FE0000H

FDFFFF^H

FD0000H

FCFFFF^H

FC0000H

FFFFFF^H

FF0000H

FEFFFF^H

FE0000H

FDFFFF^H

FD0000H

FCFFFF^H

FC0000H

FBFFFF^H

FB0000H

FAFFFF^H

FA0000H

F9FFFF^H

F90000H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

00FFFFH

004000H

ROM

(Image of FF bank)

00FFFFH

004000H

ROM

(Image of FF bank)

00FFFFH

004000H

ROM

(Image of FF bank)

0028FF^H

002100H

0020FF^H

0028FF^H

002100H

0020FFH

RAM 2K

001FFFH

001900H

0018FF^H

001FFF^H

001900H

0018FFH

001FFF^H

001900H

0018FFH

Peripheral

RAM 6K

Peripheral

RAM 6K

Peripheral

RAM 6K

000100H

0000BF^H

000000H

0000BF^H

000000H

0000BF^H

000000H

Peripheral

Memory space map

Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C

compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same

address, enabling reference of the table on the ROM without stating “far”.

For example, if an attempt has been made to access 00C000^H, the contents of the ROM at FFC000H are

accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the

image for the 00 bank. The ROM data at FF4000^Hto FFFFFFH looks, therefore, as if it were the image for

004000^Hto 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to

FFFFFF^H.

18

DS07-13704-6E

MB90590G Series

■ I/O MAP

Address

00^H

Register

Abbreviation Access

Peripheral

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Initial value

XXXXXXXXB

_ _ XXXXXXB

Port 0 Data Register

Port 1 Data Register

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

Port 7 Data Register

Port 8 Data Register

Port 9 Data Register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

R/W

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH to 0FH

10^H

Reserved

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

Port 7 Direction Register

Port 8 Direction Register

Port 9 Direction Register

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

0 0 0 0 0 0 0 0B

_ _ 0 0 0 0 0 0B

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

Reserved

1B^H

Analog Input Enable Register

ADER

R/W

Port 6, A/D

1 1 1 1 1 1 1 1B

1CH to 1FH

20^H

Reserved

Serial Mode Control Register 0

Serial Status Register 0

UMC0

USR0

R/W

0 0 0 0 0 1 0 0B

0 0 0 1 0 0 0 0B

21H

UART0

UIDR0/

UODR0

Serial Input/Output Data Register 0

22H

R/W

XXXXXXXX^B

23H

24H

25H

Rate and Data Register 0

Serial Mode Control Register 1

Serial Status Register 1

URD0

UMC1

USR1

R/W

0 0 0 0 0 0 0XB

0 0 0 0 0 1 0 0B

0 0 0 1 0 0 0 0B

UART1

UIDR1/

UODR1

Serial Input/Output Data Register 1

Rate and Data Register 1

26H

27H

R/W

XXXXXXXX^B

URD1

0 0 0 0 0 0 0XB

(Continued)

DS07-13704-6E

19

MB90590G Series

Address

28^H

Register

Abbreviation Access

Peripheral

Initial value

0 0 0 0 0 1 0 0B

0 0 0 1 0 0 0 0B

Serial Mode Control Register 2

Serial Status Register 2

UMC2

USR2

R/W

29H

UART2

Serial Input/Output Data

Register 2

UIDR2/

UODR2

2AH

2BH

2CH

R/W

XXXXXXXX^B

0 0 0 0 0 0 0XB

_ _ _ _0 0 0 0^B

Rate and Data Register 2

URD2

Serial Mode Control Register

(low-order)

SMCS

Serial Mode Control Register

(high-order)

2DH

SMCS

R/W

0 0 0 0 0 0 1 0^B

Serial I/O

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3C^H

3DH

3EH

3FH

40^H

41H

42H

43H

44^H

45H

46H

47H

Serial Data Register

Edge Selector Register

SDR

SES

R/W

R

XXXXXXXXB

_ _ _ _ _ _ _0B

0 0 0 0 0 0 0 0B

XXXXXXXXB

External Interrupt Enable Register

External Interrupt Request Register

External Interrupt Level Register

A/D Control Status Register 0

A/D Control Status Register 1

A/D Data Register 0

ENIR

EIRR

External Interrupt

A/D Converter

ELVR

0 0 0 0 0 0 0 0B

XXXXXXXXB

ELVR

ADCS0

ADCS1

ADCR0

ADCR1

PPGC0

PPGC1

PPG01

A/D Data Register 1

R/W

0 0 0 0 1 0 XXB

0 _ 0 0 0 _ _ 1^B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

PPG0 Operation Mode Control Register

PPG1 Operation Mode Control Register

PPG0,1 Output Pin Control Register

16-bitProgrammable

Pulse

Generator 0/1

Reserved

PPG2 Operation Mode Control Register

PPG3 Operation Mode Control Register

PPG2,3 Output Pin Control Register

PPGC2

PPGC3

PPG23

R/W

0 _ 0 0 0 _ _1B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

16-bitProgrammable

Pulse

Generator 2/3

Reserved

PPG4 Operation Mode Control Register

PPG5 Operation Mode Control Register

PPG4,5 Output Pin Control Register

PPGC4

PPGC5

PPG45

R/W

0 _ 0 0 0 _ _ 1^B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

16-bitProgrammable

Pulse

Generator 4/5

Reserved

PPG6 Operation Mode Control Register

PPG7 Operation Mode Control Register

PPG6,7 Output Pin Control Register

PPGC6

PPGC7

PPG67

R/W

0 _ 0 0 0 _ _ 1B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

16-bitProgrammable

Pulse

Generator 6/7

Reserved

(Continued)

20

DS07-13704-6E

MB90590G Series

Address

48^H

Register

Abbreviation Access

Peripheral

Initial value

0 _ 0 0 0 _ _ 1^B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

PPG8 Operation Mode Control Register

PPG9 Operation Mode Control Register

PPG8,9 Output Pin Control Register

PPGC8

PPGC9

PPG89

R/W

16-bit Programmable

Pulse

49H

Generator 8/9

4AH

4BH

Reserved

PPGA Operation Mode Control Register

PPGB Operation Mode Control Register

PPGA,B Output Pin Control Register

4C^H

PPGCA

PPGCB

PPGAB

R/W

0 _ 0 0 0 _ _ 1B

0 _ 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

16-bit Programmable

Pulse

4DH

Generator A/B

4EH

4FH

Reserved

Timer Control Status Register 0

(low-order)

50^H

51H

52H

53H

54H

55H

TMCSR0

TMCSR1

ICS01

R/W

0 0 0 0 0 0 0 0^B

_ _ _ _ 0 0 0 0B

0 0 0 0 0 0 0 0^B

_ _ _ _ 0 0 0 0B

0 0 0 0 0 0 0 0^B

16-bit Reload Timer 0

16-bit Reload Timer 1

Timer Control Status Register 0

(high-order)

Timer Control Status Register 1

(low-order)

Timer Control Status Register 1

(high-order)

Input Capture Control Status

Register 0/1

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

Input Capture Control Status

Register 2/3

ICS23

Input Capture Control Status

Register 4/5

56H

57H

58^H

ICS45

Reserved

Output Compare Control Status

Register 0

OCS0

OCS1

OCS2

OCS3

OCS4

OCS5

R/W

0 0 0 0 _ _ 0 0^B

_ _ _0 0 0 0 0^B

0 0 0 0 _ _ 0 0^B

_ _ _ 0 0 0 0 0^B

0 0 0 0 _ _ 0 0^B

_ _ _ 0 0 0 0 0^B

Output Compare 0/1

Output Compare 2/3

Output Compare Control Status

Register 1

59H

5AH

5BH

5CH

5DH

Output Compare Control Status

Register 2

Output Compare Control Status

Register 3

Output Compare Control Status

Register 4

Output Compare 4/5

Sound Generator

Output Compare Control Status

Register 5

Sound Control Register (low-order)

Sound Control Register (high-order)

5EH

5FH

SGCR

R/W

0 0 0 0 0 0 0 0B

0 _ _ _ _ _ _ 0B

(Continued)

DS07-13704-6E

21

MB90590G Series

Address

Register

Abbreviation Access

Peripheral

Initial value

Watch Timer Control Register

(low-order)

60^H

WTCR

PWC0

R/W

0 0 0 _ _ 0 0 0^B

Watch Timer

Watch Timer Control Register

(high-order)

61H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 _ _ 0^B

Stepping Motor

Controller 0

62H

63H

64^H

65H

66^H

67H

68^H

PWM Control Register 0

PWM Control Register 1

PWM Control Register 2

PWM Control Register 3

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

Stepping Motor

Controller 1

PWC1

PWC2

PWC3

0 0 0 0 0 _ _ 0^B

0 0 0 0 0 _ _ 0B

Stepping Motor

Controller 2

Stepping Motor

Controller 3

69H to 6CH

6D^H

Serial I/O Prescaler Register

Timer Control Status Register

CDCR

TCCS

R/W

Prescaler (Serial I/O) 0 XXX 1 1 1 1B

16-bit Free-run Timer 0 0 0 0 0 0 0 0B

6EH

ROM Mirror Function Select

Register

6FH

ROMM

W

ROM Mirror

XXXXXXX1^B

70H to 8FH

90^Hto 9DH

Reserved for CAN Interface 0/1. Refer to section about CAN Controller

Reserved

Program Address Detection

Address Match

Detection Function

9E^H

PACSR

R/W

0 0 0 0 0 0 0 0^B

_ _ _ _ _ _ _ 0B

Control Status Register

Delayed Interrupt/Release Register

Low Power Mode Control Register

Clock Selection Register

9FH

A0H

DIRR

R/W

Delayed Interrupt

LPMCR

CKSCR

Low Power Controller 0 0 0 1 1 0 0 0B

Low Power Controller 1 1 1 1 1 1 0 0B

A1H

A2H to A7H

A8^H

Reserved

Watchdog Timer Control Register

Time Base Timer Control Register

WDTC

TBTC

R/W

Watchdog Timer

Time Base Timer

XXXXX 1 1 1B

1 - - 0 0 1 0 0B

A9H

AAH to ADH

Reserved

Flash Memory Control Status

Register

AE^H

AFH

FMCS

R/W

Flash Memory

0 0 0 X 0 0 0 0^B

(Flash product only.

Otherwise reserved)

Reserved

(Continued)

22

DS07-13704-6E

MB90590G Series

Address

B0^H

Register

Abbreviation

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Access

R/W

Peripheral

Initial value

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

0 0 0 0 0 1 1 1B

B1H

B2H

B3H

B4H

B5H

B6H

B7H

Interrupt controller

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

C0H to

FF^H

Reserved

1900^H

1901H

1902H

1903H

1904H

1905H

1906H

1907H

1908H

1909H

190AH

190BH

190CH

190DH

190EH

190FH

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

R/W

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

16-bit Programmable

Pulse

Generator 0/1

16-bit Programmable

Pulse

Generator 2/3

16-bit Programmable

Pulse

Generator 4/5

16-bit Programmable

Pulse

XXXXXXXXB

(Continued)

Generator 6/7

DS07-13704-6E

23

MB90590G Series

Address

1910^H

Register

Abbreviation Access

Peripheral

Initial value

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

Reload L Register

Reload H Register

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

R/W

16-bit Programmable

Pulse

1911H

1912H

R/W

Generator 8/9

1913H

R/W

1914H

R/W

16-bit Programmable

Pulse

1915H

R/W

1916H

R/W

Generator A/B

1917H

R/W

1918H to 191FH

Reserved

Input Capture Register 0

(low-order)

1920^H

1921H

1922H

1923H

1924H

1925H

1926H

1927H

1928H

1929H

192AH

IPCP0

IPCP1

IPCP2

IPCP3

IPCP4

IPCP5

R

XXXXXXXX^B

Input Capture Register 0

(high-order)

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

Input Capture Register 1

(low-order)

Input Capture Register 1

(high-order)

Input Capture Register 2

(low-order)

Input Capture Register 2

(high-order)

Input Capture Register 3

(low-order)

Input Capture Register 3

(high-order)

Input Capture Register 4

(low-order)

Input Capture Register 4

(high-order)

Input Capture Register 5

(low-order)

Input Capture Register 5

(high-order)

192BH

R

192CH to 192FH

Reserved

(Continued)

24

DS07-13704-6E

MB90590G Series

Address

Register

Abbreviation Access

Peripheral

Initial value

Output Compare Register 0

(low-order)

1930^H

OCCP0

OCCP1

OCCP2

OCCP3

OCCP4

OCCP5

R/W

XXXXXXXXB

Output Compare Register 0

(high-order)

1931H

1932H

1933H

1934H

1935H

1936H

1937H

1938H

1939H

193AH

XXXXXXXX^B

Output Compare

0/1

Output Compare Register 1

(low-order)

Output Compare Register 1

(high-order)

Output Compare Register 2

(low-order)

Output Compare Register 2

(high-order)

Output Compare

2/3

Output Compare Register 3

(low-order)

Output Compare Register 3

(high-order)

Output Compare Register 4

(low-order)

Output Compare Register 4

(high-order)

Output Compare

4/5

Output Compare Register 5

(low-order)

Output Compare Register 5

(high-order)

193BH

193CH to 193FH

1940^H

Reserved

Timer 0/Reload Register 0

(low-order)

TMR0/

TMRLR0

R/W

XXXXXXXX^B

16-bit Reload

Timer 0

Timer 0/Reload Register 0

(high-order)

TMR0/

TMRLR0

1941H

1942H

1943H

Timer 1/Reload Register 1

(low-order)

TMR1/

TMRLR1

16-bit Reload

Timer 1

Timer 1/Reload Register 1

(high-order)

TMR1/

TMRLR1

1944H

1945H

1946H

1947H

1948H

1949H

Timer Data Register (low-order)

Timer Data Register (high-order)

Frequency Data Register

Amplitude Data Register

TCDT

SGFR

SGAR

SGDR

SGTR

R/W

0 0 0 0 0 0 0 0 B

XXXXXXXXB

(Continued)

16-bit Free-run

Timer

Sound Generator

Decrement Grade Register

Tone Count Register

DS07-13704-6E

25

MB90590G Series

Address

Register

Abbreviation Access

Peripheral

Initial value

Sub-second Data Register

(low-order)

194A^H

WTBR

R/W

XXXXXXXXB

Sub-second Data Register

(middle-order)

194BH

194CH

XXXXXXXX^B

_ _ _ XXXXX^B

Watch Timer

Sub-second Data Register

(high-order)

194DH

194E^H

Second Data Register

Minute Data Register

WTSR

WTMR

WTHR

R/W

_ _ 0 0 0 0 0 0 B

_ _ _ 0 0 0 0 0 B

XXXXXXXX^B

XXXXXXXXB

_ _ 0 0 0 0 0 0 B

_ 0 0 0 0 0 0 0 B

XXXXXXXX^B

XXXXXXXXB

_ _ 0 0 0 0 0 0 B

_ 0 0 0 0 0 0 0 B

XXXXXXXX^B

XXXXXXXXB

_ _ 0 0 0 0 0 0 B

_ 0 0 0 0 0 0 0 B

XXXXXXXX^B

XXXXXXXXB

_ _ 0 0 0 0 0 0 B

_0 0 0 0 0 0 0 B

Watch Timer

194FH

Hour Data Register

1950H

PWM1 Compare Register 0

PWM2 Compare Register 0

PWM1 Select Register 0

PWM2 Select Register 0

PWM1 Compare Register 1

PWM2 Compare Register 1

PWM1 Select Register 1

PWM2 Select Register 1

PWM1 Compare Register 2

PWM2 Compare Register 2

PWM1 Select Register 2

PWM2 Select Register 2

PWM1 Compare Register 3

PWM2 Compare Register 3

PWM1 Select Register 3

PWM2 Select Register 3

PWC10

PWC20

PWS10

PWS20

PWC11

PWC21

PWS11

PWS21

PWC12

PWC22

PWS12

PWS22

PWC13

PWC23

PWS13

PWS23

1951H

Stepping Motor

Controller 0

1952H

1953H

1954H

1955H

Stepping Motor

Controller 1

1956H

1957H

1958H

1959H

Stepping Motor

Controller 2

195AH

195BH

195CH

195DH

Stepping Motor

Controller 3

195EH

195FH

1960H to 19FFH

1A00^Hto 1AFFH

1B00^Hto 1BFFH

1C00^Hto 1CFFH

1D00^Hto 1DFFH

1E00^Hto 1EFFH

Reserved

CAN Interface 0. Refer to section about CAN Controller

CAN Interface 1. Refer to section about CAN Controller

CAN Interface 0. Refer to section about CAN Controller

CAN Interface 1. Refer to section about CAN Controller

Reserved

(Continued)

26

DS07-13704-6E

MB90590G Series

(Continued)

Address

Register

Abbreviation Access

Peripheral

Initial value

Program Address Detection

Register 0 (low-order)

1FF0^H

1FF1H

1FF2H

1FF3H

1FF4H

PADR0

PADR1

R/W

XXXXXXXX ^B

Program Address Detection

Register 0 (middle-order)

XXXXXXXX ^B

Program Address Detection

Register 0 (high-order)

Address Match

Detection

Program Address Detection

Register 1 (low-order)

Function

Program Address Detection

Register 1 (middle-order)

Program Address Detection

Register 1 (high-order)

1FF5H

1FF6H to 1FFFH

Reserved

Note : Initial value of “_” represents unused bit; “X” represents unknown value.

Addresses in the rage 0000^Hto 00FFH, which are not listed in the table, are reserved for the primary functions

of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should

not be performed.

DS07-13704-6E

27

MB90590G Series

■ CAN CONTROLLERS

The CAN controller has the following features : Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame and extended frame formats

• Supports transmission of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as 1D acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)

List of Control Registers

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN0

CAN1

000070^H

000071H

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

000080H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

Message buffer valid register

Transmit request register

Transmit cancel register

00000000 00000000B

Transmit complete register

Receive complete register

Remote request receiving register

Receive overrun register

Receive interrupt enable register

R/W

RCR

00007AH 00008AH

00007BH 00008BH

00007CH 00008CH

00007DH 00008DH

00007EH 00008EH

00007FH 00008FH

RRTRR

ROVRR

RIER

00000000 00000000B

(Continued)

28

DS07-13704-6E

MB90590G Series

(Continued)

List of Control Registers

Register Abbreviation Access

Address

CAN0 CAN1

Initial Value

001C00^H001D00H

001C01H 001D01H

001C02H 001D02H

001C03H 001D03H

001C04H 001D04H

001C05H 001D05H

001C06H 001D06H

001C07H 001D07H

001C08H 001D08H

001C09H 001D09H

001C0AH 001D0AH

001C0BH 001D0BH

001C0CH 001D0CH

001C0DH 001D0DH

001C0EH 001D0EH

001C0FH 001D0FH

001C10H 001D10H

001C11H 001D11H

001C12H 001D12H

001C13H 001D13H

001C14H 001D14H

001C15H 001D15H

001C16H 001D16H

001C17H 001D17H

001C18H 001D18H

001C19H 001D19H

001C1AH 001D1AH

001C1BH 001D1BH

Control status register

CSR

LEIR

R/W, R

R/W

R

00---000 0----0-1B

-------- 000-0000B

Last event indicator register

Receive/transmit error counter

Bit timing register

RTEC

BTR

00000000 00000000B

-1111111 11111111B

R/W

XXXXXXXX

XXXXXXXX^B

IDE register

IDER

Transmit RTR register

TRTRR

RFWTR

TIER

00000000 00000000B

XXXXXXXX

XXXXXXXX^B

Remote frame receive waiting register

Transmit interrupt enable register

00000000 00000000B

XXXXXXXX

XXXXXXXX^B

Acceptance mask select register

Acceptance mask register 0

Acceptance mask register 1

AMSR

AMR0

AMR1

R/W

XXXXXXXX

XXXXXXXX^B

XXXXXXXX

XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX

XXXXXXXXB

XXXXX--- XXXXXXXXB

DS07-13704-6E

29

MB90590G Series

List of Message Buffers (ID Registers)

Address

CAN0 CAN1

Register

Abbreviation

Access

Initial Value

001A20H 001B20H

001A21H 001B21H

001A22H 001B22H

001A23H 001B23H

001A24H 001B24H

001A25H 001B25H

001A26H 001B26H

001A27H 001B27H

001A28H 001B28H

001A29H 001B29H

001A2AH 001B2AH

001A2BH 001B2BH

001A2CH 001B2CH

001A2DH 001B2DH

001A2EH 001B2EH

001A2FH 001B2FH

001A30H 001B30H

001A31H 001B31H

001A32H 001B32H

001A33H 001B33H

001A34H 001B34H

001A35H 001B35H

001A36H 001B36H

001A37H 001B37H

001A38H 001B38H

001A39H 001B39H

001A3AH 001B3AH

001A3BH 001B3BH

001A3CH 001B3CH

001A3DH 001B3DH

001A3EH 001B3EH

001A3FH 001B3FH

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

ID register 0

IDR0

R/W

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

R/W

XXXXX--- XXXXXXXXB

(Continued)

30

DS07-13704-6E

MB90590G Series

(Continued)

Address

CAN0 CAN1

Register

Abbreviation

Access

Initial Value

001A40^H001B40H

001A41H 001B41H

001A42H 001B42H

001A43FH 001B43H

001A44H 001B44H

001A45H 001B45H

001A46H 001B46H

001A47H 001B47H

001A48H 001B48H

001A49H 001B49H

001A4AH 001B4AH

001A4BH 001B4BH

001A4CH 001B4CH

001A4DH 001B4DH

001A4EH 001B4EH

001A4FH 001B4FH

001A50H 001B50H

001A51H 001B51H

001A52H 001B52H

001A53H 001B53H

001A54H 001B54H

001A55H 001B55H

001A56H 001B56H

001A57H 001B57H

001A58H 001B58H

001A59H 001B59H

001A5AH 001B5AH

001A5BH 001B5BH

001A5CH 001B5CH

001A5DH 001B5DH

001A5EH 001B5EH

001A5FH 001B5FH

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX^B

XXXXX--- XXXXXXXXB

ID register 8

IDR8

R/W

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

DS07-13704-6E

31

MB90590G Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN0 CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

----XXXXB

----XXXX

001A60^H001B60H

001A61H 001B61H

001A62H 001B62H

001A63H 001B63H

001A64H 001B64H

001A65H 001B65H

001A66H 001B66H

001A67H 001B67H

001A68H 001B68H

001A69H 001B69H

001A6AH 001B6AH

001A6BH 001B6BH

001A6CH 001B6CH

001A6DH 001B6DH

001A6EH 001B6EH

001A6FH 001B6FH

001A70H 001B70H

001A71^H001B71H

001A72H 001B72H

001A73H 001B73H

001A74H 001B74H

001A75H 001B75H

001A76H 001B76H

001A77H 001B77H

001A78H 001B78H

001A79H 001B79H

001A7AH 001B7AH

001A7BH 001B7BH

001A7CH 001B7CH

001A7DH 001B7DH

001A7EH 001B7EH

001A7FH 001B7FH

001A80H 001B80H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

----XXXXB

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

XXXXXXXX^B

to

Data register 0 (8 bytes)

DTR0

R/W

001A87^H001B87^H

XXXXXXXX^B

(Continued)

32

DS07-13704-6E

MB90590G Series

(Continued)

Address

CAN0 CAN1

001A88^H001B88H

to to

Register

Abbreviation

Access

Initial Value

XXXXXXXX^B

to

Data register 1 (8 bytes)

DTR1

R/W

001A8F^H001B8F^H

XXXXXXXX^B

001A90H 001B90H

XXXXXXXX^B

to

XXXXXXXX^B

to

Data register 2 (8 bytes)

Data register 3 (8 bytes)

Data register 4 (8 bytes)

Data register 5 (8 bytes)

Data register 6 (8 bytes)

Data register 7 (8 bytes)

Data register 8 (8 bytes)

Data register 9 (8 bytes)

Data register 10 (8 bytes)

Data register 11 (8 bytes)

Data register 12 (8 bytes)

Data register 13 (8 bytes)

Data register 14 (8 bytes)

Data register 15 (8 bytes)

DTR2

DTR3

R/W

001A97^H001B97^H

001A98H 001B98H

XXXXXXXX^B

to

XXXXXXXX^B

to

001A9F^H001B9F^H

001AA0H 001BA0H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR4

001AA7^H001BA7^H

001AA8H 001BA8H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR5

001AAF^H001BAF^H

001AB0H 001BB0H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR6

001AB7^H001BB7^H

001AB8H 001BB8H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR7

001ABF^H001BBF^H

001AC0H 001BC0H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR8

001AC7^H001BC7^H

001AC8H 001BC8H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR9

001ACF^H001BCF^H

001AD0H 001BD0H

XXXXXXXX^B

to

XXXXXXXX^B

to

DTR10

DTR11

DTR12

DTR13

DTR14

DTR15

001AD7^H001BD7^H

001AD8H 001BD8H

XXXXXXXX^B

to

XXXXXXXX^B

to

001ADF^H001BDF^H

001AE0H 001BE0H

XXXXXXXX^B

to

XXXXXXXX^B

to

001AE7^H001BE7^H

001AE8H 001BE8H

XXXXXXXX^B

to

XXXXXXXX^B

to

001AEF^H001BEF^H

001AF0H 001BF0H

XXXXXXXX^B

to

XXXXXXXX^B

to

001AF7^H001BF7^H

001AF8H 001BF8H

XXXXXXXX^B

to

001AFF^H001BFF^H

XXXXXXXX^B

DS07-13704-6E

33

MB90590G Series

■ INTERRUPT MAP

Interrupt vector

Interrupt control register

EI²OS

clear

Interrupt cause

Number Address

Number

Address

Reset

N/A

*1

# 08

# 09

# 10

# 11

# 12

# 13

# 14

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

# 24

# 25

# 26

# 27

# 28

# 29

# 30

# 31

# 32

# 33

# 34

# 35

# 36

# 37

# 38

# 39

# 40

# 41

# 42

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

FFFF60H

FFFF5CH

FFFF58H

FFFF54H

⎯

INT9 instruction

Exception

Time Base Timer

External Interrupt (INT0 to INT7)

CAN 0 RX

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

DS07-13704-6E

N/A

*1

CAN 0 TX/NS

CAN 1 RX

CAN 1 TX/NS

8/16 bit PPG 0/1

8/16 bit PPG 2/3

8/16 bit PPG 4/5

8/16 bit PPG 6/7

8/16 bit PPG 8/9

8/16 bit PPG A/B

16-bit Reload Timer 0

16-bit Reload Timer 1

Input Capture 0/1

Output compare 0/1

Input Capture 2/3

Output Compare 2/3

Input Capture 4/5

Output Compare 4/5

8/10 bit A/D Converter

16-bit Free-run Timer/Watch Timer

Serial I/O

*1

N/A

*1

Sound Generator

UART 0 RX

N/A

*2

UART 0 TX

*1

UART 1 RX

*2

UART 1 TX

*1

UART 2 RX

*2

UART 2 TX

*1

Flash Memory

N/A

Delayed interrupt

34

MB90590G Series

*1 : The interrupt request flag is cleared by the EI²OS interrupt clear signal.

*2 : The interrupt request flag is cleared by the EI²OS interrupt clear signal. A stop request is available.

N/A : The interrupt request flag is not cleared by the EI²OS interrupt clear signal.

Notes : • For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are

cleared by the EI²OS interrupt clear signal.

• At the end of EI²OS, the EI²OS clear signal will be asserted for all the interrupt flags assigned to the same

interrupt number. If one interrupt flag starts the EI²OS and in the meantime another interrupt flag is set by a

hardware event, the later event is lost because the flag is cleared by the EI²OS clear signal caused by the

first event. So it is recommended not to use the EI²OS for this interrupt number.

• If EI²OS is enabled, EI²OS is initiated when one of the two interrupt signals in the same interrupt control

register (ICR) is asserted. This means that different interrupt sources share the same EI²OS Descriptor

which

should be unique for each interrupt source. For this reason, when one interrupt source uses the EI²OS, the

other interrupt should be disabled.

DS07-13704-6E

35

MB90590G Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Rating

Min Max

Parameter

Symbol

Unit

Remarks

V^CC

VSS − 0.3 VSS + 6.0

V

1

AV^CC

VCC = AVCC

*

Power supply voltage

AVRH,

AVRL

1

V^SS− 0.3 VSS + 6.0

V

AVCC ≥ AVRH/L, AVRH ≥ AVRL

VCC ≥ DVCC

*

DVCC

VI

VSS − 0.3 VSS + 6.0

V

2

Input voltage

*

2

Output voltage

VO

V

*

6

Max clamp current

ICLAMP

∑ | ICLAMP |

IOL1

−2.0

—

+ 2.0

mA

*

6

Total Max clamp current

20

*

3

“L” level Max output current

“L” level avg. output current

“L” level Max output current

“L” level avg. output current

“L” level Max overall output current

“L” level avg. overall output current

“H” level Max output current

“H” level avg. output current

“H” level Max output current

“H” level avg. output current

“H” level Max overall output current

“H” level avg. overall output current

—

15

mA Normal output

*

4

3

4

IOLAV1

IOL2

—

4

mA Normal output, average value

mA High current output

—

40

IOLAV2

—

30

mA High current output, average value

mA Total normal output

∑IOL1

—

100

330

50

∑IOL2

mA Total high current output

mA Total normal output, average value

mA Total high current output, average value

mA Normal output

5

∑IOLAV1

∑IOLAV2

IOH1

—

*

5

250

–15

–4

*

3

4

—

IOHAV1

IOH2

mA Normal output, average value

mA High current output

*

3

—

–40

–30

–100

–330

–50

–250

500

400

+85

+150

*

4

IOHAV2

∑IOH1

∑IOH2

∑IOHAV1

∑IOHAV2

—

mA High current output, average value

mA Total normal output

—

mA Total high current output

mA Total normal output, average value

mA Total high current output, average value

mW MB90F594G, MB90F591G

mW MB90594G, MB90591G

°C

5

—

*

—

*

—

PD

Power consumption

—

TA

Operating temperature

Storage temperature

–40

–55

TSTG

°C

*1 : AV^CC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC.

Also, AVRL shall not exceed AVRH.

*2 : V^Iand VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum

current to/from an input is limited by some means with external components, the I^CLAMPrating supersedes the

V^Irating.

*3 : The maximum output current is a peak value for a corresponding pin.

*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.

(Continued)

36

DS07-13704-6E

MB90590G Series

(Continued)

*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P70 to P77, P80 to P87, P90 toP95

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note thatifa+Bsignal isinputwhen the microcontrollerpower supplyisoff (not fixed at 0V), the powersupply is

provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins,

etc.) cannot accept +B signal input.

• Sample recommended circuits

• Input/Output equivalent circuits

Protective diode

VCC

P-ch

Limiting

resistance

+B input (0 V to 16 V)

N-ch

R

Note : Average output current = operating current × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS07-13704-6E

37

MB90590G Series

2. Recommended Conditions

(VSS = AVSS = 0.0 V)

Value

Typ

Symbol

Parameter

Unit

Remarks

Min

Max

4.5

5.0

5.5

V

Under normal operation

MB90V590G

MB90F594G

MB90594G

Maintains RAM data in

stop mode

3.0

4.75

3.0

—

5.0

—

5.5

VCC

AVCC

Power supply voltage

5.25

Under normal operation

MB90F591G

MB90591G

Maintains RAM data in

stop mode

Smooth capacitor

C^S

T^A

0.022

–40

0.1

—

1.0

µF

°C

*

Operating temperature

+85

* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be

connected to the V^CCpin must have a capacitance value higher than CS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

• C Pin Connection Diagram

C

C^S

38

DS07-13704-6E

MB90590G Series

3. DC Characteristics

(MB90V590G, MB90F594G, MB90594G : VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Parameter

Pin name

Condition

Unit

Remarks

Min

Typ

Max

CMOS hys-

teresis input

V^IHS

—

0.8 V^CC

VCC – 0.3

V^SS– 0.3

—

VCC +0.3

0.5VCC

V

Input H

voltage

V^IHMMD input

—

CMOS hys-

V^ILS

—

teresis input

Input L

voltage

V^ILMMD input

V^ILRRST, HST

—

VSS – 0.3

—

VSS + 0.3

0.2VCC

V

Normal

V^OH1

VCC = 4.5 V,

I^OH1= –4.0 mA

V^CC– 0.5

—

0.4

0.5

5

V

output

Output H

voltage

Highcurrent VCC = 4.5 V,

output

V^OH2

V^OL1

V^OL2

I^IL

V^CC– 0.5

I^OH2= –30.0 mA

Normal

output

VCC = 4.5 V,

I^OL1= 4.0 mA

—

–5

–1

V

Output L

voltage

Highcurrent VCC = 4.5 V,

output

V

I^OL2= 30.0 mA

Input leak

current

V^CC= 5.5 V,

—

µA

V^SS< V < VCC

I

Analog input

leak current

V^CC= 5.5 V,

AV^SS< VI < AVCC

I^IAL

AN0 to AN7

1

MB90594G

VCC = 5.0 V 10%,

Internal frequency :

16 MHz,

At normal opera-

tion.

—

37

50

45

13

15

0.3

0.35

5

60

80

60

20

23

0.6

20

mA

µA

MB90F594G

MB90F591G

MB90591G

MB90594G

MB90F594G

MB90F591G

MB90591G

MB90594G

MB90F594G

MB90F591G

MB90591G

MB90594G

MB90F594G

MB90F591G

MB90591G

I^CC

ICCS

ICTS

ICCH

VCC = 5.0 V 10%,

Internal frequency :

16 MHz,

At Sleep mode.

Power

supply

current *

VCC

VCC = 5.0 V 10%,

Internal frequency :

2 MHz,

At Timer mode

VCC = 5.0 V 10%,

At Stop mode,

TA = 25°C

5

µA

5

µA

5

µA

* : The power supply current testing conditions are when using the external clock.

DS07-13704-6E

(Continued)

39

MB90590G Series

(Continued)

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Parameter

Pin name

Condition

Unit

Remarks

Min

Typ

Max

Other than C,

AVCC, AVSS,

AVRH,

AVRL, V^CC,

VSS, DVCC,

DV^SS,

—

5

15

pF

Input

capacity

CIN

P70 to P87

—

15

50

30

pF

Pull-up

resistance

RST

R^UP

25

100

kΩ

Pull-down

resistance

R^DOWNMD2

—

25

50

100

kΩ

40

DS07-13704-6E

MB90590G Series

4. AC Characteristics

(1) Clock Timing

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

name

Parameter

Symbol

Unit

Remarks

Min Typ Max

Oscillation frequency

f^C

t^CYL

X0, X1

3

—

16

333

—

MHz

ns

Oscillation cycle time

X0, X1 62.5

Input clock pulse width

Input clock rise and fall time

Machine clock frequency

Machine clock cycle time

Flash read cycle time

P^WH, PWL

t^CR, tCF

f^CP

X0

—

10

—

ns Duty ratio is about 30 to 70%.

—

5

ns When using external clock

1.5

62.5

—

16

666

—

MHz

t^CP

—

ns

t^CYCFL

2 tCP

ns When Flash is accessed by CPU

• Clock Timing

tCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tCF

tCR

Example of Oscillation circuit

X0

X1

R

C2

C1

DS07-13704-6E

41

MB90590G Series

• Guaranteed operation range

Guaranteed operation range (MB90F591G, MB90591G)

Guaranteed operation range (MB90V590G, MB90F594G, MB90594G)

5.5

5.25

4.75

4.5

Guaranteed PLL operation range

(MB90F591G, MB90591G)

Power supply voltage

V^CC(V)

Guaranteed PLL operation range

(MB90V590G, MB90F594G, MB90594G)

3.0

1.5

8

16

Machine clock fCP (MHz)

• Oscillation clock frequency and machine clock frequency

×1

×4

×3

×2

16

12

Machine clock

f^CP(MHz)

9

8

×1/2

(PLL off)

4

3

4

8

16

Oscillation frequency f^C(MHz)

42

DS07-13704-6E

MB90590G Series

(2) Reset and Hardware Standby Input Timing

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Parameter

Pin name

Unit

Remarks

Min

Max

16 tCP*¹

—

ns Under normal operation

ms In stop mode

Reset input time

t^RSTL

RST

HST

Oscillation time of

oscillator*²+ 16 tCP*¹

—

Hardware standby input time

t^HSTL

16 tCP*¹

ns Under normal operation

*1 : “t^cp” represents one cycle time of the machine clock.

No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.

*2 : Oscillation time of oscillator is time that the amplitude reached the 90%.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the

oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.

Under Normal Operation

tRSTL, tHSTL

RST

HST

0.2 VCC

In Stop Mode

tRSTL

RST

0.2VCC

90% of

amplitude

X0

Internal operation clock

16 t^CP

Oscillation setting time

Oscillation time of

oscillator

Instruction execution

Internal reset

DS07-13704-6E

43

MB90590G Series

(3) Power On Reset

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Condition

Unit

Remarks

Min

0.05

50

Max

30

Power on rise time

Power off time

t^R

VCC

ms

—

t^OFF

—

ms Due to repetitive operation

Notes : • V^CCmust be kept lower than 0.2 V before power-on.

• The above values are used for creating a power-on reset.

• Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on

the power supply using the above values.

tR

2.7 V

V^CC

0.2 V

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to

raise the voltage smoothly to suppress fluctuations as shown below.

In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1

V or fewer per second, however, you can use the PLL clock.

VCC

It is recommended to keep the

rising speed of the supply voltage

at 50 mV/ms or slower.

3V

RAM data being held

VSS

44

DS07-13704-6E

MB90590G Series

(4) UART0/1/2, Serial I/O Timing

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min Max

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SCK0 to SCK3

8 t^CP*

—

ns

SCK0 to SCK3,

SOT0 to SOT3

SCK ↓ ⇒ SOT delay time

–80

80

Internal clock opera-

tion output pins are

C^L= 80 pF + 1 TTL.

SCK0 to SCK3,

SIN0 to SIN3

Valid SIN ⇒ SCK ↑

100

60

—

ns

SCK0 to SCK3,

SIN0 to SIN3

SCK ↑ ⇒ Valid SIN hold time

Serial clock "H" pulse width

Serial clock "L" pulse width

t^SHSL

t^SLSH

SCK0 to SCK3

4 t^CP

—

ns

4 tCP

SCK0 to SCK3,

SOT0 to SOT3

SCK ↓ ⇒ SOT delay time

Valid SIN ⇒ SCK ↑

t^SLOV

t^IVSH

t^SHIX

External clock oper-

ation output pins are

C^L= 80 pF + 1 TTL.

—

60

150

—

ns

SCK0 to SCK3,

SIN0 to SIN3

SCK0 to SCK3,

SIN0 to SIN3

SCK ↑ ⇒ Valid SIN hold time

—

* : t^CPis the machine cycle (Unit : ns)

Notes : • AC characteristic in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

SOT

0.8 V

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC

0.5 VCC

0.8 VCC

0.5 VCC

SIN

DS07-13704-6E

45

MB90590G Series

• External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC 0.8 VCC

SCK

0.5 VCC 0.5 VCC

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.5 VCC

0.8 VCC

0.5 VCC

(5)Timer Input Timing

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Condition

Unit

Remarks

Min

4 tCP

1

Max

—

t^TIWH

t^TIWL

TIN0

ns Under normal operation

Input pulse width

—

IN0 to IN5

—

µs In stop mode

• Timer Input Timing

0.8 VCC

0.5 VCC

tTIWH

tTIWL

46

DS07-13704-6E

MB90590G Series

(6)Trigger Input Timing

(MB90V590G, MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

t^TRGH

tTRGL

INT0 to

INT7, ADTG

Input pulse width

—

5 t^CP

—

ns

• Trigger Input Timing

0.8 VCC

0.5 VCC

tTRGH

tTRGL

(7) Slew Rate High Current Outputs (MB90F591G, MB90591G, MB90594G and MB90F594G only)

(MB90F594G, MB90594G : V^CC= 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G : V^CC= 5.0 V 5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

t^R2

tF2

Port P70 to P77,

Port P80 to P87

Output Rise/Fall time

—

15

40

ns

• Slew Rate Output Timing

VH

VH = VOL2 + 0.1 × (VOH2 − VOL2)

V^L= VOL2 + 0.9 × (VOH2 − VOL2)

VL

tR2

tF2

DS07-13704-6E

47

MB90590G Series

5. A/D Converter

(MB90V590G, MB90F594G, MB90594G :

V^CC= AVCC = 5.0 V 10 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)

(MB90F591G, MB90591G :

V^CC= AVCC = 5.0 V 5 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)

Value

Typ

—

Parameter

Symbol Pin name

Unit

Remarks

Min

—

Max

10

Resolution

—

bit

Conversion error

Nonlinearity error

—

5.0

2.5

LSB

—

Differential linearity

error

—

1.9

LSB

V

AVRL

Zero transition voltage

V^OT

V^FST

AN0 to AN7

– 3.5 LSB + 0.5 LSB + 4.5 LSB

AVRH AVRH AVRH

– 6.5 LSB – 1.5 LSB + 1.5 LSB

Full scale transition voltage

V

Internal

Compare time

Sampling time

—

352t^CP

64t^CP

—

ns

frequency :

16 MHz

Internal

frequency :

16 MHz

Analog port input current

Analog input voltage range

I^AIN

V^AIN

—

AN0 to AN7

AVRH

-1

—

5

+1

AVRH

AV^CC

µA

V

AVRL

AVRL + 2.7

V

Reference voltage range

Power supply current

—

AVRL

0

AVRH – 2.7

—

V

I^A

AVCC

—

mA

µA

I^AH

AVCC

—

5

*

MB90V590G

MB90F594G

MB90F591G

—

400

600

µA

I^R

AVRH

Reference voltage current

MB90594G

MB90591G

—

140

—

600

5

µA

I^RH

—

AVRH

*

Offset between input

channels

AN0 to AN7

—

4

LSB

* : When not operating A/D converter, this is the current (V^CC= AVCC = AVRH = 5.0 V) when the CPU is stopped.

48

DS07-13704-6E

MB90590G Series

6. A/D Converter Glossary

Resolution : Analog changes that are identifiable with the A/D converter

Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00

0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual

conversion characteristics

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error : The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

0.5 LSB

3FE

3FD

Actual conversion

value

{1 LSB × (N – 1) + 0.5 LSB}

004

003

002

001

VNT

(measured value)

Actual conversion

characteristics

Theoretical

characteristics

0.5 LSB

Analog input

AVRL

AVRH

AVRH – AVRL

1024

V^NT– {1 LSB × (N – 1) + 0.5 LSB}

1 LSB = (Theoretical value)

[V]

Total error for digital output N

[LSB]

=

1 LSB

VOT (Theoretical value) = AVRL + 0.5 LSB[V]

VFST (Theoretical value) = AVRH – 1.5 LSB[V]

VNT : Voltage at a transition of digital output from (N – 1) to N

(Continued)

DS07-13704-6E

49

MB90590G Series

(Continued)

Linearity error

Differential linearity error

Theoretical characteristics

3FF

Actual conversion

3FE

3FD

value

N + 1

Actual conversion value

{1 LSB × (N – 1)+ VOT}

V^FST

(measured value)

N

V^NT

(measured value)

004

003

002

001

V(N + 1)T

Actual conversion

characteristics

(measured value)

N – 1

N – 2

VNT (measured value)

Theoretical

Actual conversion

value

characteristics

V^OT(measured value)

Analog input

AVRL

AVRH

AVRL

Analog input

AVRH

Linearity error of

digital output N

V^NT– {1 LSB × (N – 1) + VOT}

[LSB]

=

1 LSB

V^{(N + 1)T}– VNT

1 LSB

Differential linearity error

of digital N

– 1 LSB [LSB]

=

V^FST– VOT

1 LSB

[V]

=

1022

V^OT: Voltage at transition of digital output from “000H” to “001H”

V^FST: Voltage at transition of digital output from “3FEH” to “3FFH”

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions, :

• Output impedance values of the external circuit of 15 kΩ or lower are recommended.

• When capacitors are connected to external pins, the capacitance of several thousand times the internal

capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor

and internal capacitor.

When the output impedance of the external circuit is too high, the sampling period for analog voltages may not

be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).

• Equipment of analog input circuit model

Analog input

Comparator

3.2 kΩ Max

30 pF Max

Note : Listed values must be considered as standards.

• Error

The smaller the | AVRH − AVRL |, the greater the error would become relatively.

50

DS07-13704-6E

MB90590G Series

8. Flash Memory

• Erase and Programming Performance

Value

Parameter

Sector erase time

Chip erase time

Condition

Unit

Remarks

Min

—

Typ Max

1

7

15

—

s

Excludes 00H programming prior erasure

—

MB90F594G

MB90F591G

Excludes 00H programming

prior erasure

T^A= + 25 °C

V^CC= 5.0 V

—

12

Word (16-bit)

programming time

—

16 3,600 ns Excludes system-level overhead

cycle

Erase/Program

cycle

—

10,000

—

DS07-13704-6E

51

MB90590G Series

■ EXAMPLE CHARACTERISTICS

• “H” Level Output Voltage

VOH1 – IOH1

VOH2 – IOH2

(Vcc = 4.5 V, TA = +25˚C)

5

4.5

4

5

4.5

4

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.0

-2.0

-4.0

-6.0

-8.0 -10.0

0

-10

-20

IOH2 [mA]

-30

-40

IOH1 [mA]

• “L” Level Output Voltage

V

OL2 – IOL2

V

OL1 – IOL1

(Vcc = 4.5 V, TA = +25˚C)

(Vcc = 4.5 V, T

A

= +25˚C)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

30.0

OL2 [mA]

0.0

10.0

20.0

40.0

0.0

2.0

4.0

6.0

8.0 10.0

I

OL1 [mA]

• “H” Level Input Voltage/“L Level Input Voltage

(Hysteresis Input)

V

IN – VCC

(TA = +25˚C)

5

4

3

2

1

0

V

IH

V

IL

3

4

5

6

Vcc [V]

(Continued)

52

DS07-13704-6E

MB90590G Series

(Continued)

• Power Supply Voltage

I

CC

–

V

CC

ICCS – VCC

(T = +25˚C)

A

(T

A

= +25˚C)

60

50

25

20

fcp = 16 MHz

40

30

20

10

0

15

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

10

5

fcp = 4 MHz

fcp = 2 MHz

6.0 7.0

0

2.0

3.0

4.0

V

5.0

CC [V]

2.0

3.0

4.0

VCC [V]

5.0

6.0

7.0

I

CCH

–

VCC

I

CTS – VCC

(T

A

=˚C)

(T

A

=˚C)

20

18

16

14

12

10

8

800

fcp =

700

600

500

fcp =

400

300

200

100

0

6

4

2

0

2.0

3.0

4.0

5.0

CC [V]

6.0

7.0

2.0

3.0

4.0

5.0

6.0

7.0

V

VCC [V]

DS07-13704-6E

53

MB90590G Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90594GPF

MB90F594GPF

MB90F591GPF

MB90591GPF

100-pin Plastic QFP

(FPT-100P-M06)

256-pin Ceramic PGA

(PGA-256C-A01)

MB90V590GCR

For evaluation

54

DS07-13704-6E

MB90590G Series

■ PACKAGE DIMENSION

100-pin plastic QFP

Lead pitch

0.65 mm

14.00 × 20.00 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ^–⁺⁰⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F100008S-c-5-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-13704-6E

55

MB90590G Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

Deleted the part numbers.

⎯

MB90591, MB90F591A, MB90594, MB90F594A, MB90V590A

Changed the series name.

MB90590/590G series → MB90590G series

⎯

17

35

⎯

Changed the following name.

I/O Timer → 16-bit Free-run Timer

Peripheral Resource name is changed.

Clock Timer → Watch Timer

one of Standby mode name is changed.

Clock mode → Watch mode

Changed the number of channels of 16-bit output compare.

4 ch → 6 ch

■ BLOCK DIAGRAM

Changed the abbreviation of Extended Intelligent I/O Service.

I²OS → EI²OS

■ INTERRUPT MAP

Changed the items of “Zero transition voltage” and “Full scale

transition voltage”.

mV → V

■ ELECTRICAL CHARACTERISTICS

5. A/D Converter

48

The vertical lines marked in the left side of the page show the changes.

56

DS07-13704-6E

MB90590G Series

MEMO

DS07-13704-6E

57

MB90590G Series

MEMO

58

DS07-13704-6E

MB90590G Series

MEMO

DS07-13704-6E

59

MB90590G Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Business & Media Promotion Dept.


型号：	MB90591G
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总60页 (文件大小：1247K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90591G [FUJITSU]

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