MB90337PMC_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13735-6E

16-bit Microcontroller

CMOS

F²MC-16LX MB90335 Series

MB90337/F337/V330A

■ DESCRIPTION

The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral

devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but

also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices

such as displays and audio devices, and control of mobile devices that support USB communications. While

inheriting the AT architecture of the F²MC* family, the instruction set supports the C language and extended

addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial

collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-

ducing a 32-bit accumulator.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock

• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)

• Clock for USB is 48 MHz

• Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable

• Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V^CC= 3.3 V)

• The maximum memory space: 16 Mbytes

• 24-bit addressing

• Bank addressing

(Continued)

For the information for microcontroller supports, see the following web site.

This web site includes the "Customer Design Review Supplement" which provides the latest cautions on

system development and the minimal requirements to be checked to prevent problems before the system

development.

http://edevice.fujitsu.com/micom/en-support/

2010.5

MB90335 Series

• Instruction system

• Data types: Bit, Byte, Word, Long word

• Addressing mode (23 types)

• Enhanced high-precision computing with 32-bit accumulator

• Enhanced Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multi-task

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• Priority levels are programmable

• 20 interrupts function

• Data transfer function

• Extended intelligent I/O service function (EI²OS) : Maximum of 16 channels

• μDMAC : Maximum 16 channels

• Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time-base timer mode (with the oscillator clock and time-base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

• Package

• LQFP-64P (FPT-64P-M23 : 0.65 mm pin pitch)

• Process : CMOS technology

• Operation guaranteed temperature: − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)

(Continued)

2

DS07-13735-6E

MB90335 Series

(Continued)

• Internal peripheral function (resource)

• I/O port : Max 45 ports

• Time-base timer : 1channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 1 channel

• Multi-functional timer

• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse are

freely programmable.

• 16-bit PWC timer : 1 channel

Timer function and pulse width measurement function

• UART: 2 channels

• Equipped with a full duplex (8-bit long) double buffer

• Selectable asynchronous transfer or clock-synchronous serial (extended I/O serial) transfer.

• Extended I/O serial interface : 1 channel

• DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

• Delayed interrupt output module

• Outputs an interrupt request for task switching

• USB: 1 channel

• USB function (supports USB Full Speed)

• Supports Full Speed/Up to 6 endpoints can be specified.

• Dual port RAM (supports FIFO mode).

• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible

• USB HOST function

• I²C Interface: 1 channel

• Supports Intel SM bus standards and Phillips I²C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

DS07-13735-6E

3

MB90335 Series

■ PRODUCT LINEUP

Part number

Type

MB90V330A

For evaluation

No

MB90F337

Built-in Flash Memory

MB90337

Built-in MASK ROM

ROM capacity

RAM capacity

64 Kbytes

28 Kbytes

4 Kbytes

Emulator-specific

power supply *

Used bit

⎯

Number of basic instructions : 351 instructions

Minimum instruction

execution time

Addressing type

: 41.7 ns / at oscillation of 6 MHz

(When 4 times are used : Machine clock of 24 MHz)

: 23 types

CPU functions

Program Patch Function

Maximum memory space

: For 2 address pointers

: 16 Mbytes

Ports

I/O Ports(CMOS) Max 45 ports

Equipped with full-duplex double buffer

Clock synchronous or asynchronous operation selectable.

It can also be used for I/O serial.

UART

Built-in special baud-rate generator

Built-in 2 channels

16-bit reload timer operation

Built-in 1 channel

16-bit reload timer

8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels)

16-bit PWC timer × 1 channel

Multi-functional timer

8 channels

DTP/External interrupt

I²C

Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable

1 channel

Extended I/O serial interface 1 channel

1 channel

USB

USB function (supports USB Full Speed)

USB HOST function

Withstand voltage of 5 V

8 ports (Excluding UTEST and I/O for I²C)

Low Power Consumption

Mode

Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode

Process

CMOS

Operating voltage V^CC

3.3 V 0.3 V (at maximum machine clock 24 MHz)

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to

theMB2147-01orMB2147-20hardwaremanual(3.3Emulator-dedicatedPowerSupplySwitching)aboutdetails.

■ PACKAGES AND PRODUCT MODELS

Package

FPT-64P-M23 (LQFP)

PGA-299C-A01 (PGA)

MB90337

MB90F337

MB90V330A

: Yes

: No

Note : See “■ PACKAGE DIMENSIONS” for details.

4

DS07-13735-6E

MB90335 Series

■ PIN ASSIGNMENT

(TOP VIEW)

UTEST

Vss

1

2

3

4

5

6

7

8

9

48 Vss

47 X1

DVM

DVP

Vcc

46 X0

45 P24/PPG0

44 P23

43 P22

42 P21

41 P20

40 P17

39 P16

38 P15

37 P14

36 P13

35 P12

34 P11

33 P10

Vss

HVM

HVP

Vcc

HCON 10

P42/SIN0 11

P43/SOT0 12

P44/SCK0 13

P45/SIN1 14

P46/SOT1 15

P47/SCK1 16

(FPT-64P-M23)

DS07-13735-6E

5

MB90335 Series

■ PIN DESCRIPTION

I/O

Circuit

type*

Status at

reset/

function

Pin no.

Pin name

Function

It is a terminal which connects the oscillator.

When connecting an external clock, leave the X1 pin side

unconnected.

Oscillation

status

46 , 47

23

X0, X1

RST

A

F

Reset input External reset input pin.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor

(RD00 to RD07 = 1) by the pull-up resistor setting register

(RDR0). (When the power output is set, it is invalid.)

25 to 32

33 to 40

P00 to P07

P10 to P17

I

General purpose input/output port.

The ports can be set to be added with a pull-up resistor

(RD10 to RD17 = 1) by the pull-up resistor setting register

(RDR1). (When the power output is set, it is invalid.)

41 to 44

45

P20 to P23

P24

D

General purpose input/output port.

PPG0

P25 to P27

PPG1 to PPG3

P40

Functions as output pins of PPG timers ch.0.

General purpose input/output port.

51 to 53

62

D

H

Functions as output pins of PPG timers ch.1 to ch.3.

General purpose input/output port.

TIN0

Function as event input pin of 16-bit reload timer.

General purpose input/output port.

P41

63

TOT0

P42

Function as output pin of 16-bit reload timer.

General purpose input/output port.

Port input

(Hi-Z)

11

SIN0

Functions as a data input pin for UART ch.0.

General purpose input/output port.

P43

12

SOT0

P44

Functions as a data output pin for UART ch.0.

General purpose input/output port.

13

SCK0

P45

Functions as a clock I/O pin for UART ch.0.

General purpose input/output port.

14

SIN1

Functions as a data input pin for UART ch.1.

General purpose input/output port.

P46

15

SOT1

P47

Functions as a data output pin for UART ch.1.

General purpose input/output port.

16

SCK1

P50

Functions as a clock I/O pin for UART ch.1.

General purpose input/output port.

50

64

K

P51

General purpose input/output port.

17, 18

24

P52, P53

P54

General purpose input/output port.

(Continued)

6

DS07-13735-6E

MB90335 Series

(Continued)

I/O

Pin name Circuit

type*

Status at

reset/

function

Pin no.

Function

P60, P61

C

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.0 and ch.1.

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.2.

Data input pin for extended I/O serial interface.

54, 55

56

INT0, INT1

P62

INT2

SIN

C

P63

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.3.

Data output pin for extended I/O serial interface.

57

58

59

INT3

SOT

P64

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.4.

Clock I/O pin for extended I/O serial interface.

INT4

SCK

P65

Port input

(Hi-Z)

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.5.

Functions as the PWC input pin.

INT5

PWC

P66

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.6.

INT6

60

C

Functions as the input/output pin for I²C interface clock. The port

output must be placed in Hi-Z state during I²C interface

operation.

SCL0

P67

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.7.

INT7

61

1

C

Functions as the I²C interface data input/output pin. The port out-

SDA0

put must be placed in Hi-Z state during I²C interface operation.

UTEST

input

USB test pin.

UTEST

Connect this to a pull-down resistor during normal usage.

3

DVM

DVP

J

USB function D − pin.

USB function D + pin.

USB HOST D − pin.

USB HOST D + pin.

4

7

USB input

(SUSPEND)

HVM

J

8

HVP

J

10

HCON

MD1, MD0

MD2

E

B

G

High output External pull-up resistor connection pin.

21, 22

20

Mode input Input pin for selecting operation mode.

5, 9, 49

Vcc

Power supply pin.

Power

⎯

2, 6,

19, 48

supply

Vss

Power supply pin (GND).

* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.

DS07-13735-6E

7

MB90335 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillation feedback resistor of

approx. 1 MΩ

• With standby control

X1

X0

Clock input

Standby control signal

B

C

CMOS hysteresis input

CMOS hysteresis

input

• CMOS hysteresis input

• N-ch open drain output

N-ch

Nout

CMOS hysteresis input

Standby control signal

D

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

Pout

Nout

Notes : • Share one output buffer because

both output of I/O port and

internal resource are used.

• Share one input buffer because

both input of I/O port and internal

resource are used.

CMOS hysteresis input

Standby control signal

E

CMOS output

P-ch

N-ch

Pout

Nout

F

CMOS hysteresis input with pull-up

resistor of approx. 50 kΩ

R

CMOS hysteresis

input

G

• CMOS hysteresis input with pull-down

resistor of approx. 50 kΩ

• Flash product is not provided with pull-

CMOS hysteresis

input

R

down resistor.

(Continued)

8

DS07-13735-6E

MB90335 Series

(Continued)

Type

Circuit

Remarks

H

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Open drain control

signal

P-ch

N-ch

Pout

Nout

With open drain control signal

CMOS hysteresis input

Standby control signal

I

• CMOS output

• CMOS input

(With input interception function at

standby)

• Programmable input pull-up resistor

Control signal

R

P-ch

N-ch

Pout

Nout

CMOS input

Standby control signal

D + input

J

USB I/O pin

D - input

+

D

Differential input

−

D

Full D + output

Full D - output

Low D + output

Low D - output

Direction

Speed

K

• CMOS output

• CMOS input

(With input interception function at

standby)

P-ch

N-ch

Pout

Nout

CMOS input

Standby control signal

DS07-13735-6E

9

MB90335 Series

■ HANDLING DEVICES

1. Preventing latch-up and turning on power supply

latch-up may occur on CMOS IC under the following conditions:

• If a voltage higher than V^CCor lower than VSS is applied to input and output pins.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOS IC, take great care to prevent the occurrence of latch-up.

2. Treatment of unused pins

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent dam-

age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused

input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused

input pins. If there is unused output pin, make it to open.

3. About the attention when the external clock is used

Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or

when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper

frequency limit.

The following figure shows a sample use of external clock signals.

• Using external clock

X0

OPEN

X1

4. Treatment of power supply pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between V^CCand VSS pins

near this device.

5. About crystal oscillator circuit

Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that

X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to

the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane

because stable operation can be expected with such a layout.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

6. Caution on Operations during PLL Clock Mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while

the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its

self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

10

DS07-13735-6E

MB90335 Series

7. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage

operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations

(peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply

voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply

switching.

8. Writing to flash memory

For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.

For normal writing to flash memory, always make sure that the operating voltage V^CCis between 3.0 V and 3.6 V.

9. Serial communication

There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,

design a printed circuit board so as to avoid noise.

Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.

If an error is detected, retransmit the data.

DS07-13735-6E

11

MB90335 Series

■ BLOCK DIAGRAM

X0, X1

RST

MD0 to MD2

F²MC-16LX

CPU

Clock control

circuit

Interrupt

controller

8/16-bit PPG

timer

ch.0 to ch.3*

PPG0 to PPG3

PWC

RAM

ROM

16-bit PWC

SIN0, SIN1

SOT0, SOT1

SCK0, SCK1

UART/SIO

ch.0, ch.1

SIN

SOT

SCK

SIO

SCL0

SDA0

I²C

μDMAC

16-bit reload

timer

TOT0

TIN0

DVP

DVM

HVP

HVM

HCON

UTEST

USB

(function)

(HOST)

External interrupt

INT0 to INT7

I/O port (port 0, 1, 2, 4, 5, 6)

P00

P07

P10

P17

P20

P27

P40

P47

P50

P54

P60

P67

* : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode.

Note : I/O ports share pins with peripheral function (resources) .

For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.

Note also that pins used for peripheral function (resources) cannot serve as I/O ports.

12

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MB90335 Series

■ MEMORY MAP

Single chip mode (with ROM mirror function)

MB90V330A

MB90F337

MB90337

FFFFFF

H

FFFFFF

H

FFFFFF

H

ROM (FF bank)

FF0000

00FFFF

H

00FFFF

H

00FFFF

H

ROM area

(image of FF bank)

ROM area

(image of FF bank)

ROM area

(image of FF bank)

008000

007FFF

H

008000

H

008000

H

007FFF

Peripheral area

007900

007100

H

007900

H

007900

H

RAM area

(28 Kbytes)

001100

H

001100

H

RAM area

(4 Kbytes)

RAM area

(4 Kbytes)

Register

000100

H

000100

H

000100

H

0000FB

Peripheral area

000000

H

000000

H

000000

H

Notes : • WhentheROMmirror functionregisterhasbeenset,themirrorimagedataathigheraddresses(“FF8000H

to FFFFFFH” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

• The ROM mirror function is effective for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in

bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be

reproduced in bank 00.

• When the C compiler small model is used, the data table mirror image can be shown at “008000^Hto

00FFFFH” by storing the data table at “FF8000H to FFFFFFH”.

Therefore, data tables in the ROM area can be referred without declaring the far addressing with

the pointer.

DS07-13735-6E

13

MB90335 Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated register

Accumulator

AH

AL

User stack pointer

System stack pointer

Processor status

Program counter

USP

SSP

PS

PC

Direct page register

DPR

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8-bit

16-bit

32-bit

• General purpose registers

MSB

LSB

16-bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

R1

R0

R2

R4

R6

RW4

RW5

RW6

RW7

RL2

RL3

R3

R5

R7

• Processor status

Bit 15

PS

13 12

ILM

8 7

0

RP

CCR

14

DS07-13735-6E

MB90335 Series

■ I/O MAP

Register

Read/

Write

Address

Register

Port 0 Data Register

Resource name

Initial Value

abbreviation

000000^H

000001H

000002H

000003H

000004^H

000005H

000006H

PDR0

R/W

Port 0

Port 1

Port 2

XXXXXXXXB

PDR1

Port 1 Data Register

Port 2 Data Register

PDR2

Prohibited

PDR4

PDR5

PDR6

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

R/W

Port 4

Port 5

Port 6

XXXXXXXXB

- - - XXXXXB

XXXXXXXXB

000007H

to

00000F^H

000010^H

000011H

000012H

000013H

000014^H

000015H

000016H

DDR0

DDR1

DDR2

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

R/W

Port 0

Port 1

Port 2

0 0 0 0 0 0 0 0B

DDR4

DDR5

DDR6

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

R/W

Port 4

Port 5

Port 6

0 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

0 0 0 0 0 0 0 0B

000017H

to

00001AH

Port 4 (Open-drain

control)

00001B^H

ODR4

Port 4 Output Pin Register

R/W

0 0 0 0 0 0 0 0B

00001CH

00001DH

00001EH

00001F^H

000020H

000021H

RDR0

RDR1

Port 0 Pull-up Resistance Register

Port 1 Pull-up Resistance Register

R/W

Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B

Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B

Prohibited

SMR0

SCR0

Serial Mode Register 0

R/W

R

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Serial Control Register 0

SIDR0

SODR0

SSR0

Serial Input Data Register 0

Serial Output Data Register 0

Serial Status Register 0

UART0

000022H

XXXXXXXX^B

W

000023^H

000024H

000025H

000026H

000027H

R/W

R

0 0 0 0 1 0 0 0B

UTRLR0

UTCR0

SMR1

UART Prescaler Reload Register 0

UART Prescaler Control Register 0

Serial Mode Register 1

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Communication

Prescaler(UART0)

SCR1

Serial Control Register 1

SIDR1

SODR1

SSR1

Serial Input Data Register 1

Serial Output Data Register 1

Serial Status Register 1

UART1

000028H

000029^H

XXXXXXXX^B

W

R/W

0 0 0 0 1 0 0 0B

(Continued)

DS07-13735-6E

15

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

00002A^H

00002BH

UTRLR1

UTCR1

UART Prescaler Reload Register 1

UART Prescaler Control Register 1

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

Communication

Prescaler(UART1)

00002CH

to

Prohibited

00003BH

00003C^H

00003DH

00003EH

00003FH

ENIR

EIRR

DTP/Interrupt Enable Register

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

DTP/Interrupt source Register

DTP/External

interrupt

Request Level Setting Register Lower

Request Level Setting Register Upper

ELVR

000040H

to

Prohibited

000045^H

000046^H

000047H

000048H

000049H

00004AH

00004B^H

00004CH

00004DH

00004E^H

PPGC0

PPGC1

PPGC2

PPGC3

PPG0 Operation Mode Control Register R/W

PPG1 Operation Mode Control Register R/W

PPG2 Operation Mode Control Register R/W

PPG3 Operation Mode Control Register R/W

PPG ch.0

PPG ch.1

PPG ch.2

PPG ch.3

0X0 0 0XX1B

0X0 0 0 0 0 1B

0X0 0 0XX1B

0X0 0 0 0 0 1B

Prohibited

PPG01

PPG23

PPG0 and PPG1 Output Control Register R/W

Prohibited

PPG ch.0/ch.1

0 0 0 0 0 0XXB

PPG2 and PPG3 Output Control Register R/W

PPG ch.2/ch.3 0 0 0 0 0 0 XXB

00004FH

to

Prohibited

000057H

000058^H

000059H

00005AH

XXXX0 0 0 0^B

SMCS

Serial Mode Control Status Register

Serial Data Register

R/W

Extended Serial

0 0 0 0 0 0 1 0B

I/O

SDR

R/W

XXXXXXXXB

Communication Prescaler Control

Register

Communication

0XXX0 0 0 0B

Prescaler

00005BH

SDCR

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062^H

000063H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 XB

PWCSR

PWC Control Status Register

R/W

16-bit

PWC Timer

0 0 0 0 0 0 0 0^B

PWCR

DIVR

PWC Data Buffer Register

R/W

0 0 0 0 0 0 0 0B

- - - - - - 0 0B

PWC Dividing Ratio Control Register

Prohibited

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0B

TMCSR0

Timer Control Status Register

R/W

TMR0

TMRLR0

TMR0

16-bit Timer Register Lower

16-bit Reload Register Lower

16-bit Timer Register Upper

16-bit Reload Register Upper

R

W

R

XXXXXXXXB

(Continued)

16-bit Reload

Timer

000064H

000065H

TMRLR0

W

16

DS07-13735-6E

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

000066^H

to

Prohibited

00006EH

ROM Mirror

Function

Selection Module

ROM Mirroring Function Selection

Register

00006F^H

ROMM

W

- - - - - - 1 1B

000070H

000071H

000072H

000073H

000074H

IBSR0

IBCR0

ICCR0

IADR0

IDAR0

I²C Bus Status Register

I²C Bus Control Register

I²C Bus Clock Control Register

I²C Bus Address Register

I²C Bus Data Register

R

0 0 0 0 0 0 0 0B

R/W

R/W I²C Bus Interface XX 0 XXXXXB

R/W

XXXXXXXXB

000075H

to

Prohibited

00009AH

DMA Descriptor Channel Specification

Register

00009B^H

DCSR

R/W

0 0 0 0 0 0 0 0B

μDMAC

00009CH

00009DH

DSRL

DSRH

DMA Status Register Lower

DMA Status Register Upper

R/W

0 0 0 0 0 0 0 0B

Program Address Detection Control

Status Register

Address Match

Detection

00009EH

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0B

Delayed Interrupt Source generate/

release Register

R/W Delayed Interrupt - - - - - - - 0B

Low Power

Low Power Consumption Mode Control

Register

0000A0H

LPMCR

CKSCR

R/W

Consumption

control circuit

0 0 0 1 1 0 0 0B

1 1 1 1 1 1 0 0B

0000A1H

0000A2H

0000A3^H

0000A4H

Clock Selection Register

Prohibited

Clock

DSSR

DMA Stop Status Register

R/W

μDMAC

0 0 0 0 0 0 0 0B

0000A5H

to

Prohibited

0000A7H

0000A8^H

0000A9H

0000AAH

0000AB^H

0000ACH

0000ADH

0000AEH

0000AFH

WDTC

TBTC

Watchdog Timer Control Register

Time-base Timer Control Register

R/W Watchdog Timer X - XXX 1 1 1B

R/W Time-base Timer 1 - - 0 0 1 0 0B

Prohibited

DERL

DERH

FMCS

DMA Enable Register Lower

DMA Enable Register Upper

Flash Memory Control Status Register

Prohibited

R/W

0 0 0 0 0 0 0 0B

μDMAC

R/W Flash Memory I/F 0 0 0 X 0 0 0 0B

(Continued)

DS07-13735-6E

17

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

0000B0^H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

HCNT0

HCNT1

HIRQ

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

Host Control Register 0

R/W

0 0 0 0 0 1 1 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 1 1B

XX 0 1 0 0 1 0B

Interrupt

Controller

Host Control Register 1

Host Interruption Register

Host Error Status Register

Host State Status Register

HERR

HSTATE

SOF Interrupt FRAME Compare Reg-

ister

0000C5H

HFCOMP

R/W

0 0 0 0 0 0 0 0B

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0^H

0000D1H

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXX 0 0B

X 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XX 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XXXXX 0 0 0B

0 0 0 0 0 0 0 0B

USB HOST

HRTIMER

Retry Timer Setting Register

HADR

HEOF

Host Address Register

EOF Setting Register

HFRAME

HTOKEN

FRAME Setting Register

Host Token End Point Register

Prohibited

R/W

1 0 1 0 0 0 0 0B

0 0 0 0 0 0 0 0B

(Continued)

UDCC

UDC Control Register

USB Function

18

DS07-13735-6E

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

0000D2^H

0000D3H

0000D4H

0000D5H

0000D6H

0000D7H

0000D8H

0000D9H

0000DAH

0000DBH

0000DCH

0000DDH

0000DEH

0000DFH

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

0000E7H

0000E8H

0000E9H

0000EAH

0000EBH

0000ECH

0000EDH

0000EEH

0000EFH

0000F0H

0000F1H

0000F2H

0000F3H

0000F4H

0000F5H

0000F6H

0000F7H

0000F8H

0000F9H

R/W

R

0 1 0 0 0 0 0 0^B

XXXX 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 1 1 0 0 0 0 1B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XXXXX0 0 0B

XX0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 XXX 1 XXB

0 XXXXXXX^B

1 0 0 XX 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

EP0C

EP1C

EP2C

EP3C

EP4C

EP5C

TMSP

EP0 Control Register

EP1 Control Register

EP2 Control Register

EP3 Control Register

EP4 Control Register

EP5 Control Register

Time Stamp Register

R

UDCS

UDCIE

UDC Status Register

R/W

R/W, R

R/W

R

UDC Interrupt Enable Register

EP0IS

EP0OS

EP1S

EP0I Status Register

EP0O Status Register

EP1 Status Register

EP2 Status Register

EP3 Status Register

EP4 Status Register

EP5 Status Register

EP0 Data Register

EP1 Data Register

EP2 Data Register

EP3 Data Register

EP4 Data Register

USB Function

R/W

R

EP2S

R/W

R

EP3S

R/W

R

EP4S

R/W

R

EP5S

R/W

EP0DT

EP1DT

EP2DT

EP3DT

EP4DT

DS07-13735-6E

19

MB90335 Series

Register

Address

Read/

Write

Register

EP5 Data Register

Resource name

Initial Value

abbreviation

0000FA^H

R/W

XXXXXXXXB

EP5DT

USB Function

0000FBH

0000FCH

to

0000FFH

Prohibited

RAM Area

000100H

to

001100H

Program Address Detection Register

ch.0 Lower

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

R/W

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Program Address Detection Register

ch.0 Middle

PADR0

PADR1

Program Address Detection Register

ch.0 Upper

Address Match

Detection

Program Address Detection Register

ch.1 Lower

Program Address Detection Register

ch.1 Middle

Program Address Detection Register

ch.1 Upper

007900H

007901H

007902H

007903H

007904H

007905H

007906H

007907H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PPG Reload Register Lower ch.0

PPG Reload Register Upper ch.0

PPG Reload Register Lower ch.1

PPG Reload Register Upper ch.1

PPG Reload Register Lower ch.2

PPG Reload Register Upper ch.2

PPG Reload Register Lower ch.3

PPG Reload Register Upper ch.3

R/W

XXXXXXXXB

PPG ch.0

PPG ch.1

PPG ch.2

PPG ch.3

007908H

to

Prohibited

00790BH

Flash Memory Program Control

Register 0

00790CH

FWR0

R/W

Flash

0 0 0 0 0 0 0 0B

Flash Memory Program Control

Register 1

00790DH

00790EH

FWR1

SSR0

R/W

Flash

0 0 0 0 0 0 0 0B

0 0 XXXXX0B

Sector Conversion Setting Register

00790FH

to

Prohibited

00791FH

(Continued)

20

DS07-13735-6E

MB90335 Series

(Continued)

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

007920^H

007921H

007922H

007923H

DBAPL

DBAPM

DBAPH

DMACS

DMA Buffer Address Pointer Lower 8-bit R/W

DMA Buffer Address Pointer Middle 8-bit R/W

DMA Buffer Address Pointer Upper 8-bit R/W

XXXXXXXXB

DMA Control Register

R/W

DMA I/O Register Address Pointer Lower

8-bit

μDMAC

007924H

007925H

DIOAL

DIOAH

R/W

XXXXXXXXB

DMA I/O Register Address Pointer

Upper 8-bit

R/W

007926H

007927H

DDCTL

DDCTH

DMA Data Counter Lower 8-bit

DMA Data Counter Upper 8-bit

R/W

XXXXXXXXB

007928H

to

Prohibited

007FFFH

• Explanation on read/write

R/W : Readable and Writable

R

W

: Read only

: Write only

• Explanation of initial values

0

1

X

-

: Initial value is “0”.

: Initial value is “1”.

: Initial value is undefined.

: Initial value is undefined (None).

Note : No I/O instruction can be used for registers located between 007900^Hand 007FFFH.

DS07-13735-6E

21

MB90335 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt control

EI²OS

Interrupt vector

Address

08H FFFFDCH

register

Interrupt source

μDMAC

Priority

support

Number*¹

ICR Address

Reset

×

#08

#09

#10

#11

⎯

High

INT 9 instruction

09^HFFFFD8H

0A^HFFFFD4H

0B^HFFFFD0H

0CH FFFFCCH

0DH FFFFC8H

0EH FFFFC4H

0FH FFFFC0H

10H FFFFBCH

Exceptional treatment

×

USB Function1

0, 1

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

USB Function2

2 to 6*²#12

USB Function3

×

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

USB Function4

USB HOST1

×

USB HOST2

I²C ch.0

×

11H

12H

13H

FFFFB8H

FFFFB4H

FFFFB0H

DTP/External interrupt ch.0/ch.1

×

No

⎯

×

DTP/External interrupt ch.2/ch.3

14H FFFFACH

No

⎯

×

15H

16H

17H

FFFFA8H

FFFFA4H

FFFFA0H

DTP/External interrupt ch.4/ch.5

PWC/Reload timer ch.0

14

×

DTP/External interrupt ch.6/ch.7

18H FFFF9CH

No

⎯

×

⎯

×

19H

1AH

1BH

FFFF98H

FFFF94H

FFFF90H

No

1CH FFFF8CH

1DH FFFF88H

No

PPG ch.0/ch.1

1EH

1FH

FFFF84H

FFFF80H

No

⎯

×

⎯

×

PPG ch.2/ch.3

20H FFFF7CH

No

⎯

13

9

21H

22H

23H

FFFF78H

FFFF74H

FFFF70H

No

24H FFFF6CH

UART (Send completed) ch.0/ch.1

Extended serial I/O

25H

26H

FFFF68H

FFFF64H

×

UART(Reception completed)

ch.0/ch.1

12

#39

27H

FFFF60H

ICR14 0000BEH

ICR15 0000BFH

Time-base timer

×

#40

#41

#42

28H FFFF5CH

Flash memory status

Delay interrupt output module

29H

2AH

FFFF58H

FFFF54H

Low

(Continued)

22

DS07-13735-6E

MB90335 Series

(Continued)

: Available. EI²OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

With a stop request).

: Available (The interrupt request flag is cleared by the interrupt clear signal).

: Available when any interrupt source sharing ICR is not used.

× : Unavailable

*1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has

priority.

*2 : Ch.2 and ch.3 can be used in USB HOST operation.

Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI²OS is permitted,

the EI²OS is activated when either of the factors is detected. As any interrupt other than the activation

factor is masked while the EI²OS is running, it is recommended that you should mask either of the interrupt

requests when using the EI²OS.

• The interrupt flag is cleared by the EI²OS interrupt clear signal for the resource that has two interrupt

factors in the same interrupt control register (ICR).

• Ifaresourcehastwointerruptsourcesforthesameinterruptnumber, bothoftheinterruptrequestflagsare

cleared by the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the

DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “ 0 ” in the

appropriate resource, and take measures by software polling.

■ CONTENT OF USB INTERRUPTION FACTOR

USB interrupt factor

USB function 1

USB function 2

USB function 3

USB function 4

USB HOST1

Details

End Point 0-IN, End Point 0-OUT

End Point 1-5 *

SUSP, SOF, BRST, WKOP, COHF

SPIT

DIRQ, CHHIRQ, URIRQ, RWKIRQ

SOFIRQ, CMPIRQ

USB HOST2

* : End Point 1and 2 can be used in USB HOST operation.

DS07-13735-6E

23

MB90335 Series

■ USB

1. USB Function

The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.

Features of USB function

• Supports USB Full Speed

• Supports full speed (12 Mbps).

• The device status is auto-answer.

• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.

• Toggle check by data synchronization bit.

• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these

three commands can be processed the same way as the class vendor commands).

• The class vendor commands can be received as data and responded via firmware.

• Supports up to a maximum of six EndPoints (EndPoint0 is fixed to control transfer).

• Two built-in transfer data buffers for each end point (one IN buffer and one OUT buffer for end point 0).

• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).

24

DS07-13735-6E

MB90335 Series

2. USB HOST

USB HOST provides minimal host operations required and is a function that enables data to be transferred

between devices without PC intervention.

• Features of USB HOST

• Automatic detection of Low Speed/Full Speed transfer

• Low Speed/Full Speed transfer support

• Automatic detection of connection and cutting device

• Reset sending function support to USB-bus

• Support of IN/OUT/SETUP/SOF token

• In-token handshake packet automatic transmission (excluding STALL)

• Handshake packet automatic detection at out-token

• Supports a maximum packet length of 256 bytes

• Error (CRC error/toggle error/time-out) various supports

• Wake-Up function support

• Restrictions on USB HOST

USB HOST

HUB support

Transfer

*

Bulk transfer

Control transfer

Interrupt transfer

Isochronous transfer

Low Speed

×

Transfer speed

Full Speed

PRE packet support

SOF packet support

CRC error

Toggle error

Error

Time-out

Maximum packet < receive data

Detection of connection and cutting of device

Transfer speed detection

: Supported

×

: Not supported

* : Only supports full speed, and supports hubs up to one level.

DS07-13735-6E

25

MB90335 Series

■ SECTOR CONFIGURATION OF FLASH MEMORY

512 Kbits flash memory is located in FF^Hbank in the CPU memory map.

Flash Memory CPU address Writer address *

FF0000^H

FF0FFFH

FF1000H

FF1FFFH

FF2000H

FF2FFFH

FF3000^H

FF3FFFH

FF4000H

FF7FFFH

FF8000H

FFBFFFH

FFC000H

FFCFFFH

FFD000^H

FFDFFFH

FFE000H

FFEFFFH

FFF000H

FFFFFFH

70000H

70FFFH

71000H

71FFFH

72000H

72FFFH

73000H

73FFFH

74000H

77FFFH

78000H

7BFFFH

7C000H

7CFFFH

7D000H

7DFFFH

7E000H

7EFFFH

7F000H

7FFFFH

SA0 (4 Kbytes)

SA1 (4 Kbytes)

SA2 (4 Kbytes)

SA3 (4 Kbytes)

SA4 (16 Kbytes)

SA5 (16 Kbytes)

SA6 (4 Kbytes)

SA7 (4 Kbytes)

SA8 (4 Kbytes)

SA9 (4Kbytes)

* : Flash memory writer address indicates the address equivalent to the CPU address when data is written

to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel

programmer are executed based on writer addresses.

26

DS07-13735-6E

MB90335 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

Power supply voltage*¹

VCC

VSS − 0.3

VSS + 4.0

V

*2

N-ch open-drain

Input voltage*¹

VI

V^SS− 0.3

VSS + 6.0

V

(Withstand voltage I/O of 5 V)*³

− 0.5

VSS − 0.3

− 0.5

VSS + 4.5

VSS + 4.0

V^SS+ 4.5

+2.0

V

USB I/O

*2

Output voltage*¹

VO

V

USB I/O

*4

Maximum clamp current

I^CLAMP

− 2.0

mA

Total maximum clamp

current

Σ⏐I^CLAMP⏐

⎯

20

mA

*4

I^OL1

IOL2

⎯

10

43

4

mA

Other than USB I/O*⁵

USB I/O*⁵

“L” level maximum output

current

I^OLAV1

*6

“L” level average output

current

USB-IO

I^OLAV2

ΣIOL

⎯

15/4.5

100

mA

(Full speed/Low speed) *⁶

“L” level maximum total

output current

“L” level average total

output current

ΣI^OLAV

50

*7

I^OH1

IOH2

⎯

− 10

− 43

− 4

mA

Other than USB I/O*⁵

USB I/O*⁵

“H” level maximum output

current

I^OHAV1

*6

“H” level average output

current

USB-IO

I^OHAV2

ΣIOH

⎯

−15/−4.5

− 100

mA

(Full speed/Low speed) *⁶

“H” level maximum total

output current

“H” level average total

output current

ΣI^OHAV

− 50

*7

Power consumption

Pd

T^A

⎯

270

+ 85

mW

°C

Operating temperature

− 40

− 55

+ 150

+ 125

°C

Storage temperature

Tstg

°C

USB I/O

*1 : The parameter is based on VSS = 0.0 V.

*2 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some

means with external components, the ICLAMP rating supersedes the VI rating.

*3 : Applicable to pins : P60 to P67, UTEST

(Continued)

DS07-13735-6E

27

MB90335 Series

(Continued)

*4 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P54

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than P60 to P67, DVP, DVM, HVP, HVM, UTEST, HCON

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

N-ch

+B input (0 V to 16 V)

R

*5 : A peak value of an applicable one pin is specified as a maximum output current.

*6 : The average output current specifies the mean value of the current flowing in the relevant single pin during a

period of 100 ms.

*7 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins

during a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

28

DS07-13735-6E

MB90335 Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V

At normal operation (When using USB)

At normal operation (When not using USB)

Hold state of stop operation

CMOS input pin

Power supply voltage

V^CC

2.7

3.6

1.8

V^IH

0.7 VCC

0.8 VCC

VCC + 0.3

V^IHS1

CMOS hysteresis input pin

N-ch open-drain

(Withstand voltage I/O of 5 V)*

Input “H” voltage

Input “L” voltage

V^IHS2

0.8 VCC

VSS + 5.3

V

VIHM

VIHUSB

V^IL

VCC − 0.3

2.0

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

0.8

V

MD pin input

USB pin input

VSS − 0.3

VSS

CMOS input pin

CMOS hysteresis input pin

MD pin input

V^ILS

VILM

VILUSB

USB pin input

Differential input

sensitivity

V^DI

0.2

0.8

⎯

V

USB pin input

Differential common

mode input voltage

range

VCM

2.5

V

USB pin input

− 40

+ 85

+ 70

°C

When not using USB

When using USB

Operating

temperature

T^A

0

* : Applicable to pins : P60 to P67, UTEST

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

DS07-13735-6E

29

MB90335 Series

3. DC Characteristics

Sym-

(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Parameter

Pin name

Conditions

Unit Remarks

bol

Min

Typ

Max

Output pins other

than P60 to P67,

HVP, HVM, DVP,

DVM

VCC − 0.5

I^OH= −4.0 mA

⎯

Vcc

V

Output “H”

voltage

V^OH

HVP, HVM, DVP,

DVM

R^L= 15 kΩ 5%

2.8

Vss

0

⎯

3.6

Vss + 0.4

0.3

V

Output pins other

than HVP, HVM, DVP, I^OL= 4.0 mA

DVM

Output “L”

voltage

V^OL

HVP, HVM, DVP,

DVM

R^L= 1.5 kΩ 5%

V

Input pins other than

P60 to P67, HVP,

HVM, DVP, DVM

V^CC= 3.3 V,

Vss < VI < VCC

− 10

+ 10

μA

Input leak

current

I^IL

HVP, HVM, DVP,

DVM

⎯

− 5

⎯

+ 5

μA

kΩ

Pull-up

resistance

P00 to P07,

P10 to P17

VCC = 3.3 V,

TA = + 25 °C

R^PULL

25

50

100

Open drain

output leak I^LIODP60 to P67

current

⎯

0.1

10

μA

VCC = 3.3 V,

⎯

55

50

45

65

60

55

mA MB90F337

mA MB90337

mA MB90F337

mA MB90337

Internal frequency 24 MHz,

At normal operating

At USB operating

(USTP = 0)

I^CC

V^CC= 3.3 V,

Internal frequency 24 MHz,

At normal operating

At non-operating USB

(USTP = 1)

Power

supply

current

VCC

VCC = 3.3 V,

Internal frequency 24 MHz,

At sleep mode

I^CCS

⎯

25

40

10

mA

VCC = 3.3 V,

Internal frequency 24 MHz,

At timer mode

3.5

I^CTS

V^CC= 3.3 V,

Internal frequency 3 MHz,

At timer mode

⎯

1.0

1

2.0

40

TA = +25 °C,

At stop mode

I^CCH

μA

(Continued)

30

DS07-13735-6E

MB90335 Series

(Continued)

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ

Max

Input

capacitance

Other than Vcc and

Vss

C^IN

⎯

5

15

pF

Pull-up

resistor

R^upRST

25

50

100

kΩ

Pull-down

resistor

VCC = 3.0 V

R^downMD2

kΩ MB90337

At TA = +25 °C

USB I/O

output

impedance

DVP, DVM

HVP, HVM

Z^USB

⎯

3

⎯

14

Ω

Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.

DS07-13735-6E

31

MB90335 Series

4. AC Characteristics

(1) Clock input timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Sym-

Parameter

bol

Unit

Remarks

name

Min

⎯

Typ

6

Max

⎯

MHz When oscillator is used

MHz External clock input

ns When oscillator is used

ns External clock input

Clock frequency

f^CH

X0, X1

6

⎯

24

⎯

166.7

⎯

Clock cycle time

tHCYL

166.7

41.7

P^WH

PWL

A reference duty ratio is

30% to 70%.

Input clock pulse width

X0

⎯

10

⎯

3

⎯

5

ns

Input clock rise time and fall

time

tcr

tcf

ns At external clock

Internal operating clock

frequency

fCP

24

333

MHz When main clock is used

ns When main clock is used

Internal operating clock

cycle time

t^CP

⎯

42

• Clock Timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

32

DS07-13735-6E

MB90335 Series

• PLL operation guarantee range

Relation between power supply voltage and internal operation clock frequency

PLL operation guarantee range

3.6

3.0

2.7

Normal operation

assurance range

3

6

12

24

Internal clock fCP (MHz)

Note : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.

Relation between internal operation clock frequency and external clock frequency

24

4 x

External clock

2 x

1 x

12

6

3

24

6

External clock FC (MHz)

The AC standards provide that the following measurement reference voltages.

• Output signal waveform

• Input signal waveform

Hysteresis input pin

Output pin

0.8 VCC

0.2 VCC

2.4 V

0.8 V

Hysteresis input/other than MD input pin

0.7 V^CC

0.3 VCC

DS07-13735-6E

33

MB90335 Series

(2) Reset

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Sym-

bol

name

Parameter

Conditions

Unit

Remarks

Min

Max

At normal operating,

At time base timer mode,

At main sleep mode,

At PLL sleep mode

500

⎯

ns

Reset input

time

t^RSTL

RST

⎯

Oscillation time of

oscillator* + 500 ns

⎯

μs At stop mode

* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several

dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a

ceramic oscillator, and 0 milliseconds on an external clock.

• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode

t

RSTL

RST

0.2 VCC

• During stop mode

t

RSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operation

clock

Oscillation time

of oscillator

500 ns

Oscillation stabilization wait time

Execute instruction

Internal reset

34

DS07-13735-6E

MB90335 Series

(3) Power-on reset

Parameter

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Symbol Pin name Conditions

Unit

Remarks

Min

Max

Power supply rising time

t^R

VCC

0.05

30

ms

⎯

Waiting time

until power-on

Power supply shutdown time

t^OFF

1

⎯

Notes : • VCC must be lower than 0.2 V before the power supply is turned on.

• The above standard is a value for performing a power-on reset.

• Inthedevice, thereareinternalregisterswhichisinitializedonlybyapower-onreset. Whentheinitialization

of these items is expected, turn on the power supply according to the standards.

tR

2.7 V

VCC

0.2 V

t^OFF

Note : Sudden change of power supply voltage may activate the power-on reset function.

When changing the power supply voltage during operation as illustrated below, voltage fluctuation should

be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL

clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.

VCC

The rising edge should be 50 mV/ms

or less.

1.8 V

RAM data hold

V

SS

DS07-13735-6E

35

MB90335 Series

(4) UART0, UART1 I/O extended serial timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCKx

8 t^CP

⎯

ns

SCKx

SOTx

SCK ↓ → SOT delay time

− 80

100

60

+ 80

⎯

Internal shift clock

Mode output pin is

C^L= 80 pF + 1 TTL

SCKx

SINx

Valid SIN → SCK ↑

t^IVSH

ns

SCK ↑ → valid

SIN hold time

SCKx

SINx

t^SHIX

t^SHSL

t^SLSH

⎯

Serial clock H pulse width

Serial clock L pulse width

SCKx, SINx

4 t^CP

⎯

ns

4 tCP

SCKx

SOTx

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

External shift clock

Mode output pin is

C^L= 80 pF + 1 TTL

⎯

60

150

⎯

ns

SCKx

SINx

SCK ↑ → valid

SIN hold time

SCKx

SINx

⎯

Notes : • Above rating is the case of CLK synchronous mode.

• C^Lis a load capacitance value on pins for testing.

• t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

2.4 V

0.8 V

SOT

SIN

t

IVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

36

DS07-13735-6E

MB90335 Series

(5) I²C timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Parameter

Symbol

Conditions

Unit

Min

Max

SCL clock frequency

f^SCL

0

100

kHz

(Repeat) [start] condition hold

time

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

μs

Power-supply of external pull-up resistor

at 5.0 V

R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

SCL clock “L” width

SCL clock “H” width

tLOW

tHIGH

4.7

4.0

⎯

μs

Repeat [start] condition setup time

SCL ↑ → SDA ↓

t^SUSTA

R = 1.0 kΩ, C = 50 pF*²

4.7

0

⎯

μs

Data hold time

SCL ↓ → SDA ↓ ↑

tHDDAT

3.45*³

Power-supply of external pull-up resistor

at 5.0 V

fCP*¹≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

250*⁴

200*⁴

⎯

fCP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Data setup time

SDA ↓ ↑ → SCL ↑

t^SUDAT

ns

Power-supply of external pull-up resistor

at 5.0 V

f^CP*¹> 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

fCP*¹> 20 MHz, R = 1.0 kΩ, C = 50 pF*²

[Stop] condition setup time

SCL ↑ → SDA ↑

Power-supply of external pull-up resistor

at 5.0 V

t^SUSTO

4.0

4.7

⎯

μs

R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

Bus free time between [stop]

condition and [start] condition

t^BUS

R = 1.0 kΩ, C = 50 pF*²

*1 : f^CPis internal operating clock frequency. Refer to “ (1) Clock input timing”.

*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.

*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*4 : Refer to “• Note of SDA, SCL set-up time”.

DS07-13735-6E

37

MB90335 Series

•Note of SDA, SCL set-up time

SDA

Input data set-up time

SCL

6 tcp

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on

the load capacitance or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be

satisfied.

•Timing definition

SDA

tBUS

tHDSTA

tLOW

tSUDAT

SCL

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

38

DS07-13735-6E

MB90335 Series

(6) Timer Input Timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

t^TIWH

tTIWL

Input pulse width

PWC

⎯

4 tCP

⎯

ns

Note : t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

PWC

t

TIWH

tTIWL

(7) Timer output timing

Parameter

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Symbol

Pin name

Conditions

Unit

Min

Max

CLK ↑ → T^OUTchange time

PPG0 to PPG3 change time

tTO

PPGx

⎯

30

⎯

ns

2.4 V

CLK

t^TO

2.4 V

0.8 V

PPGx

(8) Trigger Input Timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min

5 t^CP

1

Max

⎯

ns

At normal operating

At Stop mode

t^TRGH

Input pulse width

INTx

⎯

tTRGL

⎯

μs

Note : t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

INTx

t

TRGH

tTRGL

DS07-13735-6E

39

MB90335 Series

5. USB characteristics

(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Symbol

Unit

Remarks

Min

2.0

⎯

Max

⎯

Input High level voltage

Input Low level voltage

Differential input sensitivity

V^IH

V^IL

V^DI

V

0.8

⎯

Input

characteristics

0.2

0.8

2.8

0.0

1.3

4

V

Differential common mode range V^CM

2.5

3.6

0.3

2.0

20

V

Output High level voltage

Output Low level voltage

Cross over voltage

V^OH

V^OL

V^CRS

t^FR

V

IOH = −200 μA

IOL = 2 mA

V

ns

%

Ω

Full Speed

Low Speed

Full Speed

Low Speed

(TFR/TFF)

Rise time

Fall time

t^LR

75

4

300

20

Output

characteristics

t^FF

t^LF

75

90

80

28

300

111.11

125

44

t^RFM

t^RLM

Z^DRV

Rising/falling time matching

Output impedance

(TLR/TLF)

Including Rs = 27 Ω

Recommended value

= 27 Ω at using USB*

Series resistance

R^S

25

30

Ω

* : Arrange the series resistance R^Svalues in order to set the impedance value within the output impedance ZSRV.

• Data signal timing (Full Speed)

Fall time

Rise time

DVP/HVP

DVM/HVM

90%

VCRS

10%

tFF

tFR

• Data signal timing (Low Speed)

Rise time

Fall time

HVP

V

90%

CRS

10%

HVM

tLF

tLR

40

DS07-13735-6E

MB90335 Series

• Load condition (Full Speed)

Testing point

Z

USB

R

S

= 27 Ω

DVP/HVP

DVM/HVM

C

L

= 50 pF

Z

USB

RS

Testing point

CL

= 50 pF

• Load condition (Low Speed)

Testing point

ZUSB

RS = 27 Ω

HVP

C^L= 50 pF ∼ 150 pF

Testing point

ZUSB

HVM

C^L= 50 pF ∼ 150 pF

DS07-13735-6E

41

MB90335 Series

6. Flash memory write/erase characteristics

Value

Typ

Parameter

Condition

Unit

Remarks

Min

Max

Sector erase time

(4 Kbytes sector)

Excludes 00^Hprogramming

prior to erasure.

⎯

0.2

0.5

2.6

0.5

s

Sector erase time

(16 Kbytes sector)

Excludes 00^Hprogramming

prior to erasure.

⎯

7.5

T^A= + 25 °C

VCC = 3.0 V

Excludes 00H programming

prior to erasure.

Chip erase time

⎯

Word (8 bits width)

programming time

Except for over head time of

system

⎯

10000

20

16

⎯

3600

⎯

μs

Program/erase cycle

⎯

cycle

year

Average

T^A= + 85 °C

Flash data retention time

⎯

*

* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C)

42

DS07-13735-6E

MB90335 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F337PMC

MB90337PMC

64-pin plastic LQFP

(FPT-64P-M23)

299-pin ceramic PGA

(PGA-299C-A01)

MB90V330ACR

For evaluation

DS07-13735-6E

43

MB90335 Series

■ PACKAGE DIMENSION

64-pin plastic LQFP

Lead pitch

0.65 mm

12.0 × 12.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.47 g

Code

(Reference)

P-LQFP64-12×12-0.65

(FPT-64P-M23)

64-pin plastic LQFP

(FPT-64P-M23)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.0057 .0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ^+0.20

–

0.10

(Mounting height)

.059 ^+.008

–.004

0.25(.010)

INDEX

0~8°

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-3

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

44

DS07-13735-6E

MB90335 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

■ ELECTRICAL CHARACTERISTICS Corrected as follows;

35

4.AC Characteristics

(3) Power-on reset

Voltage of RAM data hold: 3.0 V → 1.8 V

The vertical lines marked in the left side of the page show the changes.

DS07-13735-6E

45

MB90335 Series

MEMO

46

DS07-13735-6E

MB90335 Series

MEMO

DS07-13735-6E

47

MB90335 Series

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not

warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device

based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or

any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other

right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property

rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in

connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB90337PMC
厂家：	FUJITSU
描述：	16-bit microcontrollers 16位微控制器微控制器和处理器外围集成电路时钟
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MB90337PMC [FUJITSU]

相关型号：

MB90340

MB90340E

MB90340E

MB90340E_10

MB90341ASPFV

MB90341CE

MB90341CEPF

MB90341CEPFV

MB90341CEPMC

MB90341CES

MB90341CESPF

MB90341CESPFV