MB89656AR_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12530-1E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89650AR Series

MB89653AR/655AR/656AR/657AR/P657A

MB89PV650A

■ DESCRIPTION

The MB89650AR series has been developed as a general-purpose version of the F²MC*-8L family consisting

of proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as

dual-clock control system, five operating speed control stages, timers, PWM timers, a serial interface, an A/D

converter, external interrupts, an LCD controller/driver, and a watch prescaler.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-8L family CPU core

• Dual-clock control system

• Maximum memory space: 64 Kbytes

• Minimum execution time: 0.4 µs/10 MHz

• Interrupt processing time: 3.6 µs/10 MHz

• I/O ports: max. 64 channels

• 21-bit time-base counter

• 8-bit PWM timers: 2 channels (A maximum of 4 channels can be used for output.)

• 8/16-bit timer/counter: 4 channels (16 bits × 2 channels)

• 8-bit serial I/O: 1 channel

• 8-bit A/D converter: 8 channels

(Continued)

■ PACKAGE

100-pin Ceramic MQFP

100-pin Plastic QFP

100-pin Plastic SQFP

(FPT-100P-M06)

(MQP-100C-P02)

(FPT-100P-M05)

MB89650AR Series

(Continued)

• External interrupt 1

Four independent channels with edge detection function

• External interrupt 2 (wake-up function)

Twelve “L” level-interrupt channels

• Watch prescaler

• LCD controller/driver: 16 to 32 segments × 2 to 4 commons

• Power-on reset function

• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)

• SQFP-100 and QFP-100 packages

■ PRODUCT LINEUP

Part number

MB89653AR

MB89655AR MB89656AR MB89657AR MB89P657A MB89PV650A

Parameter

Piggyback/

Classification

evaluation product

(for evaluation and

development)

Mass production products

(mask ROM products)

One-time

PROM product

32 K × 8 bits

(internal PROM,

programming

ROM size

8 K × 8 bits

(internal

mask

16 K × 8 bits

(internal

mask

24 K × 8 bits 32 K × 8 bits

32 K × 8 bits

(external ROM)

(internal

mask

(internal

mask

ROM)

with general-

ROM)

purpose EPROM

programmer)

RAM size

256 × 8 bits

512 × 8 bits

768 × 8 bits

1 K × 8 bits

LCD display

RAM

16 × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Data bit length:

Minimum execution time:

0.4 µs/10 MHz to 6.4 µs/10 MHz, 61.0 µs/32.768 kHz

Interrupt processing time: 3.6 µs/10 MHz to 57.6 µs/10 MHz, 549.3 µs/32.768 kHz

Ports

Input ports:

Output ports:

I/O ports:

Total:

8 (All also serve as peripherals.)

48 (All also serve as peripherals.)

64

8-bit timer 1,

8-bit timer 2

8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs)

16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs)

2 output channels are enabled when operating as an 8-bit timer.

8-bit timer 3,

8-bit timer 4

8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs)

16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs)

2 output channels are enabled when operating as an 8-bit timer.

Clock timer

21 bits × 1 (in main clock mode)/15 bits × 1 (at 32.768 kHz)

8-bit PWM

timer 1,

8-bit PWM

timer 2

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms)

8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms)

Both 8-bit PWM timer 1 and 8-bit PWM timer 2 can output 2 channels.

(Continued)

2

MB89650AR Series

(Continued)

Part number

MB89653AR

MB89655AR MB89656AR MB89657AR MB89P657A MB89PV650A

Parameter

8-bit serial I/O

8 bits

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D

converter

8-bit resolution × 8 channels

A/D conversion mode (conversion time: 18 µs)

Sense mode (conversion time: 5 µs)

Continuous activation by an internal timer capable

Reference voltage input

External

interrupt 1

4 independent channels (edge selection)

Rising edge/falling edge selectability

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

External

interrupt 2

(wake-up

function)

“L” level interrupt × 12 channels

Standby mode

Process

Subclock mode, sleep mode, watch mode, and stop mode

CMOS

Operating

voltage*

2.2 V to 6.0 V

2.7 V to 6.0 V

EPROM for use

MBM27C256A-

20TVM

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

In the case of the MB89PV650A, the voltage varies with the restrictions of the EPROM for use.

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89653AR

MB89655AR

MB89656AR

MB89657AR

MB89P657A

Package

MB89PV650A

FPT-100P-M05

FPT-100P-M06

MQP-100C-P02

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

3

MB89650AR Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89653AR, the upper half of the register bank cannot be used.

• On the MB89P657A, the program area starts from address 8006^Hbut on the MB89PV650A and MB89657AR

starts from 8000H.

(On the MB89P657A, addresses 8000H to 8005H comprise the option setting area, option settings can be read

by reading these addresses. On the MB89PV650A and MB89657A, addresses 8000H to 8005H could also be

used as a program ROM. However, do not use these addresses in order to maintain compatibility of the

MB89P657A.)

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• InthecaseoftheMB89PV650A,addthecurrentconsumedbytheEPROMwhichisconnectedtothetopsocket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same. (For more information, see sections

“■ Electrical Characteristics” and “■ Example Characteristics.”)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following points:

• A pull-up resistor cannot be set for P70 to P75 on the MB89P657A. On this product, a pull-up resistor must

be selected in a group of four bits for P14 to P17, P40 to P43, and P44 to P47.

• A pull-up resistor is not selectable for P30 to P37 and P40 to P47 if they are used as LCD pins.

• Options are fixed on the MB89PV650A.

4. Differences between the MB89650A and MB89650AR Series

• Electrical specifications/electrical characteristics

Electrical specifications of the MB89650AR series are the same with that of the MB89650A series.

Electrical characteristics of both series are much the same.

• Oscillation circuit type

In the MB89650A series, the circuit type of using an external clock differs from that of using a crystal or ceramic

resonator as follows.

Circuit type of the MB89650AR series is a circuit type in using external clock even when crystal or ceramic

resonator is selected.

• Memory access area and other specifications of both the MB89650A and MB89650AR series are the same.

4

MB89650AR Series

• I/O circuit type

Type

Circuit

Remarks

A

X1

• Crystal or ceramic oscillation type (main clock)

MB89PV650A and MB89P657A, external clock input

selection versions of MB89653A/655A/656A/657A

At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

X0

Standby control signal

X1

X0

• Crystal or ceramic oscillation type (main clock)

Crystal or ceramic oscillation selection versions of

MB89653A/655A/656A/657A

At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

Standby control signal

■ CORRESPONDENCE BETWEEN THE MB89650A AND MB89650AR SERIES

• The MB89650AR series is the reduction version of the MB89650A series.

• The MB89650A and MB89650AR series consist of the following products:

MB89650A series

MB89653A

MB89655A

MB89656A

MB89657A

MB89P657 MB89PV650

MB89650AR

series

MB89653A

R

MB89655A

R

MB89656A

R

MB89657A

R

A

5

MB89650AR Series

■ PIN ASSIGNMENT

(Top view)

MOD0

MOD1

X0

X1

VSS

RST

1

2

3

4

5

6

7

8

75

74

73

72

71

70

P52/PWM21

P51/PWM12

P50/PWM11

COM3/P81

COM2/P80

COM1

COM0

V0

V1

V2

V3

P83

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/INT28

P15/INT29

P16/INT2A

P17/INT2B

P20

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P82

SEG00

SEG01

SEG02

SEG03

SEG04

SEG05

VSS

SEG06

SEG07

SEG08

SEG09

SEG10

P21

P22

52

51

(FPT-100P-M05)

6

MB89650AR Series

(Top view)

V^CC

X1A

X0A

MOD0

MOD1

X0

X1

VSS

RST

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P54/TO11/LCLK

P53/PWM22

P52/PWM21

P51/PWM12

P50/PWM11

COM3/P81

COM2/P80

COM1

COM0

V0

V1

V2

9

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/INT28

P15/INT29

P16/INT2A

P17/INT2B

P20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V3

P83

P82

SEG00

SEG01

SEG02

SEG03

SEG04

SEG05

VSS

SEG06

SEG07

SEG08

SEG09

SEG10

SEG11

SEG12

SEG13

P21

P22

P24/SI

P25/SO

(FPT-100P-M06)

7

MB89650AR Series

(Top view)

1

2

3

4

5

6

7

8

MOD0

MOD1

X0

X1

VSS

RST

P52/PWM21

P51/PWM12

P50/PWM11

COM3/P81

COM2/P80

COM1

COM0

V0

V1

V2

V3

P83

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

O8

CE

121

122

123

124

125

126

127

128

112

111

110

109

108

107

106

105

A0

A1

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/INT28

P15/INT29

P16/INT2A

P17/INT2B

P20

9

A10

N.C.

OE

A2

10

11

12

13

14

15

16

17

18

19

20

21

22

N.C.

A3

P82

SEG00

SEG01

SEG02

SEG03

SEG04

SEG05

VSS

SEG06

SEG07

SEG08

SEG09

SEG10

N.C.

A11

A9

A4

A5

23

24

25

P21

P22

(MQP-100C-P02)

• Pin assignment on package top (MB89PV650A only)

Pin no.

101

Pin name

V^PP

Pin no.

109

Pin name

N.C.

A2

Pin no.

117

Pin name

O4

Pin no.

125

Pin name

OE

102

A12

A7

110

118

O5

126

N.C.

A11

A9

103

111

A1

119

O6

127

104

A6

112

A0

120

O7

128

105

A5

113

O1

121

O8

129

A8

106

A4

114

O2

122

CE

130

A13

A14

VCC

107

A3

115

O3

123

A10

N.C.

131

108

N.C.

116

V^SS

124

132

N.C.: Internally connected. Do not use.

8

MB89650AR Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

MOD0

Function

MQFP^*2

QFP^*1

SQFP^*3

4

1

J

Operating mode selection pins

Connect to VSS (GND) when using.

5

2

MOD1

X0

6

3

A

Main clock crystal oscillator pins (max. 10 MHz)

7

4

X1

8

9

5

6

V^SS

Power supply (GND) pin

Reset input pin

RST

J

10 to 17

7 to 14

P00/INT20 to

P07/INT27

F

General-purpose I/O ports

Also serve as an external interrupt 2 input (wake-up

function).

External interrupt 2 input (INT20 to INT27) is

hysteresis input while port input (P00 to P07) is

CMOS input.

18 to 21

22 to 25

15 to 18

19 to 22

P10/INT10 to

P13/INT13

F

General-purpose I/O ports

Also serve as an external interrupt 1 input.

External interrupt 1 input (INT10 to INT13) is

hysteresis input while port input (P10 to P13) is

CMOS input.

P14/INT28 to

P15/INT2B

General-purpose I/O ports

Also serve as an external interrupt 2 input (wake-up

function).

External interrupt 2 input (INT28 to INT2B) is

hysteresis input while port input (P14 to P17) is

CMOS input.

26 to 28

23 to 25

P20 to P22

C

F

General-purpose I/O ports

29,

30,

31

26,

27,

28

P24/SI,

P25/SO,

P26/SCK

General-purpose I/O ports

The output type can be switched between N-ch open-

drain and CMOS. These ports also serve as an 8-bit

serial I/O.

The P26/SCK pin is a CMOS input type when it

functions as the port input (P26) while the pin is a

hysteresis input type when it functions as the serial

clock input (SCK).

32 to 47

29 to 44

P36/SEG31 to

P47/SEG26

H

I

General-purpose I/O ports

Also serve as an LCD controller/driver segment

output.

48,

49

45,

46

SEG15,

SEG14

LCD controller/driver segment output pins

(Continued)

*1: FPT-100P-M06

*2: FPT-100P-M05

*3: MQP-100C-P02

9

MB89650AR Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

MQFP^*2

QFP^*1

SQFP^*3

50

47

VCC

Power supply pin

51 to 58

48 to 55 SEG13 to

SEG06

I

LCD controller/driver segment output pins

59

56

V^SS

Power supply (GND) pin

60 to 65

57 to 62 SEG05 to

SEG00

I

LCD controller/driver segment output pins

66,

67

63,

64

P82,

P83

C

General-purpose I/O ports

68 to 71

65 to 68 V3 to V0

LCD driving power supply pins

72,

73

69,

70

COM0,

COM1

I

LCD controller/driver common output pins

74,

75

71,

72

COM2/P80,

COM3/P81

H

G

General-purpose I/O ports

Also serve as an LCD controller/driver common output.

76 to 79

73 to 76 P50/PWM11 to

P53/PWM22

General-purpose output ports

Also serve as an 8-bit PWM timer.

80,

81,

82,

83

77,

78,

79,

80

P54/TO11/LCLK,

P55/TO12,

P56/TO21/HCLK,

P57/TO22

General-purpose output ports

Also serve as an 8/16-bit timer.

P54 and P56 also serve as a 32.768 kHz oscillation

output/10 MHz divide-by-two output.

84

81

AV^SS

A/D converter power supply (GND) pin

85 to 92

82 to 89 P60/AN0 to

P67/AN7

E

General-purpose input ports

Also serve as an analog input.

93

94

90

91

AV^CC

AVR

A/D converter power supply pin

A/D converter reference voltage input pin

95,

96

92,

93

P70/EC1,

P71/EC2

K

D

General-purpose N-ch open-drain I/O ports

Also serve as an 8/16-bit timer to input hysteresis.

97,

98 to 100

94,

P72/BUZ,

General-purpose N-ch open-drain I/O ports

P72 also serves as a buzzer output.

95 to 97 P73 to P75

1

2

3

98

99

V^CC

Power supply pin

X1A

X0A

B

Subclock crystal oscillator pins (32.768 kHz)

100

*1: FPT-100P-M06

*2: FPT-100P-M05

*3: MQP-100C-P02

10

MB89650AR Series

• External EPROM pins (MB89PV650A only)

Pin no.

Pin name

V^PP

I/O

O

Function

101

“H” level output pin

Address output pins

102

103

104

105

106

107

110

111

112

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

113

114

115

O1

O2

O3

I

Data input pins

116

V^SS

O

I

Power supply (GND) pin

Data input pins

117

118

119

120

121

O4

O5

O6

O7

O8

122

CE

O

ROM chip enable pin

Outputs “H” during standby.

123

125

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

127

128

129

A11

A9

A8

O

Address output pins

130

131

132

A13

A14

V^CC

O

Address output pin

O

EPROM power supply pin

108

109

124

126

N.C.

—

Internally connected pins

Be sure to leave them open.

11

MB89650AR Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

X1

X0

A

• Crystal or ceramic oscillation type (main clock)

MB89PV650A and MB89P657A, external clock input

selection versions of MB89653AR/655AR/656AR/

657AR

At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

Standby control signal

B

• Crystal or ceramic oscillation type (subclock)

MB89PV650A, MB89P657A

At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

X1A

X0A

Standby control signal

X1A

X0A

• Crystal or ceramic oscillation type (subclock)

MB89653AR/655AR/656AR/657AR

At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

Standby control signal

C

D

E

• CMOS I/O

R

P-ch

N-ch

• Pull-up resistor optional (except P82 and P83)

• N-ch open-drain I/O

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional

• A/D converter input

• CMOS input

R

P-ch

Ain

N-ch

• Pull-up resistor optional

(Continued)

12

MB89650AR Series

(Continued)

Type

Circuit

Remarks

F

• CMOS I/O (when selected as general-purpose ports)

P24 to P26 outputs can be switched between CMOS

and N-ch open-drain.

• When toggled as hysteresis input peripherals.

However, SI input excluded.

R

P-ch

N-ch

• Pull-up resistor optional

• CMOS output

G

H

P-ch

N-ch

• LCD controller/driver output

• CMOS I/O

P-ch

R

N-ch

P-ch

N-ch

P-ch

N-ch

• Pull-up resistor optional

I

• LCD controller/driver output

P-ch

N-ch

P-ch

N-ch

J

K

• Hysteresis input

• N-ch open-drain output

R

P-ch

N-ch

• Pull-up resistor optional

13

MB89650AR Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

14

MB89650AR Series

■ PROGRAMMING TO THE EPROM ON THE MB89P657A

The MB89P657A is an OTPROM version of the MB89650A series.

1. Features

• 32-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.

EPROM mode

(Corresponding addresses on the EPROM programmer)

Address

0000H

Single chip

I/O

0080H

0480H

RAM

Not available

8000H

8006H

0000H

Option area

0006H

PROM

32 KB

EPROM

32 KB

7FFF^H

FFFF^H

3. Programming to the EPROM

In EPROM mode, the MB89P657A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

When the operating ROM area for a single chip is 32 Kbytes (8006^Hto FFFFH) the PROM can be programmed

as follows:

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0006^Hto 7FFFH (note that addresses 8006H to FFFFH

while operating as a single chip assign to 0006H to 7FFFH in EPROM mode).

Load option data into addresses 0000H to 0005H of the EPROM programmer. (For information about each

corresponding option, see “7. Setting OTPROM Options.”)

(3) Program to 0000H to 7FFFH with the EPROM programmer.

15

MB89650AR Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Package

Compatible socket adapter

ROM-100SQF-28DP-8L

FPT-100P-M05

FPT-100P-M06

ROM-100QF-28DP-8L2

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

Note: Connect the ROM-100SQF-28DP-8L jumper pin to V^SSwhen using.

Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between V^PPand VSS or

VCC and VSS can stabilize programming operations.

16

MB89650AR Series

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

P81

Pull-up

1: No

Bit 1

P80

Pull-up

1: No

Bit 0

Vacancy

Single/dual-

clock system

1: Dual clock

2: Single

Readable

and

writable

Readable

and

writable

Readable

and

writable

Readable

and

writable

Readable

and

writable

0000^H

0: Yes

clock

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

0001^H

0002^H

0003^H

0004^H

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P67

P66

P65

P64

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47 to P44 P43 to P40 P26

Pull-up

1: No

P25

P24

P22

P21

P20

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P17 to P14 P13

P12

P11

P10

Pull-up

1: No

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

0005^HReadable

and

Readable

and

Readable

and

0: Yes

writable

Notes: • Set each bit to 1 to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

17

MB89650AR Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

LCC-32(Rectangle) ROM-32LC-28DP-YG

LCC-32(Square) ROM-32LC-28DP-S

Adapter socket part number

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

3. Memory Space

Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

8006H

0000H

Option area

0006H

PROM

32 KB

EPROM

32 KB

7FFF^H

FFFF^H

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0006^Hto 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

18

MB89650AR Series

■ BLOCK DIAGRAM

Output port

Time-base timer

P50/PWM11

8-bit PWM

Main clock

oscillator

X0

X1

timer 1

P51/PWM12

P52/PWM21

P53/PWM22

8-bit PWM

timer 2

Clock controller

Subclock oscillator

(32.768 kHz)

X0A

X1A

8-bit timer/

counter 4

P57/TO22

RST

Reset circuit

I/O port

P56/TO21

/HCLK

8-bit timer/

counter 3

P30/SEG31

8

to P37/SEG24

P71/EC2

P40/SEG23

8

to P47/SEG16

32

8-bit timer/

counter 2

P55/TO12

SEG00

16

to SEG15

P54/TO11

/LCLK

LCD

controller/driver

8-bit timer/

counter 1

2

COM0, COM1

P70/EC1

2

COM2/P80,

COM3/P81

P72/BUZ

P73 to P75

P82, P83

3

2

4

Buzzer output

8-bit serial I/O

V0 to V3

P24/SI

P25/SO

P26/SCK

LCD display RAM (16 × 8 bits)

8

4

8

4

P00/INT20

to P07/INT27

External interrupt 2

(wake-up function)

RAM

P14/INT28

to P17/INT2B

F²MC-8L

CPU

4

3

P10/INT10

External interrupt 1

to P13/INT13

P20 to P22

I/O port

8-bit A/D converter

Input port

ROM

8

P60/AN0

to P67/AN7

Other pins

MOD × 2, VCC × 2

VSS × 2

AV^CC, AVSS, AVR

19

MB89650AR Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89650AR series offer a memory space of 64 Kbytes for storing all of I/O, data,

and program areas. The I/O area is located at the lowest address. The data area is provided immediately above

the I/O area. The data area can be divided into register, stack, and direct areas according to the application.

The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables

of interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89650AR series is structured as illustrated below.

Memory Space

MB89PV650A

MB89P657A

MB89653AR

I/O

MB89655AR

I/O

MB89656AR

I/O

MB89657AR

I/O

0000H

0080H

0000H

0080H

0000^H

0080H

0000H

0080H

0000H

0080H

I/O

RAM

1 KB

RAM

256 B

RAM

512 B

RAM

768 B

RAM

1 KB

0100H

01FF^H

0100H

0180H

0100H

01FFH

Register

01FFH

0280H

01FFH

0380H

0480H

8006H

Not available

8006^H

A000H

FFFFH

C000H

FFFFH

External

ROM*

32 KB

ROM

24 KB

ROM

32 KB

ROM

16 KB

E000H

FFFFH

ROM

8 KB

FFFFH

*: This is an internal PROM on the MB89P657A.

Since addresses 8000^Hto 8005H for the MB89P657A comprise an option area, do not use this area

for the MB89PV650A.

20

MB89650AR Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

FFFD^H

: Program counter

: Accumulator

A

T

Undefined

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

21

MB89650AR Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

22

MB89650AR Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 16 banks can be used on the MB89653AR (RAM 256 × 8 bits). The bank

currently in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size. Up to a total of 32 banks can

be used on other than the MB89653AR.

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

16 banks

Memory area

23

MB89650AR Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

(R/W)

(W)

PDR1

DDR1

Port 1 data direction register

Port 2 data register

(R/W)

PDR2

DDR2

Port 2 data direction register

Vacancy

(R/W)

SCC

SMC

System clock control register

System mode control register

Watchdog time control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

WDTC

TBTC

WCR

PDR3

DDR3

PDR4

DDR4

T4CR

T3CR

T4DR

T3DR

Port 3 data direction register

Port 4 data register

Port 4 data direction register

Timer 4 control register

Timer 3 control register

Timer 4 data register

Timer 3 data register

Vacancy

(R/W)

PDR5

Port 5 data register

Vacancy

(W)

(R)

ICR6

PDR6

Port 6 input control register

Port 6 data register

(R/W)

(W)

PDR7

Port 7 data register

CHG2

CNTR1

COMP1

Port 2 switching register

PWM 0/1 control register

PWM 0/1 compare register

(Continued)

24

MB89650AR Series

(Continued)

Address

Read/write

(R/W)

Register name

CNTR2

Register description

PWM 2/3 control register

PWM 2/3 compare register

Vacancy

20^H

21H

(W)

COMP2

22^H

23^H

Vacancy

24H

(R/W)

T2CR

T1CR

T2DR

T1DR

SMR

Timer 2 control register

Timer 1 control register

Timer 2 data register

25^H

26^H

27H

Timer 1 data register

28^H

Serial mode register

29H

SDR

Serial data register

2A^H

Vacancy

2BH

Vacancy

2CH

Vacancy

2D^H

(R/W)

ADC1

ADC2

ADCD

EIE1

A/D converter control register 1

A/D converter control register 2

A/D converter data register

External interrupt 1 enable register

External interrupt 1 flag register

External interrupt 2 enable register

External interrupt 2 flag register

Vacancy

2EH

2FH

30^H

31H

EIF1

32^H

EIE2

33H

EIF2

34H to 5FH

60^Hto 6FH

70H

(R/W)

(W)

VRAM

LCR1

LCR2

PDR8

DDR8

Display data RAM

LCD controller/driver control register 1

LCD controller/driver control register 2

Port 8 data register

71H

72^H

73^H

Port 8 data direction register

Vacancy

74H to 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7D^H

7EH

7FH

Note: Do not use vacancies.

25

MB89650AR Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AVCC

Power supply voltage

VSS – 0.3

V^SS– 0.3

VSS + 7.0

V

*1

A/D converter reference input

voltage

AVR

VSS + 7.0

LCD power supply voltage

V0 to V3 V^SS– 0.3

VSS + 7.0

VCC + 0.3

VSS + 7.0

VCC + 0.3

VSS + 7.0

V

V0 to V3 must not exceed VCC.

Except P70 to P75*²

P70 to P75

V^I

VSS – 0.3

Input voltage

VI2

V^O

VO2

Except P70 to P75*²

P70 to P75

Output voltage

“L” level maximum output

current

I^OL

20

4

mA

Average value (operating

current × operating rate)

“L” level average output current

I^OLAV

∑IOL

∑I^OLAV

I^OH

“L” level total maximum output

current

100

40

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–20

–4

Average value (operating

current × operating rate)

“H” level average output current

IOHAV

∑I^OH

∑I^OHAV

“H” level total maximum output

current

–50

–20

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

300

+85

mW

°C

TA

–40

–55

Tstg

+150

°C

*1: Use AVCC and VCC set at the same voltage.

Take care so that AVR does not exceed AVCC + 0.3 V and AVCC does not exceed VCC, such as when power is

turned on.

*2: VI and VO must not exceed VCC + 0.3 V.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-

tional operation should be restricted to the conditions as detailed in the operational sections of this

data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

26

MB89650AR Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range*

MB89653AR/655AR/656AR/657AR

2.2*

6.0*

V

V^CC

AVCC

Power supply voltage

Normal operation assurance range*

MB89PV650A/P657A

2.7*

1.5

0.0

6.0*

6.0

V

Retains the RAM state in stop mode

A/D converter reference input

voltage

AVR

AV^CC

LCD power supply range

(The optimum value is dependent on

the LCD element in use.)

LCD power supply voltage

Operating temperature

V0 to V3

T^A

V^SS

VCC

V

–40

+85

°C

* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1

and “5. A/D Converter Electrical Characteristics.”

6

Analog accuracy assured in the

AVCC = 3.5 V to 6.0 V range

5

Operation assurance range

4

3

2

1

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Main clock operating frequency (at an instruction cycle of 4/F^CH) (MHz)

0.4

4.0 2.0

0.8

Minimum execution time (instruction cycle) (ms)

Note: The shaded area is assured only for the MB89653A/655A/656A/657A.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

27

MB89650AR Series

3. DC Characteristics

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

P20 to P26, P30 to P37,

P40 to P47, P60 to P67,

P80 to P83

V^CC+ 0.3

V^IH1

0.7 VCC

V

Without pull-

up resistor

P72 to P75

V^SS+ 6.0

V^CC+ 0.3

V^IH2

0.7 VCC

0.8 VCC

V

“H” level input

voltage

P00 to P07, P10 to P17,

RST,

V^IHS

V

MOD0, MOD1,

P26 (at SC input)

Without pull-

up resistor

P70, P71

V^SS+ 6.0

0.3 VCC

V^IHS2

0.8 VCC

V

P20 to P26, P30 to P37,

P40 to P47, P60 to P67,

P72 to P75, P80 to P83

P00 to P07, P10 to P17,

P26 (at SC input),

P70, P71,

V^SS− 0.3

V^IL

V

“L” level input

voltage

V^SS− 0.3

V^IS

—

0.2 VCC

RST,

MOD0, MOD1

V^SS+

0.3

N-ch open-

drain

Open-drain

output

pin application

voltage

V^SS− 0.3

V^D

V

P24 to P26

V^SS+

6.0

V^D2

V

P70 to P75

P00 to P07, P10 to P17,

P20 to P26, P30 to P37,

P40 to P47, P50 to P57,

P80 to P83

“H” level output

voltage

V^OH

IOH = –2.0 mA

IOL = 4.0 mA

4.0

P00 to P07, P10 to P17,

P20 to P26, P30 to P37,

P40 to P47, P50 to P57,

P70 to P75, P80 to P83

“L” level output

voltage

V^OL

0.4

±5

V

P00 to P07, P10 to P17,

P20 to P26, P30 to P37,

P40 to P47, P60 to P67,

P70 to P75, P80 to P83,

MOD0, MOD1, RST

Input leakage

current

(Hi-z output

leakage

0.0 V < VI <

Without pull-

µA

I^LI

VCC

up resistor

current)

P00 to P07, P10 to P17,

P20 to P26, P30 to P37,

P40 to P47, P60 to P67,

P70 to P75, P80 to P81

Pull-up

resistance

With pull-up

kΩ

R^PULL

VI = 0.0 V

25

50

100

resistor

(Continued)

28

MB89650AR Series

(AV^CC= VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

FCH = 10 MHz

V^CC= 5.0 V

t^inst= 0.4 µs

ICC1

—

12

20

mA

*2

MB89653AR/

655AR/656AR/

657AR/PV650A

FCH = 10 MHz

VCC = 3.0 V

t^inst*2= 6.4 µs

—

1.0

1.5

3

2

2.5

7

mA

ICC2

MB89P657A

F^CH= 10 MHz

V^CC= 5.0 V

t^inst*2= 0.4 µs

ICCS1

F^CH= 10 MHz

V^CC= 3.0 V

t^inst*2= 6.4 µs

I^CCS2

—

0.5

1.5

mA

MB89P657A/

655AR/656AR/

657AR/PV650A

F^CL= 32.768 kHz,

V^CC= 3.0 V

Subclock mode

—

50

100

700

µA

I^CCL

VCC

MB89P657A

500

F^CL= 32.768 kHz,

V^CC= 3.0 V

Subclock sleep

mode

ICCLS

—

15

50

µA

Power supply

current^*1

F^CL= 32.768 kHz,

V^CC= 3.0 V

• Watch mode

• Main clock stop

mode at dual-

clock system

I^CCT

—

3

15

µA

T^A= +25°C

• Subclock stop

mode

• Main clock stop

mode at single-

clock system

I^CCH

—

1

µA

F^CH= 10 MHz,

when A/D

conversion is

activated

I^A

—

1.5

—

3

1

mA

AVCC

F^CH= 10 MHz,

T^A= +25°C,

when A/D

conversion is

stopped

I^AH

µA

(Continued)

29

MB89650AR Series

(Continued)

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

Between

VCC and V0

at VCC = 5.0 V

LCD divided

resistance

R^LCD

300

500

750

kΩ

COM0 to 3 output

impedance

R^VCOM

COM0 to 3

SEG0 to 31

—

2.5

15

V1 to V3 = 5.0

V

SEG0 to 31

output

R^VSEG

impedance

LCD controller/

driver leakage

current

V0 to V3,

COM0 to 3,

SEG0 to SEG31

I^LCDL

—

±1

µA

Other than AVCC,

AVSS, VCC, and VSS

Input capacitance C^IN

f = 1 MHz

10

pF

*1: The power supply current is measured at the external clock.

*2: For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

Note: For pins which serve as the LCD and ports (P30 to P37, P40 to P47, and P80 to P81), see the port parameter

when these pins are used as ports and the LCD parameter when they are used as LCD pins.

30

MB89650AR Series

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

48 tHCYL

—

ns

tZLZH

RST

0.2 VCC

(2) Power-on Reset

Parameter

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Min. Max.

Symbol Condition

Unit

Remarks

Power supply rising time

Power supply cut-off time

t^R

—

1

50

—

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

0.2 V

V

CC

31

MB89650AR Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Symbol

Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

1

Max.

10

F^CH

X0, X1

MHz

kHz

ns

F^CL

X0A, X1A

X0, X1

—

32.768

—

t^HCYL

t^LCYL

100

—

1000

—

X0A, X1A

30.5

µs

P^WH

PWL

—

X0

20

—

15.2

—

10

ns

µs

ns

External clock

Input clock pulse

width

P^WLH

PWLL

X0A

X0

Input clock rising/

falling time

t^CR

tCF

32

MB89650AR Series

X0 and X1 Timing and Conditions

t^HCYL

PWH

P_WL

t^CR

tCF

0.8 VCC

X0

0.2 VCC

Main Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

X0A and X1A Timing and Conditions

tLCYL

P_WLL

P_WLH

t^CR

tCF

0.8 VCC

0.8 V^CC

X0A

0.2 VCC

Subclock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0A

X1A

X0A

X1A

Open

33

MB89650AR Series

(4) Instruction Cycle

Symbol

Value (typical)

Unit

Remarks

Parameter

(4/F^CH) tinst = 0.4 µs when operating at

FCH = 10 MHz

4/FCH, 8/FCH, 16/FCH, 64/FCH µs

Instruction cycle

(minimum execution time)

t^inst

t^inst= 61.036 µs when operating at

F^CL= 32.768 kHz

2/F^CL

µs

Note: When operating at 10 MHz, the cycle varies with the set execution time.

(5) Serial I/O Timing

(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

Value

Min.

Symbol

SCK

Condition

Unit Remarks

Parameter

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

tIVSH

t^SHIX

tSHSL

tSLSH

t^SLOV

tIVSH

t^SHIX

2 tinst*

–200

µs

ns

µs

ns

µs

SCK, SO

SI, SCK

SCK, SI

200

—

Internal shift

clock mode

Valid SI → SCK ↑

1/2 tinst*

1 t^inst*

1 tinst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

1/2 tinst*

SCK ↑ → valid SI hold time

—

* : For information on tinst, see “(4) Instruction Cycle.”

Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.7 VCC

0.3 VCC

0.7 VCC

SI

0.3 VCC

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK

0.2 VCC

tSLOV

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

34

MB89650AR Series

(6) Peripheral Input Timing

Parameter

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Unit Remarks

Min.

1 tinst*

2 tinst*

Max.

—

Peripheral input “H” pulse width 1

Peripheral input “L” pulse width 1

Peripheral input “H” pulse width 2

Peripheral input “L” pulse width 2

t^ILIH1

t^IHIL1

tILIH2

t^IHIL2

µs

INT10 to INT13, EC1,

EC2

—

INT20 to INT2B

—

* : For information on tinst, see “(4) Instruction Cycle.”

tIHIL1

tILIH1

INT10 to INT13,

EC1, EC2

0.8 VCC

0.2 V^CC

0.8 VCC

0.2 VCC

tIHIL2

tILIH2

INT20 to INT2B

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

35

MB89650AR Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Remarks

Parameter

Resolution

Condition

Unit

Min.

—

Typ.

—

Max.

8

—

bit

Total error

—

±1.5

±1.0

LSB

—

Linearity error

—

Differential linearity

error

—

±0.9

LSB

mV

AVR =

AV^CC

Zero transition voltage

AV^SS– 1.0 LSB AV^SS+ 0.5 LSB AV^SS+ 2.0 LSB

VOT

Full-scale transition

voltage

—

AVR – 3.0 LSB AVR – 1.5 LSB

AVR

0.5

—

V^FST

Interchannel

disparity

—

LSB

µs

A/D mode

conversion time

—

44 t^inst*

12 t^inst*

—

Sense mode

conversion time

—

µs

—

Analog port input

current

I^AIN

10

µA

AN0 to

AN7

Analog input voltage

Reference voltage

—

0.0

—

AVR

AV^CC

V

AVR = 5.0V,

when A/D

conversion is

activated

IR

—

100

—

µA

AVR

Reference voltage

supply current

AVR = 5.0V,

when A/D

conversion is

stopped

I^RH

1

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter.

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

36

MB89650AR Series

Digital output

Theoretical conversion value

Actual conversion value

1111 1111

1111 1110

•

(1 LSB × N + V^OT)

AVR

1 LSB =

•

256

•

V^NT– (1 LSB × N + VOT)

•

Linearity error =

1 LSB

•

V( N + 1 ) T – VNT

•

– 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT – (1 LSB × N + 1 LSB)

•

1 LSB

•

0000 0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

(2) Precautions

• Input impedance of the analog input pins

The A/D converter used for the MB89650AR series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating

A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

37

MB89650AR Series

■ EXAMPLE CHARACTERISTICS

(2) “H” Level Output Voltage

(1) “L” Level Output Voltage

VOL vs. IOL

V^OL(V)

VCC – VOH vs. IOH

V^CC– VOH (V)

1.0

V^CC= 2.5 V

TA = +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 2.5 V

V^CC= 3.0 V

0.5

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.4

0.3

0.2

0.1

0.0

V^CC= 4.0 V

VCC = 5.0 V

V^CC= 6.0 V

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

VIN vs.VCC

V^IN(V)

5.0

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

3.5

V^IHS

3.0

2.5

VILS

2.0

1.5

1.0

0.5

0.0

1.0

0.5

0.0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

VILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

38

MB89650AR Series

(5) Power Supply Current (External Clock)

ICC1 vs. VCC, ICC2 vs. VCC

ICC (mA)

16

ICCS1 vs. VCC, ICCS2 vs. VCC

ICCS (mA)

5.0

Divide

by 4 (ICC1)

FCH = 10 MHz

TA = +25°C

FCH = 10 MHz

14

4.5

4.0

TA = +25°C

12

Divide by

4 (I^CCS1)

3.5

3.0

10

8

Divide

by 8

Divide

by 8

2.5

2.0

Divide

by 16

6

4

2

0

Divide

by 16

1.5

1.0

Divide by

64 (I^CCS2)

Divide by

64 (I^CC2)

0.5

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

V

CC (V)

ICCL vs. VCC

ICCLS vs. VCC

ICCL (µA)

ICCLS (µA)

200

50

TA = +25°C

45

40

180

160

140

120

35

30

100

80

25

20

60

40

15

10

20

0

5

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

(Continued)

39

MB89650AR Series

(Continued)

ICCT vs. VCC

ICCH vs. VCC

ICCT (µA)

20

ICCH (µA)

2.0

TA = +25°C

18

16

1.8

1.6

14

12

1.4

1.2

10

8

1.0

0.8

6

4

0.6

0.4

2

0

0.2

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

V

CC (V)

IA vs. AVCC

IR vs. AVR

IA (µA)

5.0

IR (µA)

200

TA = +25°C

FCH = 10 MHz

TA = +25°C

4.5

4.0

180

160

3.5

3.0

140

120

2.5

2.0

100

80

1.5

1.0

60

40

0.5

0

20

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

AV^CC(V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

AVR (V)

(6) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1000

TA = +25°C

100

10

1

2

3

4

5

6

V^CC(V)

40

MB89650AR Series

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

41

MB89650AR Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

CCR

RP

Ri

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

42

MB89650AR Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

43

MB89650AR Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

A

C

←

C ← A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

44

MB89650AR Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

45

MB89650AR Series

■ INSTRUCTION MAP

46

MB89650AR Series

■ MASK OPTIONS

MB89653AR

MB89655AR

MB89656AR

MB89657AR

Part number

MB89P657A

MB89PV650A

No.

Specify

when

ordering

masking

Setting not

possible

Set with EPROM

programmer

Specifying procedure

Can be set per pin.

(Select in a group of

four bits for P14 to

P17, P40 to P43, and

P40 to P47.)

(P75 to P70 are

available only for

without a pull-up

resistor.)

Pull-up resistors

P00 to P07, P10 to P17,

P20 to P22, P24 to P26,

P30 to P37, P40 to P47,

P60 to P67, P70 to P75,

P80 to P81

Specify by

Fixed to without

pull-up resistor

1

Power-on reset selection

With power-on reset

Fixed to with

power-on reset

2

3

Selectable

With power-on reset

Without power-on reset

Selection of the oscillation stabilization

time initial value

Crystal oscillator: 2¹⁸/FCH

(Approx. 26.2 ms^*1)

2¹⁸/FC H

(Approx. 26.2 ms^*1)

Fixed to 2¹⁸/FCH

(Approx. 26.2 ms^*1)

Ceramic oscillator: 2¹³/FCH

(Approx. 26.2 ms^*1)

Selection either single- or dual-clock

system

Fixed to dual-clock

system

4

Selectable

Setting possible

Single clock

Dual clock

Can be selected from

the following six

options:

Selection of a built-in booster*²

Without booster

-101: Without booster

With booster

(Segment output switching)

16 segments:Selection of P30 to P37

and P40 to P47

20 segments:Selection of P30 to P37

and P40 to P43

Fixed to without

booster

5

Selectable

-102: 16 segments

-103: 20 segments

-104: 24 segments

-105: 28 segments

-106: 32 segments

24 segments:Selection of P30 to P37

28 segments:Selection of P30 to P33

32 segments:No port selection

*1: The value at FCH = 10 MHz

*2: On microcontrollers with a built-in booster, only 1/3 bias can be used. The 1/2 duty cannot be used.

Note: Reset is input asynchronized with the internal clock whether with or without power-on reset.

47

MB89650AR Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89653APFV

MB89655APFV

MB89656APFV

MB89657APFV

MB89P657APFV-101

MB89P657APFV-102

MB89P657APFV-103

MB89P657APFV-104

MB89P657APFV-105

MB89P657APFV-106

100-pin Plastic SQFP

(FPT-100P-M05)

MB89653APF

MB89655APF

MB89656APF

MB89657APF

MB89P657APF-101

MB89P657APF-102

MB89P657APF-103

MB89P657APF-104

MB89P657APF-105

MB89P657APF-106

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Ceramic MQFP

(MQP-100C-P02)

MB89PV650ACF

48

MB89650AR Series

■ PACKAGE DIMENSIONS

100-pin plastic LQFP

(FPT-100P-M05)

+0.20

16.00±0.20(.630±.008)SQ

1.50^–0.10

.059⁺^–.^.⁰⁰⁰⁰⁴⁸

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

+0.05

0.50(.0197)TYP

0.18–⁺0⁰.^.0⁰3⁸

0.127^–0.02

M

Details of "B" part

0.08(.003)

+.003

+.002

.007^–.001

.005^–.001

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10°

C

1994 FUJITSU LIMITED F100007S-2C-2

Dimensions in mm (inches)

49

MB89650AR Series

100-pin plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

3.35(.132)MAX

20.00±0.20(.787±.008)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F100008-3C-2

Dimensions in mm (inches)

50

MB89650AR Series

100-pin Ceramic MQFP

(MQP-100C-P02)

0.50±0.15

(.0197±.0060)

15.00±0.25SQ

(.591±.010)

0.18±0.05

(.007±.002)

PIN No.1 INDEX

14.82±0.35SQ

(.583±.014)

0.30(.012)

TYP

1.02±0.13

(.040±.005)

10.92(.430)

TYP

7.14(.281)

TYP

12.00(.472) 17.20(.667)

TYP

PAD No.1 INDEX

4.50(.177)SQ

TYP

1.10⁺^–0⁰^.^.²⁴⁵⁵

12.00(.472)TYP

17.20(.667)TYP

.043–⁺.^.0⁰1¹0⁸

10.92(.430)

TYP

9.94(.392)MAX

0.15±0.05

(.006±.002)

C

1994 FUJITSU LIMITED M100002SC-2-2

Dimensions in mm (inches)

51

MB89650AR Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

KAWASAKI PLANT, 4-1-1, Kamikodanaka,

Nakahara-ku, Kawasaki-shi,

Kanagawa 211-8588, Japan

Tel: +81-44-754-3763

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0004

FUJITSU LIMITED Printed in Japan


型号：	MB89656AR
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总52页 (文件大小：733K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89656AR [FUJITSU]

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