MB89623R [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89623R |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总61页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12534-4E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89620R Series
MB89623R/625R/P625/W625/626R/627R/P627/W627/T627R
MB89PV620
■ DESCRIPTION
The MB89620R series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external
interrupt.
The MB89620R series is applicable to a wide range of applications from consumer products to industrial equip-
ment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Various package options
Three types of QFP packages (1 mm, 0.65 mm, or 0.5 mm lead pitch)
SDIP packages
• High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• Four types of timers
8-bit PWM timer (also usable as a reload timer)
8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.)
16-bit timer/counter
20-bit timebase timer
• Two serial interfaces
Switchable transfer direction allows communication with various equipment.
• 8-bit A/D converter
Sense mode function enabling comparison at 5 µs
Activation by an external input capable
(Continued)
MB89620R Series
(Continued)
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface functions
Including hold and ready functions
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic LQFP
64-pin Plastic QFP
64-pin Plastic QFP
(FPT-64P-M09)
(DIP-64P-M01)
(FPT-64P-M03)
(FPT-64P-M06)
64-pin Ceramic SH-DIP
64-pin Ceramic MQFP
64-pin Ceramic MDIP
(DIP-64C-A06)
(MQP-64C-P01)
(MDP-64C-P02)
2
MB89620R Series
■ PRODUCT LINEUP
Part number
MB89P625 MB89P627
MB89W625 MB89W627
MB89T627R
MB89PV620
MB89623R MB89625R MB89626R MB89627R
Parameter
Classificati
on
Piggyback/
evaluation
product for
evaluation
and
External
ROM
products
One-time PROM
products/EPROM
products
Mass production products
(mask ROM products)
development
16 K × 8 bits 32 K × 8 bits
ROM size 8 K × 8 bits 16 K × 8 bits 24 K × 8 bits 32 K × 8 bits External
(internal (internal (internal (internal ROM
mask ROM) mask ROM) mask ROM) mask ROM)
32 K × 8 bits
(external
ROM)
(internal
PROM,
(internal
PROM,
programmable programmable
with
with
general-
purpose
EPROM
general-
purpose
EPROM
programmer) programmer)
RAM size 256 × 8 bits 512 × 8 bits 768 × 8 bits 1 K × 8 bits 1 K × 8 bits 512 × 8 bits 1 K × 8 bits 1 K × 8 bits
CPU
functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs /10 MHz
3.6 µs/10 MHz
Ports
Input ports:
5 (4 ports also serve as peripherals.)
8 (All also serve as peripherals.)
8 (4 ports also serve as peripherals.)
8 (All also serve as bus control pins.)
24 (All also serve as bus pins or peripherals.)
53
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain)
Output ports (CMOS):
I/O ports (CMOS):
Total:
8-bit PWM
timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms)
8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms)
8-bit pulse
width
count
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation
timer
(Continuous measurement “H” pulse width/“L” pulse width/from ↑ to ↑/from ↓ to ↓ capable)
16-bit
timer/
counter
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (Rising/falling/both edges selectable)
8-bit serial
I/O 1,
8-bit serial
I/O 2
8 bits
LSB first/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
8-bit A/D
converter
8-bit resolution × 8 channels
A/D conversion mode (conversion time: 18 µs)
Sense mode (conversion time: 5 µs)
Continuous activation by an external activation or an internal timer capable
Reference voltage input
(Continued)
3
MB89620R Series
(Continued)
Part number
MB89P625 MB89P627
MB89W625 MB89W627
MB89PV620
MB89623R MB89625R MB89626R MB89627R MB89T627R
Parameter
External
interrupt
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectable
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby
modes
Sleep mode, stop mode
CMOS
Process
Operating
voltage*
2.2 V to 6.0 V
2.7 V to 6.0 V
MBM27C256
A-20TV
MBM27C256
A-20CZ
EPROM
for use
—
*: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89626R
MB89623R
MB89625R
MB89627R
MB89T627R
MB89P625
MB89W625
MB89W627
Package
MB89P627
MB89PV620
DIP-64P-M01
FPT-64P-M03
FPT-64P-M06
FPT-64P-M09
DIP-64C-A06
MQP-64C-P01
MDP-64C-P02
×
×*
×
×
×*
×
×*
×*
×*
×*
×
×
×
×
×
×
×
×
×
×
×
×
: Available
×: Not available
*: Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available.
64SD-64QF2-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M03
64SD-64SQF-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M09
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89620R Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89623R, the upper half of the register bank cannot be used.
• On the MB89P627, the program area starts from address 8007H but on the MB89PV620 and MB89627R starts
from 8000H.
(On the MB89P627, addresses 8000H to 8006H comprise the option setting area, option settings can be read
by reading these addresses. On the MB89PV620 and MB89627R, addresses 8000H to 8006H could also be
used as a program ROM. However, do not use these addresses in order to maintain compatibility of the
MB89P627.)
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics”.)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P40 to P47 on the MB89P625, MB89W625, MB89P627, and MB89W627.
• A pull-up resistor is not selectable for P50 to P57 when the A/D converter is used.
• Options are fixed on the MB89PV620.
5
MB89620R Series
4. Differences between the MB89620 and MB89620R Series
• Memory access area
Memory access area of the following products is the same; both the MB89625 and MB89625R, and both the
MB89627 and MB89627R.
The access area of the MB89623 and MB89626 is different from that of the MB89623R and MB89626R respec-
tively when using in external bus mode. See below.
Memory area
Address
MB89623
MB89623R
0000H to 007FH
0080H to 017FH
0180H to 027FH
0280H to BFFFH
C000H to DFFFH
E000H to FFFFH
I/O area
I/O area
RAM area
RAM area
Access prohibited
External area
External area
ROM area
Access prohibited
ROM area
Memory area
Address
MB89626
MB89626R
0000H to 007FH
0080H to 037FH
0380H to 047FH
0480H to 7FFFH
8000H to 9FFFH
A000H to FFFFH
I/O area
I/O area
RAM area
RAM area
Access prohibited
External area
Access prohibited
ROM area
External area
ROM area
• Other specifications
Both the MB89620R and MB89620 series is the same.
• Electrical specifications/electrical characteristics
Electrical specifications of the MB89620R series are the same with that of the MB89620 series.
■ CORRESPONDENCE BETWEEN THE MB89620 AND MB89620R SERIES
• The MB89620R series is the reduction version of the MB89620 series.
• The MB89620 and MB89620R series consist of the following products:
MB89620 series
MB89623
MB89625
MB89626
MB896267
MB89P625
MB89P627 MB89PV620
MB89620R series
MB89623R
MB89625R
MB89626R MB896267R
MB89620 series
MB89620R series
MB89W625 MB89W627 MB89T627R
6
MB89620R Series
■ PIN ASSIGNMENT
(Top view)
1
VCC
P36/WTO
P37/PTO
P40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
P35/PWC
P34/EC
3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCC
A14
A13
A8
VPP
A12
A7
92
91
90
89
88
87
86
85
84
83
82
81
80
79
4
P33/SI1
P32/SO1
P31/SCK1
P30/ADST
VSS
P41
5
P42
P43
6
A6
7
P44/BZ
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
A9
A5
8
A11
OE
A10
CE
O8
A4
9
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A2
A1
A0
O7
O1
O2
O3
VSS
O6
O5
O4
AVR
AVSS
Each pin inside the
dashed line is for the
MB89PV620 only.
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
RST
MOD0
MOD1
X0
X1
VSS
(DIP-64P-M01)
(DIP-64C-A06)
(MDP-64C-P02)
(Top view)
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
1
2
3
4
5
6
7
8
48
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
9
10
11
12
13
14
15
16
(FPT-64P-M03)
(FPT-64P-M09)
7
MB89620R Series
(Top view)
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P30/ADST
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
9
10
11
12
13
14
15
16
17
18
19
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
Each pin inside the dashed line
is for the MB89PV620 only.
(FPT-64P-M06)
(MQP-64C-P01)
• Pin assignment on package top (MB89PV620 only)
Pin no.
65
Pin name
N.C.
VPP
Pin no.
73
Pin name
A2
Pin no.
81
Pin name
N.C.
O4
Pin no.
89
Pin name
OE
66
74
A1
82
90
N.C.
A11
A9
67
A12
A7
75
A0
83
O5
91
68
76
N.C.
O1
84
O6
92
69
A6
77
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
A14
VCC
71
A4
79
O3
87
CE
95
72
A3
80
VSS
88
A10
96
N.C.: Internally connected. Do not use.
8
MB89620R Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
X0
Function
SH-DIP*1 QFP1*3
LQFP*5
MDIP*2
30
MQFP*4
23
QFP2*6
22
A
B
C
Crystal oscillator pins
31
24
23
X1
28
21
20
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VCC or VSS.
29
22
21
27
20
19
Reset I/O pin
This pin is an N-ch open-drain output type with a
pull-up resistor, and a hysteresis input type.
“L” is output from this pin by an internal reset source.
The internal circuit is initialized by the input of “L”.
56 to 49 49 to 42 48 to 41 P00/AD0 to
P07/AD7
D
D
F
F
General-purpose I/O ports
When an external bus is used, these ports function as
multiplex pins of lower address output and data I/O.
48 to 41 41 to 34 40 to 33 P10/A08 to
P17/A15
General-purpose I/O ports
When an external bus is used, these ports function as
upper address output.
40
39
33
32
32
31
P20/BUFC
P21/HAK
General-purpose output-only port
When an external bus is used, this port can also be
used as a buffer control output by setting the BCTR.
General-purpose output-only port
When an external bus is used, this port can also be
used as a hold acknowledge output by setting the
BCTR.
38
37
36
35
34
33
31
30
29
28
27
26
30
29
28
27
26
25
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
D
D
F
F
F
F
General-purpose output-only port
When an external bus is used, this port can also be
used as a hold request input by setting the BCTR.
General-purpose output-only port
When an external bus is used, this port functions as a
ready input.
General-purpose output-only port
When an external bus is used, this port functions as a
clock output.
General-purpose output-only port
When an external bus is used, this port functions as a
write signal output.
General-purpose output-only port
When an external bus is used, this port functions as a
read signal output.
P27/ALE
General-purpose output-only port
When an external bus is used, this port functions as
an address latch signal output.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*4: MQP-64C-P01
*2: MDP-64C-P02
*5: FPT-64P-M03
*3: FPT-64P-M06
*6: FPT-64P-M09
9
MB89620R Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
General-purpose I/O port
Also serves as an A/D converter external activation.
This port is a hysteresis input type.
SH-DIP*1 QFP1*3
LQFP*5
QFP2*6
MDIP*2
MQFP*4
58
51
50
51
52
53
54
55
P30/ADST
E
E
E
E
E
E
59
60
61
62
63
52
53
54
55
56
P31/SCK1
P32/SO1
P33/SI1
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O 1.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O 1.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O 1.
This port is a hysteresis input type.
P34/EC
General-purpose I/O port
Also serves as the external clock input for the 16-bit
timer/counter. This port is a hysteresis input type.
P35/PWC
General-purpose I/O port
Also serves as the measured pulse input for the 8-bit
pulse width count timer. This port is a hysteresis input
type.
1
2
58
59
57
58
P36/WTO
P37/PTO
E
E
General-purpose I/O port
Also serves as the toggle output for the 8-bit pulse
width count timer. This port is a hysteresis input type.
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM
timer. This port is a hysteresis input type.
3 to 6
7
60 to 63 59 to 62 P40 to P43
G
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
64
1
63
64
1
P44/BZ
N-ch open-drain I/O port
Also serves as a buzzer output. This port is a
hysteresis input type.
8
9
P45/SCK2
P46/SO2
P47/SI2
G
G
G
N-ch open-drain I/O port
Also serves as the clock I/O for the 8-bit serial I/O 2.
This port is a hysteresis input type.
2
N-ch open-drain I/O port
Also serves as the data output for the 8-bit serial I/O 2.
This port is a hysteresis input type.
10
3
2
N-ch open-drain I/O port
Also serves as the data input for the 8-bit serial I/O 2.
This port is a hysteresis input type.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*4: MQP-64C-P01
*2: MDP-64C-P02
*5: FPT-64P-M03
*3: FPT-64P-M06
*6: FPT-64P-M09
10
MB89620R Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
SH-DIP*1 QFP1*3
LQFP*5
QFP2*6
MDIP*2
MQFP*4
11 to 18
4 to 11
3 to 10 P50/AN0 to
P57/AN7
H
I
N-ch open-drain output-only ports
Also serve as the analog input for the A/D converter.
22 to 25 15 to 18 14 to 17 P60/INT0 to
P63/INT3
General-purpose input-only ports
Also serve as an external interrupt input. These ports
are a hysteresis input type.
26
19
18
P64
I
General-purpose input-only port
This port is a hysteresis input type.
64
32, 57
19
57
25, 50
12
56
VCC
—
—
—
—
—
Power supply pin
24, 49 VSS
Power supply (GND) pins
11
12
13
AVCC
A/D converter power supply pin
A/D converter reference voltage input pin
20
13
AVR
AVSS
21
14
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01, DIP-64C-A06
*4: MQP-64C-P01
*2: MDP-64C-P02
*5: FPT-64P-M03
*3: FPT-64P-M06
*6: FPT-64P-M09
11
MB89620R Series
• External EPROM pins (MB89PV620 only)
Pin no.
Pin name
I/O
Function
MDIP*1
MQFP*2
65
66
VPP
O
O
“H” level output pin
Address output pins
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
I
Power supply (GND) pin
Data input pins
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
86
88
89
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
91
92
—
94
95
96
A13
A14
VCC
O
O
O
EPROM power supply pin
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
*1: MDP-64C-P02
*2: MQP-64C-P01
12
MB89620R Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
R
P-ch
• Hysteresis input
N-ch
D
• CMOS output
• CMOS input
R
P-ch
N-ch
• Pull-up resistor optional (except P22 and P23)
E
• CMOS output
• Hysteresis input
R
P-ch
N-ch
• Pull-up resistor optional
• CMOS output
F
P-ch
N-ch
(Continued)
13
MB89620R Series
(Continued)
Type
Circuit
Remarks
• N-ch open-drain output
G
• Hysteresis input
R
N-ch
• Pull-up resistor optional
(MB89623R, MB89625R, MB89626R, and
MB89627R only)
H
• N-ch open-drain output
• Analog input
R
N-ch
Analog input
• Pull-up resistor optional
I
• Hysteresis input
• Pull-up resistor optional
R
14
MB89620R Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
15
MB89620R Series
■ PROGRAMMING TO THE EPROM ON THE MB89P625
The MB89P625 is an OTPROM version of the MB89620R series.
1. Features
• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below.
EPROM mode
Single chip
(Corresponding addresses on the EPROM programmer)
Address
0000H
I/O
0080H
0280H
RAM
External area
BFF0H
BFF6H
3FF0H
External area
External area
Option area
3FF6H
Vacancy
(Read value: FFH)
C000H
FFFFH
4000H
7FFFH
PROM
16 KB
EPROM
16 KB
3. Programming to the EPROM
In EPROM mode, the MB89P625 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH
while operating as a single chip assign to 4000H to 7FFFH in EPROM mode).
Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each
corresponding option, see “4. Setting OTPROM Options.”)
(3) Program to 3FF0H to 7FFFH with the EPROM programmer.
16
MB89620R Series
4. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map.
The relationship between bits and options is shown on the following bit map:
• OTPROM option bit map (MB89P625)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Reset pin
output
Power-on
reset
1: Yes
0: No
Oscillation
stabilization
time
1: Crystal
0: Ceramic
3FF0H Readable Readable Readable Readable Readable 1: Yes
and
writable
and
writable
and
writable
and
writable
and
writable
0: No
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
3FF1H
3FF2H
3FF3H
3FF4H
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P37
P36
P35
P34
P33
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P57
P56
P55
P54
P53
P52
P51
P50
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
P64
Pull-up
P63
P62
P61
P60
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
3FF5H Readable Readable Readable 1: No
and
and
and
0: Yes
writable
writable
writable
Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.
17
MB89620R Series
■ PROGRAMMING TO THE EPROM ON THE MB89P627
The MB89P627 is an OTPROM version of the MB89620R series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
Address
0000H
I/O
0080H
0480H
RAM
External area
External area
8000H
0000H
Option area
0007H
8007HH
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P627 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH
while operating as a single chip assign to 0007H to 7FFFH in EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “4. Setting OTPROM Options.”)
(3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89620R Series
4. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map.
The relationship between bits and options is shown on the following bit map:
• OTPROM option bit map (MB89P627)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Reset pin Oscillation Power-on
stabilization
time
1: Crystal
0: Ceramic
output
0000H Readable Readable Readable Readable Readable 1: Yes
reset
1: Yes
0: No
and
writable
and
writable
and
writable
and
writable
and
writable
0: No
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0001H
0002H
0003H
0004H
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P37
P36
P35
P34
P33
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P57
P56
P55
P54
P53
P52
P51
P50
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
P64
Pull-up
P63
P62
P61
P60
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0005H Readable Readable Readable 1: No
and
and
and
0: Yes
writable
writable
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
0006H Readable Readable Readable Readable Readable Readable Readable Readable
and
writable
and
writable
and
writable
and
writable
and
writable
and
writable
and
writable
and
writable
Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.
19
MB89620R Series
■ HANDLING THE MB89P625/P627
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 h
Data verification
Assembly
2. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
3. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 Ws/cm2 is required to completely erase an internal EPROM. This dosage
can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000
µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters
should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having wave-
lengths shorter than 4000Å. Although erasure time will be much longer than with UV source at 2537Å, never-
theless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure
to them should be prevented to realize maximum system reliability. If used in such an environment, the package
windows should be covered by an opaque label or substance.
20
MB89620R Series
4. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufacturer
and programmer name
Compatible socket
adapter
Sun Hayato Co., Ltd.
Part number
Package
Advantest
Data I/O Co., Ltd.
Corp.
UNISITE
Recommended
Recommended
3900
2900
R4945A
MB89P625P-SH
MB89P625PF
SH-DIP-64 ROM-64SD-28DP-8L
—
Recommended
Recommended
QFP-64
QFP-64
ROM-64QF-28DP-8L
ROM-64QF2-28DP-8L
Recom-
mended
MB89P625PFM
—
Recommended
*: It is required to connect a capacitor of approximately 0.1 µF between VPP and GND, and VCC and GND.
Inquiry:Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
Data I/O Co., Ltd.: TEL:USA/ASIA(1)-206-881-6444
EUROPE(49)-8-985-8580
Advantest Corp.:TEL:Except JAPAN (81)-3-3930-4111
21
MB89620R Series
■ PROGRAMMING TO THE EPROM PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
3. Memory Space
Memory space in 32-Kbyte PROM is diagrammed below.
Corresponding addresses on the EPROM programmer
Single chip
Address
0000H
I/O
0080H
0480H
8000H
8006H
RAM
Not available
Not available
0000H
0006H
Not available
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0006H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
22
MB89620R Series
■ BLOCK DIAGRAM
X0
X1
20-bit timebase
timer
Oscillator
Clock controller
8-bit PWM timer
P37/PTO
Reset circuit
(WDT)
RST
P36/WTO
P35/PWC
8-bit pulse width
count timer
CMOS I/O port
P00/AD0
to P07/AD7
8
8
P34/EC
16-bit timer/counter
P10/A08
to P17/A15
P33/SI1
P32/SO1
P31/SCK1
8-bit serial I/O 1
CMOS I/O port
8-bit serial I/O 2
Buzzer output
MOD0
MOD1
External bus
interface
P30/ADST
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
P47/SI2
P46/SO2
P45/SCK2
CMOS output port
P44/BZ
4
8
P40 to P43
N-ch open-drain I/O port
N-ch open-drain output port
RAM
8
P50/AN0
to P57/AN7
8-bit A/D converter
F2MC-8L
CPU
AVR
AVCC
AVSS
ROM
4
4
P60/INT0
to P63/INT3
External interrupt
P64
Input port
The other pins
VCC, VSS × 2
23
MB89620R Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89620R series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89620R series is structured as illustrated below.
• Memory Space
MB89627R
MB89P627
MB89T627R
MB89W627
MB89625R
MB89P625
MB89W625
MB89623R
I/O
MB89PV620
I/O
MB89626R
I/O
0000H
0080H
0000H
0080H
0000H
0080H
0000H
0080H
0100H
0000H
0080H
0100H
I/O
I/O
RAM
512 B
RAM
768 B
RAM
256 B
RAM
1 KB
RAM
1 KB
0100H
0200H
0100H
0200H
0100H
0180H
0280H
Register
Register
Register
Register
Register
0200H
0280H
0200H
0380H
3
*
3
*
0480H
8000H
0480H
8000H
8006H
0480H
8000H
External area
External area
External area
External area
External area
2
2
*
*
3
*
8006H
A000H
C000H
FFFFH
C000H
E000H
ROM
32 KB
External ROM
32 KB
ROM
24 KB
3
*
ROM*1
16 KB
ROM*1
8 KB
FFFFH
FFFFH
FFFFH
FFFFH
*1: The ROM area is an external area depending on the mode.
*2: Since addresses 8000H to 8005H for the MB89P627 and MB89W627 comprise an option area, do not
use this area for the MB89PV620 and MB89627R.
*3: Access to this area is prohibited when using external bus mode.
24
MB89620R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
25
MB89620R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag:Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low
N-flag:Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is
cleared to ‘0’.
Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag:Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’
otherwise.
Set to the shift-out value in the case of a shift instruction.
26
MB89620R Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89620R. In the MB89623R, there are 16
banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to
addresses 0180H to 01FFH using an external circuit. The bank currently in use is indicated by the register bank
pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
27
MB89620R Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
DDR0
Port 0 data direction register
Port 1 data register
(R/W)
(W)
PDR1
DDR1
Port 1 data direction register
Port 2 data register
(R/W)
(R/W)
PDR2
BCTR
External bus pin control register
Vacancy
Vacancy
(R/W)
(R/W)
(R/W)
STBC
WDTC
TBTC
Standby control register
Watchdog timer control register
Timebase timer control register
Vacancy
(R/W)
(W)
PDR3
DDR3
PDR4
BZCR
PDR5
PDR6
CNTR
COMR
PCR1
PCR2
RLBR
Port 3 data register
Port 3 data direction register
Port 4 data register
(R/W)
(R/W)
(R/W)
(R)
Buzzer register
Port 5 data register
Port 6 data register
(R/W)
(W)
PWM control register
PWM compare register
PWC pulse width control register 1
PWC pulse width control register 2
PWC reload buffer register
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
TMCR
TCHR
TCLR
16-bit timer control register
16-bit timer count register (H)
16-bit timer count register (L)
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
SMR1
SDR1
SMR2
SDR2
Serial I/O 1 mode register
Serial I/O 1 data register
Serial I/O 2 mode register
Serial I/O 2 data register
(Continued)
28
MB89620R Series
(Continued)
Address
Read/write
(R/W)
Register name
ADC1
Register description
20H
21H
A/D converter control register 1
(R/W)
ADC2
A/D converter control register 2
A/D converter data register
Vacancy
22H
(R/W)
ADCD
23H
24H
(R/W)
(R/W)
EIC1
EIC2
External interrupt 1 control register 1
External interrupt 1 control register 2
Vacancy
25H
26H to 7BH
7CH
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
7DH
7EH
7FH
Note: Do not use vacancies.
29
MB89620R Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Rating
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
AVCC
1
Power supply voltage
VSS – 0.3
VSS – 0.3
VSS + 7.0
V
V
*
AVR must not exceed AVCC + 0.3
V.
A/D converter reference input
voltage
AVR
VSS + 7.0
VI
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VCC + 0.3
VSS + 7.0
VCC + 0.3
VSS + 7.0
V
V
V
V
Except P40 to P47*2
P40 to P47
Input voltage
VI2
VO
VO2
Except P40 to P47*2
P40 to P47
Output voltage
“L” level maximum output
current
IOL
20
4
mA
mA
mA
mA
mA
mA
mA
mA
Average value (operating
current × operating rate)
“L” level average output current
IOLAV
∑IOL
∑IOLAV
IOH
“L” level total maximum output
current
100
40
“L” level total average output
current
Average value (operating
current × operating rate)
“H” level maximum output
current
–20
–4
Average value (operating
current × operating rate)
“H” level average output current
IOHAV
∑IOH
∑IOHAV
“H” level total maximum output
current
–50
–20
“H” level total average output
current
Average value (operating
current × operating rate)
Power consumption
Operating temperature
Storage temperature
PD
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
*1: Use AVCC and VCC set to the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
*2: VI and VO must not exceed VCC + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB89620R Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation assurance range*
(MB89623R/625R/626R/627R)
2.2*
6.0*
V
VCC
AVCC
Power supply voltage
Normal operation assurance range*
(MB89P625/W625/P627/T627R/W627/PV620)
2.7*
1.5
6.0*
6.0
V
V
Retains the RAM state in stop mode
A/D converter reference input
voltage
AVR
TA
0.0
AVCC
+85
V
Operating temperature
–40
°C
*: These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics.”
Figure 1 Operating Voltage vs. Clock Operating Frequency
6
Analog accuracy assured in the
AVCC = VCC = 3.5 V to 6.0 V range
5
Operation assurance range
4
3
2
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Clock operating frequency (MHz)
Note: The shaded area is assured only for the MB89623R/625R/626R/627R.
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
31
MB89620R Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P22, P23
0.7 VCC
VCC + 0.3
VIH
V
“H” level input
voltage
RST, MOD0,
MOD1,
P30 to P37,
P60 to P64
0.8 VCC
VCC + 0.3
VIHS
V
0.8 VCC
VCC + 0.3
0.3 VCC
VIHS2
VIL
P40 to P47
V
V
P00 to P07,
P10 to P17,
P22, P23
VSS − 0.3
“L” level input
voltage
RST, MOD0,
MOD1,
VSS − 0.3
0.2 VCC
VILS
P30 to P37,
P40 to P47,
P60 to P64
V
Open-drain
output pin
application
voltage
VSS − 0.3
VSS − 0.3
VCC + 0.3
VSS + 6.0
VD
V
V
P50 to P57
P40 to P47
VD2
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
“H” level output
voltage
4.0
VOH
IOH = –2.0 mA
IOL = +4.0 mA
V
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57
0.4
0.4
VOL
V
V
“L” level output
voltage
VOL2
RST
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P64,
MOD0, MOD1
Input leakage
current
(Hi-z output
leakage current)
0.0 V < VI <
VCC
Without
pull-up resistor
±5
ILI1
µA
kΩ
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P64,
RST
Pull-up
resistance
25
50
100
RPULL
VI = 0.0 V
(Continued)
32
MB89620R Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
MB89623R/
625R/626R/
627R/T627R/
PV620
—
9
15
mA
FC = 10 MHz
Normal
operating
mode
ICC
MB89P625/
W625
MB89P627/
W627
*2
tinst = 0.4 µs
—
10
18
mA
VCC
FC = 10 MHz
Sleep mode
tinst = 0.4 µs
ICCS
ICCH
IA
—
—
—
3
—
1
4
1
3
mA
µA
Power supply
current*1
*2
Stop mode
TA = +25°C
FC = 10 MHz,
when starting
A/D conversion
mA
AVCC
FC = 10 MHz,
TA = +25°C,
IAH
—
—
—
1
µA
when stopping
A/D conversion
Other than
AVCC, AVSS,
VCC, and VSS
Input
capacitance
CIN
f = 1 MHz
10
pF
*1: In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included.
The power supply current is measured at the external clock.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
33
MB89620R Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
16 tXCYL
—
ns
Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Condition
Unit
Remarks
Parameter
Min.
—
Max.
Power supply rising time
Power supply cut-off time
tR
50
—
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
1
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
34
MB89620R Series
(3) Clock Timing
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
1
Max.
10
Clock frequency
Clock cycle time
FC
X0, X1
X0, X1
MHz
ns
tXYCL
100
1000
PWH
PWL
—
Input clock pulse width
X0
X0
20
—
—
ns
ns
External clock
External clock
Input clock rising/falling tCR
time
10
tCF
• X0 and X1 Timing and Conditions
tXCYL
PW
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
tinst = 0.4 µs when operating at
FC = 10 MHz
tinst
4/FC
µs
35
MB89620R Series
(5) Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Cycle time
CLK ↑ → CLK ↓
Min.
Max.
tXCYL × 2 at 10 MHz
oscillation
tCYC
200
—
ns
ns
CLK
—
Approx. tCYC/2 at
10 MHz oscillation
tCHCL
30
100
tCYC
tCHC
2.4 V
2.4 V
CLK
0.8 V
36
MB89620R Series
(6) Bus Read Timing
Parameter
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
1/4 tinst*– 64 ns
1/4 tinst*– 20 ns
—
Max.
—
RD, A15 to A08,
AD7 to AD0
Valid address → RD ↓ time
RD pulse width
tAVRL
tRLRH
tAVDV
µs
µs
RD
—
AD7 to AD0,
A15 to A08
In the case
µs
Valid address → data read time
1/2 tinst*
of no wait
1/2 tinst*– 80
ns
In the case
µs
RD, AD7 to AD0
—
RD ↓ → data read time
tRLDV
of no wait
AD7 to AD0, RD
RD, ALE
0
—
—
—
—
—
—
RD ↑ → data hold time
RD ↑ → ALE ↑ time
tRHDX
tRHLH
µs
µs
µs
µs
ns
µs
—
1/4 tinst*– 40 ns
1/4 tinst*– 40 ns
1/4 tinst*– 40 ns
0
RD, A15 to A08
RD ↑ → address invalid time tRHAX
RD ↓ → CLK ↑ time
CLK ↓ → RD ↑ time
RD ↓ → BUFC ↓ time
tRLCH
tCLRH
tRLBL
RD, CLK
RD, BUFC
–5
A15 to A08,
AD7 to AD0,
BUFC
5
—
BUFC ↑ → valid address time tBHAV
µs
*: For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
tRHL
ALE
0.8 V
0.7 VCC
2.4 V
2.4 V
0.7 VCC
0.3 VCC
AD
0.8 V
0.8 V
0.3 VCC
tRHDX
tAVD
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
tCLRH
A
tRLC
0.8 V
tAVRL
tRLDV
tRHA
tRLR
2.4 V
RD
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
0.8 V
37
MB89620R Series
(7) Bus Write Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit Remarks
Parameter
Min.
Max.
AD7 to AD0,
ALE, A15 to A08
1/4 tinst*1– 64 ns
Valid address → ALE ↓ time tAVLL
—
µs
ALE ↓ time → address
tLLAX
AD7 to AD0,
ALE, A15 to A08
5
—
ns
invalid time
WR, ALE
inst*1– 60 ns
1/4 t
Valid address → WR ↓ time
WR pulse width
tAVWL
tWLWH
tDVWH
—
—
—
—
—
—
—
—
—
—
µs
µs
µs
ns
µs
µs
µs
ns
µs
µs
WR
1/2 tinst*1– 20 ns
1/2 tinst*1– 60 ns
AD7 to AD0, WR
WR, A15 to A08
AD7 to AD0, WR
WR, ALE
Write data → WR ↑ time
inst*1– 40 ns
—
1/4 t
WR ↑ → address invalid time tWHAX
1/4 tinst*1– 40 ns
1/4 tinst*1– 40 ns
1/4 tinst*1– 40 ns
0
WR ↑ → data hold time
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
CLK ↓ → WR ↑ time
ALE pulse width
tWHDX
tWHLH
tWLCH
tCLWH
tLHLL
WR, CLK
ALE
1/4 tinst*1– 35 ns*2
ALE,CLK
inst*1– 30 ns*2
1/4 t
ALE ↓ → CLK ↑ time
tLLCH
*1: For information on tinst, see “(4) Instruction Cycle.”
*2: These characteristics are also applicable to the bus read timing.
2.4 V
CLK
0.8 V
tLHLL
tLLC
tWHL
2.4 V
ALE
AD
A
0.8 V
0.8 V
tAVL
tLLAX
2.4 V
0.8 V
2.4 V 2.4 V
0.8 V 0.8 V
2.4 V
0.8 V
tWHD
tDVW
2.4 V
tCLWH
2.4 V
0.8 V
tWLC
0.8 V
tAVW
tWHA
tWLW
2.4 V
WR
0.8 V
38
MB89620R Series
(8) Ready Input Timing
Parameter
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name Condition
Unit Remarks
Min.
60
0
Max.
—
RDY valid → CLK ↑ time
CLK ↑ → RDY invalid time
tYVCH
tCHYX
ns
ns
*
*
RDY, CLK
—
—
*: These characteristics are also applicable to the read cycle.
2.4 V
2.4 V
CLK
ALE
AD
A
Address
Data
WR
tYVCH tCHYX
RDY
tYVCH tCHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
39
MB89620R Series
(9) Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
SCK1,
SCK2
Serial clock cycle time
tSCYC
2 tinst*
—
µs
SCK1,
SO1
SCK2,
SO2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
–200
200
ns
Internal shift
clock mode
SI1, SCK1
SI2, SCK2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
tSHIX
tSHSL
tSLSH
1/2 tinst*
1/2 tinst*
1 tinst*
—
—
—
—
µs
µs
µs
µs
SCK1, SI1
SCK2, SI2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
SCK1,
SCK2
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK1,
SCK2
1 tinst*
SCK1,
SO1
SCK2,
SO2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
External shift
clock mode
tSLOV
0
200
ns
SI1, SCK1
SI2, SCK2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
tSHIX
1/2 tinst*
1/2 tinst*
—
—
µs
µs
SCK1, SI1
SCK2, SI2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
*: For information on tinst, see “(4) Instruction Cycle.”
40
MB89620R Series
• Internal Shift Clock Mode
tSCYC
SCK1
SCK2
2.4 V
0.8 V
0.8 V
tSLOV
SO1
SO2
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
SI1
SI2
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
tSHSL
SCK1
SCK2
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO1
SO2
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI1
SI2
41
MB89620R Series
(10) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
tILIH1
PWC,
EC, INT0
to INT3
2 tinst*
—
µs
µs
—
tIHIL1
2 tinst*
—
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
tILIH2
tIHIL2
tILIH2
tIHIL2
32 tinst*
32 tinst*
8 tinst*
—
—
—
—
µs
µs
µs
µs
A/D mode
ADST
Sense mode
8 tinst*
*: For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
0.8 VCC
0.8 VCC
0.2 VCC
PWC
EC
INT0 to INT3
0.2 VCC
tIHIL2
tILIH2
0.8 VCC
0.8 VCC
0.2 VCC
ADST
0.2 VCC
42
MB89620R Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Resolution
Pin name Condition
Unit Remarks
Min.
—
Typ.
—
Max.
8
—
bit
Total error
—
—
±1.5
±1.0
LSB
LSB
—
Linearity error
—
—
Differential linearity
error
—
—
±0.9
LSB
mV
mV
LSB
µs
Zero transition
voltage
AVR=AVCC
AVSS –1.0LSB AVSS +0.5LSB AVSS +2.0LSB
VOT
—
Full-scale transition
voltage
AVR–3.0LSB AVR–1.5LSB
AVR
0.5
—
VFST
Interchannel
disparity
—
—
—
—
—
A/D mode
conversion time
—
44 tinst*
12 tinst*
—
Sense mode
conversion time
—
µs
—
Analog port input
current
IAIN
10
µA
AN0 to AN7
Analog input voltage
Reference voltage
—
—
0.0
0.0
—
—
AVR
AVCC
V
V
AVR = 5.0 V,
when starting
A/D
IR
—
—
100
—
µA
µA
AVR
conversion
Reference voltage
supply current
AVR = 5.0 V,
when
stopping A/D
conversion
IRH
1
*: For information on tinst, see “(4) Instruction Cycle” in “4 AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
43
MB89620R Series
Digital output
1
Theoretical conversion value
1111 1111
1
11111110
•
Actual conversion value
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1 LSB × N + VOT)
AVR
256
1 LSB =
VNT – (1 LSB × N + VOT)
Linearity error =
1 LSB
V(N+1)T–VNT
Differential linearity error =
– 1
1 LSB
Linearity error
VNT – (1 LSB × N + 1 LSB)
Total error =
1 LSB
0
0000 • 0010
0
0000 0001
0
0000 0000
VOT
VNT V (N + I)T
VFST
Analog input
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the
sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
• Analog Input Equivalent Circiut
Sample hold circuit
.
C = 33 pF
.
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R = 6 kΩ
.
Close for 8 instruction cycles after activating
A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
44
MB89620R Series
■ EXAMPLE CHARACTERISTICS
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
TA = +25°C
VOL (V)
VCC – VOH (V)
1.0
VCC = 3.0 V
VCC = 4.0 V
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
0.5
0.4
0.3
0.2
0.1
VCC = 5.0 V
VCC = 6.0 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
TA = +25°C
4.5
4.5
VIHS
4.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
VCC (V)
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
45
MB89620R Series
(5) Power Supply Current (External Clock)
ICCS vs. VCC
ICC vs. VCC
ICC (mA)
16
ICCS (mA)
5
TA = +25°C
FC = 10 MHz
TA = +25°C
14
4
12
10
FC = 8 MHz
3
2
FC = 10 MHz
8
FC = 8 MHz
6
4
2
FC = 4 MHz
FC = 1 MHz
FC = 4 MHz
FC = 1 MHz
1
0
1
0
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
IA vs. AVCC
IR vs. AVR
IA (mA)
5.0
IR (µA)
200
TA = +25°C
FC = 10 MHz
TA = +25°C
4.5
4.0
180
160
3.5
3.0
140
120
2.5
2.0
100
80
1.5
1.0
60
40
0.5
0
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVCC (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVR (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
100
10
1
2
3
4
5
6
VCC (V)
46
MB89620R Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
#vct
#d8
#d16
dir: b
rel
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
@
A
AH
AL
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
T
TH
TL
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
( × )
(( × ))
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
#:
The number of instructions
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
47
MB89620R Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
AL
AL
–
–
–
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
–
–
F0
Note: During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
48
MB89620R Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
A
←
←
C
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
(A) − (Ri)
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
49
MB89620R Series
(Continued)
Mnemonic
~
#
Operation
(A) ← (AL) ( (EP) )
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
50
MB89620R Series
■ INSTRUCTION MAP
51
MB89620R Series
■ MASK OPTIONS
MB89623R
MB89625R
MB89626R
MB89627R
MB89P625
MB89W625
MB89P627
MB89W627
MB89PV620
MB89T627R
Part number
No.
Specify when
ordering masking
Set with EPROM
programmer
Setting not
possible
Specifying procedure
Selectable per pin.
(P50 to P57 must
be set to without a
pull-up resistor
when an A/D
converter is used.)
Can be set per pin.
(P40 to P47 are
available only for
without a pull-up
resistor.)
Pull-up resistors
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P64
Fixed to without pull-up
resistor
1
Power-on reset selection
Fixed to with power-on
reset
2
3
4
With power-on reset
Without power-on reset
Selectable
Selectable
Selectable
Setting possible
Setting possible
Setting possible
Oscillation stabilization time
selection
Crystal oscillator
(218/FC(s))
Crystal oscillator: 218/FC(s)
Ceramic oscillator: 214/FC(s)
Reset pin output
With reset output
Without reset output
With reset output
52
MB89620R Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89623RP-SH
MB89625RP-SH
MB89626RP-SH
MB89627RP-SH
MB89P625P-SH
MB89P627-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89T627RP-SH
MB89623RPFV
MB89625RPFV
64-pin Plastic LQFP
(FPT-64P-M03)
Lead pitch: 0.5 mm
Lead pitch: 1.0 mm
MB89623RPF
MB89625RPF
MB89626RPF
MB89627RPF
MB89P625PF
MB89P627PF
MB89T623RPF
MB89T625RPF
MB89T627RPF
64-pin Plastic QFP
(FPT-64P-M06)
MB89623RPFM
MB89625RPFM
MB89626RPFM
MB89627RPFM
MB89P625PFM
MB89P627PFM
MB89T627RPFM
64-pin Plastic QFP
(FPT-64P-M09)
Lead pitch: 0.65 mm
MB89W625C-SH
MB89W627C-SH
64-pin Ceramic SH-DIP
(DIP-64C-A06)
64-pin Ceramic MQFP
(MQP-64C-P01)
MB89PV620CF
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV620C-SH
53
MB89620R Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
58.00 +–00..5252
2.283 +–..002028
INDEX-1
INDEX-2
17.00±0.25
(.669±.010)
5.65(.222)MAX
3.00(.118)MIN
0.25±0.05
(.010±.002)
1.00 –+00.50
.039 +–0.020
0.45±0.10
(.018±.004)
0.51(.020)MIN
19.05(.750)
TYP
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
55.118(2.170)REF
Dimensions in mm(inches).
(Continued)
C
1994 FUJITSU LIMITED D64001S-3C-4
54
MB89620R Series
(Continued)
64-pin Plastic LQFP
(FPT-64P-M03)
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
48
33
49
32
0.08(.003)
Details of "A" part
1.50 +–00..1200
INDEX
(Mounting height)
.059 +–..000048
64
17
"A"
0~8°
1
16
LEAD No.
0.50±0.08
(.020±.003)
0.18 –+00..0038
.007 –+..000013
0.145±0.055
(.006±.002)
M
0.08(.003)
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030)
0.25(.010)
Dimensions in mm (inches).
(Continued)
C
1998 FUJITSU LIMITED F64009S-3C-6
55
MB89620R Series
(Continued)
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
51
33
0.05(.002)MIN
(STAND OFF)
52
32
14.00±0.20 18.70±0.40
(.551±.008) (.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
1
19
LEAD No.
0.15±0.05(.006±.002)
Details of "B" part
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
M
0.20(.008)
Details of "A" part
0.25(.010)
"B"
0.30(.012)
0.18(.007)MAX
0.10(.004)
18.00(.709)REF
0
10°
1.20±0.20
0.63(.025)MAX
(.047±.008)
22.30±0.40(.878±.016)
Dimensions in mm (inches).
C
2000 FUJITSU LIMITED F64013S-3C-3
(Continued)
56
MB89620R Series
(Continued)
64-pin Plastic QFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
1.50 –+00..1200
48
49
33
32
(Mounting height)
.059 +–..000048
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
17
M
1
16
Details of "A" part
0.10±0.10
LEAD No.
"A"
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.127 +–00..0025
.005 +–..000012
0.13(.005)
(STAND OFF)
(.004±.004)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
Dimensions in mm (inches).
(Continued)
C
2000 FUJITSU LIMITED F64018S-1C-3
57
MB89620R Series
(Continued)
64-pin Ceramic SH-DIP
(DIP-64C-A06)
56.90±0.56
(2.240±.022)
8.89(.350) DIA
TYP
R1.27(.050)
REF
18.75±0.25
(.738±.010)
INDEX AREA
1.27±0.25
(.050±.010)
5.84(.230)MAX
3.40±0.36
0.25±0.05
(.010±.004)
1.778±0.180
(.070±.007)
0.90±0.10
(.0355±.0040)
0.46 –+00..0183
19.05±0.25
(.750±.010)
(.134±.014)
.018 +–..000035
0°~9°
1.45(.057)
MAX
55.118(2.170)REF
Dimensions in mm (inches).
(Continued)
C
1994 FUJITSU LIMITED D64006SC-1-2
58
MB89620R Series
(Continued)
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
1.00±0.25
INDEX AREA
1.20 –+00..2400
.047 –+..000186
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.00(.709)
TYP
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20 –+00..2400
.047 –+..000186
10.82(.426)
MAX
0.15±0.05
0.50(.020)TYP
(.006±.002)
Dimensions in mm (inches).
(Continued)
C
1994 FUJITSU LIMITED M64004SC-1-3
59
MB89620R Series
(Continued)
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
19.05±0.30
(.750±.012)
INDEX AREA
2.54±0.25
(.100±.010)
0.25±0.05
(.010±.002)
33.02(1.300)REF
1.27±0.25
(.050±.010)
10.16(.400)MAX
0.46–+00..0183
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
1.778±0.25
(.070±.010)
.018+–..000035
55.12(2.170)REF
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED M64002SC-1-4
60
MB89620R Series
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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Tel: +81-3-5322-3347
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The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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are requested to consult with FUJITSU sales representatives before
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equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
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F0012
FUJITSU LIMITED Printed in Japan
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