MB89585BPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12543-2E

8-bit Proprietary Microcontrollers

CMOS

F²MC-8L MB89580B/580BW Series

MB89583B/585B/589B/P585B/P589B/

MB89583BW/585BW/P585BW

■ DESCRIPTION

The MB89580B/BW series is a line of general-purpose, single-chip microcontrollers. In addition to a compact

instruction set, these microcontrollers contain a variety of peripheral functions, such as PLL clock control, timers,

a serial interface, a PWM timer, and the USB function. In particular, these microcontrollers contain one USB

function channel to support both high and low speeds.

■ FEATURES

• Package type

64-pin LQFP package (0.5 mm pitch) and 64-pin QFP package (0.65 mm pitch)

• High-speed operations at low voltage

Minimum execution time : 0.33 µs (Automatically generates a 12 MHz main clock and a 48 MHz USB interface

synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.)

• F²MC-8L CPU core

Instruction set that is optimum to the controllers

-Multiplication and division instructions

-16-bit arithmetic operations

-branch instructions by bit testing

-bit manipulation instructions, etc.

(Continued)

■ PACKAGE

64-pin plastic LQFP

64-pin plastic QFP

(FPT-64P-M03)

(FPT-64P-M09)

MB89580B/580BW series

(Continued)

• PLL clock control

The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise character-

istics.

(6 MHz externally-supplied clock : Internal system clock oscillated at 12 MHz)

• Various timers

8-bit PWM timer (can be used as either 8-bit PWM timer × 2 channels or PPG timer × 1 channel)

Internal 21-bit timebase timer

• Internal USB transceiver circuit (Compatible with high and low speeds)

• USB function

Compliant to USB Protocol Revision 1.0

Support for both low and full speeds (selectable)

Allows four endpoints to be specified at maximum.

Types of transfer supported : control/interrupt/bulk/isochronous

Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for

function’s send and receive data.)

• UART/serial interface

Built-in UART/SIO function (selectable by switching)

• External interrupt

External interrupt (level detection × 8 channels)

Eight inputs are independent of one another and can also be used for resetting from low-power consumption

mode (the L-level detection feature available) .

• Low power consumption (standby mode supported)

Stop mode (There is almost no current consumption since oscillation stops.)

Sleep mode (This mode stops the running CPU.)

• A maximum of 53 general-purpose I/O ports

General-purpose I/O ports (CMOS) : 34

General-purpose output ports (CMOS) : 8

General-purpose I/O ports (Nch open drain) : 3

General-purpose input ports (CMOS 3.3 V input-compatible) : 8

• Parallel ports

Also serve as eight of the general-purpose I/O ports (CMOS)

Interrupt function available

Allows asynchronous read and write by external signals

• Power supply

Supply voltage : 3.0 to 5.5 V

2

MB89580B/580BW series

■ PRODUCT LINEUP

Part number

MB89583BW MB89585BW MB89P585BW

MB89583B MB89585B MB89P585B MB89589B MB89P589B

Parameter

ROM size

RAM size

8 KB

16 KB

8 KB

16 KB

1 KB

512 B

1 KB

18 KB

512 B

QFP-64

(FPT-64P-M09)

Package

LQFP-64 (FPT-64P-M03)

Low-level output

Operation at USB

reset

High impedance state

OTP/EVA MASK OTP/EVA

OTP/EVA

product

Others

MASK product

product

Number of instructions

Instruction bit length

Instruction length

Data bit length

Minimum execution time

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

: 0. 33 µs (6 MHz)

: 3 µs (6 MHz)

CPU functions

Interrupt processing time

General-

purpose

ports

General-purpose I/O ports

General-purpose output ports

General-purpose input ports

(34 : CMOS, 3 : Nch open drain)

(8 : CMOS)

(8 : CMOS 3.3 V input)

Shares eight (P40 through P47) of the above general-purpose I/O ports.

Allows asynchronous read and write by external signals.

An interrupt function is available to set data.

Parallel

ports

Can be set to full/low speed.

Four endpoints at maximum

Power supply mode : Can be set to own power supply/bus power supply mode.

FIFO 8 bits × 8 built in

Periph-

eral

func-

tions

USB

function

Built-in DMAC (Can be set to DMA transfer to the internal RAM or to the external FIFO.)

PWM timer 8-bit PWM timer operation × 2 channels (can also be used as a PPG × 1 channel timer)

Allows switching between UART (clock-synchronous/asynchronous data transfer allowed)

and SIO (simple serial transfer) .

UART SIO

Timebase

21-bit timebase timer

timer

Clock

Allows output of two main clock divisions

output

Standby mode

Sleep mode and Stop mode

■ PACKAGES AND CORRESPONDING PRODUCTS

MB89583B MB89585B MB89P585B MB89589B MB89P589B MB89583BW MB89585BW MB89P585BW

Package

FPT-64P-M03

FPT-64P-M09

×

: Available

: Not available

3

MB89580B/580BW series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTP product, verify its differences from the product that will actually be used.

2. Current Consumption

When operated at low speeds, a product mounted with either one-time PROM or EPROM consumes more

current than a product mounted with a mask ROM. However, in sleep/stop mode the current consumption is the

same.

For detailed information on each package, see “■ PACKAGE DIMENSIONS.”

3. Differences Between the MB89580B series and the MB89580BW Series

MB89580B series : Remains in high impedance state until USB connection takes place. Before the USB con-

nection, use one general-purpose port output to control pullup resistance connection of

this port by software.

MB89580BW :

Outputs at low level until USB connection takes place.

• Example MB89580B product connection

3.3 V

MB89580B series

Host PC

General-purpose

port

1.5 kΩ

RPVP pin

RPVM pin

D+

D−

• Example MB89580BW product connection

3.3 V

Host PC

MB89580BW series

1.5 kΩ

RPVP pin

RPVM pin

D+

D−

Note : Full speed is assumed in the above examples.

4

MB89580B/580BW series

■ PIN ASSIGNMENT

(TOP VIEW)

DO4/P44/UCK/D4

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

DO5/P45/UO/D5

DO6/P46/UI/PWM1/D6

DO7/P47/PWM2/D7

P30/INT0/CLK

P31/INT1

3

4

5

6

P32/INT2

7

P33/INT3

8

P34/INT4

9

P35/INT5

10

11

12

13

14

15

16

P36/INT6/WEX

P37/INT7/RDX

P50/OBF/IBFX/W

VSS

P51/R

P52/EFX

(FPT-64P-M03)

(FPT-64P-M09)

5

MB89580B/580BW series

■ PIN DESCRIPTION

Circuit

type

Pin No.

Pin name

Function

General-purpose CMOS I/O pin

UART/S10 clock I/O

This pin also serves as a parallel interface/external FIFO data output pin.

P44/UCK/D4/

DO4

1

E

General-purpose CMOS I/O pin

UART/S10 serial data output

This pin also serves as a parallel interface/external FIFO data output pin.

P45/UO/D5/

DO5

2

3

4

5

B

E

B

E

General-purpose CMOS I/O pin

UART/S10 serial data input

PWM timer

P46/UI/

PWM1/D6/

DO6

This pin also serves as a parallel interface/external FIFO data output pin.

General-purpose CMOS I/O pin

PWM timer

This pin also serves as a parallel interface/external FIFO data output pin.

P47/PWM2/

D7/DO7

General-purpose CMOS I/O pin

Clock output pin

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

P30/INT0/

CLK

General-purpose CMOS I/O pin

6

7

P31/INT1

P32/INT2

P33/INT3

P34/INT4

P35/INT5

E

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

General-purpose CMOS I/O pin

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

General-purpose CMOS I/O pin

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

8

General-purpose CMOS I/O pin

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

9

General-purpose CMOS I/O pin

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

10

General-purpose CMOS I/O pin

P36/INT6/

WEX

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

This pin also serves as the parallel interface write strobe input pin.

11

E

General-purpose CMOS I/O pin

P37/INT7/

RDX

This pin also serves as an external interrupt input pin.

The external interrupt input is a hysteresis input. (Level detection)

This pin also serves as the parallel interface read strobe input pin.

12

13

E

B

General-purpose CMOS I/O pin

Interrupt output to the parallel interface host.

This pin also serves the OUT FIFO data strobe pin.

P50/OBF/

IBFX/W

(Continued)

6

MB89580B/580BW series

Circuit

type

Pin No.

14

Pin name

V^SS

Function

Power supply pin (GND)

General-purpose CMOS I/O pin.

This pin also serves the IN FIFO data strobe pin.

15

P51/R

B

K

General-purpose Nch open drain I/O pin.

This pin also serves as the IN FIFO data enable input pin.

16

17

18

P52/EFX

P53/A0/FFX

P54/CEX

General-purpose Nch open drain I/O pin.

Parallel interface’s data select input

This pin also serves as the OUT FIFO data enable input pin.

K

General-purpose Nch open drain I/O pin.

This pin also serves as the parallel interface device select input pin.

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

RST

MOD0

MOD1

X0

I

Reset pin. (Reset on the negative logic low level.)

F

An operating mode designation pin. Connect directly to Vss.

A

Pins for the crystal oscillator (6 MHz)

X1

V^SS

Power supply pin (GND)

P27

P26

P25

P24

P23

P22

P21

P20

P17

P16

P15

P14

P13

P12

P11

P10

P07

P06

P05

P04

B

General-purpose CMOS output pin

General-purpose CMOS I/O pin

(Continued)

7

MB89580B/580BW series

(Continued)

Circuit

type

Pin No.

Pin name

Function

General-purpose CMOS I/O pin

45

46

47

48

49

P03

P02

P01

P00

V^CC

B

General-purpose CMOS I/O pin

Power supply pin

B

Connect an external capacitor of 0.1 µF. When using with 3.3 V power

supply, connect this pin with the Vcc pin to set to 3.3 V input.

50

C

51

52

RPVP

RPVM

USBDRV USB route port + pin

USBDRV USB router port − pin

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin. (LSB)

53

54

55

56

57

58

59

60

61

62

63

64

P60/DI0

P61/DI1

F

B

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

P62/DI2

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

P63/DI3

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

P64/DI4

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

P65/DI5

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin.

P66/DI6

General-purpose CMOS input pin (3.3 V input)

This pin also serves as an external FIFO data input pin. (MSB)

P67/DI7

General-purpose CMOS I/O pin

This pin serves as a parallel interface/external FIFO data output pin.

P40/D0/DO0

P41/D1/DO1

P42/D2/DO2

P43/D3/DO3

General-purpose CMOS I/O pin

This pin serves as a parallel interface/external FIFO data output pin.

General-purpose CMOS I/O pin

This pin serves as a parallel interface/external FIFO data output pin.

General-purpose CMOS I/O pin

This pin serves as a parallel interface/external FIFO data output pin.

8

MB89580B/580BW series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Oscillation feedback resistance

Approx. 1 MΩ

X1

A

X0

CMOS I/O

R

Pch

Pullup control register

Pch

Nch

B

Input

CMOS I/O

R

Hysteresis input

Pch

Pullup control register

Pch

Nch

E

Port input

Resource input

CMOS input

Input

F

Hysteresis I/O

R

Pullup resistance

Pch

I

Nch

Input

(Continued)

9

MB89580B/580BW series

(Continued)

Type

Circuit

Remarks

USB I/O

+

–

D

input

D

+

–

D

Operation input

D

+

Full D output

–

Full D output

USBDRV

+

Low D output

–

Low D output

Direction

Speed

Nch open drain I/O

R

Pch

Pullup control register

K

Nch

Input

10

MB89580B/580BW series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins

other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply

to the analog power system is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the

pins. These unused pins should be connected to a pullup or pulldown resistance of at least 2 kΩ between the

pin and the power supply.

Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled

the same as unused input pins.

3. Power Supply Voltage Fluctuations

Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

11

MB89580B/580BW series

■ ONE-TIME PROM AND EPROM MICROCONTROLLER

PROGRAMMING SPECIFICATIONS

PROM mode is available on the MB89P585B/BW microcontrollers. The use of a dedicated adapter allows you

to program the devices with a general-purpose ROM programmer. However, keep in mind that electronic sig-

nature mode is not available.

1. ROM programmer adapter and its compatible programmers

Compatible adapter

Compatible programmers and models

Package

Sun Hayato Co, Ltd.

Ando Denki K. K.

AF9708 (Version 1.40 or higher)

AF9709 (Version 1.40 or higher)

AF9723 (Version 1.50 or higher)

FTP-64P-M03

ROM2-64LQF-32DP-8LA

Inquiry:

Sun Hayato Co., Ltd.

: TEL. 81-3-3986-0403

: TEL. 81-3-3733-1160

Ando Denki K. K.

2. Memory map in PROM mode

(Corresponding addresses

on the ROM programmer)

Normal operating mode

0000H

I/O

0080H

RAM

0480H

C000H

Not available

0000H

Program area

(PROM)

Program area

(PROM)

FFFFH

3FFFH

3. Programming the EPROM (Using the Ando Denki K.K. programmer)

(1) Set the EPROM programmer type code to 17209.

(2) Load program data on to the EPROM programmer at 0000^Hto 3FFFH.

(3) Program C000H to FFFFH with the EPROM programmer.

12

MB89580B/580BW series

■ BLOCK DIAGRAM

X0

X1

Main clock oscillator

Reset output

Power on

Clock control

circuit

RST

reset circuit

(watchdog timer)

PLL circuit

21-bit

timebase timer

8-bit

P46/UI/PWM1/D6/DO6

P47/PWM2/D7/DO7

PWM timer

P44/UCK/D4/DO4

P45/UO/D5/DO5

UART

SIO

RPVP

RPVM

P40/D0/DO0 to P43/D3/DO3

P00 to P07, P10 to P17

USB

Function

circuit

P20 to P27

P51/R

P50/OBF/IBFX/W

P36/INT6/WEX

P37/INT7/RDX

P30/INT0/CLK

DMA

P60/DI0 to P67/DI7

Clock output

P31/INT1 to

P35/INT5

External

interrupt (level)

RAM 18 K / 1 K / 512 Byte

F²MC - 8L CPU

P52/EFX

P53/FFX

ROM 8 K / 16 KByte

P54/CEX

Other pins

VSS

VCC

MOD0 MOD1

C

13

MB89580B/580BW series

■ CPU CORE

1. Memory Space

The MB89580B/BW microcontrollers offer a memory space of 64 Kbytes consisting of the I/O, RAM and ROM

areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register

and a vector table.

• I/O area (addresses : 0000H through 007FH)

This area is assigned with the control and data registers, for example, of peripheral functions to be built in.

The I/O area is as accessible as the memory since the area is assigned to a part of the memory space. Direct

addressing also allows the area to be accessed faster.

• RAM area

As an internal data area, a static RAM is built in.

The internal RAM capacity varies with the product type.

The area 80^Hto FFH can be accessed at high speed with direct addressing.

The area 100^Hto 1FFH can be used a general-purpose register area. (The usable area is limited depending

on the product.)

When reset, RAM data becomes undefined.

• ROM area

As an internal program area, a ROM is built in.

The internal ROM capacity varies with the product type.

The area FFCO^Hto FFFFH should be used for a vector table, for example.

• Memory map

MB89585B

MB89585BW

MB89583B

MB89589B

MB89P585B

MB89583BW

MB89P589B

MB89P585BW

0000

H

0000

H

0000

H

I/O

0080

RAM

512 B

RAM

1 KB

RAM

18 KB

0100

H

0100

0200

0480

H

0100

H

General-

purpose

register

General-

purpose

register

General-

purpose

register

0200

H

0200

0280

4880

H

Not available

E000

H

C000

H

C000

ROM

8 KB

ROM*

16 KB

ROM*

16 KB

FFC0

H

FFC0

H

FFC0

H

FFFF

Vector table

* : The area is EPROM on the MB89P585B,

(reset, interrupt and vector call instructions)

MB89P585BW, and MB89P589B microcontrollers.

14

MB89580B/580BW series

2. Registers

The MB89580B/BW series has two types of registers; the registers dedicated to specific purposes in the CPU

and the general-purpose registers.

The dedicated registers are as follows:

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored.

Accumulator (A)

: A 16-bit register for temporary storage of operations. In the case of an 8-bit data

processing instruction, the lower one byte is used.

Temporary accumulator (T) : A 16-bit register which performs operations with the accumulator. In the case of

an 8-bit data processing instruction, the lower one byte is used.

Index register (IX)

Extra pointer (EP)

Stack pointer (SP)

Program status (PS)

: A 16-bit register for index modification.

: A 16-bit register to point to a memory address.

: A 16-bit register to indicate a stack area.

: A 16-bit register to store a register pointer or a condition code.

16 bits

Initial value

PC

A

: Program counter

: Accumulator

FFFD^H

Indeterminate

T

: Temporary accumulator

: Index register

Indeterminate

IX

: Extra pointer

EP

SP

: Stack pointer

RP

CCR

: Program status

I-flag = 0, IL1, 0 = 11

Initial values for other

bits are indeterminate.

PS

15

MB89580B/580BW series

The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code

register in the lower 8 bits (CCR) . (See the diagram below.)

RP

CCR

CCR initial value

X011XXXXB

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

R4

R3 R2 R1 R0

−

H

I

IL1 IL0

N

Z

PS

C

V

H-Flag

I-Flag

IL 1,0

N-Flag

Z-Flag

V-Flag

C-Flag

X : Undefined

The RP points to the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule shown next.

Rule for Conversion of Actual Addresses in the General-purpose Register Area

RP higher bits

OP code in lower bits

b1 b0

"0" "0" "0" "0" "0" "0" "0" "1"

A15 A14 A13 A12 A11 A10 A9 A8

R4 R3 R2 R1 R0 b2

A7 A6 A5 A4 A3 A2 A1 A0

Generated addresses

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at the time of an interrupt.

H flag

: The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow

from bit 4 to bit 3. The bit is cleared to “0” in other instances. The flag is for decimal adjustment

instructions; do not use for other than additions and subtractions.

I flag

: Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The

flag is set to “0” when reset.

IL1, 0

: Indicates the level of the interrupt currently enabled. An interrupt is processed only if its level is

higher than the value this bit indicates.

IL1 IL0

Interrupt level

1

High-low

Higher

0

1

0

1

0

1

2

3

Lower = no interruption

16

MB89580B/580BW series

N flag

: The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared

to “0” when the MSB is set to “1.”

Z flag

V flag

: The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances.

: The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is

cleared to “0” if no overflow occurs.

C flag

: The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit

7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is

set to the shift-out value.

The following general-purpose registers are provided:

General-purpose registers : 8-bit data storage registers

The general-purpose registers are 8 bits in length and located in the register banks in the memory. One bank

contains eight registers and the MB89580B/BW microcontrollers allow a total of 16 banks to be used at maximum.

The bank currently in use is indicated by the register bank pointer (RP) .

Register Bank Configuration

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

16 banks

Memory area

17

MB89580B/580BW series

■ I/O MAP

Address Register name

Register description

Read/write

Initial value

XXXXXXXX

0 0 0 00 0 0 0

XXXXXXXX

0 0 0 00 0 0 0

00^H

01^H

02H

03^H

04^H

05H

06^H

07^H

08H

09^H

0AH

0B^H

0CH

0DH

0E^H

0FH

10^H

11H

12H

13^H

14H

15H

PDR0

DDR0

PDR1

DDR1

PDR2

Port 0 data register

Port 0 direction register

Port 1 data register

Port 1 direction register

Port 2 data register

R/W

W

R/W

W

R/W

Vacancy

SYCC

STBC

WDTC

TBTC

System clock control register

Standby control register

R/W

XXX1 1X 0 0

0 0 0 1XXXX

0 XXXXXXX

0 0 XXX 0 0 0

Watchdog timer control register

Timebase timer control register

Vacancy

PDR3

DDR3

Port 3 data register

R/W

XXXXXXXX

0 0 0 00 0 0 0

Port 3 direction register

Vacancy

PDR4

DDR4

PDR5

DDR5

PDR6

PDCR

Port 4 data register

Port 4 direction register

Port 5 data register

Port 5 direction register

Port 6 data register

R/W

XXXXXXXX

0 0 0 00 0 0 0

XXX1 1 1XX

XXXXXX 00

XXXXXXXX

XXX0 00 0 0

Parallel port data control register

16^Hto

20H

Vacancy

21H

22H

23H

24^H

25H

26H

27^H

28H

29H

2A^H

2BH

PURR0

PURR1

PURR2

PURR3

PURR4

PURR5

CTR1

Port 0 pullup option setting register

Port 1 pullup option setting register

Port 2 pullup option setting register

Port 3 pullup option setting register

Port 4 pullup option setting register

Port 5 pullup option setting register

PWM control register 1

R/W

W

1 1 1 11 1 1 1

XXX 1 1 11 1

0 0 0 00 0 0 0

00 0 X 0 0 00

X 0 00 XXXX

XXXXXXXX

CTR2

PWM control register 2

CTR3

PWM control register 3

CMR1

CMR2

PWM compare register 1

PWM compare register 2

W

(Continued)

18

MB89580B/580BW series

Address Register name

Register description

Clock output control register

Serial clock switching register

Vacancy

Read/write

R/W

Initial value

XXXXXXX 0

2C^H

2D^H

2EH

2F^H

30^H

31H

32^H

33^H

CKR

SCS

R/W

SMC1

SMC2

SSD

Serial mode control register 1

Serial mode control register 2

Serial status and control register

R/W

R

0 0 0 0 00 0 0

00 0 0 1XXX

XXXXXXXX

SIDR/SODR Serial input/serial output data register

R/W

SRC

Serial rate control register

34H to

3B^H

Vacancy

3C^H

3DH

EIE

EIF

External interrupt control register

External interrupt flag register

R/W

0 0 0 0 00 0 0

XXXXXXX 0

3E^Hto

3FH

Vacancy

USB power supply mode register

Vacancy

40H

DMDR

R/W

XXXXXXX 0

41H to

4EH

4F^H

50H

51^H

52H

53H

54^H

55H

56H

57^H

58^H

59H

5AH

5B^H

5CH

5DH

5E^H

5FH

60H

61^H

DBARH

UMDR

DMA base address register H

USB reset mode register

R/W

R

0 0 0 00 0 XX

1 0 0 0XX0 0

XXXXXXXX

X 00 0 0 0 00

0 0 0 0 00 0 0

XXXXXX 0 0

0 0 0 0 00 0 0

XXXXXX 0 0

X 00 0 0 0 00

0 0 0 0 00 0 0

XXXXXX 0 0

0 0 0 0 00 0 0

XXXXXXXX

XXXX0 0 0 1

X 00 0 0 0 00

0 X0 0 0 0 00

0 0 0 0 00 0 0

DBAR

DMA base address register

Transfer data count register 0

Transfer data count register 11

Transfer data count register 12

Transfer data count register 21

Transfer data count register 22

Transfer data count register 3

USB control register

TDCR0

TDCR11

TDCR12

TDCR21

TDCR22

TDCR3

UCTR

USTR1

USTR2

UMSKR

UFRMR1

UFRMR2

EPER

USB status register 1

USB status register 2

USB interrupt mask register

USB frame status register 1

USB frame status register 2

USB endpoint enable register

Endpoint 0 setup register

Endpoint setup register 11

Endpoint setup register 12

R/W

R

R/W

EPBR0

EPBR11

EPBR12

(Continued)

19

MB89580B/580BW series

(Continued)

Address Register name

Register description

Read/write

R/W

Initial value

0X 00 0 0 0 0

00 0 0 00 0 0

XX00 0 0 XX

X0 00 0 0 0 0

62^H

63^H

64H

65^H

EPBR21

EPBR22

EPBR31

EPBR32

Endpoint setup register 21

Endpoint setup register 22

Endpoint setup register 31

Endpoint setup register 32

R/W

66^Hto

7BH

Vacancy

7CH

7D^H

7E^H

7FH

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

level setting register 3

W

1 1 1 1 11 1 1

Vacancy

• Information about read/write

R/W : Read/write enabled, R : Read only, W : Write only

• Information about initial values

0 : The initial value of this bit is “0.” 1 : The initial bit of this bit is “1.” X : The initial value of this bit is undefined.

Note : Vacancies are not for use.

20

MB89580B/580BW series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0 V)

Value

Parameter

Power supply voltage

Input voltage

Symbol

V^CC

Unit

Remarks

Min.

Max.

VSS − 0.3

VSS − 0.5

VSS − 0.3

VSS + 6.0

VCC + 0.3

VSS + 4.0

VCC + 0.3

V

Other than P60 to P67

P60 to P67

V^I

Output voltage

V^O

“L” level average output cur-

rent

Average value (operating current

× operating rate)

I^OLAV

4

mA

“L” level total maximum output

current

ΣIOL

ΣIOLAV

IOH

100

40

“L” level total average output

current

Average value (operating current

× operating rate)

“H” level maximum output

current

−15

−4

“H” level average output

current

Average value (operating current

× operating rate)

I^OHAV

ΣIOH

“H” level total maximum output

current

−50

−20

“H” level total average output

current

Average value (operating current

× operating rate)

ΣI^OHAV

Power consumption

Operating temperature

Storage temperature

PD

TA

300

+85

mW

°C

−40

−55

Tstg

+150

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

21

MB89580B/580BW series

2. Recommended Operating Conditions

(VSS = 0 V)

Remarks

Value

Typ.

Parameter

Symbol

Unit

Min.

3.0

Max.

5.5

Power supply voltage

Operating temperature

Smoothing capacitor

V^CC

TA

V

−40

0.1

+85

1.0

°C

µF

C^S

At Vcc = 5.0 V*

When the USB function is in

use

Series resistance

R^S

16

Ω

* : Useeitheraceramiccapacitororacapacitorwithsimilarfrequencycharacteristics. Thecapacityofthesmoothing

capacitor for the Vcc pin should be greater than that of the Cs. When using with a supply voltage of 3.3 V,

connect pin C with Vcc to input 3.3 V.

• C, RPVP and RPVM Pin Connection Diagram

RS

RPVP

RS

RPVM

C

CS

22

MB89580B/580BW series

5.5

5.0

4.0

3.0

2.0

1.0

0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0

CPU operating frequency (FCH MHz)

(At instruction cycle 4/ FCH)

4.0 2.0

0.8

0.4

0.33

Minimum execution time (instruction cycle) (µs)

However, FCH = clock frequency (Fc) × 2

Figure 1 Operating voltage - operating frequency

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

23

MB89580B/580BW series

3. DC Characteristics

(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter Symbol

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P50 to P54,

MOD0, MOD1

V^IH

0.7 V^CC

VCC + 0.3

V

“H” level input

voltage

RST,

VIHS

INT0 to INT7,

UCK, UI

0.8 VCC

VCC + 0.3

VSS + 3.8

V

V^IH1

P60 to P67

VSS + 2.0

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P50 to P54,

MOD0, MOD1

V^IL

V^SS− 0.3

0.3 VCC

V

“L” level input

voltage

RST,

V^ILS

INT0 to INT7,

UCK, UI

VSS − 0.3

VSS − 0.5

VSS − 0.3

0.2 VCC

VSS + 0.8

VCC + 0.3

V

V^IL1

P60 to P67

Open-drain

output applica-

tion voltage

V^D1

P52 to P54

P00 to P07,

P10 to P17,

P20 to P24,

P30 to P37,

P40 to P47,

P50, P51

“H” level out-

put voltage

VOH

IOH = −2.0 mA

4.0

V

P00 to P07,

P10 to P17,

P20 to P24,

P30 to P37,

P40 to P47,

P50 to P54,

RST

“L”leveloutput

voltage

V^OL

IOL = 4.0 mA

0.4

(Continued)

24

MB89580B/580BW series

(Continued)

(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter Symbol

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P50, P51,

Input leakage

current

(Hi-Z output

leakage cur-

rent)

When no pullup re-

µA sistance is speci-

I^LI

0.0 < V^I< VCC

−5

+5

fied

P60 to P67

Open-drain

output leak-

age current

I^LIOD

P52 to P54

0.0 < VI < VSS + 5.5

+5

µA

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P50 to P54,

RST

RST is excluded

when pullup resis-

tance available is

specified.

Pullup

resistance

R^PULL

VI = 0.0 V

25

50

100

kΩ

MB89P585B/BW,

MB89585B/BW,

mA MB89583B/BW

MB89P589B,

FCH = 12.0 MHz

VCC = 5.0 V

tinst = 0.333 µs

I^CC

25

20

38

Power supply

current

MB89589B

VCC

FCH = 12.0 MHz

VCC = 5.0 V

tinst = 0.333 µs

ICCS1

30

20

mA Sleep mode

I^CCH

TA = 25 °C

f = 1 MHz

5

µA Stop

Input capaci-

tance

Other than

Vcc and Vss

CIN

10

pF

25

MB89580B/580BW series

4. AC Characteristics

(1) Reset Timing

(V^CC= 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

RST “L” pulse width

tZLZH

16 tHCLY

ns

Note : t^HCYLis the internal main clock oscillating cycle (1/2 Fc) .

tZLZH

RST

0.2 VCC

(2) Power-on Reset and Power On Time

(V^SS= 0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

Power supply rising time

Power supply cutoff time

t^R

0.066

50

ms

ns

Due to repeated

operations

t^OFF

4

Note : The power supply must be up within the selected oscillation stabilization time.

When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the

voltage.

tR

tOFF

3.5 V

VCC

0.2 V

26

MB89580B/580BW series

(3) Clock Timing

Parameter

(V^SS= 0 V, TA = −40 °C to +85 °C)

Value

Symbol Pin name Condition

Unit

Remarks

Min.

Typ.

6

Max.

Clock frequency

Clock cycle time

F^C

X0, X1

MHz

ns

t^XCYL

166.6

Internal main clock

frequency

Twice the

Fc

F^CH

12

MHz

ns

Internal clock cycle

tHCYL

83.3

tXCYL/2

• X0 and X1 Timing and Conditions

tXCYL

X0

0.2 VCC

• Clock Conditions

When a crystal resonator is used

X0

X1

C1

C2

(4) Instruction Cycle

Parameter

(V^SS= 0 V, TA = −40 °C to +85 °C)

Symbol

Value

Unit

Remarks

Instruction cycle

(Min. execution time)

4 / FCH, 8 / FCH,

16 / FCH, 64 / FCH

When operating at FCH = 12 MHz

tinst = 0.33 µs (4 / FCH)

t^inst

µs

27

MB89580B/580BW series

(5) UART Serial I/O Timing

(V^CC= 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

2 tinst

−200

200

1 t^inst

1 tinst

0

Max.

Serial clock cycle time

UCK ↓ → UO

t^SCYC

t^SLOV

t^IVSH

tSHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

UCK

µs

ns

µs

ns

UCK, UO

UI, UCK

UCK, UI

200

Internal shift

clock mode

Valid UI → UCK↑

UCK ↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

UCK

External

shift clock

mode

UCK, UO

UI, UCK

UCK, UI

200

Valid UI → UCK↑

200

UCK ↑ → valid UI hold time

* : For information about t^inst, see “Instruction Cycle.”

• Internal shift clock mode

tSCYC

UCK

2.4 V

0.8 V

tSLOV

2.4 V

UO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

• External shift clock mode

tSLSH

tSHSL

UCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

UO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

28

MB89580B/580BW series

(6) Peripheral Input Timing

(V^CC= 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

Max.

Peripheral input “H”

pulse width 1

t^ILIH1

t^IHIL1

2 tinst

µs

INT0 to INT7

Peripheral input “L”

pulse width 1

2 tinst

* : For information about t^inst, see “Instruction Cycle.”

tIHIL1

tILIH1

INT0 to INT7

0.8 VCC

0.2 VCC

29

MB89580B/580BW series

(7) Parallel Port Timing

(V^CC= 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name Condition

Unit Remarks

Min.

Max.

IBFX

WEX

IBFX ↑ → WEX ↓ timing

CEX ↓ → WEX ↓ delay

t^IHWL

t^CLWL

1 / 2•tinst

µs

CEX

WEX

0

ns

CEX

WEX

WEX ↑ → CEX ↑ delay

WEX pulse width

t^WHCH

tWLWH

t^DVWH

0

ns

WEX

40

10

D0 to D7

WEX

Write data setup

D0 to D7

WEX

Write data hold

t^WHDX

t^AVWH

t^WHAX

t^OHRL

t^CLRL

10

ns

µs

ns

A0

WEX

Write address setup

Write address hold

OBF ↑ → RDX ↓ timing

CEX ↓ → RDX ↓ delay

A0

WEX

10

OBF

RDX

1 / 2•tinst

0

CEX

RDX

CEX

RDX

RDX ↑ → CEX ↑ delay

RDX pulse width

t^RHCH

t^RLRH

t^RLDV

0

ns

RDX

40

D0 to D7

RDX

Read data delay

15

D0 to D7

RDX

Read data hold

t^RHDX

t^AVRL

tRHAX

0

ns

A0

RDX

Read address setup

Read address hold

10

A0

RDX

30

MB89580B/580BW series

• Write Timing

IBFX

tIHWL

tCLWL

CEX

tWHCH

WEX

tWLWH

D0 to D7

tDVWH

tAVWH

tWHDX

tWHAX

A0

• Read Timing

OBF

tOHRL

CEX

RDX

tCLRL

tRHCH

tRLRH

D0 to D7

tRLDV

tAVRL

tRHDX

A0

tRHAX

31

MB89580B/580BW series

(8) External FIFO Connection Timing

(V^CC= 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C, FC = 6 MHz)

Value

Parameter

Symbol Pin name Condition

Unit

Remarks

Min.

Max.

Not includ-

ing the initial

resetting af-

ter reset

Resetting be-

ns fore PKEND is

not allowed.

FIFO empty resetting timing

t^EFXH

EFX

0

FIFO empty timing

t^EFXL

t^RSCY

t^RHWD

t^DISP

EFX, R

R

0

360

ns

Read cycle time

645

145

50

Read clock “H” pulse width

Valid DI → R ↓ setup time

R ↓ → valid DI hold time

DI7 to DI0,

R

t^DIHD

0

Resetting be-

ns fore PKEND is

not allowed.

FIFO full reset timing

t^FFXH

FFX

0

FIFO full timing

tFFXL

tWSCY

t^WHWD

tDOSP

t^DOHD

FFX, W

W

0

360

ns

Write recycle time

645

145

200

40

Write clock “H” pulse width

Valid DO → W ↑ setup time

W ↓ → valid DO hold time

DO7 to

DO0, W

32

MB89580B/580BW series

• Read Data from External FIFO

tEFXH

PKEND

0.7 VCC

EFX (P52)

0.3 VCC

tRSYC

tEFXL

2.4 V

R (P51)

0.8 V

tRHWD

tDISP tDIHD

2.0 V

Valid

0.8 V

DI7 to DI0

Invalid

Valid

Invalid

• Write Data to External FIFO

PKEND

tFFXH

0.7 VCC

FFX (P53)

W (P50)

0.3 VCC

tWSCY

tFFXL

2.4 V

0.8 V

tWHWD

tDOSP

tDOHD

2.4 V

0.8 V

2.4 V

0.8 V

DO7 to DO0

33

MB89580B/580BW series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

34

MB89580B/580BW series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

35

MB89580B/580BW series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

36

MB89580B/580BW series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

37

MB89580B/580BW series

■ INSTRUCTION MAP

38

MB89580B/580BW series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89589BPFM

MB89P589BPFM

64-pin plastic QFP

(FPT-64P-M09)

MB89583BPFV

MB89585BPFV

MB89P585BPFV

MB89583BWPFV

MB89585BWPFV

MB89P585BWPFV

64-pin plastic LQFP

(FPT-64P-M03)

39

MB89580B/580BW series

■ PACKAGE DIMENSION

64-pin plastic LQFP

Note: Pins width and pins thickness include plating thickness.

(FPT-64P-M03)

12.00±0.20(.472±.008)SQ

10.00±0.10(.394±.004)SQ

48

33

49

32

0.08(.003)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

INDEX

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

64

17

"A"

0~8°

1

16

LEAD No.

0.50±0.08

(.020±.003)

0.18 –⁺0⁰.^.0⁰3⁸

.007 –⁺.^.0⁰0⁰1³

0.145±0.055

(.006±.002)

M

0.08(.003)

0.10±0.10

(.004±.004)

(Stand off)

0.50±0.20

(.020±.008)

0.45/0.75

(.018/.030)

0.25(.010)

C

1998 FUJITSU LIMITED F64009S-3C-6

Dimensions in mm (inches)

(Continued)

40

MB89580B/580BW series

(Continued)

64-pin plastic QFP

Note: Pins width and pins thickness include plating thickness.

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

1.50 –⁺0⁰.^.1²0⁰

48

33

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

49

32

9.75

(.384)

REF

13.00

(.512)

NOM

1 PIN INDEX

64

17

M

1

16

Details of "A" part

0.10±0.10

LEAD No.

"A"

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.127 ⁺–0⁰.^.0⁰2⁵

.005 ⁺^–.^.⁰⁰⁰⁰¹²

0.13(.005)

(STAND OFF)

(.004±.004)

0.50±0.20

(.020±.008)

0.10(.004)

0

10°

C

2000 FUJITSU LIMITED F64018S-1C-3

Dimensions in mm (inches)

41

MB89580B/580BW series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0012

FUJITSU LIMITED Printed in Japan


型号：	MB89585BPFV
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontrollers 8位微控制器专用微控制器
文件：	总42页 (文件大小：558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89585BPFV [FUJITSU]

相关型号：

MB89585BPMC1

MB89585BW

MB89585BWPFV

MB89585BWPMC1

MB89589B

MB89589BPFM

MB89589BPMC

MB89589BPMC

MB89593B

MB89593BPFV

MB89593BW

MB89593BWPFV