MB881822APVA1-GE1 [FUJITSU]
Clock Generator, 100MHz, CMOS, PBCC20, 3.50 X 3.50 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, PLASTIC, BCC-20;
| 型号： | MB881822APVA1-GE1 |
| 厂家： | 
FUJITSU |
| 描述： | Clock Generator, 100MHz, CMOS, PBCC20, 3.50 X 3.50 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, PLASTIC, BCC-20 时钟 外围集成电路 晶体 |
| 文件： | 总36页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS04-29138-3E
ASSP
Spread Spectrum Clock Generator
MB88182
■ DESCRIPTION
MB88182 is the multi-output clock generator for EMI (Electro Magnetic Interference) reduction. The peak of
unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate
periodically with the internal modulator.
It ispossibleto setthefrequencyinthebuilt-in register usingtheI2C busthatcanvarydependingontheapplication.
■ FEATURES
• Built-in PLL : 3
Without spread-spectrum function : 1 (PLL)
With spread-spectrum function : 2 (SSCG1, SSCG2)
• Clock output pins : 5 pins
CLK1 : Clock output when setting to CLK1 (PLL).
CLK2 : Clock output when setting to CLK2 (SSCG1) .
CLK3 : Clock output when setting to CLK3 (SSCG2) .
CLK4 : Clock output when setting to CLK4 (SSCG2) .
Note: It is not possible to output CLK3 and CLK4 at the same time.
CKREF : Buffered output for CKIN clock.
• Power down pins : 5 pins
XPD1 : Control the stop state of PLL and the CLK1 output.
XPD2 : Control the stop state of SSCG1 and the CLK2 output.
XPD3 : Control the stop state of the CLK3 output.
XPD4 : Control the stop state of the CLK4 output.
Note: Halting both CLK3 and CLK4 stops operating the SSCG2.
XPDREF: Control the stop state of the CKREF output.
(Continued)
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.12
MB88182
(Continued)
• Modulation enable pins : ENS
Switch on and off for the modulation (For SSCG1, SSCG2)
• Function to set the output clock frequency
This has the slave transfer function for the I2C bus, and can set the output frequency of CLK1 (when setting
to CLK1), CLK2 (when setting to CLK2), CLK3 (when setting to CLK3) and CLK4 (when setting to CLK4) from
the outside.
Also, it is possible to set the output drive ability of CLK1, CLK2, CLK3 and CLK4.
Output frequency* : 8 MHz to 100 MHz, internal oscillation frequency : 16 MHz to 168 MHz
*: When VDP is 1.8 V 0.15 V, the frequency range to output is 8 MHz to 50 MHz.
Programmable of the parameter of N divider, M divider, K divider
Setting to CLK1 : N divider : 5-bit, M divider : 6-bit, K divider : 5-bit
Setting to CLK2, 3, 4 : N divider : 11-bit, M divider : 12-bit, K divider : 5-bit
Modulationrate:Selectablefromnomodulation, 0.25%, 0.5%, 0.75%, 1.0%, 1.25%, 1.5%and 1.75%.
• Input clock 10 MHz to 30 MHz
• Power supply voltage: 1.8 V 0.15 V (VDD), 2.6 V 0.1 V (VDDE), 1.65 V to 2.7 V (VDP)
• Operating temperature: − 40 °C to + 85 °C
• Power consumption:
At operation
18 mW (Power supply voltage:1.8 V (VDD),
2.6 V (VDDE, VDP) normal temperature, no load,
CKREF(19.2 MHz), CLK1 (48 MHz, 1.8 V), CLK2 (27 MHz),
CLK3 (37 MHz) during the clock output)
During the power down state for all outputs
0.01 mW (Power supply voltage: 1.8 V (VDD) ,
2.6 V (VDDE, VDP), normal temperature)
• Cycle-Cycle Jitter : Less than 100 ps-rms
• Package : BCC20 (3.50 mm × 3.50 mm, Lead pitch 0.50 mm, Mounting height 0.60 mm)
QFN24 (2.50 mm × 3.50 mm, Lead pitch 0.40 mm, Mounting height 0.80 mm)
■ PRODUCT LINEUP
MB88182 has the following lineups corresponding to the different voltages of CLK1 pin and I2C addresses.
Part number
CLK1
CLK2
CLK3/CLK4/CKREF
I2C address
1001111B
1011111B
BCC20 package
MB881821APVA1
MB881822APVA1
MB881821BPVA1
MB881822BPVA1
QFN24 package
MB881821AWQN
MB881822AWQN
MB881821BWQN
MB881822BWQN
1.8 V
2.6 V
1.8 V
2.6 V
VDP level
(1.8 V / 2.6 V)
2.6 V
2
DS04-29138-3E
MB88182
■ PIN ASSIGNMENT
• BCC20
(TOP VIEW)
1
2
3
17
16
15
14
VDP
CKREF
CKIN
ENS
18
20
19
VDDE
VSS
4
5
6
7
VSS
CLK2
XPD4
XPD3
XPD2
13
12
11
VDD
CLK1
10
8
9
XPDREF
(LCC-20P-M06)
DS04-29138-3E
3
MB88182
• QFN24
(TOP VIEW)
24 23 22 21 20
1
19
18
17
16
15
14
VSS
XPD3
XPD4
CLK2
VSS
VSS
2
3
4
5
6
7
CLK1
VDD
VSS
CKIN
CKREF
NC
VDDE
ENS
13
8
9
10 11 12
(LCC-24P-M61)
4
DS04-29138-3E
MB88182
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
Description
BCC20
1
QFN24
12
13
14
15
16
17
18
19
20
21
22
23
24
1
VDP
NC
⎯
⎯
O
I
Power supply pin (2.6 V / 1.8 V)
NC pin
⎯
2
CKREF
CKIN
VSS
Reference clock output pin
Clock input pin (19.2 MHz)
GND pin
3
⎯
⎯
O
⎯
I
4
VDD
5
Power supply pin (1.8 V)
Clock output pin 1
GND pin
CLK1
VSS
6
⎯
7
XPDREF
SCL
CKREF Power down pin
I2C bus clock input pin
I2C bus data I/O pin
CLK1 Power down pin
CLK2 Power down pin
GND pin
I
8
SDA
I/O
I
9
XPD1
XPD2
VSS
10
11
⎯
12
13
14
15
16
17
18
⎯
19
20
I
⎯
I
XPD3
XPD4
CLK2
VSS
2
CLK3 Power down pin
CLK4 Power down pin
Clock output pin 2
GND pin
I
3
O
⎯
⎯
I
4
5
VDDE
ENS
6
Power supply pin (2.6 V)
Modulation enable pin
Clock output pin 3
GND pin
7
CLK3
VSS
O
⎯
O
⎯
8
9
CLK4
VSS
10
11
Clock output pin 4
GND pin
DS04-29138-3E
5
MB88182
■ I/O CIRCUIT TYPE
Pin
Circuit type
Remarks
XPDREF
XPD1
XPD2
XPD3
XPD4
• CMOS hysteresis input
• With pull-up resistor (20 kΩ)
The pull-up resistor is cut off during
the “L” input.
2.6 V
ENS
CMOS hysteresis input
2.6 V
SCL
SDA
CMOS hysteresis input
• CMOS hysteresis input
• N-ch open drain output
• IOL = 4 mA
(Continued)
6
DS04-29138-3E
MB88182
Pin
Circuit type
Remarks
CKIN
• Feedback resistors 1 MΩ
• Possible to input clock via the cou-
pling capacity
1.8 V
1 MΩ
CLK1
• CMOS output
1.8 V
or
2.6 V
• IOH = − 2 mA or − 4 mA
• IOL = 2 mA or 4 mA
(Switchable by the output drive
ability setting bit)
• Operates at 1.8 v or 2.6 v depending
on the part number.
CLK2
• CMOS output
2.6 V
• IOH = − 2 mA or − 4 mA
• IOL = 2 mA or 4 mA
(Switchable by the output drive
ability setting bit)
CLK3
CLK4
• CMOS output
VDP
• At VDP = 2.6 V 0.1 V
IOH = − 2 mA or − 4 mA
IOL = 2 mA or 4 mA
(Switchable by the output drive
ability setting bit)
• At VDP = 1.8 V 0.15 V
IOH = − 1 mA or − 2 mA
IOL = 1 mA or 2 mA
(Continued)
DS04-29138-3E
7
MB88182
(Continued)
Pin
Circuit type
Remarks
• CMOS output
• At VDP = 2.6 V 0.1 V
IOH = − 2 mA
CKREF
VDP
IOL = 2 mA
• At VDP = 1.8 V 0.15 V
IOH = − 1 mA
IOL = 1 mA
8
DS04-29138-3E
MB88182
■ HANDLING DEVICES
(1) Preventing latch-up
A latch-up may occur in a CMOS IC if a voltage greater than power supply voltage or a voltage less than GND
is applied to an input or output pin, or if an above-rating voltage is applied between power supply and GND.
A latch-up, if it occurs, significantly increases the power-supply current and may cause thermal destruction of
an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.
(2) Handling control input pins
The input pins (ENS, XPD1, XPD2, XPD3, XPD4, and XPDREF) of this device should be high or low level
preventing the pins from being undefined by connecting a pull-down or pull-up resistor, or performing level input
by control signals.
The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS
pin or power down control pins (XPD1, XPD2, XPD3, XPD4, and XPDREF). Please use the clock after the lock-
up time has passed. (The lock-up time varies depending on the setting value to the respective register. Please
confirm the recommended value with the Fujitsu Microelectronics support tool.)
(3) Power supply pins
Ensure that the impedance of the connection from the power supply source to the power supply pins on the
device is as low as possible.
We recommend connecting the electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF)
in parallel between power supply and GND near the device, as a bypass capacitor.
We also recommend inserting a low pass filter less than 3.4 kHz of a cutoff frequency to the power-supply line
of MB88182 for not being affected by the power-supply noise on the customer's system.
The supply voltage to MB88182 is decreased when a resistor is inserted; therefore, please use the resistor less
than 10 Ω in case of inserting a resistor. (An example of recommended combination is 4.7 μF for a capacitance
and 10 Ω for a resistor.)
• Example of recommended circuit of low pass filter to remove power-supply noise
VCC
(Power supply line)
10 Ω
MB88182
4.7 μF
0.1 μF
(Bypass capacitor)
DS04-29138-3E
9
MB88182
■ BLOCK DIAGRAM
Power down control
CLK4
XPD4
SSCG2
XPD3
CLK3
Oscillates when setting to the
enable side
Setting to CLK4
Setting to CLK3
Setting to CLK2
Setting to CLK1
SCL
SDA
I2C circuit
XPD2
SSCG1
CLK2
XPD1
CKIN
PLL
CLK1
CKREF
XPDREF
ENS
10
DS04-29138-3E
MB88182
■ PIN SETTING
ENS Modulation enable setting
ENS
Modulation
No modulation
Modulation
0
1 (2.6 V)
When setting “0” to the ENS pin, the spectrum will not spread.
The setting is for CLK2 (SSCG1) and CLK3, and CLK4 (SSCG2).
XPD Power down setting
0
CKREF is fixed to the output “L”.
CKREF is the clock output.
XPDREF
1 (2.6 V)
PLL1 is in the power down state.
CLK1 is fixed to the output “L”.
0
1 (2.6 V)
0
XPD1
PLL1 and CLK1 are in operation.
SSCG1 is in the power down state.
CLK2 is fixed to the output “L”.
XPD2
1 (2.6 V)
0
SSCG1 and CLK2 are in operation.
CLK3 is fixed to the output “L”.
SSCG2 and CLK3 are in operation.
CLK4 is fixed to the output “L”.
SSCG2 and CLK4 are in operation.
XPD3
XPD4
1 (2.6 V)
0
1 (2.6 V)
The pin in XPDREF, XPD1, XPD2, XPD3 and XPD4 is connected to the pull-up resistor.
However, the pull-up resistor is cut off during “0” input.
When both XPD3 and XPD4 are “0”, SSCG2 is in the power down state.
DS04-29138-3E
11
MB88182
■ SETTING REGISTER
<Memory map>
Setting register for CLK2, CLK3, CLK4 (All registers have the same configurations.)
Address
bit0 to 11
bit12 to 22
bit23 to 27
bit28 to 30
Function
Remarks
M divider setting (12-bit)
N divider setting (11-bit)
K divider setting (5-bit)
L divider setting (3-bit)
Selectable in the range of 100 to 3600
Selectable in the range of 3 to 2047
Selectable in the range of 1 to 32
Modulation frequency setting (selectable in the range of 1 to 8)
Charge pump current setting due to internal oscillation frequency
and M divider setting
bit31 to 34
bit35 to 40
bit41 to 43
Charge Pump setting (4-bit)
VCO Gain setting (6-bit)
Gain setting due to internal oscillation frequency
Modulation rate setting
(3-bit)
modulation off, 0.25%, 0.50%, 0.75%, 1.00%,
1.25%, 1.50%, 1.75% are selectable
bit44
bit45
Output drive setting
Slewing rate setting
0 : Ability small, 1 : Ability large
0 : Slewing rate low, 1 : Slewing rate high
When in writing : The written data is ignored.
When in reading : Undefined
bit46, 47
Invalid bit
CLK1 setting register
Address
Function
Remarks
Selectable in the range of 3 to 52
Selectable in the range of 3 to 31
Selectable in the range of 1 to 32
bit0 to 5
bit6 to 10
bit11 to 15
M divider setting (6-bit)
N divider setting (5-bit)
K divider setting (5-bit)
Charge pump current setting due to internal oscillation frequency
and M divider setting
bit16 to 19
Charge Pump setting (4-bit)
bit20 to 25
bit26
VCO Gain setting (6-bit) Gain setting due to internal oscillation frequency
Output drive setting
Slewing rate setting
0 : Ability small, 1 : Ability large
bit27
0 : Slewing rate low, 1 : Slewing rate high
When in writing : The written data is ignored.
When in reading : Undefined
bit28 to 31
Invalid bit
Note: The bit's initial value in a register is undefined. Therefore, if the power down of clock output is released before
the register setting, the clock is output with settings unintended. The power down of the clock output for
CLK1, CLK2, CLK3 and CLK4 should be released after setting to registers.
12
DS04-29138-3E
MB88182
<Frequency setting>
When setting each divider parameter of the oscillator to a register, the output frequency can be set.
Internal oscillation frequency and output frequency can be calculated with following formula:
Internal oscillation frequency (fvco*) = Input frequency (fin) × M/N
* : Please set the fvco range from 16 MHz to 168 MHz.
Output frequency (fout*) = fvco/K
* : Please set the fout range from 8 MHz to 100 MHz.
Set the output frequencyto 8MHz to 50 MHzfor CLK3 and CLK4 setting registers when VDP is 1.8 V 0.15 V.
(Setting example)
fin : 19.2 MHz, fout : 29.6 MHz
M divider parameter : 222 ( = 0DEH) , N divider parameter : 144 ( = 090H) , K divider parameter : 1 ( = 01H)
(19.2 × 222 / 144) / 1 = 29.6 (MHz) (fvco : 19.2 × 222 / 144 = 29.6 (MHz) )
Note: The recommended setting value of the VCO gain and the M divider depends on the internal oscillation
frequency.
Also, the recommended setting value of the Charge Pump depends on the setting values of the VCO gain
and the M divider. Please confirm the recommended value with the Fujitsu Microelectronics support tool.
Contact the sales representatives for details on the support tools.
<Modulation frequency setting>
Modulation frequency can be set by writing L divider parameter to the register.
The average of modulation frequency can be calculated with following formula:
Input frequency
266 × L
(L = 1, 2, 3, 4, 5, 6, 7, 8)
(Setting example) fin : 19.2 MHz, average of modulation freq. 19.2 / (266 × 6) × 1000 = Approximately 12.0 (kHz)
bit30
bit29
bit28
L divider parameter
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
8
1
2
3
4
5
6
1
1
1
1
0
1
(Recommended value)
7
DS04-29138-3E
13
MB88182
<Modulation rate setting>
Modulation rate can be selectable from no modulation, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%,
1.75%.
bit43
bit42
bit41
Modulation rate setting
No modulation
0.25%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.50%
0.75%
1.00%
1.25%
1.50%
1.75%
<Charge Pump setting, VCO gain setting>
Please refer and confirm the recommended value by our support tool. Contact the sales representatives for
details on the support tools.
<Output drive ability setting>
Output drive ability of clock output pin can be selected.
bit44
Output drive ability
0
1
Small
Large
<Slew rate setting>
Slew rate of clock output pin can be selected.
bit45
Slew rate
Low
0
1
High
14
DS04-29138-3E
MB88182
■ I2C
This device contains the I2C macro and enables the slave transfer operation. The I2C is set to the corresponding
registers via the I2C bus.
<Bus specification>
• The transfer rate should be in either standard mode or the fast mode (The high speed mode is not supported) .
• 7-bit address specified (The general call and the 10-bit address specifications are not supported).
<Bus format when writing register>
first S6
S0 R/W
C7
Command
(8 bit)
C0
D7
Register setting
(8 bit)
D0
Last
P
Slave address
(7 bit)
S
0
A
A
A
A
Register setting
: Transmit from master device
: Transmit from this device (slave)
S : START condition A : Acknowledge P : STOP condition
<Slave address>
When receiving the slave address, the address is compared with the address in the following table. If the slave
address matches the address in the table only, I2C judges to access to this device.
Slave address (7-bit)
S6
1
S5
0
S4
0
S3
1
S2
1
S1
1
S0
1
Part number
MB881821APVA1/MB881822APVA1
MB881821BPVA1/MB881822BPVA1
1
0
1
1
1
1
1
<Select R/W>
“0” : Write to slave device
“1” : Read from slave device
DS04-29138-3E
15
MB88182
<Command>
Set for the CLK2, CLK3 and CLK4 setting registers with either individual or successive settings. Settings other
than those in the following table are prohibited.
Command (8-bit)
Transfer
bytes
C7
C6
C5
C4
C3
C2
C1
C0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
4
6
Set to CLK1 setting register
Set to CLK2 setting register
Set to CLK3 setting register
Set to CLK4 setting register
Successive set to all registers
6
6
22
Other than “0000” or
those above
Successive set to the register
corresponding to the bit which is set “1”.
0
0
0
0
10 to 18
<Register setting for writing data>
Transfer data from the upper address. When writing successively to the setting registers of multiple clocks, the
data will be written from the setting registers CLK1, CLK2, CLK3 and to CLK4 in order.
<Bus format for reading register>
first S6
S0 R/W
D7
D0
D7
D0
Last
P
Slave address
CLK1 setting register
bit31-24 output
CLK1 setting register
bit23-16 output
outputregister
values
S
1
A
A
A
A
(7 bit)
: Transmit from master device
: Transmit from this device (slave)
S : START condition A : Acknowledge P : STOP condition
When reading data, the data will be output from the upper address of the CLK1 setting register, then CLK2
setting register, CLK3 setting register, CLK4 setting register, in order. The data will be output 22 bytes in total.
Note: When all outputs in this device are powered down, the I2C function also stops. Therefore, setting by the I2C
should be performed when the CKREF clock is being output.
16
DS04-29138-3E
MB88182
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Pin
Unit
Min
− 0.5
Max
+ 2.5
+ 4.0
+ 4.0
VDD
VDDE
VDP
VDD
VDDE
VDP
V
V
V
Power supply voltage*1
− 0.5
− 0.5
CKIN
VSS − 0.5
VDD + 0.5
V
XPDREF,
XPD1, XPD2,
XPD3, XPD4,
SCL, SDA
Input voltage*1
VI
VSS − 0.5
VDDE + 0.5
V
VDD + 0.5*2
VDDE + 0.5*3
CLK1
VSS − 0.5
VSS − 0.5
VSS − 0.5
− 55
V
V
Output voltage*1
VO
CLK2, SDA
VDDE + 0.5
VDP + 0.5
+ 125
CLK3, CLK4,
CKREF
V
Storage temperature
TST
TJ
⎯
⎯
⎯
°C
°C
mA
V
Operation junction
temperature
− 40
+ 125
Output current
IO
− 13
+ 13
VDDE + 1.0
(tOVER ≤ 50 ns)
XPDREF,
XPD1, XPD2,
XPD3, XPD4,
SCL, SDA
Overshoot
VIOVER
⎯
VSS − 1.0
(tUNDER ≤ 50 ns)
Undershoot
VIUNDER
⎯
V
*1 : The parameter is based on VSS = 0.0 V.
*2 : Part number: MB881821A/MB881821B
*3 : Part number: MB881822A/MB881822B
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Overshoot / Undershoot
tunder ≤ 50 ns
VIOVER ≤ VDDE + 1.0 V
V
DDE
Input pin
V
SS
tOVER ≤ 50 ns
VIUNDER ≤ VSS − 1.0 V
DS04-29138-3E
17
MB88182
■ RECOMMENDED OPERATING CONDITIONS
Value
Typ
1.8
Parameter
Symbol
Pin
Condition
Unit
Min
1.65
Max
1.95
VDD
VDD
⎯
⎯
VDDE
VDDE
2.5
2.6
2.7
Power supply voltage
V
1.65
1.8
1.95
VDP
VIH1
VDP
⎯
⎯
2.5
2.6
2.7
CKIN
VDD × 0.8
⎯
VDD + 0.3
ENS,XPDREF,
XPD1,
XPD2,XPD3,
XPD4
“H” level input voltage
VIH2
⎯
VDDE × 0.8
⎯
VDDE + 0.3
V
V
VIH3
VIL1
SDA, SCL
CKIN
⎯
⎯
VDDE × 0.7
Vss − 0.3
⎯
⎯
VDDE + 0.3
VDD × 0.2
ENS,XPDREF,
XPD1, XPD2,
XPD3, XPD4
“L” level input voltage
VIL2
⎯
⎯
Vss − 0.3
⎯
VDDE × 0.2
VIL3
VIC
SDA, SCL
Vss − 0.3
⎯
⎯
VDDE × 0.3
Input clock amplitude
level
During clock
input of
capacitive
coupling
CKIN
0.45
VDD
V p-p
pF
⎯ *
Input coupling capacity
CC
20
⎯
⎯
19.2
[MHz]
Input clock duty cycle
Operating temperature
tDCI
Ta
CKIN
40
50
60
%
⎯
⎯
− 40
⎯
+ 85
°C
* : Capacity value when clock signal is input to the CKIN pin via coupling capacity.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Input clock duty cycle (tDCI = th/tp)
t
P
t
h
VDD/2
CKIN
18
DS04-29138-3E
MB88182
■ ELECTRICAL CHARACTERISTICS
• DC Characteristics
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V)
Value
Parameter Symbol
Pin
Conditions
Unit
Min
⎯
Typ
7
Max
11
ICC
VDD*1
VDDE
CKREF = 19.2 MHz,
CLK1 = 48 MHz*2,
CLK2 = 27 MHz,
CLK3 = 37 MHz,
CLK4 output stop,
output no load,
ICCE
⎯
0.5
⎯
mA
Power
ICCP
VDP
⎯
0.9
⎯
supply
current
CKIN direct input
ICCH
ICCEH
ICCPH
VDD
VDDE
VDP
⎯
⎯
⎯
2
1
1
50
5
When all clock output
disable
μA
5
Driving ability small setting
“H” level output
VDDE − 0.2
VDP − 0.2
VDDE
VDP
VOH1
VOL1
VOH2
VOL2
⎯
⎯
⎯
⎯
IOH = − 2 mA
Driving ability small setting
“L” level output
CLK1*3,
CLK2,
CLK3,
CLK4
VSS
0.2
IOL = 2 mA
V
Driving ability large setting
“H” level output
VDDE − 0.2
VDP − 0.2
VDDE
VDP
IOH = − 4 mA
Driving ability large setting
“L” level output
VSS
0.2
IOL = 4 mA
“H” level output
IOL = − 2 mA
VOH1
VDP − 0.2
⎯
⎯
VDP
Output
voltage
CKREF
V
“L” level output
VOL1
VSS
0.2
IOL = 2 mA
Driving ability small setting
“H” level output
VOH3
VOL3
VOH4
VOL4
VDD − 0.2
⎯
⎯
⎯
⎯
VDD
0.2
VDD
0.2
IOH = − 2 mA
Driving ability small setting
“L” level output
VSS
IOL = 2 mA
CLK1*2
V
Driving ability large setting
“H” level output
VDD − 0.2
IOH = − 4 mA
Driving ability large setting
“L” level output
VSS
IOL = 4 mA
(Continued)
DS04-29138-3E
19
MB88182
(Continued)
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
Typ
Max
“L” level output
Output voltage
VOL2
SDA
VSS
⎯
0.2
V
IOL = 4 mA
XPDREF,
XPD1, XPD2,
XPD3, XPD4
Pull-up resistance
value*4
RPU
VIH = VDDE × 0.8
10
20
30
10
kΩ
CKIN, ENS,
XPDREF,
XPD1, XPD2, VDD = VDDE = VI = 0 V
XPD3, XPD4,
SDA, SCL
Ta = + 25 °C
Input capacitance
CIN
⎯
⎯
pF
f = 1 MHz
*1 : Excluding power supply current in the CLK1 output
*2 : Part number: MB881821APVA1/MB881821BPVA1
*3 : Part number: MB881822APVA1/MB881822BPVA1
*4 : The pull up resistor for each pin is cut off when the pin input is in “L” level.
(Ta = − 40 °C to + 85 °C, VDP = 1.8 V 0.15 V)
Value
Unit
Parameter
Symbol
Pin
Conditions
Min
Typ
Max
Driving ability small
setting
“H” level output
IOH = − 1 mA
VOH5
VDP − 0.2
⎯
VDP
Driving ability small
setting
“L” level output
IOL = 1 mA
VOL5
VOH6
VOL6
VSS
VDP − 0.2
VSS
⎯
⎯
⎯
0.2
VDP
0.2
CLK3,
CLK4
V
Driving ability large
setting
“H” level output
IOH = − 2 mA
Output voltage
Driving ability large
setting
“L” level output
IOL = 2 mA
“H” level output
IOL = − 1 mA
VOH5
VOL5
VDP − 0.2
⎯
⎯
VDP
CKREF
V
“L” level output
VSS
0.2
IOL = 1 mA
20
DS04-29138-3E
MB88182
• AC characteristics 1
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
Typ
Max
Input frequency
fIN
CKIN
⎯
10
19.2
30
MHz
Load capacitance
15 pF or less
CKREF
10
8
19.2
⎯
30
100
90
Load capacitance
15 pF or less
CLK1*1
Output
frequency
fOUT
MHz
CLK1*2,
CLK2,
CLK3,
CLK4
Load capacitance
15 pF or less
8
⎯
Load capacitance
10 pF or less
8
⎯
100
Slewing rate low,
Driving ability small setting
15 pF load capacitance
8 MHz to 70 MHz
0.32
0.33
0.37
0.43
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Slewing rate high,
Driving ability small setting
15 pF load capacitance
8 MHz to 70 MHz
Output slewing
rate
SR
CLK1*1
V/ns
Slewing rate low,
Driving ability large setting
15 pF load capacitance
8 MHz to 80 MHz
Slewing rate high,
Driving ability large setting
15 pF load capacitance
8 MHz to 100 MHz
(Continued)
DS04-29138-3E
21
MB88182
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
Typ
Max
Slewing rate low,
Driving ability small setting
15 pF load capacitance
8 MHz to 50 MHz
0.31
⎯
⎯
Slewing rate high,
Driving ability small setting
15 pF load capacitance
8 MHz to 60 MHz
0.33
0.46
0.50
0.63
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CLK1*2,
CLK2,
CLK3,
CLK4
Slewing rate low,
Driving ability large setting
15 pF load capacitance
8 MHz to 60 MHz
Output
slewing rate
SR
V/ns
Slewing rate high,
Driving ability large setting
15 pF load capacitance
8 MHz to 90 MHz
Slewing rate high,
Driving ability large setting
10 pF load capacitance
90 MHz to 100 MHz
CKREF
CLK1*1
15 pF load capacitance
Driving ability small setting
Driving ability large setting
Driving ability small setting
Driving ability large setting
Driving ability small setting
0.33
⎯
⎯
40
28
60
30
60
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CLK1*2
Output
impedance
⎯
ZO
Ω
CLK2,
CLK3,
CLK4
⎯
Driving ability large setting
⎯
⎯
30
60
⎯
⎯
CKREF
⎯
(Continued)
22
DS04-29138-3E
MB88182
(Continued)
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
40
45
40
45
40
Typ
⎯
Max
60
VDD / 2*3
VDD / 2*4
VDDE / 2*3
CLK1*1
CLK1*2
⎯
55
⎯
60
VDDE / 2*4
⎯
55
Output clock
duty cycle
tDCC
%
CLK2,
CLK3,
CLK4
VDDE / 2, VDP / 2*3
⎯
60
VDDE / 2, VDP / 2*4
VDP / 2
45
⎯
⎯
55
CKREF
tDCI − 5*5
tDCI + 5*5
CLK2,
CLK3,
CLK4
Modulation
frequency
fin/ (224 × L) fin/ (266 × L) fin/ (308 × L)
kHz
(clks)
FMOD
⎯
⎯
⎯
( 224 × L )
( 266 × L )
( 308 × L )
CLK1
⎯
⎯
0.3
ms
ms
CLK2,
CLK3,
CLK4
Lock-up time*6
tLK
⎯
⎯
16
CLK1,
CLK2,
CLK3,
CLK4
Cycle-cycle
jitter
No load
capacitance
tJC
⎯
⎯
100
ps-rms
CKREF
Power down
tRPD
CKREF
⎯
⎯
⎯
⎯
⎯
⎯
tP × 2 + 2
tP × 2 + 2
ns
ns
CKREF
Power down
release
tROE
CKREF
*1: Part number: MB881821APVA1/MB881821BPVA1
*2: Part number: MB881822APVA1/MB881822BPVA1
*3 : When K divider parameter = 1 and output frequency is above 50 MHz.
*4 : When K divider parameter ≠ 1, or K divider parameter = 1 and output frequency is 50 MHz or less.
*5 : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.
*6 : The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS/
power down pins. The lock-up time varies depending on the setting value to the respective register. Please
confirm the recommended value with the Fujitsu Microelectronics support tool. Contact the sales representa-
tives for details on the support tools.
DS04-29138-3E
23
MB88182
(Ta = − 40 °C to + 85 °C, VDP = 1.8 V 0.15 V)
Value
Unit
Parameter
Symbol
Pin
Conditions
Min
Typ
Max
Load capacitance
10 pF or less
8
⎯
50
Output
frequency
CLK3,
CLK4
fOUT
MHz
Load capacitance
15 pF or less
8
⎯
⎯
40
Slewing rate low,
Driving ability small setting
15 pF load capacitance
8 MHz to 25 MHz
0.13
⎯
Slewing rate high,
Driving ability small setting
15 pF load capacitance
8 MHz to 30 MHz
0.14
0.19
0.22
0.29
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Slewing rate low,
Driving ability large setting
15 pF load capacitance
8 MHz to 30 MHz
CLK3,
CLK4
Output slewing
rate
SR
V/ns
Slewing rate high,
Driving ability large setting
15 pF load capacitance
8 MHz to 40 MHz
Slewing rate high,
Driving ability large setting
10 pF load capacitance
8 MHz to 50 MHz
CKREF
15 pF load capacitance
Driving ability small setting
Driving ability large setting
⎯
0.14
⎯
⎯
80
40
80
⎯
⎯
⎯
⎯
CLK3,
CLK4
Output
impedance
ZO
⎯
Ω
%
CKREF
⎯
CLK3,
CLK4
VDP / 2
VDP / 2
⎯
45
tDCI − 5*
⎯
⎯
⎯
⎯
55
Output clock
duty cycle
tDCC
CKREF
tDCI + 5*
tP × 2 + 2
CKREF
Power down
tRPD
CKREF
ns
ns
CKREF
Power down
release
tROE
CKREF
⎯
⎯
⎯
tP × 2 + 2
* : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.
24
DS04-29138-3E
MB88182
<Definition of modulation frequency and number of input clocks per modulation>
f (Output frequency)
Modulation waveform
t
F
MOD (Min)
FMOD (Max)
V
Input clock
t
Clock count
NMOD (Max)
Clock count
NMOD (Min)
This product contains the modulation period to realize the efficient EMI reduction.
The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max).
Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modulation
period FMOD.
<Output slew rate (SR) >
CLK1
(VDD − 0.2) V*,(VDP − 0.2) V*,
(VDDE − 0.2) V*
CLK2
CLK3
CLK4
0.2 V
t
f
t
r
* : The value is differ depending on the power supply pin.
CLK1 : (VDD − 0.2)V or (VDDE − 0.2)V (depending on models)
CLK2 : (VDDE − 0.2)V
CLK3 : CLK4: (VDP − 0.2)V
Note: SR = (power supply voltage − 0.4) / tr, SR = (power supply voltage − 0.4) / tf
<Cycle-cycle jitter (tJC = |tn − tn + 1|)>
CLK1
CLK2
CLK3
t
n
tn+1
CLK4
DS04-29138-3E
25
MB88182
<Output timing with XPDREF control>
XPDREF
CKREF
VIL
tRPD
tP
VIH
XPDREF
CKREF
tROE
<Lock-up time>
CKIN
V
IH
XPD1, XPD2,
V
IL
tLK (lock-up time)
XPD3, XPD4
CLK1, CLK2,
CLK3, CLK4
If the power down control is performed on pins XPD1, XPD2, XPD3 and XPD4, the desired clock frequency will
be obtained once the power down pin becomes at the “H” level and after the lock-up time tLK has passed at
maximum.
CKIN
VIH
ENS
V
IL
tLK
tLK
(lock-up time)
(lock-up time)
CLK2,
CLK3,CLK4
If the ENS pin setting changes during the normal operation, setting clocks CLK2, CLK3 and CLK4 will be output
once the ENS pin level is decided and after lock-up time tLK has passed at maximum.
Note: When the ENS pin setting is changed, the stabilization wait time is needed for the output clock from CLK2,
CLK3 and CLK4 pins. During the stabilization wait time, the output frequency, output clock duty cycle,
modulation frequency, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform pro-
cessing such as cancelling a reset of the device at the succeeding stage after the lock-up time.
26
DS04-29138-3E
MB88182
• AC characteristics 2 (Serial timing)
(Ta = − 40 °C to + 85 °C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
Max
SCL clock frequency
fSCL
tISU
SCL
SDA
⎯
⎯
0
400
kHz
ns
During data input
set up time
100
0
⎯
⎯
During data input
hold time
tIH
SDA
⎯
⎯
⎯
⎯
⎯
ns
ns
V
SDA
SCL
Noise removal width
Input hysteresis
tNC
100
0.3
0.5
0.5
160
⎯
SDA
SCL
VHYS
tSTAH
tSTASU
(Repeat) START condition
hold time
SDA
SCL
⎯
μs
μs
Repeat START condition
setup time
SDA
SCL
⎯
SCL clock “L” width
SCL clock “H” width
tCL
tCH
SCL
SCL
⎯
⎯
1
⎯
⎯
μs
μs
0.5
SDA
SCL
STOP condition setup time
tSTOSU
tBUF
tOSU
tOH
⎯
⎯
0.5
1
⎯
⎯
μs
μs
μs
μs
ns
Bus free time between stop
condition and start condition
SDA
SCL
During bus drive
set up time
SDA
SDA
SDA
1
⎯
Bus load: under 400 pF,
Resistor value for bus
pull-up: at least 750 Ω
During bus drive
hold time
0
0.6
300
During bus drive
fall time
tOF
⎯
DS04-29138-3E
27
MB88182
• During data input/bus drive
VDDE 0.7
SCL
VDDE 0.3
t
t
ISU
,
t
t
IH
,
OSU
OH
SDA
• Noise cancel operation
t
NC
tNC
External SCL
signal
InternalSCLsignal
afternoiseremoval
The pulse in the tNC range is
removed.
• (Repeat) Start operation, Stop operation
tSTASU
tSTOSU
SCL
tBUF
tSTAH
SDA
28
DS04-29138-3E
MB88182
■ RECOMMENDED CIRCUIT
CLK3
CLK4
2.6 V to 1.8 V
+
ENS
R
3
R
4
C3
2.6 V
1
2
3
4
5
6
7
17
16
15
14
13
12
11
20 19 18
R5
CKREF
CKIN
6
C
R
2
CLK2
MB88182
1.8 V
R1
XPD4
CLK1
8
9
10
XPD3
C
4
XPD2
XPD1
C5
R7
R
6
XPDREF
+
+
C1
SCL SDA
C2
C1, C2, C3
C4, C5, C6
: Capacitor of 10 μF or higher
: Capacitor of about 0.01 μF (connect a capacitor of good high frequency
property (ex. laminated ceramic capacitor) to close to this device)
R1, R2, R3, R4, R5 : Impedance matching resistor for board pattern
R6, R7
: I2C bus Pull-up resistor
DS04-29138-3E
29
MB88182
■ CLOCK INPUT VIA COUPLING CAPACITY
It is possible to input clocks to the CKIN pin via the coupling capacity as shown in the following figure. The device
input part contains the CMOS inverter and the feedback resistor (1 MΩ). The clock input via the coupling capacity
operates near the threshold level of the CMOS inverter, therefore the current for the capacity connection clock
input increases compared to the normal input.
LSI external
Clock after the coupling
capacity passes by
LSI internal
Input clock
VIC
CKIN pin
CC
Input via
coupling capacity
Rf (1 MΩ)
30
DS04-29138-3E
MB88182
■ ORDERING INFORMATION
Part number
Package
MB881821APVA1-GE1
MB881821APVA1-G-ERE1
MB881821APVA1-G-EFE1
MB881821BPVA1-GE1
MB881821BPVA1-G-ERE1
MB881821BPVA1-G-EFE1
MB881822APVA1-GE1
20-pin plastic BCC
(LCC-20P-M06)
MB881822APVA1-G-ERE1
MB881822APVA1-G-EFE1
MB881822BPVA1-GE1
MB881822BPVA1-G-ERE1
MB881822BPVA1-G-EFE1
MB881821AWQN-G-JNE1
MB881821AWQN-G-JN-ERE1
MB881821AWQN-G-JN-EFE1
MB881821BWQN-G-JNE1
MB881821BWQN-G-JN-ERE1
MB881821BWQN-G-JN-EFE1
MB881822AWQN-G-JNE1
MB881822AWQN-G-JN-ERE1
MB881822AWQN-G-JN-EFE1
MB881822BWQN-G-JNE1
MB881822BWQN-G-JN-ERE1
MB881822BWQN-G-JN-EFE1
24-pin plastic QFN
(LCC-24P-M61)
DS04-29138-3E
31
MB88182
■ PACKAGE DIMENSION
20-pin plastic BCC
Lead pitch
0.50 mm
3.50 mm × 3.50 mm
Plastic mold
Package width ×
package length
Sealing method
Mounting height
Weight
0.60 mm MAX
0.01 g
(LCC-20P-M06)
20-pin plastic BCC
(LCC-20P-M06)
3.00(.118)REF.
0.55±0.050
(.022±.0020)
Mount height
3.50±0.10
(.138±.004)
0.50±0.10
(.020±.004)
0.50(.020)
TYP
11
17
17
11
0.50(.020)
TYP.
2.90(.114)
TYP.
INDEX AREA
3.50±0.10
(.138±.004)
2.90(.114)
TYP.
1PIN INDEX
0.95
(.037)
"B"
1.55(.061)
"A"
1.00(.004)
REF.
0.075±0.025
(.003±.001)
(Stand off)
1
7
7
1
Details of "A" part
Details of "B" part
0.40±0.06
(.016±.002)
0.40±0.06
(.016±.002)
0.30±0.06
(.012±.002)
0.14(.006)
MIN
0.20(.008)
0.05(.002)
0.30±0.06
(.012±.002)
0.20(.008)
1PIN INDEX
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2004-2008 FUJITSU MICROELECTRONICS LIMITED C20057S-c-1-2
TD -
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
32
DS04-29138-3E
MB88182
(Continued)
24-pin plastic QFN
Lead pitch
0.40 mm
Package width ×
package length
2.50 mm × 3.50 mm
Sealing method
Mounting height
Weight
Plastic mold
0.80 mm MAX
0.02 g
(LCC-24P-M61)
24-pin plastic QFN
(LCC-24P-M61)
2.60±0.10
(.102±.004)
3.50±0.10
(.138±.004)
2.50±0.10
(.098±.004)
1.60±0.10
(.063±.004)
0.15±0.05
(.006±.002)
INDEX AREA
0.24±0.05
(.009±.002)
0.40(.016)
TYP
1PIN CORNER
(C0.50(C.020))
0.02 +–00..0032
+.001
0.75±0.05
(.030±.002)
(.001
)
–.001
(0.20(.008))
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS04-29138-3E
33
MB88182
MEMO
34
DS04-29138-3E
MB88182
MEMO
DS04-29138-3E
35
MB88182
FUJITSU MICROELECTRONICS LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-8508, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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