MB84VD22396EJ-90-PBS [FUJITSU]
Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA71, PLASTIC, FBGA-71;
| 型号： | MB84VD22396EJ-90-PBS |
| 厂家： | 
FUJITSU |
| 描述： | Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA71, PLASTIC, FBGA-71 静态存储器 内存集成电路 |
| 文件： | 总62页 (文件大小：983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50212-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
32M (×16) FLASH MEMORY &
16M (×16) SRAM Interface FCRAM
MB84VD22386EJ/VD22387EJ/VD22388EJ-85/90
MB84VD22396EJ/VD22397EJ/VD22398EJ-85/90
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V for FCRAM
• Power Supply Voltage of 2.7 V to 3.3 V for Flash
• High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 71-ball BGA
(Continued)
■ PRODUCT LINE-UP
Flash Memory
FCRAM
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
VCCf* = 2.7 to 3.3
VCCs* = 2.7 to 3.1
85
85
35
85
85
50
*: Both VCCf and VCCs must be the same level when either part is being accessed.
■ PACKAGE
71-ball plastic BGA
(BGA-71P-M02)
Note : These guarantee both FCRAM and Flash at 85 ns Access Cycle.
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1. FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Multiple devices available with different bank sizes
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased. The devices also support full chip erase.
• Boot Code Sector Architecture
MB84VD22386EJ/VD22387EJ/VD22388EJ: Top sector
MB84VD22396EJ/VD22397EJ/VD22398EJ: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Hidden ROM (Hi-ROM) Region
64 Kbyte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
Allows protection of boot sectors at VIL, regardless of sector protection/unprotection status
(MB84VD22386EJ/VD22387EJ/VD22388EJ: SA69,SA70
MB84VD22396EJ/VD22397EJ/VD22398EJ: SA0,SA1)
Allows removal of boot sector protection at VIH.
At VACC, program time will reduce by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please Refer to “MBM29DL32XTE/BE” Data Sheet in Detailed Function
2. FCRAM
• Power Dissipation
Operating: 20 mA Max
Standby: 70 µA Max
Power Down: 10 µA Max
• Power Down Control by CE2s
• Byte Write Control: LBs (DQ7-DQ0), UBs (DQ15-DQ5)
• 4 Words Address Access Capability
2
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PIN ASSIGNMENT
(Top View)
Marking side
A8
B8
D8
E8
F8
G8
H8
J8
L8
M8
N.C.
N.C.
A15
N.C.
N.C.
A16
Vccf
Vss
N.C.
N.C.
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
N.C.
N.C.
A11
A12
A13
A14
N.C.
DQ15
DQ7
DQ14
N.C.
N.C.
C6
A8
D6
E6
A9
F6
G6
H6
J6
K6
A19
A10
DQ6
DQ13
DQ12
DQ5
C5
D5
E5
H5
J5
K5
WE
CE2s
A20
DQ4
Vccs
N.C.
C4
D4
E4
H4
J4
K4
WP/ACC RESET RY/BY
DQ3
Vccf
DQ11
C3
D3
E3
F3
G3
H3
J3
K3
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
C2
A7
D2
A6
E2
A5
F2
A4
G2
H2
J2
K2
L2
M2
N.C.
VSS
OE
DQ0
DQ8
N.C.
N.C.
A1
B1
D1
A3
E1
A2
F1
A1
G1
A0
H1
J1
L1
M1
N.C.
N.C.
CEf
CE1s
N.C.
N.C.
(BGA-71P-M02)
3
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PIN DESCRIPTIONS
Pin Name
A19 to A0
A20
Input/Output
Function
I
Address Inputs (Common)
Address Input (Flash)
I
DQ15 to DQ0
CEf
I/O
Data Inputs/Outputs (Common)
Chip Enable (Flash)
I
CE1s
CE2s
OE
I
Chip Enable (FCRAM)
Chip Enable (FCRAM)
Output Enable (Common)
Write Enable (Common)
I
I
WE
I
RY/BY
UBs
O
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (FCRAM)
I
LBs
I
Lower Byte Control (FCRAM)
RESET
WP/ACC
N.C.
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
I
—
VSS
Power
Power
Power
Device Ground (Common)
VCCf
Device Power Supply (Flash)
VCCs
Device Power Supply (FCRAM)
4
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ BLOCK DIAGRAM
VCCf
VSS
A20 to A0
RY/BY
A20 to A0
WP/ACC
RESET
CEf
32 M bit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A19 to A0
DQ15 to DQ0
LBs
UBs
WE
16 M bit
FCRAM
OE
CE1s
CE2s
5
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ DEVICE BUS OPERATION
WP/ACC
Operation *1, *2
Full Standby
CEf CE1s CE2s OE WE LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET
7
*
H
H
L
H
L
H
H
H
H
H
H
X
H
H
L
X
H
H
H
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
DOUT
High-Z
High-Z
High-Z
DOUT
H
H
X
Output Disable *3
X
H
H
H
L
Read from Flash *4
Write to Flash
L
H
H
H
X
X
X
L
H
L
DIN
DIN
Read from FCRAM *5
H
H
DOUT
DOUT
DIN
DIN
Write to FCRAM
H
L
H
H
L
H
L
L
High-Z
DIN
DIN
H
X
H
High-Z
Temporary Sector
X
X
X
X
X
H
X
X
X
H
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
X
High-Z
X
VID
L
X
X
L
Group Unprotection *6
Flash Hardware Reset
BootBlockSectorWrite
Protection
X
FCRAM Power Down *8
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ DC CHARACTERISTICS” for voltage levels.
*1: Other operations except for indicated this column are prohibited.
*2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*3: FCRAM Output Disable condition should not be kept longer than 1 µs.
*4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*5: FCRAM Byte control at Read operation is not supported.
*6: Also used for the extended sector group protections.
*7: Protect “outermost” 2 × 8 Kbytes (4 words) on both ends of the boot block sectors.
*8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
6
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and sixty three 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
1FFFFFh
SA70 : 8KB (4KW)
1FF000h
SA69 : 8KB (4KW)
1FE000h
SA68 : 8KB (4KW)
1FD000h
SA67 : 8KB (4KW)
1FC000h
SA66 : 8KB (4KW)
1FB000h
SA65 : 8KB (4KW)
1FA000h
SA64 : 8KB (4KW)
1F9000h
SA63 : 8KB (4KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
1F8000h
1F0000h
Bank 1
MB84VD22386EJ
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
Bank 1
MB84VD22387EJ
Bank 1
MB84VD22388EJ
Bank 2
MB84VD22386EJ
Bank 2
MB84VD22387EJ
Bank 2
MB84VD22388EJ
MB84VD22386EJ/VD22387EJ/VD22388EJ Sector Architecture (Top Boot Block)
(Continued)
7
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1FFFFFh
SA70 : 64KB (32KW)
1F8000h
SA69 : 64KB (32KW)
1F0000h
SA68 : 64KB (32KW)
1E8000h
SA67 : 64KB (32KW)
1E0000h
SA66 : 64KB (32KW)
1D8000h
SA65 : 64KB (32KW)
1D0000h
SA64 : 64KB (32KW)
1C8000h
SA63 : 64KB (32KW)
1C0000h
SA62 : 64KB (32KW)
1B8000h
SA61 : 64KB (32KW)
1B0000h
SA60 : 64KB (32KW)
1A8000h
SA59 : 64KB (32KW)
Bank 2
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
MB84VD22398EJ
Bank 2
MB84VD22397EJ
Bank 2
MB84VD22396EJ
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
Bank 1
MB84VD22398EJ
Bank 1
MB84VD22397EJ
Bank 1
MB84VD22396EJ
MB84VD22396EJ/VD22397EJ/VD22398EJ Sector Architecture (Bottom Boot Block)
8
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22386EJ)
Sector Address
Bank Sector Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
Bank 2 SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
(Continued)
9
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank Sector Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Address Range
SA35
SA36
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1F8FFFh
1F9000h to 1F9FFFh
1FA000h to 1FAFFFh
1FB000h to 1FBFFFh
1FC000h to 1FCFFFh
1FD000h to 1FDFFFh
1FE000h to 1FEFFFh
1FF000h to 1FFFFFh
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
Bank 2 SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
Bank 1 SA63
SA64
0
0
1
SA65
0
1
0
SA66
0
1
1
SA67
1
0
0
SA68
1
0
1
SA69
1
1
0
SA70
1
1
1
10
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22396EJ)
Sector Address
Bank Sector Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
Bank 1
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
(Continued)
11
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank Sector Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Address Range
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
Bank 2
12
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22387EJ)
Sector Address
Bank
Address
Bank Sector
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
Bank 2
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
(Continued)
13
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Address
Bank Sector
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1F8FFFh
1F9000h to 1F9FFFh
1FA000h to 1FAFFFh
1FB000h to 1FBFFFh
1FC000h to 1FCFFFh
1FD000h to 1FDFFFh
1FE000h to 1FEFFFh
1FF000h to 1FFFFFh
SA39
Bank 2
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
Bank 1 SA59
SA60
SA61
SA62
SA63
SA64
0
0
1
SA65
0
1
0
SA66
0
1
1
SA67
1
0
0
SA68
1
0
1
SA69
1
1
0
SA70
1
1
1
14
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22397EJ)
Sector Address
Bank
Address
Bank Sector
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
Bank 1 SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
Bank 2
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
(Continued)
15
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank Sector
Address Range
Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
SA54
Bank 2
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
16
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22388EJ)
Sector Address
Bank
Address
Bank Sector
Address Range
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
Bank 2
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
(Continued)
17
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Address
Bank Sector
Address Range
A20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
Bank 1 SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1F8FFFh
1F9000h to 1F9FFFh
1FA000h to 1FAFFFh
1FB000h to 1FBFFFh
1FC000h to 1FCFFFh
1FD000h to 1FDFFFh
1FE000h to 1FEFFFh
1FF000h to 1FFFFFh
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
18
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22398EJ)
Sector Address
Bank
Address
Bank Sector
Address Range
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Bank 1 SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
(Continued)
19
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Address
Bank Sector
Address Range
A20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19 A18 A17 A16 A15 A14 A13 A12 A11
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
SA54
Bank 2
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
20
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22386EJ/VD22387EJ/VD22388EJ)
(Top Boot Block)
Sector Group
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
X
X
X
SA0
0
1
SGA1
0
0
0
0
1
0
X
X
X
SA1 to SA3
1
1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SA28 to SA31
SA32 to SA35
SA36 to SA39
SA40 to SA43
SA44 to SA47
SA48 to SA51
SA52 to SA55
SA56 to SA59
SGA16
1
1
1
1
0
1
X
X
X
SA60 to SA62
1
0
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22396EJ/VD22397EJ/VD22398EJ)
(Bottom Boot Block)
Sector Group
SGA0
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SA0
0
0
0
0
0
0
0
0
0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
0
1
SGA8
0
0
0
0
1
0
X
X
X
SA8 to SA10
1
1
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SGA23
SGA24
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
SA67 to SA69
SA70
1
0
1
1
22
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Autoselect Codes
Type
Manufacturer’s Code
A19 to A12
A6
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
A1
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
A0
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Code (HEX)
04h
BA
MB84VD22386EJ
MB84VD22396EJ
MB84VD22387EJ
MB84VD22397EJ
MB84VD22388EJ
MB84VD22398EJ
BA
2255h
2256h
2250h
2253h
225Ch
225Fh
01h *
BA
BA
Device Code
BA
BA
BA
Sector Group protect
Sector Group Address
*: Output 01h at protected sector address and output 00h at unprotected sector address.
23
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Command Definitions
Fourth Bus
Read/Write
Cycle
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Command
Sequence
Addr. Data Addr. Data
Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
Read/Reset *1
1
3
XXXh F0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
555h AAh 2AAh
555h AAh 2AAh
55h
555h
F0h
RA
RD
(BA)
555h
Autoselect
3
55h
90h
A0h
—
—
—
—
—
—
—
—
—
—
Program
4
6
6
1
1
1
1
3
2
555h AAh 2AAh
555h AAh 2AAh
555h AAh 2AAh
55h
55h
55h
—
555h
555h
555h
—
PA
PD
Chip Erase
80h 555h AAh 2AAh 55h 555h 10h
Sector Erase
80h 555h AAh 2AAh 55h
SA
—
—
—
—
—
—
30h
—
—
—
—
—
—
Sector Erase Suspend
Sector Erase Resume
Program Suspend
Program Resume
Set to Fast Mode
Fast Program *2
Reset from Fast Mode
BA
BA
BA
BA
B0h
30h
B0h
30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
555h AAh 2AAh
XXXh A0h PA
55h
PD
555h
—
20h
—
2
BA
90h XXXh F0h*6
—
—
—
—
—
—
—
—
2
*
Extended Sector
4
XXXh 60h SPA
55h 98h
60h
SPA
40h SPA
SD
—
—
—
—
Group Protection *3
Query *4
1
3
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hi-ROM Entry
Hi-ROM Program *5
Hi-ROM Erase *5
555h AAh 2AAh
555h AAh 2AAh
555h AAh 2AAh
55h
55h
55h
555h
555h
555h
88h
A0h
PA
PD
80h 555h AAh 2AAh 55h HRA 30h
90h XXXh 00h
(HRBA)
555h
Hi-ROM Exit *5
4
555h AAh 2AAh
55h
—
—
—
—
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A6 to A0.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Notes: Address bits A20 to A11 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA), and Bank Address (BA).
Bus operations are defined in “■ DEVICE BUS OPERATION”.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A20 to A15)
SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0).
24
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
HRA= Address of the Hidden-ROM area.
MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type)
Word mode: 1F8000h to 1FFFFFh
Byte mode: 3F0000h to 3FFFFFh
MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type)
Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area
MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type)
A20 = A19 = A18 = A17 = A16 = A15 = 1
MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type)
A20 = A19 = A18 = A17 = A16 = A15 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0
25
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
–55
–30
Max
+125
Storage Temperature
Tstg
TA
°C
°C
V
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins *1
+85
VCCf +0.3
VCCs +0.3
+3.6
VIN, VOUT
–0.3
V
VCCf Supply *1
VCCs Supply *1
RESET *2
VCCf
VCCs
VIN
–0.2
–0.2
–0.5
–0.5
V
+3.3
V
+13.0
+10.5
V
WP/ACC *3
VIN
V
*1: Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3
V. During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCs + 1.0 V for periods of up to 5 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS
to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
–30
Max
+85
Ambient Temperature
VCCf Supply Voltage
VCCs Supply Voltage
TA
°C
V
VCCf
VCCs
+2.7
+2.7
+3.3
+3.1
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
26
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ DC CHARACTERISTICS
Value
Sym-
bol
Parameter
Conditions
Unit
Min
–1.0
–1.0
Typ
—
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCC
µA
µA
ILO
VOUT = VSS to VCC
—
RESET Inputs Leakage
Current
VCC = VCC Max,
RESET = 12.5 V
ILIT
—
—
—
—
35
20
µA
ACC Input Leakage
Current
VCC = VCC Max,
WP/ACC = VACC Max
ILIA
mA
tCYCLE = 5 MHz
—
—
—
—
18
7
mA
mA
Flash VCC Active Current
(Read) *1
CEf = VIL,
OE = VIH
ICC1f
tCYCLE = 1 MHz
Flash VCC Active Current
(Program/Erase) *2
ICC2f
ICC3f
ICC4f
ICC5f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
—
—
—
—
—
—
—
—
35
53
53
35
mA
mA
mA
mA
Flash VCC Active Current
(Read-While-Program) *5
Flash VCC Active Current
(Read-While-Erase) *5
Flash VCC Active Current
(Erase-Suspend-Program)
CEf = VIL, OE = VIH
VCCs = VCCs Max,
tRC / tWC =Min
tRC / tWC =Max
—
—
15
20
FCRAM VCC Active Current
Flash VCC Standby Current
ICC1s CE1s = VIL, CE2s = VIH,
VIN = VIH or VIL, IOUT = 0 mA
mA
2.5
3.0
VCCf = VCCf Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
ISB1f
ISB2f
—
—
1
1
5
5
µA
µA
Flash VCC Standby Current
(RESET)
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
VCCf = VCCf Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
FlashVCC Current(Automatic
Sleep Mode) *3
ISB3f
ISBs
—
1
5
µA
VIN = VCCf± 0.3 V or VSS ± 0.3 V
VCCs = VCCs Max,CE1s = CE2s = VIH,
VIN = VIH or VIL, IOUT = 0 mA
FCRAM VCC Standby Current
—
—
0.5
—
1
mA
VCCs = VCCs Max,CE1s > VCCs – 0.2 V,
FCRAM VCC Standby Current ISB1s CE2s > VCCs– 0.2 V,
VIN < 0.2 V or VCCs – 0.2 V, IOUT = 0 mA
70
µA
VCCs = VCCs Max,CE1s > VCCs – 0.2 V,
FCRAM VCC Standby Current ISB2s CE2s > VCCs– 0.2 V,
—
—
—
—
5 *6
10
mA
VIN Cycle time = tRC Min, IOUT = 0 mA
VCCs = VCCs Max,
VIN > VCCf – 0.2 V or VIN < 0.2 V
CE2s < 0.2 V, IOUT = 0 mA
FCRAM VCC Power Down
Current
IPDs
µA
(Continued)
27
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Value
Symbol
Parameter
Conditions
Unit
Min
–0.3
2.3
Typ
—
Max
0.4
Input Low Level
VIL
VIH
—
—
V
V
Input High Level
—
VCC+0.3
Voltage for Autoselect and
VID
—
—
11.5
8.5
—
12.5
9.5
V
V
Sector Protection (RESET) *4
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration
VACC
9.0
FCRAM Output Low Level
FCRAM Output High Level
Flash Output Low Level
VOL
VOH
VOL
VCCs = VCCs Min, IOL =1.0 mA
VCCs = VCCs Min, IOH = –0.5 mA
VCCf = VCCf Min, IOL = 4.0 mA
—
2.1
—
—
—
—
0.4
—
V
V
V
0.45
VCCf–
0.4
Flash Output High Level
VOH
VCCf = VCCf Min, IOH = –0.1 mA
—
—
—
—
V
V
Low Vcc Lock-Out
Voltage
VLKO
2.3
2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCC applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5MHz)
*6: ISB2s depends on VIN cycle time. Refer to “■ APPENDIX”.
28
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ AC CHARACTERISTICS
• CE Timing
Symbol
Value
Parameter
Condition
Unit
JEDEC
Standard
tCCR
Min
0
Max
—
CE Recover Time
CE Hold Time
—
—
—
—
ns
ns
tCHOLD
3
—
• Timing Diagram for alternating FCRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD
tCHOLD
tCCR
tCCR
CE2s
29
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Read Only Operations Characteristics (Flash)
Symbol
Value
Parameter
Read Cycle Time
Conditions
Unit
JEDEC
tAVAV
Standard
Min
Max
tRC
—
85
—
ns
ns
CEf = VIL
OE = VIL
Address to Output Delay
tAVQV
tACC
—
85
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
—
—
—
—
85
35
30
30
ns
ns
ns
ns
—
—
—
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
0
—
ns
µs
RESET Pin Low to Read Mode
tREADY
—
20
Note: Test Conditions– Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or VCC
Timing measurement reference level
Input: 0.5×VCC
Output: 0.5×VCC
30
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Read Cycle (Flash)
tRC
Address
Address Stable
tACC
CEf
OE
tOE
tDF
tOEH
WE
tCE
tOH
High-Z
High-Z
Outputs
Output Valid
• Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
Outputs
tOH
High-Z
Output Valid
31
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Erase/Program Operations Characteristics (Flash)
Symbol
JEDEC Standard Min
Value
Typ
—
Parameter
Unit
Max
—
Write Cycle Time
tAVAV
tAVWL
—
tWC
tAS
85
0
ns
ns
ns
ns
Address Setup Time (WE to Addr.)
—
—
Address Setup Time to CEf Low During Toggle Bit Polling
Address Hold Time (WE to Addr.)
tASO
tAH
15
45
—
—
tWLAX
—
—
Address Hold Time from CEf or OE High During Toggle
Bit Polling
—
tAHT
0
—
—
ns
Data Setup Time
tDVWH
tWHDX
—
tDS
tDH
35
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
Data Hold Time
Output Enable Setup Time
tOES
0
Read
Output Enable Hold Time
0
—
tOEH
Toggle and Data Polling
10
20
20
0
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write (OE to CEf)
Read Recover Time Before Write (OE to WE)
WE Setup Time (CEf to WE)
CEf Setup Time (WE to CEf)
WE Hold Time (CEf to WE)
CEf Hold Time (WE to CEf)
Write Pulse Width
—
tCEPH
tOEPH
tGHEL
tGHWL
tWS
—
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
0
0
tCS
0
tWH
0
tCH
0
tWP
35
35
30
30
—
—
CEf Pulse Width
tCP
Write Pulse Width High
tWPH
tCPH
CEf Pulse Width High
Word Programming Operation
Sector Erase Operation *1
tWHWH1
tWHWH2
(Continued)
32
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Symbol
JEDEC Standard Min
Value
Typ
—
Parameter
Unit
Max
—
VCCf Setup Time
—
—
—
—
—
—
—
—
—
—
—
tVCS
tVLHT
tVIDR
tVACCR
tRB
50
4
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
Voltage Transition Time *2
Rise Time to VID *2
—
—
500
500
0
—
—
Rise Time to VACC
—
—
Recover Time from RY/BY
RESET Pulse Width
—
—
tRP
500
—
—
—
Delay Time from Embedded Output Enable
RESET Hold Time Before Read
Program/Erase Valid to RY/BY Delay
Erase Time-out Time *3
tEOE
tRH
—
85
—
200
—
—
tBUSY
tTOW
tSPD
—
90
—
50
—
—
Erase Suspend Transition Time *4
—
20
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection Operation.
*3: The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
33
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
PA
PA
Address
CEf
tWC
tRC
tAS
tAH
tCH
tCS
tCE
OE
tOE
tWP
tWPH
tGHWL
tWHWH1
WE
tDF
tOH
tDS
tDH
PD
DOUT
DOUT
A0h
DQ7
Data
Notes: • PA is an address of the memory location to be programmed.
• PD is data to be programmed at the word address.
• DQ7 is the output of the data complement written to the device.
• DOUT is the data output written to the device.
• Figure indicates the last two out of four bus cycle sequence.
34
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
PA
PA
555h
Address
WE
tWC
tAH
tAS
tWS
tWH
OE
tCP
tCPH
tWHWH1
tGHEL
CEf
tDS
tDH
PD
DOUT
DQ7
A0h
Data
Notes: • PA is an address of the memory location to be programmed.
• PD is data to be programmed at the word address.
• DQ7 is the output of the data complement written to the device.
• DOUT is the data output written to the device.
• Figure indicates the last two out of four bus cycle sequence.
35
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms Chip/Sector Erase Operations (Flash)
2AAh
555h
555h
SA*
2AAh
Address
CEf
555h
tWC
tAS
tAH
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h
AAh
AAh
55h
80h
55h
Data
tVCS
VCCf
*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
36
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ
6
to DQ
0
DQ6 to DQ0
RY/BY
DQ6 to DQ0 = Output Flag
Valid Data
tBUSY
tEOE
* : DQ7 = Valid Data (the device has completed the Embedded operation).
37
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
OE
tOEH
tOEH
tOEPH
*
tOE
tCE
tDH
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
DQ6/DQ2
RY/BY
Data
tBUSY
* : DQ6 stops toggling (the device has completed the Embedded operation).
38
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Back-to-back Read/Write Timing Diagram (Flash)
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
BA2
BA2
(PA)
BA2
(PA)
Address
CEf
BA1
BA1
BA1
(555h)
tACC
tCE
tAS
tAS
tAH
tAHT
tOE
tCEPH
OE
WE
DQ
tDF
tGHWL
tOEH
tWP
tDH
tDS
tDF
Valid
Input
Valid
Output
Valid
Output
Valid
Input
Valid
Output
Status
(A0h)
(PD)
Note: This is an example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
39
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
40
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Temporary Sector Group Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection period
RY/BY
• Acceleration Mode Timing Diagram (Flash)
VCCf
tVACCR
tVCS
tVLHT
VID
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
RY/BY
Acceleration Mode Period
41
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
Address
A0
tVLHT
tVIDR
tWC
tWC
SPAX
SPAX
SPAY
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
60h
40h
01h
tOE
SPAX: Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
42
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ OPERATION (FCRAM)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Read Cycle Time
tRC
tCE
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Access Time
Output Enable Access Time
Chip Enable Access Time
Output Data Hold Time
85
45
85
*1, *3
*1
tOE
tAA
*1, *4
*1
tOH
5
5
0
CE1s Low to Output Low-Z
OE Low to Output Low-Z
CE1s High to Output High-Z
OE High to Output High-Z
Address Setup Time to CE1s Low
tCLZ
*2
tOLZ
*2
tCHZ
tOHZ
tASC
tASO
tASO[ABS]
tAX
30
25
*2
*2
−5
45
10
*5
*3, *6
*7
Address Setup Time to OE
Address Invalid Time
5
*4
CE1s Low to Address Hold Time
OE Low to Address Hold Time
CE1s High to Address Hold Time
OE High to Address Hold Time
CE1s Low to OE Low Delay Time
OE Low to CE1s High Delay Time
CE1s High Pulse Width
tCLAH
tOLAH
tCHAH
tOHAH
tCLOL
tOLCH
tCP
90
45
−5
−5
45
45
20
45
20
*4
*4, *8
1000
1000
*4, *6, *8, *9
*8
tOP
*6, *8, *9
*7
OE High Pulse Width
tOP[ABS]
*1: The output load is 30 pF.
*2: The output load is 5 pF.
*3: The tCE is applicable if OE is brought to Low before CE1s goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
*4: Applicable only to A0 and A1 when both CE1s and OE are kept at Low for the address access.
*5: Applicable if OE is brought to Low before CE1s goes Low.
*6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1s stays Low) , the tOE becomes tOE (Max) + tASO (Min) − tASO (actual) .
*7: The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
*8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
− tCLOL (actual) or tRC (Min) − tOP (actual) .
*9: Maximum value is applicable if CE1s is kept at Low.
43
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE OPERATION (FCRAM)
Value
Parameter
Symbol
Unit
Notes
Min
90
0
Max
Write Cycle Time
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1
*2
*2
Address Setup Time
Address Hold Time
CE1s Write Setup Time
CE1s Write Hold Time
WE Setup Time
tAH
45
0
tCS
1000
1000
tCH
0
tWS
0
WE Hold Time
tWH
0
LBs and UBs Setup Time
LBs and UBs Hold Time
OE Setup Time
tBS
0
tBH
−5
0
tOES
tOEH
tOEH[ABS]
tOHCL
tOHAH
tCW
1000
1000
*3
*3, *4
*5
45
20
−3
−5
60
60
15
15
20
0
OE Hold Time
OE High to CE1s Low Setup Time
OE High to Address Hold Time
CE1s Write Pulse Width
WE Write Pulse Width
*6
*7
*1, *8
*1, *8
*1, *9
*1, *3, *9
tWP
CE1s Write Recovery Time
WE Write Recovery Time
Data Setup Time
tWRC
tWR
1000
tDS
Data Hold Time
tDH
CE1s High Pulse Width
tCP
20
*9
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
*2: New write address is valid from either CE1s or WE that is brought to High.
*3: Maximum value is applicable if CE1s is kept at Low and both WE and OE are kept at High.
*4: The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1s stays Low.
*6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1s Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
*7: Applicable if CE1s stays Low after read operation.
*8: tCW and tWP are applicable if write operation is initiated by CE1s and WE, respectively.
*9: tWRC and tWR are applicable if write operation is terminated by CE1s and WE, respectively.
The tWR (Min) can be ignored if CE1s is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
44
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER DOWN PARAMETER (FCRAM)
Value
Parameter
Symbol
Unit
Note
Min
10
Max
CE2s Low Setup Time for Power Down Entry
CE2s Low Hold Time after Power Down Entry
tCSP
ns
ns
tC2LP
100
CE1s High Hold Time following CE2s High after
Power Down Exit
tCHH
tCHS
350
10
µs
CE1s High Setup Time following CE2s High after
Power Down Exit
ns
• OTHER TIMING PARAMETER (FCRAM)
Value
Parameter
Symbol
Unit
Note
Min
20
Max
CE1s High to OE Invalid Time for Standby Entry
CE1s High to WE Invalid Time for Standby Entry
CE2s Low Hold Time after Power-up
tCHOX
tCHWX
tC2LH
tC2HL
ns
ns
µs
µs
20
*1
*2
*3
50
CE2s High Hold Time after Power-up
50
CE1s High Hold Time following CE2s High after
Power-up
tCHH
350
1
µs
*2
*4
Input Transition Time
tT
25
ns
*1: It may write date into any address location tCHWX is not satisfied.
*2: Must satisfy tCHH (Min) after tC2LH (Min) .
*3: Requires Power Down mode entry and exit after tC2HL.
*4: The Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate
AC specification of some timing parameters.
• AC TEST CONDITIONS (FCRAM)
Parameter
Input High Level
Symbol
VIH
Condition
Value
2.3
0.4
1.3
5
Unit
V
Note
VCCs = 2.7 V to 3.1 V
VCCs = 2.7 V to 3.1 V
VCCs = 2.7 V to 3.1 V
Between VIL and VIH
Input Low Level
VIL
V
Input Timing Measurement Level
Input Transition Time
VREF
tT
V
ns
45
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ Timing #1 (OE Control Access) (FCRAM)
tRC
tRC
Address
CE1s
OE
Address Valid
tCE
Address Valid
tOHAH
tASO
tOHAH
tOLCH
tCLOL
tCE
tOP
tOE
tOHZ
tOH
tOHZ
tASO
tOLZ
tOH
tOLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
• READ Timing #2 (CE1s Control Access) (FCRAM)
tRC
tRC
Address
CE1s
OE
Address Valid
tCE
Address Valid
tCE
tASC
tCHAH
tASC
tCHAH
tCHZ
tOLCH
tCP
tCHZ
tOE
tOH
tCLZ
tCLZ
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
46
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ Timing #3 (Address Access after OE Control Access) (FCRAM)
tRC
tRC
Address
(A19 - A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tAA
Address Valid
tOHAH
tASO
tOLAH
tAX
CE1s
OE
tOHZ
tOE
tOH
tOH
tOLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
• READ Timing #4 (Address Access after CE1s Control Access) (FCRAM)
tRC
tRC
Address
(A19 - A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tAA
Address Valid
tCHAH
tCLAH
tASC
tAX
CE1s
OE
tCHZ
tCE
tOH
tOH
tCLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
47
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #1 (CE1s Control) (FCRAM)
tWC
Address
CE1s
Address Valid
tAH
tAS
tAS
tCW
tWRC
tWS
tWH
tBH
tWS
WE
UBs, LBs
OE
tBS
tBS
tOHCL
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
48
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #2-1 (WE Control, Single Write Operetion) (FCRAM)
tWC
Address Valid
tAH
Address
CE1s
tOHAH
tAS
tAS
tCH
tCP
tOHCL
tCS
tWP
tWR
WE
tBS
tBH
UBs, LBs
OE
tOES
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
49
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #2 (WE Control, Continuous Write Operetion) (FCRAM)
tWC
Address Valid
Address
CE1s
tOHAH
tAS
tAH
tAS
tOHCL
tCS
tWP
tWR
WE
UBs, LBs
OE
tBH
tBS
tBS
tOES
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
50
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ/WRITE Timing #1-1 (CE1s Control) (FCRAM)
tWC
Write Address
tAH
Read Address
Address
CE1s
tCHAH
tASC
tAS
tCP
tWRC
tWS
tCW
tWH
tWS
tWH
tBH
WE
tBS
UBs, LBs
OE
tCLOL
tOHCL
tOLZ
tCLZ
tCHZ
tOH
tDS
tDH
DQ
Read Data Output
Write Data Input
Note : Write address is vaild from either CE1s or WE of the last falling edge.
51
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ/WRITE Timing #1-2 (CE1s Control) (FCRAM)
tRC
Address
CE1s
Read Address
Write Address
tASC
tCHAH
tAS
tWRC
tWRC (Min)
tWH
tCP
tWS
tWH
tWS
WE
tBS
tBH
tCE
UBs, LBs
OE
tOHCL
tCHZ
tOEH
tDH
tCLZ
tOH
DQ
Write Data Input
Read Data Output
Note : tOEH is specified from the time satisfied both tWRC and tWR (Min) .
52
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ (OE Control) /WRITE (WE Control) Timing #2-1 (FCRAM)
tWC
Write Address
tAH
Read Address
Address
CE1s
tOHAH
tAS
tASO
Low
tWR
tWP
WE
tBS
tBH
UBs, LBs
OE
tOEH
tOES
tOHZ
tOH
tDS
tDH
tOLZ
DQ
Read Data Output
Write Data Input
Note : CE1s can be tied to Low for WE and OE controlled operation.
When CE1s is tied to Low, output is exclusively controlled by OE.
53
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ (OE Control) / WRITE (WE Control) Timing #2-2
tRC
Address
CE1s
Read Address Valid
Write Address
tOHAH
tAS
tASO
Low
tWR
WE
tBH
tBS
UBs, LBs
tOES
tOHZ
tOEH
tOE
OE
DQ
tDH
tOLZ
tOH
Write Data Input
Read Data Output
Note : CE1s can be tied to Low for WE and OE controlled operation.
When CE1s is tied to Low, output is exclusively controlled by OE.
54
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER DOWN Timing (FCRAM)
CE1s
tCHS
CE2s
tCSP
tC2LP
tCHH
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
• Standby Entry Timing after Read or Write (FCRAM)
CE1s
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied,
it takes tRC (Min) period from either last address transition of A0 and A1, or CE1s Low to High transition.
55
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER-UP Timing 1 (FCRAM)
CE1s
tCHS
tC2LH
tCHH
CE2s
VCCs
*
VCCs Min
0 V
* : It is recommended to keep CE2s at Low during VCCs power-up.
tC2LH specifies after VCCs reaches specified minimum level.
• POWER-UP Timing 2 (FCRAM)
CE1s
tCHS
tCSP
tC2HL
tC2HL
tC2LP
tCHH
CE2s
VCCs
VCCs Min
0 V
Note : tC2LH specifies from CE2S Low to High transition after VCCS reaches specified minimum level.
CE1s must be brought to High prior to or together with CE2s Low to High transition.
56
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Value
Parameter
Unit
Remarks
Min
—
Typ
1
Max
10
Sector Erase Time
s
Excludes programming time prior to erasure
Word Programming Time
Chip Programming Time
Erase/Program Cycle
—
16
—
—
360
200
—
µs Excludes system-level overhead
—
s
Excludes system-level overhead
100,000
cycle
■ DATA RETENTION CHARACTERISTICS (FCRAM)
Value
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
VCCS Data Retention Supply
Voltage
CE1s = CE2s ≥ VCCs – 0.2 V or,
CE1s = CE2s = VIH
VDR
2.3
—
3.1
V
2.3 V ≤ VCCs ≤ 2.7 V,
VIN = VIH * or VIL
IDR
—
0.5
1
mA
CE1s = CE2s = VIH *, IOUT=0 mA
VCCS Data Retention Supply
Current
2.3 V ≤ VCCs ≤ 2.7 V,
VIN ≤ 0.2 V or VIN ≥ VCCs – 0.2 V,
CE1s = CE2s ≥ VCCs – 0.2 V,
IOUT=0 mA
IDR1
—
0
—
—
70
—
µA
2.7 V ≤ VCCs ≤ 3.1 V
at data retention entry
Data Retention Setup Time
tDRS
ns
2.7 V ≤ VCCs ≤ 3.1 V
after data retention
Data Retention Recovery Time
tDRR
90
—
—
—
—
ns
VCCS Voltage Transition Time
∆V/∆t
—
0.5
V/µs
*: 2.0 V ≤ VIH ≤ VCCs + 0.3 V
57
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Data Retention Timing
tDRS
tDRR
3.1 V
2.7 V
VCCs
∆V/∆t
∆V/∆t
CE2s
CE1s
2.3 V
( )
VCCs ≥ 0.2 V or VIH * Min
0.4 V
VSS
Data Retention Mode
Data bus must be in High-Z at data retention entry.
* : 2.0 V ≤ VIH ≤ VCCS + 3 V
■ PIN CAPACITANCE
Value
Parameter
Symbol
Condition
Unit
Typ
Max
14
Input Capacitance
CIN
COUT
CIN2
CIN3
VIN = 0 V
11
12
pF
pF
pF
pF
Output Capacitance
VOUT = 0 V
VIN = 0 V
VIN = 0 V
16
Control Pin Capacitance
WP/ACC Pin Capacitance
14
16
21.5
26
Note: Test conditions TA = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package are created acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET.
Exception is when autoselect and sector protect function are used. Then the high voltage (VID) can be applied
to RESET.
• Without the high voltage (VID) , sector protection can be achieved by using “Extended Sector Group Protection”
command.
58
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ORDERING INFORMATION
MB84VD2238
X
EJ
-90
-PBS
PACKAGE TYPE
PBS = 71-ball BGA
SPEED OPTION
See Product Selector Guide
Device Revision
Bank Size
6 = 4 Mbit / 28 Mbit
7 = 8 Mbit / 24 Mbit
8 = 16 Mbit / 16 Mbit
DEVICE NUMBER/DESCRIPTION
32 Mega-bit (2 M × 16-bit) Dual Operation Flash Memory
3 V-only Read, Program, and Erase
16 Mega-bit(1M × 16-bit) FCRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2238 = Top sector
84VD2239 = Bottom sector
59
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ APPENDIX
• ISB2s vs. VIN Cycle time
2.5
2.0
1.5
1.0
0.5
0.0
: RT = + 25 °C
: LT = − 30 °C
: HT = + 85 °C
0
200
400
600
VIN cycle time (ns)
800
1000
60
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PACKAGE DIMENSION
71-pin plastic FBGA
(BGA-71P-M02)
8.80(.346)
11.00±0.10(.433±.004)
1.05 ±+00..1105
.041 –+..000046
7.20(.283)
(Mounting height)
(Stand off)
5.60(.220)REF
0.38±0.10
(.015±.004)
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
7.00±0.10
(.276±.004)
REF
0.80
(.031)
M
L K J H G F E D C B A
INDEX-MARK AREA
71-Ø0.45 –+00..0150
71-Ø.018 –+..000024
M
0.08(.003)
0.10(.004)
C
2000 FUJITSU LIMITED B71002S-1c-1
Dimensions in mm (inches).
61
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0111
FUJITSU LIMITED Printed in Japan
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