MB84VD21091EM-70PBS_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

SMCP0.3E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

16M (×8/×16) FLASH MEMORY &

2M (×8/×16) STATIC RAM

MB84VD2108XEM^-70/MB84VD2109XEM^-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.3 V

• High Performance

70 ns maximum access time (Flash)

70 ns maximum access time (SRAM)

• Operating Temperature

–40°C to +85°C

• Package 56-ball BGA

(Continued)

■ PRODUCT LINE UP

Part No.

MB84VD2108XEM/MB84VD2109XEM

+0.3 V

–0.3 V

+0.3V

Supply Voltage(V)

V^CCf= 3.0V

V^CCs= 3.0V

–0.3 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

70

30

70

35

Note: Both V^CCf and V^CCs must be in recommended operation range when either part is being accessed.

■ PACKAGE

56-ball plastic BGA

(BGA-56P-M02)

MB84VD2108XEM/MB84VD2109XEM^-70

(Continued)

— FLASH MEMORY

• Simultaneous Read/Write Operations (Dual Bank)

Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 Write/Erase Cycles

• Sector Erase Architecture

Eight 4 K words and thirty one 32 K words.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD2108XEM: Top sector

MB84VD2109XEM: Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready-Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCWrite Inhibit ≤ 2.5 V

• Hidden ROM (Hi-ROM) Region

64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status

(MB84VD2108XEM:SA37,SA38 MB84VD2109XEM:SA0,SA1)

At V^IH, allows removal of boot sector protection

At V^ACC, program time will reduse by 40%.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function

— SRAM

• Power Dissipation

Operating: 40 mA max.

Standby : 7 µA max.

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.3 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ⁰to DQ⁷), UB (DQ⁸to DQ¹⁵)

2 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

■ PIN ASSIGNMENT

(Top View)

Marking side

B8

C8

D8

E8

F8

G8

A15

N.C.

A16

CIOf

Vss

A7

B7

C7

D7

E7

SA

F7

G7

H7

A11

A12

A13

A14

DQ15/A-1

DQ7

DQ14

A6

A8

B6

C6

A9

D6

E6

F6

G6

H6

A19

A10

DQ6

DQ13

DQ12

DQ5

A5

B5

C5

F5

G5

H5

WE

CE2s

N.C.

DQ4

Vccs

CIOs

INDEX

LAND*1

A4

B4

C4

F4

G4

H4

WP/ACC RESET RY/BY

DQ3

Vccf

DQ11

A3

LB

B3

C3

D3

E3

F3

G3

H3

UB

A18

A17

DQ1

DQ9

DQ10

DQ2

A2

A7

B2

A6

C2

A5

D2

A4

E2

F2

G2

H2

VSS

OE

DQ0

DQ8

B1

A3

C1

A2

D1

A1

E1

A0

F1

G1

CEf

CE1s

*1) There is no solder ball. This land should be open electrically.

(BGA-56P-M02)

(MB84VD2108X/9XEM SMCP0.3E) 3

MB84VD2108XEM/MB84VD2109XEM^-70

■ PIN DESCRIPTION

Pin Name

A¹⁶to A⁰

A¹⁹to A¹⁷, A^-1

SA

Function

Address Inputs (Common)

Address Input (Flash)

Input/Output

I

Address Input (SRAM)

Data Inputs / Outputs (Common)

Chip Enable (Flash)

I

DQ¹⁵to DQ⁰

CEf

I/O

I

CE1s

Chip Enable (SRAM)

CE2s

Chip Enable (SRAM)

OE

Output Enable (Common)

Write Enable (Common)

WE

Ready/Busy Outputs (Flash) Open Drain

Output

RY/BY

O

UB

LB

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

I

I/O Configuration (Flash)

CIOf=V^CCf is Word mode ( ×16),

CIOf=V^SSis Byte mode ( × 8)

CIOf

I

I/O Configuration (SRAM)

CIOs=V^CCs is Word mode ( ×16),

CIOs=V^SSis Byte mode ( × 8)

CIOs

I

Hardware Reset Pin / Sector Protection

Unlock (Flash)

RESET

WP/ACC

N.C.

Write Protect / Acceleration (Flash)

No Internal Connection

I

—

V^SS

Device Ground (Common)

Device Power Supply (Flash)

Device Power Supply (SRAM)

Power

V^CCf

V^CCs

4 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

■ BLOCK DIAGRAM

VCCf

V^SS

A⁰to A19

RY/BY

A⁰to A¹⁹

A–1

WP/ACC

RESET

CEf

16 M bit

Flash Memory

DQ⁰to DQ15/A–1

CIOf

DQ0 to DQ15/A–1

VCCs

VSS

A0 to A16

DQ⁰to DQ¹⁵

2 M bit

SA

LB

Static RAM

UB

WE

OE

CE1s

CE2s

CIOs

(MB84VD2108X/9XEM SMCP0.3E) 5

MB84VD2108XEM/MB84VD2109XEM^-70

■ DEVICE BUS OPERATIONS

Table 1. 1 User Bus Operations (Flash=Word mode; CIOf=V^CCf, SRAM=Word mode; CIOs=V^CCs)

WP/

Operation (1), (3) CEf CE1s CE2s OE WE SA LB UB DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET ACC

(5)

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

Read from Flash

(2)

L

H

X

Write to Flash

L

H

L

H

L

DOUT

High-Z

D^OUT

High-Z

D^IN

Read from SRAM

H

L

H

L

H

X

H

X

H

L

D^IN

Write to SRAM

H

X

L

H

X

L

X

H

L

High-Z

D^IN

H

X

H

High-Z

Temporary Sector

Group

X

V^ID

Unprotection(4)

H

X

L

Flash Hardware

Reset

X

High-Z

X

High-Z

X

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

Notes: 1. Other operations except for indicated this column are inhibited.

2. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

3. Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

4. It is also used for the extended sector group protections.

5. WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V) ; Program time will reduce by 40%.

6 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

Table 1. 2 User Bus Operations (Flash=Word mode; CIOf=V^CCf, SRAM=Byte mode; CIOs=V^SS)

WP/

Operation (1), (3) CEf CE1s CE2s OE WE SA LB UB DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET ACC

(5)

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

X

L

Read from Flash

(2)

L

H

X

L

Write to Flash

L

H

Read from SRAM

Write to SRAM

H

L

H

L

SA

X

D^OUT

D^IN

High-Z

H

X

L

X

Temporary Sector

Group

X

V^ID

X

Unprotection(4)

H

X

L

Flash Hardware

Reset

X

High-Z

X

High-Z

X

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

Notes: 1. Other operations except for indicated this column are inhibited.

2. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

3. Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

4. It is also used for the extended sector group protections.

5. WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V); Program time will reduce by 40%.

(MB84VD2108X/9XEM SMCP0.3E) 7

MB84VD2108XEM/MB84VD2109XEM^-70

Table 1. 3 User Bus Operations (Flash=Byte mode; CIOf=V^SS, SRAM=Byte mode; CIOs=V^SS)

WP/

RESET ACC

(5)

DQ⁰to

DQ7

DQ⁸to

DQ14

Operation (1), (3) CEf CE1s CE2s DQ¹⁵/A^–1OE WE SA LB UB

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

H

X

L

X

L

A^–1

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

X

L

Read from Flash

(2)

L

X

H

X

L

Write to Flash

L

H

Read from SRAM

Write to SRAM

H

X

L

H

L

SA

X

D^OUT

D^IN

High-Z

H

X

L

X

Temporary

Sector

Group

X

V^ID

X

Unprotection(4)

H

X

L

Flash Hardware

Reset

X

High-Z

X

High-Z

X

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

Notes: 1. Other operations except for indicated this column are inhibited.

2. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

3. Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

4. It is also used for the extended sector group protections.

5. WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V); Program time will reduce by 40%.

8 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

–55

–40

Max.

+125

Storage Temperature

Tstg

T^A

°C

V

Ambient Temperature with Power Applied

+85

V^CCf +0.4

V^CCs +0.4

+4.0

Voltage with Respect to Ground All pins

except RESET, WP/ACC (Note 1)

V^IN, V^OUT

–0.3

V

V^CCf/V^CCs Supply (Note 1)

RESET (Note 2)

V^CCf,V^CCs

V^IN

–0.3

–0.5

V

+ 13.0

+10.5

V

WP/ACC (Note 3)

V^IN

V

Notes: 1. Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may

undershoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V^CCf

+0.4 V or V^CCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to V^CCf+2.0 V or

V^CCs+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may

undershoot V^SSto –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage

(VIN-V^CCf or V^CCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which

may overshoot to +14.0 V for periods of up to 20 ns.

3. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may

undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is

+10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when V^CCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min.

–40

Max.

+85

Ambient Temperature

V^CCf/V^CCs Supply Voltages

T^A

°C

V

Vccf, Vccs

+2.7

+3.3

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

(MB84VD2108X/9XEM SMCP0.3E) 9

MB84VD2108XEM/MB84VD2109XEM^-70

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Parameter

Parameter Description

Test Conditions

V^IN= V^SSto V^CCf, V^CCs

Min.

Typ.

Max. Unit

Symbol

I^LI

Input Leakage Current

Output Leakage Current

–1.0

—

+1.0

µA

I^LO

V^OUT= V^SSto V^CCf, V^CCs

RESET Inputs Leakage

Current

V^CCf= V^CCf Max.,V^CCs = V^CCs Max.,

RESET = 12.5V

I^LIT

—

35

µA

t^CYCLE= 5 MHz Byte

—

13

15

7

mA

Flash V^CCActive Current

(Read)

(Note 1)

t^CYCLE= 5 MHz Word

t^CYCLE= 1 MHz Byte

t^CYCLE= 1 MHz Word

CEf = V^IL,

OE = V^IH

I^CC1f

mA

7

Flash V^CCActive Current

(Program/Erase) (Note 2)

I^CC2f

CEf = V^IL, OE = V^IH

—

35

Flash V^CCActive Current

(Read-While-Program)

(Note 5)

Byte

Word

Byte

Word

—

48

50

48

50

I^CC3f

Flash V^CCActive Current

(Read-While-Erase)

(Note 5)

I^CC4f

CEf = V^IL, OE = V^IH

mA

Flash V^CCActive Current

(Erase-Suspend-Program)

I^CC5f

I^LIA

—

35

20

mA

ACC Input Leakage

Current

V^CCf= V^CCf Max.,V^CCs = V^CCs Max.,

WP/ACC = V^ACCMax

V^CCs = V^CCs Max.,

I^CC1s SRAM V^CCActive Current CE1s = V^IL,

CE2s = V^IH

t^CYCLE=10 MHz

—

40

mA

t^CYCLE= 10 MHz

t^CYCLE= 1 MHz

—

40

8

mA

CE1s = 0.2 V,

CE2s = V^CCs – 0.2 V

I^CC2s SRAM V^CCActive Current

V^CCf = V^CCf Max., CEf = V^CCf ± 0.3 V

I^SB1f

Flash V^CCStandby Current RESET = V^CCf ± 0.3 V,

—

1

5

µA

WP/ACC = V^CCf± 0.3 V

Flash V^CCStandby Current V^CCf = V^CCf Max., RESET = V^SS± 0.3 V,

I^SB2f

(RESET)

WP/ACC = V^CCf± 0.3 V

V^CCf = V^CCf Max., CEf = V^SS± 0.3 V

RESET = V^CCf ± 0.3 V,

Flash V^CCCurrent

(Automatic Sleep Mode)

(Note 3)

I^SB3f

—

1

5

µA

WP/ACC = V^CCf± 0.3 V

V^IN= V^CCf± 0.3 V or V^SS± 0.3 V

I^SB1s

SRAM V^CCStandby Current CE1s > V^CCs – 0.2 V, CE2s > V^CCs – 0.2 V

—

7

µA

I^SB2s SRAM V^CCStandby Current CE2s < 0.2 V

(Continued)

10 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

(Continued)

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Typ.

Max. Unit

V^IL

V^IH

Input Low Level

Input High Level

—

–0.3

2.4

—

0.5

V

V^CC+0.3*

Voltage for Sector

Protection, and Temporary

Sector Unprotection

(RESET) (Note 4)

V^ID

—

11.5

8.5

—

12.5

9.5

V

Voltage for Program

Acceleration (WP/ACC)

(Note4)

V^ACC

9.0

V^OL

V^OH

V^OL

V^OH

SRAM Output Low Level

SRAM Output High Level

Flash Output Low Level

Flash Output High Level

V^CCs = V^CCsMin., I^OL=4.0 mA

V^CCs = V^CCsMin., I^OH=–0.5 mA

V^CCf = V^CCfMin., I^OL=4.0 mA

V^CCf = V^CCfMin., I^OH=–0.5 mA

—

2.4

—

0.45

—

V

0.4

—

2.4

Flash Low V^CCf Lock-Out

Voltage

V^LKO

—

2.3

—

2.5

V

Notes: 1. The I^CCcurrent listed includes both the DC operating current and the frequency dependent component.

2. I^CCactive while Embedded Algorithm (program or erase) is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only V^CCf applying.

5. Embedded Alogorithm (program or erase) is in progress. (@5 MHz)

(MB84VD2108X/9XEM SMCP0.3E) 11

MB84VD2108XEM/MB84VD2109XEM^-70

2. AC Characteristics

• CE Timing

Parameter

Symbols

Description

Test Setup

Value

Unit

JEDEC Standard

t^CCR

—

CE Recover Time

—

Min.

0

ns

• Timing Diagram for alternating SRAM to Flash

CEf

tCCR

CE1s

CE2s

tCCR

• Flash Characteristics

Prease refer to “16M Flash Memory for MCP“ part.

• SRAM Characteristics,

Prease refer to “2M SRAM for MCP“ part.

12 (MB84VD2108X/9XEM SMCP0.3E)

SMCP0.1E

16M Flash for MCP

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

• Eight 4 K words, and thirty one 32 K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

Word mode

Byte mode

Bank size 1

Bank size 4 Bank size 3 Bank size 2

0FFFFFH

0FF000H

0FE000H

0FD000H

0FC000H

0FB000H

0FA000H

0F9000H

0F8000H

0F0000H

0E8000H

0E0000H

0D8000H

0D0000H

0C8000H

0C0000H

0B8000H

0B0000H

0A8000H

0A0000H

098000H

090000H

088000H

080000H

078000H

070000H

068000H

060000H

058000H

050000H

048000H

040000H

038000H

030000H

028000H

020000H

018000H

010000H

008000H

000000H

1FFFFFH

1FE000H

1FC000H

1FA000H

1F8000H

1F6000H

1F4000H

1F2000H

1F0000H

1E0000H

1D0000H

1C0000H

1B0000H

1A0000H

190000H

180000H

170000H

160000H

150000H

140000H

130000H

120000H

110000H

100000H

0F0000H

0E0000H

0D0000H

0C0000H

0B0000H

0A0000H

090000H

080000H

070000H

060000H

050000H

040000H

030000H

020000H

010000H

000000H

SA38 : 8KB (4KW)

SA37 : 8KB (4KW)

SA36 : 8KB (4KW)

SA35 : 8KB (4KW)

SA34 : 8KB (4KW)

SA33 : 8KB (4KW)

SA32 : 8KB (4KW)

SA31 : 8KB (4KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 64KB (32KW)

SA6 : 64KB (32KW)

SA5 : 64KB (32KW)

SA4 : 64KB (32KW)

SA3 : 64KB (32KW)

SA2 : 64KB (32KW)

SA1 : 64KB (32KW)

SA0 : 64KB (32KW)

Bank 1

Bank 2

Sector Architecture (Top Boot Block)

(Continued)

(16M Flash for MCP) 1

SMCP0.1E

16M Flash for MCP

(Continued)

Word mode Byte mode

Bank size 1

Bank size 4 Bank size 3 Bank size 2

0FFFFFH

0F8000H

0F0000H

0E8000H

0E0000H

0D8000H

0D0000H

0C8000H

0C0000H

0B8000H

0B0000H

0A8000H

0A0000H

098000H

090000H

088000H

080000H

078000H

070000H

068000H

060000H

058000H

050000H

048000H

040000H

038000H

030000H

028000H

020000H

018000H

010000H

008000H

007000H

006000H

005000H

004000H

003000H

002000H

001000H

000000H

1FFFFFH

1F0000H

1E0000H

1D0000H

1C0000H

1B0000H

1A0000H

190000H

180000H

170000H

160000H

150000H

140000H

130000H

120000H

110000H

100000H

0F0000H

0E0000H

0D0000H

0C0000H

0B0000H

0A0000H

090000H

080000H

070000H

060000H

050000H

040000H

030000H

020000H

010000H

00E000H

00C000H

00A000H

008000H

006000H

004000H

002000H

000000H

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 8KB (4KW)

SA6 : 8KB (4KW)

SA5 : 8KB (4KW)

SA4 : 8KB (4KW)

SA3 : 8KB (4KW)

SA2 : 8KB (4KW)

SA1 : 8KB (4KW)

SA0 : 8KB (4KW)

Bank 2

Bank 1

Sector Architecture (Bottom Boot Block)

2 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Top Boot Block, Bank Size=1)

Sector Address

Bank Address

Address Range

(Byte mode)

Address Range

(Word mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

Bank 2

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1F1FFFH

1F2000H to 1F3FFFH

0F8000H to 0F8FFFH

0F9000H to 0F9FFFH

0

1

0

1

0

1F4000H to 1F5FFFH 0FA000H to 0FAFFFH

1F6000H to 1F7FFFH 0FB000H to 0FBFFFH

1F8000H to 1F9FFFH 0FC000H to 0FCFFFH

1FA000H to 1FBFFFH 0FD000H to 0FDFFFH

1FC000H to 1FDFFFH 0FE000H to 0FEFFFH

1FE000H to 1FFFFFH 0FF000H to 0FFFFFH

0

1

Bank 1

1

0

1

0

1

0

1

(16M Flash for MCP) 3

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Bottom Boot Block, Bank Size=1)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000H to 001FFFH

002000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 009FFFH

00A000H to 00BFFFH

00C000H to 00DFFFH

00E000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 000FFFH

001000H to 001FFFH

002000H to 002FFFH

003000H to 003FFFH

004000H to 004FFFH

005000H to 005FFFH

006000H to 006FFFH

007000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

0

1

SA2

0

1

0

SA3

0

1

Bank 1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

Bank 2

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1FFFFFH

0F8000H to 0FFFFFH

4 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Top Boot Block, Bank Size=2)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

Bank 2

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1F1FFFH

1F2000H to 1F3FFFH

0F8000H to 0F8FFFH

0F9000H to 0F9FFFH

0

1

0

1

0

1F4000H to 1F5FFFH 0FA000H to 0FAFFFH

1F6000H to 1F7FFFH 0FB000H to 0FBFFFH

1F8000H to 1F9FFFH 0FC000H to 0FCFFFH

1FA000H to 1FBFFFH 0FD000H to 0FDFFFH

1FC000H to 1FDFFFH 0FE000H to 0FEFFFH

1FE000H to 1FFFFFH 0FF000H to 0FFFFFH

Bank 1

0

1

0

1

0

1

0

1

(16M Flash for MCP) 5

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Bottom Boot Block, Bank Size=2)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000H to 001FFFH

002000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 009FFFH

00A000H to 00BFFFH

00C000H to 00DFFFH

00E000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 000FFFH

001000H to 001FFFH

002000H to 002FFFH

003000H to 003FFFH

004000H to 004FFFH

005000H to 005FFFH

006000H to 006FFFH

007000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

Bank 1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

Bank 2

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1FFFFFH

0F8000H to 0FFFFFH

6 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Top Boot Block, Bank Size=3)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 2

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1F1FFFH

1F2000H to 1F3FFFH

0F8000H to 0F8FFFH

0F9000H to 0F9FFFH

Bank 1

0

1

0

1

0

1F4000H to 1F5FFFH 0FA000H to 0FAFFFH

1F6000H to 1F7FFFH 0FB000H to 0FBFFFH

1F8000H to 1F9FFFH 0FC000H to 0FCFFFH

1FA000H to 1FBFFFH 0FD000H to 0FDFFFH

1FC000H to 1FDFFFH 0FE000H to 0FEFFFH

1FE000H to 1FFFFFH 0FF000H to 0FFFFFH

0

1

0

1

0

1

0

1

(16M Flash for MCP) 7

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Bottom Boot Block, Bank Size=3)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000H to 001FFFH

002000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 009FFFH

00A000H to 00BFFFH

00C000H to 00DFFFH

00E000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 000FFFH

001000H to 001FFFH

002000H to 002FFFH

003000H to 003FFFH

004000H to 004FFFH

005000H to 005FFFH

006000H to 006FFFH

007000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

Bank 1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

Bank 2

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1FFFFFH

0F8000H to 0FFFFFH

8 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Top Boot Block, Bank Size=4)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA0

SA1

000000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

SA2

SA3

SA4

SA5

SA6

SA7

Bank 2

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

Bank 1

1F0000H to 1F1FFFH

1F2000H to 1F3FFFH

0F8000H to 0F8FFFH

0F9000H to 0F9FFFH

0

1

0

1

0

1F4000H to 1F5FFFH 0FA000H to 0FAFFFH

1F6000H to 1F7FFFH 0FB000H to 0FBFFFH

1F8000H to 1F9FFFH 0FC000H to 0FCFFFH

1FA000H to 1FBFFFH 0FD000H to 0FDFFFH

1FC000H to 1FDFFFH 0FE000H to 0FEFFFH

1FE000H to 1FFFFFH 0FF000H to 0FFFFFH

0

1

0

1

0

1

0

1

(16M Flash for MCP) 9

SMCP0.1E

16M Flash for MCP

Sector Address Tables (Bottom Boot Block, Bank Size=4)

Sector Address

Bank Address

Address Range

(BYTE mode)

Address Range

(WORD mode)

Bank

Sector

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

SA0

SA1

000000H to 001FFFH

002000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 009FFFH

00A000H to 00BFFFH

00C000H to 00DFFFH

00E000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

000000H to 000FFFH

001000H to 001FFFH

002000H to 002FFFH

003000H to 003FFFH

004000H to 004FFFH

005000H to 005FFFH

006000H to 006FFFH

007000H to 007FFFH

008000H to 00FFFFH

010000H to 017FFFH

018000H to 01FFFFH

020000H to 027FFFH

028000H to 02FFFFH

030000H to 037FFFH

038000H to 03FFFFH

040000H to 047FFFH

048000H to 04FFFFH

050000H to 057FFFH

058000H to 05FFFFH

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank 1

0C0000H to 0CFFFFH 060000H to 067FFFH

0D0000H to 0DFFFFH 068000H to 06FFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

070000H to 077FFFH

078000H to 07FFFFH

080000H to 087FFFH

088000H to 08FFFFH

090000H to 097FFFH

098000H to 09FFFFH

0A0000H to 0A7FFFH

0A8000H to 0AFFFFH

0B0000H to 0B7FFFH

0B8000H to 0BFFFFH

Bank 2

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

1F0000H to 1FFFFFH

0F8000H to 0FFFFFH

10 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Sector Group Addresses (Top Boot Block)

Sector Group

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

X

0

1

A¹⁵

0

1

0

1

X

0

1

0

1

A¹⁴

X

0

1

A¹³

X

0

1

0

1

A¹²

X

0

1

0

1

0

1

0

1

Sectors

SA0

SGA0

SGA1

SA1 to SA3

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SGA8

SA28 to SA30

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1

Sector Group Addresses (Bottom Boot Block)

Sector Group

SGA0

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

X

0

A¹⁵

0

1

0

1

X

0

A¹⁴

0

1

X

A¹³

0

1

0

1

X

A¹²

0

1

0

1

0

1

0

1

X

Sectors

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SA8 to SA10

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SGA15

SGA16

0

1

0

1

SA35 to SA37

SA38

(16M Flash for MCP) 11

SMCP0.1E

16M Flash for MCP

Flash Memory Autoselect Codes

Type

A¹²to A¹⁹

A⁶

A¹

A⁰

A^–1*¹

V^IL

X

Code (HEX)

04H

Manufacturer’s Code

X

V^IL

Byte

36H

Top Boot Block

Bank Size=1

X

V^IL

V^IH

V^IL

Word

Byte

2236H

39

V^IL

X

Bottom Boot Block

Bank Size=1

Word

Byte

2239H

2D

V^IL

X

Top Boot Block

Bank Size=2

Word

Byte

222DH

2E

V^IL

X

Bottom Boot Block

Bank Size=2

Word

Byte

222EH

28H

Device

Code

V^IL

X

Top Boot Block

Bank Size=3

Word

Byte

2228H

2BH

V^IL

X

Bottom Boot Block

Bank Size=3

Word

Byte

222BH

33H

V^IL

X

Top Boot Block

Bank Size=4

Word

Byte

2233H

35

V^IL

X

Bottom Boot Block

Bank Size=4

Word

2235H

Sector

Group

Address

01H*²

Sector Group protect

V^IL

*1: A^–1is for Byte mode.

*2: Output 01H at protected sector address and output 00H at unprotected sector address.

12 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

Flash Memory Command Definitions

Fourth Bus

Read/Write

Cycle

Bus

Write

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Command

Sequence

Write Cycle

Write Cycle Write Cycle

Cycles

Req’d

Addr. Data Addr. Data

Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset (Note 1)

1

3

XXXH F0H

—

Word

Byte

555H

AAH

2AAH

555H

AAAH

Read/Reset

(Note 1)

55H

F0H

RA

RD

—

AAAH

(BA)

555H

Word

Byte

555H

AAH

AAAH

2AAH

555H

Autoselect

3

55H

90H

—

(BA)

AAAH

Word

Byte

Word

Byte

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

AAAH

Program

4

6

55H

A0H

80H

PA

PD

—

AAAH

555H

AAH

555H

AAAH

555H

AAAH

2AAH

555H

2AAH

555H

Chip Erase

Sector Erase

AAH

55H

10H

30H

AAAH

555H

AAH

SA

AAAH

Sector Erase

Suspend

1

BA

B0H

30H

—

Sector Erase

Resume

Word

Byte

555H

2AAH

555H

Set to

Fast Mode

3

2

AAH

55H

PD

20H

—

AAAH

Word

Byte

Fast Program

(Note 2)

XXXH A0H

PA

—

Reset from

Fast Mode

(Note 2)

Word

F0H

(Note6)

2

4

BA

90H XXXH

—

Byte

Word

Byte

Extended

Sector Group

Protection

(Note 3)

Query

(Note 4)

XXXH 60H SPA

55H

60H

SPA

—

40H SPA

SD

Word

Byte

1

3

98H

—

AAH

555H

AAAH

555H

Word

Byte

2AAH

555H

2AAH

555H

AAAH

555H

Hi-ROM Entry

AAH

55H

88H

Hi-ROM

Program

(Note 5)

Word

4

6

AAH

55H

A0H

80H

PA

PD

—

Byte

Word

Byte

AAAH

555H

AAAH

555H

2AAH

555H

AAAH

555H

AAAH

Hi-ROM

Erase

(Note 5)

555H

2AAH

555H

AAH

55H HRA 30H

AAAH

(HRBA)

555H

Word

Byte

555H

2AAH

555H

Hi-ROM Exit

(Note 5)

4

AAH

55H

90H XXXH 00H

—

(HRBA)

AAAH

1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

2: This command is valid while Fast Mode.

3: This command is valid while RESET=V^ID.

4: The valid Address is A⁶to A⁰.

5: This command is valid while Hi-ROM mode.

(16M Flash for MCP) 13

SMCP0.1E

16M Flash for MCP

6: The data "00H" is also acceptable.

Address bits A¹²to A¹⁹= X = “H” or “L” for all address commands except for Program Address (PA),

Sector Address (SA),and Bank Address (BA).

Bus operations are defined in Table 2 "User Bus Operations".

RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

BA = Bank address (A¹⁵to A¹⁹)

SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A¹, A⁰) = (0, 1, 0).

HRA= Address of the Hidden-ROM area.

Top Boot Block

Word mode: 0F8000H to 0FFFFFH

Byte mode: 1F0000H to 1FFFFFH

Bottom Boot Block Word mode: 000000H to 007FFFH

Byte mode: 000000H to 00FFFFH

HRBA = Bank address of the Hidden-ROM area.

Top Boot Block

: A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 1

Bottom Boot Block : A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 0

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA.

SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H

at unprotectedsector addresses.

The system should generate the following address patterns;

Word mode: 555H or 2AAH to addresses A¹⁰to A⁰

Byte mode : AAAH or 555H to addresses A¹⁰to A⁰and A^–1

14 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• Read Only Operations Characteristics (Flash)

Parameter

Symbols

Description

Stan-

Value (Note)

Test Setup

Unit

JEDEC

t^AVAV

t^AVQV

Min.

70

Max.

—

dard

t^RC

Read Cycle Time

—

ns

CEf = V^IL

OE = V^IL

t^ACC

Address to Output Delay

—

70

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CEf

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = V^IL

—

70

30

25

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

ns

µs

t^READY

RESET Pin Low to Read Mode

—

20

Note: Test Conditions–Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

(16M Flash for MCP) 15

SMCP0.1E

16M Flash for MCP

• Read Cycle (Flash)

t^RC

Addresses Stable

ADDRESSES

t^ACC

CEf

OE

t^OE

tDF

t^OEH

WE

t^CEf

HIGH-Z

DQ

Output Valid

t^RC

ADDRESSES

Addresses Stable

t^ACC

CEf

t^RH

t^CEf

t^RP

RESET

DQ

t^OH

HIGH-Z

Output Valid

16 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• Erase/Program Operations (Flash)

Parameter

Symbols

Value

Unit

Min. Typ. Max.

Description

Stan-

JEDEC

dard

t^WC

t^AS

t^AVAV

t^AVWL

—

Write Cycle Time

70

0

—

8

—

70

—

90

—

20

ns

µs

sec

µs

ns

µs

Address Setup Time (WE to Addr.)

Address Setup Time to CEf Low During Toggle Bit Polling

Address Hold Time (WE to Addr.)

Address Hold Time from CEf or OE High During Toggle Bit Polling

Data Setup Time

t^ASO

t^AH

t^AHT

t^DS

12

45

0

t^WLAX

—

t^DVWH

t^WHDX

—

30

0

t^DH

Data Hold Time

t^OES

Output Enable Setup Time

0

Read

Output Enable Hold Time

0

—

t^OEH

Toggle and Data Polling

10

20

0

—

t^CEPH

t^OEPH

t^GHEL

t^GHWL

t^WS

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

—

t^GHEL

t^GHWL

t^WLEL

t^ELWL

t^EHWH

t^WHEH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

0

t^CS

0

t^WH

0

t^CH

0

t^WP

35

25

—

50

4

t^CP

CEf Pulse Width

t^WPH

t^CPH

Write Pulse Width High

CEf Pulse Width High

Byte Programming Operation

Word Programming Operation

Sector Erase Operation (Note 1)

V^CCf Setup Time

t^WHWH1

16

1

t^WHWH2

—

t^WHWH2

t^VCS

—

t^VLHT

t^VIDR

t^VACCR

t^RB

Voltage Transition Time (Note 2)

Rise Time to V^ID(Note 2)

—

500

0

—

Rise Time to V^ACC

—

Recover Time from RY/BY

—

t^RP

RESET Pulse Width

500

—

200

—

50

—

t^EOE

t^RH

Delay Time from Embedded Output Enable

RESET Hold Time Before Read

Program/Erase Valid to RY/BY Delay

Erase Time-out Time (Note 3)

Erase Suspend Transition Time (Note 4)

—

t^BUSY

t^TOW

t^SPD

—

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Protection Operation.

3. The time between writes must be less than "t^TOW" otherwise that command will not be accepted and

erasure will start. A time-out or "t^TOW" from the rising edge of last CEf or WE whichever happens first will

initiate the execution of the Sector Erase command(s).

4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a

maximum of "t^SPD" to suspend the erase operation.

(16M Flash for MCP) 17

SMCP0.1E

16M Flash for MCP

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555H

t^WC

PA

ADDRESSES

t^RC

t^AS

t^AH

CEf

t^CH

t^CS

t^CEf

OE

t^GHWL

t^OE

t^WHWH1

t^WP

t^WPH

WE

t^OH

t^DS

t^DH

PD

D^OUT

A0H

DQ⁷

DQ

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

18 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

PA

ADDRESSES

PA

555H

t^WC

t^AH

t^AS

WE

t^WS

t^WH

OE

t^GHEL

t^WHWH1

t^CP

t^CPH

CEf

t^DS

t^DH

PD

D^OUT

DQ⁷

A0H

DQ

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

(16M Flash for MCP) 19

SMCP0.1E

16M Flash for MCP

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA^*1

555H

t^WC

2AAH

t^AS

555H

2AAH

ADDRESSES

t^AH

CEf

t^CS

t^CH

OE

t^WP

t^WPH

t^GHWL

WE

t^DS

t^DH

30H for Sector Erase

10H/

30H

AAH

55H

80H

55H

DQ

t^VCS

V^CCf

Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.

2. These waveform are for the ×16 mode. (The addresses differ from ×8 mode.)

20 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

t^CH

t^DF

t^OE

OE

t^OEH

WE

t^CEf

*

High-Z

DQ⁷=

Data In

DQ⁷

Valid Data

t^{WHWH1 or 2}

DQ

(DQ⁶to DQ⁰)

DQ⁶to DQ⁰

Valid Data

DQ⁶to DQ⁰= Output Flag

t^BUSY

t^EOE

RY/BY

*DQ⁷= Valid Data (The device has completed the Embedded operation.)

(16M Flash for MCP) 21

SMCP0.1E

16M Flash for MCP

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

ADDRESSES

t^AHT

t^ASO

t^AHT

t^AS

CEf

t^CEPH

WE

OE

t^OEH

t^OEPH

*

t^OE

t^CEf

t^DH

Toggle

Data

Toggle

Data

Toggle

Data

Stop

Toggling

Output

Valid

DQ⁶/DQ²

RY/BY

Data

t^BUSY

* : DQ⁶stops toggling (The device has completed the Embedded operation).

22 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• Back-to-back Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

CEf

tOE

tCEPH

OE

OEf

tDF

tGHWL

tOEH

tWP

tDS

WE

WEf

tDH

tDF

Valid

Output

Valid

Output

Valid

DQ

Status

Intput

Output

(A0h)

(PD)

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.

BA2: Address of Bank 2.

(16M Flash for MCP) 23

SMCP0.1E

16M Flash for MCP

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

The rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

t^BUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

RY/BY

t^RP

t^RB

t^READY

24 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

• Temporary Sector Unprotection (Flash)

VCCf

t^VIDR

t^VCS

t^VLHT

VID

VIH

RESET

CEf

WE

t^VLHT

Program or Erase Command Sequence

RY/BY

Unprotection period

• Acceleration Mode Timing Diagram (Flash)

V^CCf

t^VACCR

t^VCS

t^VLHT

V^ACC

V^IH

WP/ACC

CEf

WE

t^VLHT

RY/BY

Acceleration Mode Period

(16M Flash for MCP) 25

SMCP0.1E

16M Flash for MCP

• Extended Sector Protection (Flash)

V^CCf

t^VCS

RESET

Add

t^VLHT

t^VIDR

t^WC

SGAx

SGAy

A⁰

A¹

A⁶

CEf

OE

TIME-OUT

t^WP

WE

Data

60H

40H

01H

60H

t^OE

SGAx : Sector Group Address to be protected

SGAy : Next Group Sector Address to be protected

TIME-OUT : Time-Out window = 250 µs (min)

26 (16M Flash for MCP)

SMCP0.1E

16M Flash for MCP

■ ERASE AND PROGRAMMING PERFORMANCE (Flash)

Limits

Parameter

Unit

Comment

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

sec

µs

Excludes system-level

overhead

Byte Programming Time

Word Programming Time

—

8

300

360

Excludes system-level

overhead

16

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

50

—

sec

100,000

cycles

(16M Flash for MCP) 27

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Read Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min.

70

—

5

Max.

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

70

35

70

—

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

t^CO1

t^CO2

t^OE

LB, UB to Output Valid

t^BA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

UB, LB Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

UB, LB Output Enable to Output High-Z

Output Data Hold Time

t^COE

t^OEE

t^BE

0

—

0

—

t^OD

—

10

25

—

t^ODO

t^BD

t^OH

Note: Test Conditions– Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCs

Timing measurement reference level

Input: 0.5×V^CCs

Output: 0.5×V^CCs

(2M SRAM x8x16 -70 for MCP) 1

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Read Cycle (Note 1) (SRAM)

tRC

Address

tAA

tOH

t^CO1

CE1s

tCOE

tCO2

tOD

CE2s

t^OD

tOE

OE

tODO

tOEE

LB, UB

t^BA

t^BD

tBE

t^COE

DQ

Valid Data Out

Note : WE remains “H” for the read cycle.

2 (2M SRAMx8x16 -70 for MCP)

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min

70

50

55

0

Max

—

25

—

Write Cycle Time

t^WC

t^WP

t^CW

t^AW

t^BW

t^AS

ns

Write Pulse Width

Chip Enable to End of Write

Address valid to End of Write

UB, LB to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

t^ODW

t^OEW

t^DS

0

—

0

30

0

Data Hold Time

t^DH

(2M SRAM x8x16 -70 for MCP) 3

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Write Cycle(Note 3) (WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

CE1s

CE2s

tAW

t^CW

tCW

tBW

LB, UB

tOEW

t^ODW

D^OUT

Note 1

Note 4

Note 2

Note 4

tDS

tDH

D^IN

Valid Data In

Notes: 1.If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will

remain at High-Z.

2.If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will

remain at High-Z.

3.If OE is “H” during the write cycle, the outputs will remain at High-Z.

4.Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

4 (2M SRAMx8x16 -70 for MCP)

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Write Cycle (Note 1) (CE1s control) (SRAM)

tWC

Address

t^AS

tWP

tWR

WE

tAW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

tBE

t^ODW

t^COE

D^OUT

t^DS

t^DH

DIN

Note 2

Valid Data In

Notes: 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.

2. Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

(2M SRAM x8x16 -70 for MCP) 5

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Write Cycle (Note 1) (CE2s Control) (SRAM)

tWC

Address

WE

t^AS

tWP

tWR

tCW

CE1s

CE2s

tAW

tCW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

Note 2

Valid Data In

Notes: 1.If OE is “H” during the write cycle, the outputs will remain at High-Z.

2.Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

6 (2M SRAMx8x16 -70 for MCP)

SMCP0.1E

2M SRAM(x8,x16) for MCP

• Write Cycle (Note 1) (LB, UB Control) (SRAM)

tWC

Address

WE

tWP

t^WR

tCW

CE1s

CE2s

tCW

tAW

t^AS

t^BW

LB, UB

tBE

t^COE

t^ODW

D^OUT

t^DS

t^DH

Note 2

Valid Data In

D^IN

Notes: 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.

2. Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

(2M SRAM x8x16 -70 for MCP) 7

SMCP0.1E

2M SRAM(x8,x16) for MCP

■ DATA RETENTION CHARACTERISTICS (SRAM)

Value

Typ.

—

Parameter

Symbol

Unit

Min.

1.5

—

Max.

3.3

4

Data Retention Supply Voltage

V^DH

I^DDS2

t^CDR

t^R

V

Standby Current

V^DH= 1.5 V

1

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

0

—

t^RC

—

Note: t^RC: Read cycle time

• CE1s Controlled Data Retention Mode (Note 1)

V^CCs

DATA RETENTION MODE

2.7 V

See Note 2

V^IH

V^DH

V^CCS–0.2 V

CE1s

tCDR

t^R

GND

• CE2s Controlled Data Retention Mode (Note 3)

V^CCs

DATA RETENTION MODE

2.7 V

V^DH

V^IH

CE2s

t^CDR

t^R

V^IL

0.2 V

GND

8 (2M SRAMx8x16 -70 for MCP)

SMCP0.1E

2M SRAM(x8,x16) for MCP

Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss

to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to

Vccs+0.3 V.

2. When CE1s is operating at the V^IHMin. level (2.2 V), the standby current is given by I^SB1s during the

transition of V^CCs from 3.6 to 2.2 V.

3. In CE2s controlled data retention mode, input and input/output pins can be used between

–0.3 V to Vccs+0.3 V.

(2M SRAM x8x16 -70 for MCP) 9

MB84VD2108XEM/MB84VD2109XEM^-70

■ PIN CAPACITANCE

Parameter

Parameter Description

Test Setup

V^IN= 0

Typ.

Max.

Unit

Symbol

C^IN

Input Capacitance

11

12

14

17

14

16

20

pF

C^OUT

C^IN2

Output Capacitance

V^OUT= 0

V^IN= 0

Control Pin Capacitance

WP/ACC Pin Capacitance

C^IN3

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (V^ID) cannot apply to address pins and control pins except RESET.

Exception is when autoselect and sector group protect function are used, then the high voltage (V^ID) can be

applied to RESET.

• Without the high voltage (V^ID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

(MB84VD2108X/9XEM SMCP0.3E) 13

MB84VD2108XEM/MB84VD2109XEM^-70

■ ORDERING INFORMATION

MB84VD2108

X

EM

-70

PBS

PACKAGE TYPE

PBS = 56-ball BGA

SPEED OPTION

See Product Selector Guide

Device Revision (Valid Combination)

EM

Bank Size

1 = 0.5Mbit / 15.5Mbit

2 = 2Mbit / 14Mbit

3 = 4Mbit / 12Mbit

4 = 8Mbit / 8Mbit

DEVICE NUMBER/DESCRIPTION

16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

2Mega-bit (256k × 8-bit or 128K × 16-bit) SRAM

BOOT CODE SECTOR ARCHITECTURE

84VD2108 = Top sector

84VD2109 = Bottom sector

14 (MB84VD2108X/9XEM SMCP0.3E)

MB84VD2108XEM/MB84VD2109XEM^-70

■ PACKAGE DIMENSIONS

56-pin plastic FBGA

(BGA-56P-M02)

Now Printing

Dimension in mm.

(MB84VD2108X/9XEM SMCP0.3E) 15

MB84VD2108XEM/MB84VD2109XEM^-70

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Electronic Devices

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Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

The products described in this document are designed, and

manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use,

and household use, but are not designed, developed and

manufactured as contemplated (1) for use accompanying fatal risks

or dangers that, unless extremely high safety is secured, could have

a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

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Tel: +49-6103-690-0

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Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

http://www.fujitsu-fme.com/

Asia Pacific

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

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Korea

FUJITSU MICROELECTRONICS KOREA LTD.

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Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0207

FUJITSU LIMITED Printed in Japan

16 (MB84VD2108X/9XEM SMCP0.3E)


型号：	MB84VD21091EM-70PBS
厂家：	FUJITSU
描述：	Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA56, PLASTIC, BGA-56 静态存储器内存集成电路
文件：	总53页 (文件大小：762K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB84VD21091EM-70PBS [FUJITSU]

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