MB84VD2002_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50110-1E

MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

8M (× 8/× 16) FLASH MEMORY &

2M (× 8) STATIC RAM

MB84VD2002^-10/MB84VD2003^-10

■ FEATURES

• Power supply voltage of 2.7 to 3.6 V

• High performance

100 ns maximum access time

• Operating Temperature

–20 to +85°C

— FLASH MEMORY

• Simultaneous operations Read-while Erase or Read-while-Program

• Minimum 100,000 write/erase cycles

• Sector erase architecture

Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD2002: Top sector

MB84VD2003: Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready-Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to "MBM29DL800TA/BA" data sheet in detailed function

— SRAM

• Power dissipation

Operating: 35 mA max.

Standby : 50 µA max.

• Power down features using CE1s and CE2s

• Data retention supply voltage: 2.0 V to 3.6 V

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

MB84VD2002^-10/MB84VD2003^-10

■ BLOCK DIAGRAM

V^CCf

V^SS

A⁰to A¹⁸

RY/BY

A⁰to A¹⁸

DQ⁸to DQ¹⁵

A^-1

RESET

CEf

8 M bit

Flash Memory

BYTE

DQ⁰to DQ⁷

V^CCs

V^SS

A⁰to A¹⁶

2 M bit

Static RAM

SA

WE

OE

CE1s

CE2s

■ EXAMPLE OF CONNECTION WITH CHIPSET

V^CC

A[1:19]

A0

A[0:19]

V^CCf

A[0:18]

SA

BYTE

RESET

RY/BY

ROM_CS/

RAM_CS/

CEf

CE1s

Battery

Backup

Control

V^CCs

CE2s

BATTERY BACKUP

HWR/

LWR/

RD/

WE

OE

D[0:15]

DQ[0:15]

CHIPSET

MB84VD2002/3

2

MB84VD2002^-10/MB84VD2003^-10

■ PIN ASSIGNMENTS

(Top View)

A

B

C

D

E

F

G

H

6

5

4

3

2

1

CE1s

A¹⁰

V^SS

DQ⁵

DQ⁷

A⁸

DQ¹

DQ²

DQ⁴

A⁵

A¹

A²

A⁴

CE2s

RY/BY

A⁹

A¹⁴

A⁰

A³

A⁷

OE

A¹¹

DQ⁰

DQ⁸

CEf

V^SS

A⁶

A¹⁸

DQ¹²

V^CCf

DQ¹¹

RESET A¹⁵

DQ³

DQ¹⁰

DQ⁹

A¹²

BYTE

A¹³

A¹⁷

V^CCs

SA*

A¹⁶

DQ⁶

DQ¹³

DQ¹⁵/A^-1

DQ¹⁴

WE

*: A¹⁷for SRAM

Table 1 Pin Configuration

Function

Input/

Output

A⁰to A¹⁶

A^-1, A¹⁷to A¹⁸

SA

Address Inputs (Common)

Address Input (Flash)

I

Address Input (SRAM)

I

DQ⁰to DQ⁷

DQ⁸to DQ¹⁵

CEf

Data Inputs/Outputs (Common)

Data Inputs/Outputs (Flash)

Chip Enable (Flash)

I/O

I

CE1s

Chip Enable (SRAM)

I

CE2s

Chip Enable (SRAM)

I

OE

Output Enable (Common)

Write Enable (Common)

Ready/Busy Outputs (Flash)

Selects 8-bit or 16-bit mode (Flash)

I

WE

I

RY/BY

BYTE

RESET

N.C.

O

I

Hardware Reset Pin/Sector Protection Unlock (Flash)

No Internal Connection

I

—

V^SS

Device Ground (Common)

Power

V^CCf

Device Power Supply (Flash)

V^CCs

Device Power Supply (SRAM)

3

MB84VD2002^-10/MB84VD2003^-10

■ PRODUCT LINE UP

Flash Memory

SRAM

+0.6 V

Ordering Part No.

MB84VD2002-10/MB84VD2003-10

V^CC= 3.0 V

–0.3 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

100

40

100

50

■ BUS OPERATIONS

Table 2 User Bus Operations (BYTE=V^IL)

Operation (1), (3)

Full Standby

CEf

CE1s CE2s

OE

X

WE

X

DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET

H

X

H

X

H

X

L

X

L

H

X

L

HIGH-Z

D^OUT

HIGH-Z

H

Output Disable

X

L

H

Read from Flash (2)

L

H

X

L

Write to Flash

L

H

L

D^IN

HIGH-Z

H

Read from SRAM

Write to SRAM

H

X

L

H

L

D^OUT

D^IN

HIGH-Z

H

L

X

H

X

Flash Hardware Reset

X

HIGH-Z

L

Table 3 User Bus Operations (BYTE=V^IH)

Operation (1), (3)

Full Standby

CEf

CE1s CE2s

OE

WE

DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET

H

X

H

X

H

X

L

X

L

H

X

HIGH-Z

D^OUT

HIGH-Z

D^OUT

H

Output Disable

X

L

H

Read from Flash (2)

L

H

X

L

Write to Flash

L

H

L

D^IN

H

Read from SRAM

Write to SRAM

H

X

L

H

L

D^OUT

D^IN

HIGH-Z

H

L

X

H

X

Flash Hardware Reset

X

HIGH-Z

L

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

Notes: 1. Other operations except for indicated this column are inhibited.

2. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

4. Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

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MB84VD2002^-10/MB84VD2003^-10

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

• Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.

• Individual-sector, multiple-sector, or bulk-erase capability.

(×8)

(×16)

(×8)

(×16)

FFFFFH 7FFFFH

FC000H 7E000H

F4000H 7A000H

F2000H 79000H

F0000H 78000H

EE000H 77000H

EC000H 76000H

E4000H 72000H Bank 2

E0000H 70000H

D0000H 68000H

C0000H 60000H

B0000H 58000H

A0000H 50000H

90000H 48000H

80000H 40000H

70000H 38000H

60000H 30000H

50000H 28000H

40000H 20000H Bank 1

30000H 18000H

20000H 10000H

10000H 08000H

00000H 00000H

FFFFFH 7FFFFH

F0000H 78000H

E0000H 70000H

D0000H 68000H

C0000H 60000H

B0000H 58000H

A0000H 50000H

90000H 48000H

80000H 40000H

70000H 38000H

60000H 30000H

50000H 28000H

40000H 20000H

30000H 18000H

20000H 10000H

1C000H 0C000H

14000H 0A000H

12000H 09000H

10000H 08000H

0E000H 07000H

0C000H 06000H

04000H 02000H

00000H 00000H

16K byte/8K word

32K byte/16K word

8K byte/4K word

64K byte/32K word

16K byte/8K word

32K byte/16K word

8K byte/4K word

Bank 1

8K byte/4K word

32K byte/16K word

16K byte/8K word

64K byte/32K word

Bank 2

8K byte/4K word

32K byte/16K word

16K byte/8K word

MBM29DL800TA Sector Architecture

MB84VD2002 Sector Architecture

MBM29DL800BA Sector Architecture

MB84VD2003 Sector Architecture

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MB84VD2002^-10/MB84VD2003^-10

Table 4 Sector Address Tables (MB84DV2002)

Sector Address

Sector Size

Address

Bank

(×8)

(×16)

Address Range

Bank Sector

(Kbytes/

Kwords)

Address Range

A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA0

SA1

SA2

SA3

SA4

SA5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

0

64/32

16/8

00000H to 0FFFFH 00000H to 07FFFH

10000H to 1FFFFH 08000H to 0FFFFH

20000H to 2FFFFH 10000H to 17FFFH

30000H to 3FFFFH 18000H to 1FFFFH

40000H to 4FFFFH 20000H to 27FFFH

50000H to 5FFFFH 28000H to 2FFFFH

60000H to 6FFFFH 30000H to 37FFFH

70000H to 7FFFFH 38000H to 3FFFFH

80000H to 8FFFFH 40000H to 47FFFH

90000H to 9FFFFH 48000H to 4FFFFH

A0000H to AFFFFH 50000H to 57FFFH

B0000H to BFFFFH 58000H to 5FFFFH

C0000H to CFFFFH 60000H to 67FFFH

D0000H to DFFFFH 68000H to 6FFFFH

E0000H to E3FFFH 70000H to 71FFFH

SA6

Bank 2

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

0

1

E4000H to E7FFFH, 72000H to 73FFFH,

E8000H to EBFFFH 74000H to 75FFFH

SA15

1

0

32/16

1

0

SA16

1

0

1

8/4

EC000H to EDFFFH 76000H to 76FFFH

EE000H to EFFFFH 77000H to 77FFFH

F0000H to F1FFFH 78000H to 78FFFH

F2000H to F3FFFH 79000H to 79FFFH

SA17

Bank 1

1

SA18

0

SA19

SA20

SA21

0

1

0

1

X

F4000H to F7FFFH, 7A000H to 7BFFFH,

F8000H to FBFFFH 7C000H to 7DFFFH

1

32/16

16/8

1

0

1

FC000H to FFFFFH 7E000H to 7FFFFH

Note:The address range is A¹⁸: A^-1if in byte mode (BYTE = V^IL). The address range is A¹⁸: A⁰if in word mode (BYTE

= V^IH).

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MB84VD2002^-10/MB84VD2003^-10

Table 5 Sector Address Tables (MB84DV2003)

Sector Address

Sector Size

Address

Bank

(×8)

(×16)

Address Range

Bank Sector

(Kbytes/

Kwords)

Address Range

A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA21

SA20

SA19

SA18

SA17

SA16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

X

1

X

1

64/32

16/8

F0000H to FFFFFH 78000H to 7FFFFH

E0000H to EFFFFH 70000H to 77FFFH

D0000H to DFFFFH 68000H to 6FFFFH

C0000H to CFFFFH 60000H to 67FFFH

B0000H to BFFFFH 58000H to 5FFFFH

A0000H to AFFFFH 50000H to 57FFFH

90000H to 9FFFFH 48000H to 4FFFFH

80000H to 8FFFFH 40000H to 47FFFH

70000H to 7FFFFH 38000H to 3FFFFH

60000H to 6FFFFH 30000H to 37FFFH

50000H to 5FFFFH 28000H to 2FFFFH

40000H to 4FFFFH 20000H to 27FFFH

30000H to 3FFFFH 18000H to 1FFFFH

20000H to 2FFFFH 10000H to 17FFFH

1C000H to 1FFFFH 0E000H to 0FFFFH

SA15

Bank 2

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA7

1

0

14000H to 17FFFH, 0A000H to 0BFFFH,

18000H to 1BFFFH 0C000H to 0DFFFH

SA6

0

1

32/16

0

1

SA5

0

1

0

8/4

12000H to 13FFFH 09000H to 09FFFH

10000H to 11FFFH 08000H to 08FFFH

0E000H to 0FFFFH 07000H to 07FFFH

0C000H to 0DFFFH 06000H to 06FFFH

SA4

Bank 1

0

SA3

1

SA2

SA1

SA0

1

0

1

0

X

08000H to 0BFFFH, 04000H to 05FFFH,

04000H to 07FFFH 02000H to 03FFFH

0

32/16

16/8

0

1

0

00000H to 03FFFH 00000H to 01FFFH

Note: The address range is A¹⁸: A^-1if in byte mode (BYTE = V^IL). The address range is A¹⁸: A⁰if in word mode

(BYTE = V^IH).

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MB84VD2002^-10/MB84VD2003^-10

Table 6. 1 Flash Memory Autoselect Codes

*1

Type

Manufacturer’s Code

A⁶

A¹

A⁰

A_-1

Code (HEX)

04H

V^IL

X

Byte

Word

Byte

4AH

MB84VD2002

MB84VD2003

V^IL

V^IH

224AH

CBH

Device Code

V^IL

X

Word

22CBH

*1: A^-1is for Byte mode.

Table 6. 2 Expanded Autoselect Code Table

Code DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

04H A^-1/0

0

1

0

Manufacturer’s Code

MB84VD2002 (B)

4AH

A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

0

1

0

1

0

1

0

1

0

1

0

224AH

(W)

Device

Code

MB84VD2003 (B)

(W)

CBH

A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

1

0

1

0

1

0

1

0

1

0

22CBH

(B): Byte mode

(W): Word mode

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MB84VD2002^-10/MB84VD2003^-10

Table 7 Flash Memory Command Definitions

Fourth Bus

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req’d

Read/Write

Cycle

Command

Sequence

Write Cycle Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Read/Reset

1

3

XXXH F0H

—

Byte

Word

Byte

555H

AAH

2AAH

555H

55H

F0H

RA

RD

AAAH

(BA)

555H

Word

Byte

555H

AAH

AAAH

2AAH

555H

Autoselect

3

55H

90H

—

(BA)

AAAH

Word

Byte

Word

Byte

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

—

555H

AAAH

555H

AAAH

555H

AAAH

—

Program

4

6

55H

A0H

80H

PA

PD

—

AAAH

555H

AAH

555H

AAAH

555H

AAAH

—

2AAH

555H

2AAH

555H

—

555H

Chip Erase

Sector Erase

AAH

55H

10H

30H

AAAH

555H

AAH

SA

AAAH

Erase Suspend

Erase Resume

1

BA

B0H

30H

—

Word

555H

AAAH

XXXH

BA

2AAH

555H

AAAH

Set to

3

2

4

AAH

A0H

90H

55H

PD

20H

—

Fast Mode

Byte

Word

Byte

Word

Byte

Word

Byte

Fast

Program *

PA

—

XXXH

Reset from

Fast Mode *

F0H

—

BA

Extended

Sector

Protect

XXXH 60H SPA 60H SPA 40H SPA SD

Notes: 1. Address bits A¹¹to A¹⁸= X = “H” or “L” for all address commands except or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

2. Bus operations are defined in Tables 2 and 3.

3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

BA = Bank Address (A¹⁶to A¹⁸)

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. SPA =Sector address to be protected. Set sector address (SA) and (A⁶, A¹, A⁰) = (0, 1, 0).

SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at

unprotected sector addresses.

* : This command is valid while Fast Mode.

9

MB84VD2002^-10/MB84VD2003^-10

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature ..................................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ..................................................................–25°C to +85°C

Voltage with Respect to Ground All pins (Note)..........................................................–0.3 V to V^CCf +0.5 V

–0.3 V to V^CCs +0.5 V

V^CCf/V^CCs Supply (Note) ..............................................................................................–0.3 V to +4.6 V

Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negativeovershoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V^CCf +0.5 V or V^CCs

+0.5 V. During voltage transitions, outputs may positive overshoot to V^CC+2.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Commercial Devices

Ambient Temperature (T^A) .........................................................................–20°C to +85°C

V^CCf/V^CCs Supply Voltages.........................................................................+2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

10

MB84VD2002^-10/MB84VD2003^-10

■ DC CHARACTERISTICS

Parameter

Parameter Description

Test Conditions

Min.

Typ.

Max. Unit

Symbol

I^LI

Input Leakage Current

Output Leakage Current

—

–1.0

—

+1.0

18

µA

I^LO

—

Byte

t^CYCLE= 10 MHz

V^CCf = V^CCMax.,

CEf = V^IL

OE = V^IH

Word

Byte

—

20

Flash V^CCActive Current

(Read)

I^CC1f

mA

—

8

t^CYCLE= 5 MHz

Word

—

10

Flash V^CCActive Current

(Program/Erase)

I^CC2f

V^CCf = V^CCMax., CEf = V^IL, OE = V^IH

—

35

mA

Byte

CE = V^IL,OE = V^IH

—

45

Flash V^CCActive Current

(Read-While-Program)

I^CC3f***

Word

Byte

CE = V^IL,OE = V^IH

Flash V^CCActive Current

(Read-While-Erase)

I^CC4f***

mA

Word

Flash V^CCActive Current

(Erase-Suspend-

Program)

I^CC5f

CE = V^IL,OE = V^IH

—

35

t^CYCLE=10 MHz

—

40

12

35

mA

SRAM V^CCActive

Current

V^CCs = V^CCMax.,

I^CC1s

I^CC2s

CE1s = V^IL, CE2s = V^IH

t^CYCLE= 1 MHz

t^CYCLE= 10 MHz

CE1s = 0.2 V,

CE2s = V^CCs – 0.2 V,

WE = V^CCs – 0.2 V

SRAM V^CCActive

Current

t^CYCLE= 1 MHz

—

6

5

mA

Flash V^CCStandby

Current

V^CCf = V^CCMax., CEf = V^CCf ± 0.3 V

RESET = V^CCf ± 0.3 V

I^SB1f

I^SB2f

I^SB1s

µA

Flash V^CCStandby

Current (RESET)

V^CCf = V^CCMax., RESET = V^SS± 0.3 V

CE1s = V^IHor CE2s = V^IL

—

5

µA

SRAM V^CCStandby

Current

—

1

2

mA

V^CCs T^A= 25°C

= 3.0

2.5

µA

T^A= –20 to

V

—

55

3

µA

+85°C

±10%

V^CCs T^A= 25°C

= 3.3

1.5

V

±0.3

V

T^A= –20 to

+85°C

SRAM V^CCStandby

Current

CE1s = V^CC–0.2

V or CE2s = 0.2 V

—

60

µA

I^SB2s**

T^A= 25°C

—

1

2

5

µA

V^CCs T^A= –20 to

= 3.0 +40°C

—

V

T^A= –20 to

+85°C

—

50

µA

V^IL

V^IH

Input Low Level

Input High Level

—

–0.3

2.2

—

0.6

V

V^CC+0.3*

Output Low Voltage

Level

I^OL= 2.1 mA,

V^OL

V^OH

V^LKO

—

V^CC– 0.5

2.3

—

0.4

—

V

V^CCf = V^CCs = V^CCMin.

Output High Voltage

Level

I^OH= –500 µA,

V^CCf = V^CCs = V^CCMin.

Flash Low V^CCLock-Out

Voltage

—

2.5

* : V^CCindicate lower of V^CCf or V^CCs

** :During standby mode with CE1s = V^CCS– 0.2 V, CE2s should be CE2s < 0.2V or CE2s > V^CCS– 0.2V

*** :Embeded Algorithm (program or erase) is in progress. (@5 MHz)

11

MB84VD2002^-10/MB84VD2003^-10

■ AC CHARACTERISTICS

• CE Timing

Parameter

Symbols

Description

Test Setup

-10

Unit

JEDEC Standard

—

t^CCR

CE Recover Time

—

Min.

0

ns

• Timing Diagram for alternating SRAM to Flash

CEf

t^CCR

CE1s

CE2s

t^CCR

• Read Only Operations Characteristics (Flash)

Parameter

-10

(Note)

Symbols

Test

Setup

Description

Unit

JEDEC Standard

Min.

Max.

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

100

—

ns

CEf = V^IL

OE = V^IL

t^ACC

Address to Output Delay

100

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CEf

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = V^IL

—

100

40

ns

—

30

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

20

5

ns

µs

ns

t^READY

RESET Pin Low to Read Mode

—

t^ELFL

t^ELFH

—

CE or BYTE Switching Low or High

Note: Test Conditions–Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

12

MB84VD2002^-10/MB84VD2003^-10

• Read Cycle (Flash)

t^RC

Addresses Stable

ADDRESSES

t^ACC

CEf

OE

t^OE

t^DF

t^OEH

WE

DQ

t^CE

HIGH-Z

Output Valid

t^RC

ADDRESSES

Addresses Stable

t^ACC

t^RH

RESET

DQ

t^OH

HIGH-Z

Output Valid

13

MB84VD2002^-10/MB84VD2003^-10

• Erase/Program Operations (Flash)

Parameter Symbols

Description

-10

Unit

JEDEC

t^AVAV

Standard

Min. Typ. Max.

t^WC

t^AS

Write Cycle Time

100

0

—

ns

t^AVWL

Address Setup Time (WE to Addr.)

Address Setup Time (CEf to Addr.)

t^AVEL

0

Address Setup Time to OE Low During Toggle Bit

Polling

—

t^ASO

15

—

ns

t^WLAX

t^ELAX

t^AH

Address Hold Time (WE to Addr.)

Address Hold Time (CEf to Addr.)

50

—

ns

Address Hold Time from CE or OE High During Toggle

Bit Polling

—

t^AHT

0

—

ns

t^DVWH

t^WHDX

t^DS

t^DH

Data Setup Time

Data Hold Time

50

0

—

8

—

15

—

100

90

30

—

ns

µs

sec

µs

ns

Read

Output Enable Hold Time

Toggle and Data Polling

0

—

t^OEH

10

20

0

—

t^CEPH

t^OEPH

t^GHEL

t^GHWL

t^WS

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

t^GHEL

t^GHWL

t^WLEL

t^ELWL

t^EHWH

t^WHEH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^WHWH1

0

t^CS

0

t^WH

0

t^CH

0

t^WP

50

30

—

50

4

t^CP

CEf Pulse Width

t^WPH

t^CPH

t^WHWH1

Write Pulse Width High

CEf Pulse Width High

Byte Programming Operation

1

t^WHWH2

Sector Erase Operation (Note 1)

—

t^VCS

t^VLHT

t^VIDR

t^RB

V^CCf Setup Time

Voltage Transition Time (Note 2)

Rise Time to V^ID(Note 2)

500

0

Recover Time from RY/BY

t^RP

RESET Pulse Width

500

200

—

30

t^RH

RESET Hold Time Before Read

Delay Time from Embedded Output Enable

Program/Erase Valid to RY/BY Delay

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

t^EOE

t^BUSY

t^FLQZ

t^FHQV

Note : 1. This does not include the preprogramming time.

2. This timing is for Sector Protection Operation.

14

MB84VD2002^-10/MB84VD2003^-10

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555H

t^WC

PA

ADDRESSES

t^RC

t^AS

t^AH

CEf

t^CH

t^CS

t^CO

OE

t^GHWL

t^F^OE

t^WHWH1

t^WP

t^WPH

WE

t^OH

t^DS

t^DH

PD

D^OUT

A0H

DQ⁷

DQ

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence

6. These waveforms are for the x16 mode. The addresses differ from x8 mode.

15

MB84VD2002^-10/MB84VD2003^-10

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

555H

Data Polling

ADDRESSES

PA

t^WC

t^AH

t^AS

WE

t^WS

t^WH

OE

t^GHEL

t^WHWH1

t^CP

t^CPH

CEf

t^DS

t^DH

PD

D^OUT

DQ⁷

A0H

DQ

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence

6. These waveforms are for the x16 mode. The addresses differ from x8 mode.

16

MB84VD2002^-10/MB84VD2003^-10

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA^*1

2AAH

555H

t^WC

2AAH

t^AS

555H

ADDRESSES

t^AH

CEf

t^CS

t^CH

OE

t^WP

t^WPH

t^GHWL

WE

t^DS

t^DH

30H for Sector Erase

10H/

30H

AAH

55H

80H

55H

DQ

V^CC

t^VCS

Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H forChip Erase.

2. These waveforms are for the x16 mode. The addresses differ from x8 mode.

17

MB84VD2002^-10/MB84VD2003^-10

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CE

t

CH

t

OE

t

DF

OE

t

OEH

WE

t

CE

*

High-Z

DQ

7

=

Data

DQ

7

DQ

7

Valid Data

t

WHWH1 or 2

DQ to DQ

Val⁰id Data⁶

DQ

0

to DQ

6

DQ

0

to DQ

6

= Output Flag

t

BUSY

t

EOE

RY/BY

* : DQ⁷= Valid Data (The device has completed the Embedded operation).

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

t

AHT

t

ASO

t

AHT tAS

CE

t

CEPH

WE

t

OEPH

t

OEH

tOEH

OE

t

OE

tCE

t

DH

*

Stop

Toggling

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ

6/DQ

2

Data

t

BUSY

RY/BY

* : DQ⁶stops toggling (The device has completed the Embedded operation).

18

MB84VD2002^-10/MB84VD2003^-10

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

WE

The rising edge of the last WE signal

Entire programming

or erase operations

RY/BY

t^BUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

t^RP

t^RB

RY/BY

t^READY

• Timing Diagram for Word Mode Configuration (Flash)

CE

BYTE

Data Output

DQ⁰to DQ¹⁴

Data Output

(DQ⁰to DQ¹⁴)

(DQ⁰to DQ⁷)

t^ELFH

t^FHQV

DQ¹⁵

DQ¹⁵/A^-1

A^-1

19

MB84VD2002^-10/MB84VD2003^-10

• Timing Diagram for Byte Mode Configuration (Flash)

CE

BYTE

t^ELFL

DQ⁰to DQ¹⁴

Data Output

(DQ⁰to DQ⁷)

Data Output

(DQ⁰to DQ¹⁴)

DQ¹⁵/A^-1

DQ¹⁵

A^-1

t^FLQZ

• BYTE Timing Diagram for Write Operations (Flash)

The falling edge of the last WE signal

CE or WE

BYTE

Input

Valid

t^SET

(t^AS)

t^HOLD

(t^AH)

• Temporary Sector Unprotection (Flash)

VCC

t

VIDR

t

VCS

t

VLHT

V

ID

3 V

RESET

CE

WE

t

VLHT

t

VLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

20

MB84VD2002^-10/MB84VD2003^-10

• Back-to-back Read/Write Timing Diagram

Read

Command

Read

Command

Read

t

RC

t

WC

t

RC

t

WC

t

RC

t

RC

BA2

(555H)

BA2

(PA)

BA2

(PA)

Address

CE

BA1

t

ACC

t

AS

t

AS

t

AH

t

AHT

t

CE

t

OE

t

CEPH

OE

WE

DQ

t

DF

t

GHWL

t

OEH

t

WP

t

DH

t

DS

t

DF

Valid

Output

Valid

Intput

Valid

Output

Valid

Output

Status

Intput

(A0H)

(PD)

21

MB84VD2002^-10/MB84VD2003^-10

• Extended Sector Protection (Flash)

V^CC

t^VCS

RESET

Add

t^VLHT

t^VIDR

SPAX

SPAY

A⁰

A¹

A⁶

CE

OE

TIME-OUT

WE

Data

60H

40H

01H

60H

t^OE

SPAX : Sector Address to be protected

SPAY : Next Sector Address to be protected

TIME-OUT : Time-Out window = 150 µs (min)

22

MB84VD2002^-10/MB84VD2003^-10

• Read Cycle (SRAM)

Parameter

Symbol

Parameter Description

Min.

Max.

Unit

t^RC

t^AA

Read Cycle Time

Address Access Time

100

—

5

—

100

50

ns

t^CO1

t^CO2

t^OE

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

t^COE

t^OEE

t^OD

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

Output Data Hold Time

—

0

—

10

40

t^ODO

t^OH

40

—

• Read Cycle (Note 1) (SRAM)

t^RC

ADDRESSES

CE1s

t^AA

t^OH

t^CO1

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

DQ

t^ODO

t^OEE

t^COE

VALID DATA OUT

Note: 1. WE remains HIGH for the read cycle.

23

MB84VD2002^-10/MB84VD2003^-10

•

Write Cycle (SRAM)

Parameter

Symbol

Parameter Description

Write Cycle Time

Min.

Max.

Unit

t^WC

t^WP

t^CW

t^AS

100

60

80

0

—

40

—

ns

Write Pulse Width

Chip Enable to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

t^ODW

t^OEW

t^DS

0

—

0

40

0

t^DH

Data Hold Time

• Write Cycle (Note 4) (WE control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

CE1s

CE2s

t^CW

t^ODW

t^OEW

D^OUT

Note 2

Note 5

Note 3

t^DS

t^DH

D^IN

VALID DATA IN

Note 5

Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

24

MB84VD2002^-10/MB84VD2003^-10

• Write Cycle (Note 4) (CE1s control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^CW

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

Note 5

VALID DATA IN

Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

25

MB84VD2002^-10/MB84VD2003^-10

• Write Cycle (Note 4) (CE2s Control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^CW

t^ODW

t^COE

D^OUT

t^DS

t^DH

D^IN

Note 5

VALID DATA IN

Note 5

Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

26

MB84VD2002^-10/MB84VD2003^-10

■ ERASE AND PROGRAMMING PERFORMANCE (Flash)

Limits

Typ.

Parameter

Unit

Comment

Min.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

sec

Byte Programming Time

Word Programming Time

—

8

300

360

µs

Excludes system-level

overhead

16

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

8.4

—

T.B.D

—

sec

100,000

cycles

■ DATA RETENTION CHARACTERISTICS (SRAM)

Parameter

Parameter Description

Symbol

Min.

Typ.

Max.

Unit

V^DH

Data Retention Supply Voltage

2.0

—

0

—

3.6

50*

60

—

V

V^DH= 3.0 V

V^DH= 3.6 V

µA

ns

I^DDS2

Standby Current

t^CDR

t^R

Chip Deselect to Data Retention Mode Time

Recovery Time

5

—

ms

* : 5 µA (Max.) at T^A= –20°C to +40°C

• CE1s Controlled Data Retention Mode (Note 1)

V^CCs

DATA RETENTION MODE

2.7 V

See Note 2

V^IH

V^CCS–0.2 V

CE1s

t^CDR

t^R

GND

27

MB84VD2002^-10/MB84VD2003^-10

• CE2s Controlled Data Retention Mode (Note 3)

V^CCs

DATA RETENTION MODE

2.7 V

V^IH

CE2s

t^CDR

t^R

V^IL

0.2 V

GND

Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss

to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to

Vccs+0.3V.

2. When CE1s is operating at the V^IHmin. level (2.2 V), the standby current is given by I^SB1s during the

transition of V^CCs from 3.6 to 2.2 V.

3. In CE2s controlled data retention mode, input and input/output pins can be used between between

-0.3V to Vccs+0.3V.

■ PIN CAPACITANCE

Parameter

Parameter Description

Test Setup

V^IN= 0

Typ.

Max.

Unit

Symbol

C^IN

Input Capacitance

T.B.D

pF

C^OUT

Output Capacitance

Control Pin Capacitance

V^OUT= 0

V^IN= 0

C^IN2

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of packages are right angle.

■ CAUTION

1.)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not

use autoselect and sector protect function by applying the high voltage (VID) to specific pins.

2.)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the

sector useing "Extended sector protect" command.

28

MB84VD2002^-10/MB84VD2003^-10

■ PACKAGE

48-pin plastic FBGA

(BGA-48P-M06)

■ PACKAGE DIMENSIONS

48-pin plastic BGA

(BGA-48P-M06)

Note: The actual shape of coners may differ from the dimension.

11.00±0.15(.433±.006)

1.40±0.20

7.00±0.15(.276±.006)

(.055±.008)

0.30±0.10

(.012±.004)

Ø0.40±0.10

(Ø.016±.004)

10.00±0.15

(.394±.006)

5.00±0.15

(.197±.006)

0.15(.006)

1st PIN

INDEX

1.00±0.15

(.039±.006)

Dimension in mm (inches).

C

1998 FUJITSU LIMITED MCM-M001-2-3

29

MB84VD2002^-10/MB84VD2003^-10

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9805

FUJITSU LIMITED Printed in Japan

30


型号：	MB84VD2002
厂家：	FUJITSU
描述：	8M (x 8/x 16) FLASH MEMORY & 2M (x 8) STATIC RAM 8M （ ×8 / ×16 ）Flash存储器和2M （ ×8 ）静态RAM 存储
文件：	总30页 (文件大小：399K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB84VD2002 [FUJITSU]

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