EOB1UV6411-60TG-S [FUJITSU]
EDO DRAM Module, 1MX64, 60ns, CMOS, PDMA144;
| 型号： | EOB1UV6411-60TG-S |
| 厂家： | 
FUJITSU |
| 描述： | EDO DRAM Module, 1MX64, 60ns, CMOS, PDMA144 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1996
Revision 1.0
DATA SHEET
EOB1UV641(1/4)-(60/70)TG-S
8MByte (1M x 64) CMOS EDO DRAM Module - 3.3V
General Description
The EOB1UV641(1/4)-(60/70)TG-S is a high performance, EDO (Extended Data Out) 8-megabyte dynamic RAM module orga-
nized as 1M words by 64 bits, in a 144-pins, small outline dual-in-line (SO DIMM) memory modules.
The module utilizes four, Fujitsu MB81V1(8/6)165A-(60/70) (FN) CMOS 1Mx16 EDO dynamic RAMs in a surface mount package
on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that byte control is possible. Serial PD on the module is provided by using 128 byte serial EEPROM.
Features
• High Density:8MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power: 2.6/2.4 W (max.) - Active (60/70 ns) - 1KR
1.3/1.1 W (max.) - Active (60/70 ns) - 4KR
29mW (max.)
14mW (max.)
- Standby (LVTTL)
- Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.00 inch
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to +4.6
4
Unit
V
Voltage on any pin relative to V
V
P
SS
T
Power Dissipation
W
T
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
50
°C
°C
mA
opr
T
stg
OS
I
Short Circuit Output Current
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
Typ
Max
3.6
0
Unit
V
V
V
V
3.0
0
3.3
V
V
V
V
CC
SS
IH
Ground
0
-
V
+0.3
Input High voltage
Input Low voltage
2.0
-0.3
CC
-
0.8
IL
Fujitsu Microelectronics, Inc.
1
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
Functional Diagram
CAS7*
CAS6*
CAS5*
CAS4*
CAS3*
CAS2*
CAS1*
CAS0*
1Mx16
1Mx16
EDO
1Mx16
EDO
1Mx16
EDO
RAS0*
EDO
WE*
DRAM
DRAM
DRAM
DRAM
OE*
DQ0~DQ15
DQ16~DQ31
DQ62~DQ47
DQ48~DQ63
DQ0~DQ63
SERIAL PD EEPROM
V
V
SS
CC
SCL
SCL
SDA
SDA
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1. signifies active low signal.
2. Addresses A0 ~ A11 are connected to all DRAMs. (A10 & A11 are NC for the 1K refresh module.)
3. A0~A2 of the Serial PD EEPROM device are grounded.
Fujitsu Microelectronics, Inc.
2
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
Pin Name
A0~A9
A0~A11
A0~A7
Row and Column Addresses for 1K Refresh
OE*
SCL
SDA
VCC
VSS
NC
Output Enable Input
Serial PD Clock
Serial PD Data Input/Output
Power Supply
Ground
No Connection
Row Addresses for 4K Refresh
Column Addresses for 4K Refresh
Data Inputs/Outputs
DQ0~DQ63
RAS0*
CAS0*~CAS7* Column Address Strobes
WE* Write Enable Input
Row Address Strobes
Pin No.
Pin Designation
Pin No.
Pin Designation
Pin No.
Pin Designation
OE*
Pin No.
Pin Designation
V
V
SS
1
2
73
74
NC
V
SS
V
3
5
7
9
DQ0
DQ1
DQ2
DQ3
4
6
DQ32
DQ33
DQ34
DQ35
75
77
79
81
76
78
80
82
SS
SS
NC
NC
V
NC
NC
V
8
10
CC
CC
V
V
11
13
15
17
19
12
14
16
18
20
83
85
87
89
91
DQ16
DQ17
DQ18
DQ19
84
86
88
90
92
DQ48
DQ49
DQ50
DQ51
CC
CC
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
V
V
SS
SS
V
V
21
23
25
27
22
24
26
28
93
95
97
99
DQ20
DQ21
DQ22
DQ23
94
96
DQ52
DQ53
DQ54
DQ55
SS
SS
CAS0*
CAS1*
CAS4*
CAS5*
98
V
V
100
CC
CC
V
V
29
31
33
35
37
39
41
43
45
A0
A1
A2
30
32
34
36
38
40
42
44
46
A3
A4
A5
101
103
105
107
109
111
113
115
117
102
104
106
108
110
112
114
116
118
CC
CC
A6
A8
A7
A11 (Note)
V
V
V
V
SS
SS
SS
SS
DQ8
DQ40
DQ41
DQ42
DQ43
A9
NC
NC
DQ9
A10 (Note)
V
V
DQ10
DQ11
CC
SS
CAS2*
CAS3*
CAS6*
CAS7*
V
V
CC
CC
V
V
47
49
51
53
55
DQ12
DQ13
DQ14
DQ15
48
50
52
54
56
DQ44
DQ45
DQ46
DQ47
119
121
123
125
127
120
122
124
126
128
SS
CC
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
V
V
SS
SS
V
V
57
59
61
63
65
67
69
71
NC
NC
NC
58
60
62
64
66
68
70
72
NC
NC
NC
129
131
133
135
137
139
141
143
130
132
134
136
138
140
142
144
CC
CC
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
V
V
CC
CC
NC
NC
NC
NC
NC
V
V
WE*
RAS0*
NC
SS
SS
SDA
SCL
V
V
CC
CC
Note: Address A10 and A11 are NC for the 1K refresh module but are used for the 4K refresh module.
Fujitsu Microelectronics, Inc.
3
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
DC CHARACTERISTICS
(VCC = 3.3V±0.3V, VSS = 0V, TA = 0 to +70 °C)
60
70
Parameter
Symbol
Test Condition
Unit
Note
Min.
Max.
720
Min.
Max.
680
1KR
4KR
-
-
-
-
I
RAS*, CAS* cycling; t = min.
Operating Current
mA
1, 2
CC1
RC
360
320
LVTTL Interface
RAS*, CAS* ≥ V
I
-
-
8
4
-
-
8
4
mA
mA
IH
CC2
D
= HIgh-Z
out
Standby current
CMOS Interface
RAS*, CAS* ≥ V - 0.2V
cc
D
= HIgh-Z
out
1KR
4KR
1KR
4KR
1KR
4KR
-
720
360
680
360
480
440
40
-
680
320
640
320
440
400
40
CAS* ≥ V ; RAS*, Address
RAS* -only Refresh
Current
IH
I
mA
mA
2
CC3
cycling @ t = min.
RC
-
-
-
-
RAS*, CAS* cycling @
CAS*-before-RAS*
Refresh Current
I
CC4
t
= min.
RC
-
-
-
-
RAS* ≤ V ; CAS*, Address
Hyper Page Mode
Current
IL
I
mA
µA
µA
1, 3
CC5
cycling @ t = min.
PC
-
-
I
0V ≤ Vin ≤ V + 0.3V
Input Leakage Current
Output Leakage Current
-40
-40
LI
CC
0V ≤ Vout ≤ V
CC
I
-10
10
-10
10
LO
D
= Disable
out
V
High I = -2mA
Output High Voltage
Output Low Voltage
2.4
0
-
2.4
0
-
V
V
OH
out
V
Low I = 2 mA
0.4
0.4
OL
out
Notes:
1. Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
2. Address can be changed once or less while RAS* = V .
IL
3. Address can be changed once or less while CAS* = V
.
IH
CAPACITANCE
(TA =+25°C, VCC = 3.3V±0.3V)
Parameter
Symbol
Max.
25
Unit
pF
Note
1
C
Input Capacitance (Address)
I1
C
Input Capacitance (RAS*, OE*, WE*)
Input Capacitance (CAS0*~CAS7*)
Input/Output Capacitance (DQ0~DQ63)
33
pF
1
I2
C
12
pF
1
I3
C
12
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* - V to disable D
.
out
IH
Fujitsu Microelectronics, Inc.
4
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)
60
70
Parameter
Symbol
Unit
Notes
Min
110
-
Max
Min
130
-
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read/write cycle time
Access time from RAS*
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
60
70
3, 4
3, 4, 5
3, 10
2
RAC
CAC
AA
Access time from CAS*
-
15
-
20
Access time from column address
Transition time (rise and fall)
RAS* precharge time
-
30
-
35
2
50
2
50
T
40
60
15
45
10
20
15
5
-
50
70
20
50
15
20
15
5
-
RP
RAS* pulse width
10000
10000
RAS
RSH
CSH
CAS
RCD
RAD
CRP
ASR
RAH
ASC
CAH
RAL
RCS
RCH
RRH
WCH
WP
RAS* hold time
-
-
CAS* hold time
-
-
CAS* pulse width
10000
10000
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
45
30
-
50
35
-
4
10
0
-
0
-
10
0
-
10
0
-
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
-
-
10
30
0
-
15
35
0
-
-
-
-
-
0
-
0
-
8
0
-
0
-
10
10
15
10
0
-
15
15
17
15
0
-
-
-
-
-
RWL
CWL
DS
-
-
-
-
9
9
Data-in hold time
10
-
-
15
-
-
DH
1KR
16
64
-
16
64
-
t
Refresh period
4KR
ms
REF
-
-
t
t
t
t
t
t
t
t
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
0
0
ns
ns
ns
ns
ns
ns
ns
ns
7
1
1
WCS
CSR
CHR
RPC
CPA
HPC
CP
10
10
5
-
10
15
5
-
-
-
-
-
-
35
-
40
3, 11
12
25
10
60
-
30
10
70
-
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
Fujitsu Microelectronics, Inc.
-
-
100000
100000
RASP
5
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
Notes:
1. An initial pulse of at least 200µs is required after power-up followed by a minimum of eight RAS* cycles before device operation
is achieved.
2.
V
(min.) and V (max.) are reference levels for measuring timing of input signals. Transition times are measured between V
IH IL IH
(min.) and V (max.) and are assumed to be 5 ns for all inputs.
IL
3. Measure with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the t (max.) limit ensures that t (max.) limit can be met; t (max.) is specified as a reference point
RCD
RCD
RAC
only. If t
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
RCD
CAC
5. Assumes that tRCD ≥ t
(max.).
RAD
6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to V or V
.
OH
OL
7.
t
is non restrictive operating parameter. It is included in the data sheet as an electrical characteristic only. If tWCS ≥ t
(min.)
WCS
WCS
the cycle is an early write cycle and the data out pin will remain at high impedance for the duration of the cycle.
8. Either t or t must be satisfied for a read cycle.
RCH
RRH
9. These parameters are referenced to the CAS* leading edge in early write cycles.
10. Operation within the t (max.) limit ensures that t (max.) limit can be met. t (max.) is specified as a reference point only.
RAD
RAD
RAC
If t
is greater than the specified t
(max.) limit, then access time is controlled by t
.
RAD
RAD
AA
11. Access time is determined by the longer of t , t
, or t
.
AA CAC
ACP
12.
t
defines RAS* pulse width in fast page mode cycles.
RASC
Physical Dimensions
144-pin 3.4V SODIMM
Front View
0.160
(max.)
2.661
2.503
0.158x2
070x2
1
59
61
143
0.913
1.291
0.181
0.098
0.083
0.130
0.145
0.040
± 0.004
0.031
2
60
62
144
Back View
( All dimensions are in inches with 0.005" tolerance unless otherwise specified)
Fujitsu Microelectronics, Inc.
6
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
All Rights Reserved.
Circuit diagrams using fujitsu products are included to illustrate typical semiconductor applications.
Information sufficient for construction purpose may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable.
However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent
rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu
Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of the publication may be copied or reproduced in any form or by any means, or transferred
to any third party without prior written consent of Fujitsu Microelectronics, Inc.
7
September 1996
Revision 1.0
EOB1UV641(1/4)-(60/70)TG-S
Visit our web site for the latest information:
http://www.fujitsumicro.com
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MP-DRAMM-DS-20393-9/96
8
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