CE66S4 [FUJITSU]

0.35um CMOS Technology; 0.35微米CMOS技术
CE66S4
型号: CE66S4
厂家: FUJITSU    FUJITSU
描述:

0.35um CMOS Technology
0.35微米CMOS技术

文件: 总2页 (文件大小:30K)
中文:  中文翻译
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CE66 Series Embedded Array  
0.35µm CMOS Technology  
Features  
• 0.28µm Leff (0.34µm drawn)  
• Propagation delay of 98 ps  
5V I/O  
5V I/O  
5V I/O  
5V I/O  
5V I/O  
3V I/O  
3V I/O  
3V I/O  
PCML  
3V I/O  
3V I/O  
5V I/O  
5V I/O  
5V I/O  
5V I/O  
5V I/O  
Mixed-signal macros:A/D and D/A converters  
• High-density diffused RAMs and ROMs  
Separate core and I/O supply voltages  
• I/Os: 5V, 3.3V, 5V tolerant  
Core power supply voltage: 3.3V, 2.5V~2.0V  
Fixed  
Layout  
Soft Macro  
Embedded  
Hard  
Macro  
Clk  
Clock Tree  
• Junction temperature: -40ºC~125ºC  
2
Fixed  
Layout  
Soft Macro  
Special I/Os: PCI, I C, USB  
Analog and digital PLLs  
• Packaging options: QFP, HQFP, LQFP,TQFP, PBGA,FBGA  
Support for major third party EDA tools  
Description  
Fujitsus CE66 is a series of high-performance, CMOS  
embedded arrays featuring mixed-signal macros, diffused  
high-speed RAMs, ROMs, and a variety of other embedded  
functions.The CE66 series combines the density and  
performance of standard cells with the time-to-market  
advantage of gate arrays. In addition, the I/Os, operating  
at 5V, 3.3V, and 5V tolerant conditions, are designed to  
provide cost-effective solutions for both core-limited and  
pad-limited designs.The CE66 series features a very low  
power consumption of 0.29µW/gate/MHz at 3.3V. Potential  
applications for the CE66 series include the consumer  
market, communications, and networking designs.  
P-Series with 100µm Inline Pad Pitch  
Frame  
CE66P1  
CE66P2  
CE66P3  
CE66P4  
CE66P5  
CE66P6  
CE66P7  
CE66P8  
CE66P9  
CE66PA  
CE66PB  
CE66PC  
CE66PD  
CE66PE  
CE66PF  
Total Gates  
188K  
Total Pads  
144  
Signals  
126  
138  
132  
152  
178  
178  
178  
206  
228  
228  
228  
264  
264  
264  
312  
233K  
160  
283K  
176  
337K  
192  
396K  
208  
427K  
216  
460K  
224  
528K  
240  
602K  
256  
680K  
272  
761K  
288  
847K  
304  
940K  
320  
1037K  
1138K  
336  
352  
S-Series with 70µm Inline Pad Pitch  
Frame  
CE66S1  
CE66S2  
CE66S3  
CE66S4  
CE66S5  
CE66S6  
CE66S7  
CE66S8  
CE66S9  
CE66SA  
Total Gates  
91K  
Total Pads  
144  
Signals  
126  
113K  
137K  
164K  
207K  
256K  
311K  
391K  
481K  
580K  
160  
138  
176  
152  
192  
160  
216  
178  
240  
193  
264  
228  
296  
248  
328  
248  
360  
312  
CE66 SeriesEmbedded Array  
Mixed-Signal Macros  
Smart Card I/F  
IRDA I/R Interface  
More IPs are being added  
D/A Converters  
• 8-bit: 220 MHz (video)  
• 8-bit: 50 MHz (video)  
• 8-bit: 1.5 MHz (general purpose)  
• 10-bit: 30 MHz (general purpose)  
• 10-bit: 1.5 MHz (general purpose)  
A/D Converters  
ASIC Design Kit and EDA Support  
Verilog Logic Simulators from  
Cadence, Synopsys, and Mentor  
Verilog-XL, NC-Verilog,  
VCS, Model-sim (Verilog)  
VHDL/VITAL Logic  
Simulators from Synopsys,  
Cadence, and Mentor  
VSS, Model-sim (VHDL), V-System,  
Leapfrog  
• 6-bit: 300 MHz (disk)  
• 8-bit: 50 MHz (video)  
• 10-bit: 20 MHz (general purpose)  
• 10-bit: 1 MHz (general purpose)  
Synthesis, DFT, and STA tools  
from Synopsys  
Design Compiler, Test Compiler,  
PrimeTime, MOTIVE, and  
Sunrise TestGen  
Other EDA tools  
Chrysalis Design Verifyer  
Multiplier Compiler  
Multiplicand (m): 4 < m < 32  
Multiplier (n): 4 < n < 32 (even numbers only)  
PACKAGE AVAILABILITY  
No. of Pins  
Frame Size  
Memory Macros  
TQFP  
SRAM Compiler: single and dual port (1 R/W, 1R),  
up to 72K bits per block, partial write option  
ROM Compiler: up to 512K bits per block  
• Delay line: up to 32K bits  
100  
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S1, S2  
LQFP  
100  
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S1, S2  
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S1, S2  
P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF  
144  
176  
Phase-Locked Loops  
208  
P6, P7, P8, P9, PA, PB, PC, PD, S5, S6, S7  
QFP  
120  
Analog: 50-200 MHz  
• Digital: 180-360 MHz (Preliminary)  
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S1, S2  
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S1, S2  
P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S2, S3, S4  
P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S3, S4  
P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S5, S6  
P8, P9, PA, PB, PC, PD, PE, PF, S7, S8  
144  
I/Os  
160  
176  
• 3.3V, 5V, and 5V tolerant  
Slew-rate controlled  
208  
240  
CMOS,TTL, LVTTL,T-LVTTL, SDRAM I/F,  
256  
P9, PA, PB, PC, PD, PE, PF  
2
PCI, I C, USB  
HQFP  
208  
P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S5, S6  
P8, P9, PA, PB, PC, PD, PE, PF, S7, S8  
P9, PA, PB, PC, PD, PE, PF, S8  
SOC IP Cores  
240  
ARC 32-bit RISC  
256  
832/833/835 SPARClite Hard Macros  
Oak DSP Hard Macro  
10/100 MAC  
304  
PC, PD, PE, PF, S9, SA  
PBGA  
256  
P9, PA, PB, PC, PD, PE, PF, S7, S8  
PF, SA  
352  
64/256 QAM  
FBGA  
112  
144  
168  
176  
192  
224  
288  
MPEG2 Decoder/Demultiplexer  
8VSBTV Demodulator  
AC-3 DolbyVoice Decoder  
JPEG Encoder and Decoder  
PCI–33/66 MHz, 32/64-bit cores  
USB Host Controller/Device  
P2, P3, P4, P5, P6, P7, S1, S2, S3  
P3, P4, P5, P6, P7, S1, S2, S3, S4  
P6, P7, P8, P9, S3, S4, S5, S6, S7  
P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, S3, S4  
P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF, S4, S5  
P7, P8, P9, PA, PB, PC, PD, PE, PF, S6, S7  
PC, PD, PE, PF, S8, S9, SA  
2
I C  
IDE (ATA3) Host Controller  
FUJITSU MICROELECTRONICS AMERICA, INC.  
Corporate Headquarters  
© 1999 Fujitsu Microelectronics, Inc.  
1250 East Arques Avenue, Sunnyvale, California 94088-3470  
Tel: (800) 866-8608 Fax: (408) 737-5999  
All company and product names are trademarks or  
registered trademarks of their respective owners.  
Printed in the U.S.A. ASIC-FS-20640-11/99  
E-mail: inquiry@fma.fujitsu.com Web Site: http://www.fma.fujitsu.com  

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