FT234XD_技术文档

FT234XD USB TO BASIC UART IC

Version 1.2

Document No.: FT_000753 Clearance No.: FTDI#324

Future Technology

Devices International

Ltd

.

FT234XD

(USB to BASIC UART IC)



USB Battery Charging Detection. Allows for USB

peripheral devices to detect the presence of a

higher power source to enable improved

charging.

The FT234XD is a USB to serial UART

interface with optimised packaging (3mm

x 3mm 12 pin DFN) for smaller PCB

designs and the following advanced

features:



Device supplied pre-programmed with unique

USB serial number.

USB Power Configurations; supports bus- powered,

self-powered and bus-powered with power switching



Single chip USB to asynchronous serial data

transfer interface.



Integrated +3.3V level converter for USB I/O.

Entire USB protocol handled on the chip. No USB

specific firmware programming required.

True 3.3V CMOS drive output and TTL input;

Operates down to 1V8 with external pull ups.

Tolerant of 5V input.

Fully

integrated

2048

byte

multi-time-

programmable (MTP) memory, storing device

descriptors and CBUS I/O configuration.



Fully integrated clock generation with no external

crystal required plus optional clock output selection

enabling a glue-less interface to external MCU or

FPGA.



Configurable I/O pin output drive strength;

4 mA (min) and 16 mA (max).



Integrated power-on-reset circuit.

Fully integrated AVCC supply filtering - no

external filtering required.



Data transfer rates from 300 baud to 3 Mbaud

(RS422, RS485, and RS232) at TTL levels.



UART signal inversion option.

+ 5V Single Supply Operation.

Internal 3.3V/1.8V LDO regulators

512 byte receive buffer and 512 byte transmit

buffer utilising buffer smoothing technology to

allow for high data throughput.



FTDI’s royalty-free Virtual Com Port (VCP) and

Direct (D2XX) drivers eliminate the requirement

for USB driver development in most cases.

Low operating and USB suspend current;

8mA (active-typ) and 70uA (suspend-typ).



UHCI/OHCI/EHCI host controller compatible.

USB 2.0 Full Speed compatible.



Configurable CBUS I/O pin.

Transmit and receive LED drive signals.

Extended operating temperature range; -40 to

85⁰C.

UART interface support for 7 or 8 data bits, 1 or 2

stop bits and odd / even / mark / space / no parity



Synchronous and asynchronous bit bang interface

options with RD# and WR# strobes.



Available in compact Pb-free 12 pin DFN package

(3mm x 3mm) RoHS compliant.

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form

without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any

particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure

of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of

the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No

freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward

Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640

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FT234XD USB TO BASIC UART IC

Version 1.2

Document No.: FT_000753 Clearance No.: FTDI#324

1 Typical Applications



USB to RS232/RS422/RS485 Converters

Upgrading Legacy Peripherals to USB

Utilising USB to add system modularity



USB Industrial Control

USB FLASH Card Reader and Writers

Set Top Box PC - USB interface

USB Wireless Modems

Incorporate USB interface to enable PC

transfers for development system

communication

USB Bar Code Readers

USB dongle implementations for Software/

Hardware Encryption and Wireless Modules



Cellular and Cordless Phone USB data transfer

cables and interfaces



Detection of dedicated charging port for battery

charging at higher supply currents.

Interfacing MCU/PLD/FPGA based designs to

add USB connectivity

USB Audio and Low Bandwidth Video data

transfer



USB Smart Card Readers

USB Instrumentation

1.1 Driver Support

Royalty free VIRTUAL COM PORT

(VCP) DRIVERS for...

Royalty free D2XX Direct Drivers

(USB Drivers + DLL S/W Interface)



Windows 10 32,64-bit



Windows 10 32,64-bit

Windows 8/8.1 32,64-bit

Windows 7 32,64-bit

Windows 8/8.1 32,64-bit

Windows 7 32,64-bit

Windows Vista and Vista 64-bit

Windows XP and XP 64-bit

Windows Vista and Vista 64-bit

Windows XP and XP 64-bit

Windows 98, 98SE, ME, 2000, Server 2003, XP,

Server 2008 and server 2012 R2

Windows 98, 98SE, ME, 2000, Server 2003, XP,

Server 2008 and server 2012 R2



Windows XP Embedded

Windows CE 4.2, 5.0 and 6.0

Mac OS 8/9, OS-X



Windows XP Embedded

Windows CE 4.2, 5.0 and 6.0

Linux 2.4 and greater

Android(J2xx)

Linux 2.4 and greater

The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com).

Various 3rd party drivers are also available for other operating systems - see FTDI website

(www.ftdichip.com) for details.

For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm

1.2 Part Numbers

Part Number

FT234XD-x

Package

12 Pin DFN

Note: Packing codes for x is:

- R: Taped and Reel - 5,000pcs per reel.

- T: Tray packing - 490pcs per tray.

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FT234XD USB TO BASIC UART IC

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1.3 USB Compliant

The FT234XD is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID

(TID) 40001465 (Rev D).

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FT234XD USB TO BASIC UART IC

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2 FT234XD Block Diagram

VCC

1V8 Internal

Core Supply

48MHz

3.3 Volt LDO

Regulator

1.8 Volt LDO

Regulator

Baud Rate

Generator

3V3OUT

FIFO RX Buffer

(512 bytes)

TXD

RXD

RTS#

CTS#

USB

USBDP

USBDM

Transceiver

with

Integrated

1.5k pullups

and battery

charge

UART Controller

Serial Interface

Engine

USB

Protocol Engine

UART FIFO

Controller

with

Programmable

Signal Inversion

(SIE)

CBUS0

detection

Internal MTP

Memory

USB DPLL

FIFO TX Buffer

(512 bytes)

3V3OUT

RESET#

Internal

12MHz

Oscillator

X4 Clock

Multiplier

Reset

Generator

48MHz

To USB Transceiver Cell

GND

Figure 2.1 FT234XD Block Diagram

For a description of each function please refer to Section 4.

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FT234XD USB TO BASIC UART IC

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Table of Contents

1

Typical Applications...................................................................... 2

1.1 Driver Support.................................................................................... 2

1.2 Part Numbers...................................................................................... 2

1.3 USB Compliant.................................................................................... 3

FT234XD Block Diagram ............................................................... 4

Device Pin Out and Signal Description.......................................... 7

2

3

3.1 12-Pin DFN Package.......................................................................... 7

3.1.1 DFN Package PinOut Description....................................................................................7

3.2 CBUS Signal Options ........................................................................... 9

4

5

Function Description................................................................... 11

4.1 Key Features..................................................................................... 11

4.2 Functional Block Descriptions........................................................... 11

Devices Characteristics and Ratings........................................... 14

5.1 Absolute Maximum Ratings............................................................... 14

5.2 DC Characteristics............................................................................. 15

5.3 MTP Memory Reliability Characteristics ............................................ 19

5.4 Internal Clock Characteristics........................................................... 19

USB Power Configurations.......................................................... 20

6.1 USB Bus Powered Configuration ...................................................... 20

6.2 Self Powered Configuration .............................................................. 21

6.3 USB Bus Powered with Power Switching Configuration .................... 22

Application Examples ................................................................. 23

7.1 USB to RS232 Converter ................................................................... 23

7.2 USB to RS485 Coverter ..................................................................... 24

7.3 USB to RS422 Converter ................................................................... 25

7.4 USB Battery Charging Detection ....................................................... 26

7.5 LED Interface.................................................................................... 27

Internal MTP Memory Configuration........................................... 28

8.1 Default Values .................................................................................. 28

6

7

8

9

8.2 Methods of Programming the MTP Memory....................................... 29

8.2.1 Programming the MTP memory over USB...................................................................... 29

8.3 Memory Map ..................................................................................... 30

Package Parameters................................................................... 31

9.1 DFN-12 Package Mechanical Dimensions.......................................... 31

9.2 DFN-12 Package Markings ................................................................ 32

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FT234XD USB TO BASIC UART IC

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9.3 Solder Reflow Profile ........................................................................ 33

10 Contact Information................................................................... 34

Appendix A – References........................................................................... 35

Appendix B - List of Figures and Tables..................................................... 36

Appendix C - Revision History.................................................................... 37

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3 Device Pin Out and Signal Description

3.1 12-Pin DFN Package

3

7

10

8

3V3OUT

TXD

RXD

RTS#

CTS#

1

12

11

USBDM

USBDP

6

CBUS0

2

RESET#

Figure 3.1 DFN Schematic Symbol

3.1.1 DFN Package PinOut Description

Note: # denotes an active low signal.

Pin No.

Name

Type

Description

**

POWER

Input

4

5 V (or 3.3V) supply to IC

VCC

POWER

Input

9

3

VCCIO

1.8V – 3.3V supply for the IO cells

3.3V output at 50mA. May be used to power VCCIO.

**

POWER

Output

When VCC is 3.3V; pin 3 is an input pin and should be

connected to pin 4.

3.3VOUT

POWER

Input

5, 13

GND

0V Ground input.

Table 3.1 Power and Ground

*Pin 13 is the centre pad under the IC. Connect to GND.

** If VCC is 3.3V then 3.3VOUT must also be driven with 3.3V input

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Pin No.

Name

USBDM

USBDP

RESET#

Type

Description

1

12

2

INPUT/OUTPUT USB Data Signal Minus.

INPUT/OUTPUT USB Data Signal Plus.

INPUT

Reset input (active low).

Table 3.2 Common Function pins

Pin No.

Name

Type

Output

Input

Description

7

10

8

TXD

RXD

Transmit Asynchronous Data Output.

Receiving Asynchronous Data Input.

RTS#

CTS#

Output

Input

Request to Send Control Output / Handshake Signal.

Clear To Send Control Input / Handshake Signal.

11

Configurable CBUS I/O Pin. Function of this pin is configured in the

device MTP memory. The default configuration is TXDEN. See CBUS

Signal Options, Table 3.4.

6

CBUS0

I/O

Table 3.3 UART Interface and CBUS Group (see note 1)

Notes:

1. When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors.

These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an

option in the MTP memory.

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FT234XD USB TO BASIC UART IC

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3.2 CBUS Signal Options

The following options can be configured on the CBUS0 I/O pin. These options can be configured in the

internal MTP memory using the software utility FT_PROG which can be downloaded from the FTDI Utilities

(www.ftdichip.com). The default configuration is described in Section 8.

CBUS Signal

CBUS Pin

Description

Option

TRI-STATE

DRIVE 1

DRIVE 0

TXDEN

CBUS0

IO Pad is tri-stated

Output a constant 1

Output a constant 0

Enable transmit data for RS485

Output is low after the device has been configured by

USB, then high during USB suspend mode. This output

can be used to control power to external logic P-Channel

logic level MOSFET switch. Enable the interface pull-down

option when using the PWREN# in this way.

PWREN#

CBUS0

Transmit data LED drive – pulses low when transmitting

data via USB. See Section 7.5 for more details.

TXLED#

RXLED#

CBUS0

Receive data LED drive – pulses low when receiving data

via USB. See Section 7.5 for more details.

LED drive – pulses low when transmitting or receiving

data via USB. See Section 7.5 for more details.

TX&RXLED#

Goes low during USB suspend mode. Typically used to

power down an external TTL to RS232 level converter IC

in USB to RS232 converter designs.

SLEEP#

CBUS0

CLK24MHz

CLK12MHz

CLK6MHz

CBUS0

24 MHz Clock output.*

12 MHz Clock output.*

6 MHz Clock output.*

CBUS bit bang mode option. Allows the CBUS pin to be

used as general purpose I/O. Configured in the internal

MTP memory. A separate application note, AN232R-01,

available from FTDI website (www.ftdichip.com) describes

in more detail how to use CBUS bit bang mode.

GPIO

CBUS0

Battery Charging Detection indicates when the device is

connected to a dedicated battery charger host. Active

high output.

BCD Charger

BCD Charger#

BitBang_WR#

CBUS0

Inverse of BCD Charger

Synchronous and asynchronous bit bang mode WR#

strobe output.

Synchronous and asynchronous bit bang mode RD#

strobe output.

BitBang_RD#

CBUS0

VBUS Sense

Time Stamp

CBUS0

Input to detect when VBUS is present.

Toggle signal which changes state each time a USB

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CBUS Signal

Option

CBUS Pin

Description

SOF is received

Prevents the device from entering suspend state

when unplugged.

Keep_Awake#

CBUS0

Table 3.4 CBUS Configuration Control

*When in USB suspend mode the outputs clocks are also suspended.

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4 Function Description

The FT234XD is a compact USB to a basic serial UART interface device which simplifies USB

implementations in a small optimised package. The device reduces external component count by fully

integrating an MTP memory, and an integrated clock circuit which requires no external crystal. It has

been designed to operate efficiently with USB host controllers by using as little bandwidth as possible

when compared to the total USB bandwidth available.

4.1 Key Features

Functional Integration. Fully integrated MTP memory, clock generation, AVCC filtering, Power-On-

Reset (POR) and LDO regulators.

Configurable CBUS I/O Pin Options. The fully integrated MTP memory allows configuration of the

Control Bus (CBUS) functionality and drive strength selection. There is one CBUS I/O pin CBUS0. The

configurable options of CBUS0 are detailed in section 3.2

The CBUS line can be configured with any one of these output options by setting bits in the internal MTP

memory. The device is shipped with the most commonly used pin definitions pre-programmed - see

Section 8 for details.

Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT234XD supports FTDI’s previous

chip generation bit-bang mode. In bit-bang mode, the four UART lines can be switched from the regular

interface mode to a 4-bit general purpose I/O port. Data packets can be sent to the device and they will

be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate

pre-scalar). Either the internal RD# or the internal WR# strobe signal can mapped to the CBUS0 pin

(only one CBUS pin available) which can be used to allow external logic to be clocked by access to the

bit-bang I/O bus. This option will be described more fully in a separate application note available from

FTDI website (www.ftdichip.com).

Synchronous Bit Bang Mode. The FT234XD supports synchronous bit bang mode. This mode differs

from asynchronous bit bang mode in that the interface pins are only read when the device is written to.

This makes it easier for the controlling program to measure the response to an output stimulus as the

data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI

website (www.ftdichip.com) describes this feature.

Source Power and Power Consumption. The FT234XD is capable of operating at a voltage supply

between +3.3V and +5.25V with a nominal operational mode current of 8mA and a nominal USB suspend

mode current of 125µA. This allows greater margin for peripheral designs to meet the USB suspend mode

current limit of 2.5mA. An integrated level converter within the UART interface allows the FT234XD to

interface to UART logic running at +1.8V to +3.3V (5V tolerant).

4.2 Functional Block Descriptions

The following paragraphs detail each function within the FT234XD. Please refer to the block diagram

shown in Figure 2.1

Internal MTP Memory. The internal MTP memory in the FT234XD is used to store USB Vendor ID (VID),

Product ID (PID), device serial number, product description string and various other USB configuration

descriptors. The internal MTP memory is also used to configure the CBUS pin functions. The FT234XD is

supplied with the internal MTP memory pre-programmed as described in Section 8. A user area of the

internal MTP memory is available to system designers to allow storing additional data from the user

application over USB. The internal MTP memory descriptors can be programmed in circuit, over USB

without any additional voltage requirement. The descriptors can be programmed using the FTDI utility

software called FT_PROG, which can be downloaded from FTDI Utilities on the FTDI website

(www.ftdichip.com).

+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the

USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the

3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on

USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells

rather than to power external logic. However, it can be used to supply external circuitry requiring a

+3.3V nominal supply with a maximum current of 50mA.

+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8V reference voltage for internal use

driving the IC core functions of the serial interface engine and USB protocol engine.

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USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface

to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential

input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB

reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP.

The block also detects when connected to a USB power supply which will not enumerate the device but

still supply power and may be used for battery charging.

USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock

and data signals for the Serial Interface Engine (SIE) block.

Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This

provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference

clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.

Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal

Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz

clock reference is used by the USB DPLL and the Baud Rate Generator blocks.

Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial

and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it

performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also verifies the CRC on the USB data

stream.

USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control

endpoint. It handles the low level USB protocol requests generated by the USB host controller and the

commands for controlling the functional parameters of the UART in accordance with the USB 2.0

specification chapter 9.

FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the UART via the USB data OUT

endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit

register under control of the UART FIFO controller. (Rx relative to the USB interface).

FIFO TX Buffer (512 bytes). Data from the UART receive register is stored in the TX buffer. The USB

host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device

data IN endpoint. (Tx relative to the USB interface).

UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and

TX buffers and the UART transmit and receive registers.

UART Controller with Programmable Signal Inversion and High Drive. Together with the UART

FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX

buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial

and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface.

Control signals supported by UART mode include RTS, CTS. The UART Controller also provides a

transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485 transceivers.

RTS/CTS and XON / XOFF handshaking options are also supported. Handshaking is handled in hardware to

ensure fast response times. The UART interface also supports the RS232 BREAK setting and detection

conditions.

Additionally, the UART signals can each be individually inverted and have a configurable high drive

strength capability (using FT_PROG). Both these features are configurable in the MTP memory.

Baud Rate Generator - The Baud Rate Generator provides a 16x clock input to the UART Controller

from the 48MHz reference clock. It consists of a 14 bit pre-scalar and 3 register bits which provide fine

tuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines the

baud rate of the UART, which is programmable from 183 baud to 3 Mbaud.

The FT234XD supports all standard baud rates and non-standard baud rates from 183 Baud up to 3

Mbaud. Achievable non-standard baud rates are calculated as follows -

Baud Rate = 3000000 / (n + x)

14

Where ‘n’ can be any integer between 2 and 16,384 (= 2 ) and ‘x’ can be a sub-integer of the value 0,

0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values

between 1 and 2 are not possible.

This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud

rate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver will

calculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI

website (www.ftdichip.com) for more details.

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RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device

internal circuitry at power up. The RESET# input pin allows an external device to reset the FT234XD.

RESET# can be tied to VCC or left unconnected if not being used.

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5 Devices Characteristics and Ratings

5.1 Absolute Maximum Ratings

The absolute maximum ratings for the FT234XD devices are as follows. These are in accordance with the

Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the

device.

Parameter

Value

Unit

Conditions

Storage Temperature

-65°C to 150°C

168 Hours

Degrees C

Floor Life (Out of Bag) At Factory Ambient

(30°C / 60% Relative Humidity)

(IPC/JEDEC J-

STD-033A MSL

Level 3

Hours

Compliant)*

Ambient Operating Temperature (Power

Applied)

-40°C to 85°C

Degrees C

MTTF FT234XD

VCC Supply Voltage

TBD

Hours

-0.3 to +5.5

-0.3 to +4.0

-0.5 to +3.63

V

VCCIO IO Voltage

DC Input Voltage – USBDP and USBDM

DC Input Voltage – High Impedance

-0.3 to +5.8

22

V

Bi-directional (powered from VCCIO)

DC Output Current – Outputs

mA

Table 5.1 Absolute Maximum Ratings

* If devices are stored out of the packaging beyond this time limit the devices should be baked before

use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

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5.2 DC Characteristics

DC Characteristics (Ambient Temperature = -40°C to +85°C)

Parameter

Description

Minimum

Typical

Maximum

5.5

Units

V

Conditions

VCC Operating Supply

Voltage

VCC

2.97

5

---

8

Normal Operation

VCCIO Operating

Supply Voltage

VCC2

Icc1

1.62

3.63

V

Operating Supply

Current

6.5

8.3

mA

μA

Normal Operation

USB Suspend

Operating Supply

Current

Icc2

125

VCC must be

greater than 3V3

otherwise 3V3OUT

is an input which

must be driven

with 3.3V

3V3

3.3v regulator output

2.97

3.3

3.63

V

Table 5.2 Operating Voltage and Current

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Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Ioh = +/-2mA

2.97

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

2.97

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.8

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

2.0

Vt

Switching Threshold

V

1.49

1.15

Schmitt trigger negative

going threshold voltage

Vt-

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

1.64

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.3 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory.

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Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Ioh = +/-2mA

2.25

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

2.25

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.8

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

0.8

Vt

Switching Threshold

V

1.1

0.8

Schmitt trigger negative

going threshold voltage

Vt-

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

1.2

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.4 I/O Pin Characteristics VCCIO = +2.5V (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory.

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Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Ioh = +/-2mA

1.62

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

1.62

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.77

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

1.6

Vt

Switching Threshold

V

0.77

Schmitt trigger negative

going threshold voltage

Vt-

0.557

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

0.893

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.5 I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory.

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Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Voh

Vol

Output Voltage High

Output Voltage Low

VCC-0.2

V

0.2

0.8

Input low Switching

Threshold

Vil

V

-

Input High Switching

Threshold

Vih

2.0

Table 5.6 USB I/O Pin (USBDP, USBDM) Characteristics

5.3 MTP Memory Reliability Characteristics

The internal 2048 Byte MTP memory has the following reliability characteristics:

Parameter

Data Retention

Write Cycle

Value

10

Unit

Years

Cycles

2,000

Read Cycle

Unlimited

Table 5.7 MTP Memory Characteristics

5.4 Internal Clock Characteristics

The internal Clock Oscillator has the following characteristics:

Value

Parameter

Unit

Minimum

11.98

Typical

12.00

Maximum

12.02

Frequency of Operation

(see Note 1)

MHz

Clock Period

Duty Cycle

83.19

45

83.33

50

83.47

55

ns

%

Table 5.8 Internal Clock Characteristics

Note 1: Equivalent to +/-1667ppm

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6 USB Power Configurations

The following sections illustrate possible USB power configurations for the FT234XD. The illustrations

have omitted pin numbers for ease of understanding since the pins differ between the FT234XDS and

FT234XDQ package options.

All USB power configurations illustrated apply to both package options for the FT234XD device. Please

refer to Section 9 for the package option pin-out and signal descriptions.

6.1 USB Bus Powered Configuration

VCC

Ferrite

Bead

1

VCC

27R

2

USBDM

3

4

27R

USBDP

47pF

FT234XD

5

RESET#

VCCIO

SHIELD

10nF

GND

VCC

3V3OUT

D

N

D

GND

N

G

A

G

100nF

+

4.7uF

100nF

GND

Figure 6.1 Bus Powered Configuration

Figure 6.1 Illustrates the FT234XD in a typical USB bus powered design configuration. A USB bus

powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows –

i)

ii)

iii)

On plug-in to USB, the device should draw no more current than 100mA.

In USB Suspend mode the device should draw no more than 2.5mA.

A bus powered high power USB device (one that draws more than 100mA) should use the

CBUS pin configured as PWREN# and use it to keep the current below 100mA on plug-in and

2.5mA on USB suspend.

iv)

v)

A device that consumes more than 100mA cannot be plugged into a USB bus powered hub.

No device can draw more than 500mA from the USB bus.

The power descriptors in the internal MTP memory of the FT234XD should be programmed to match the

current drawn by the device.

A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT234XD

and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite

Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available

from Laird Technologies (http://www.lairdtech.com) for example Laird Technologies Part

MI0805K601R-10.

#

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6.2 Self Powered Configuration

VCC(3.3-5.25V)

1

VCC

27R

2

3

USBDM

27R

USBDP

4

47pF

4k7

FT234XD

5

VBUS_SENSE

SHIELD

VCCIO

RESET#

10k

GND

3V3OUT

D

N

G

A

G

GND

VCC

100nF

+

4.7uF

GND

Figure 6.2 Self Powered Configuration

Figure 6.2 illustrates the FT234XD in a typical USB self powered configuration. A USB self powered device

gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic

rules for USB self powered devices are as follows –

i) A self powered device should not force current down the USB bus when the USB host or hub

controller is powered down.

ii) A self powered device can use as much current as it needs during normal operation and USB

suspend as it has its own power supply.

iii) A self powered device can be used with any USB host, a bus powered USB hub or a self powered

USB hub.

The power descriptor in the internal MTP memory of the FT234XD should be programmed to a value of

zero (self powered).

In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the

VBUS_Sense pin of the FT2234XD device. When the USB host or hub is powered up an internal 1.5kΩ

resistor on USBDP is pulled up to +3.3V, thus identifying the device as a full speed device to the USB

host or hub. When the USB host or hub is powered off, VBUS_Sense pin will be low and the FT234XD is

held in a suspend state. In this state the internal 1.5kΩ resistor is not pulled up to any power supply

(hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to

do this may cause some USB host or hub controllers to power up erratically.

Figure 6.2 illustrates a self powered design which has a +3.3V to +5.25V supply.

Note:

1. When the FT234XD is in reset, the UART interface I/O pins are tri-stated. Input pins have internal

75kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external

logic.

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6.3 USB Bus Powered with Power Switching Configuration

P Channel Power

MOSFET

Switched 5V Power to

External Logic

0.1uF

100k

1k

PWREN#

Ferrite

Bead

1

VCC

27R

2

3

USBDM

USBDP

4

47pF

FT234XD

5

RESET#

VCCIO

SHIELD

10nF

GND

VCC

3V3OUT

CBUS0

D

N

D

GND

N

G

A

G

100nF

+

4.7uF

100nF

GND

Figure 6.3 Bus Powered with Power Switching Configuration

A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a

total current of less than 2.5mA. This requirement includes external logic. Some external logic has the

ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic

that cannot power itself down in this way, the FT234XD provides a simple but effective method of turning

off power during the USB suspend mode.

Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external

logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It

is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used

to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the

transient power surge, caused when the MOSFET switches on, will reset the FT234XD or the USB

host/hub controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of

approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in

approximately 400 microseconds.

As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A

suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or

equivalent.

With power switching controlled designs the following should be noted:

i) The external logic to which the power is being switched should have its own reset circuitry to

automatically reset the logic when power is re-applied when moving out of suspend mode.

ii) Set the Pull-down on Suspend option in the internal FT234XD MTP memory.

iii) The CBUS0 Pin should be configured as PWREN# in the internal FT234XD MTP memory, and used

to switch the power supply to the external circuitry.

iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up

to 500mA of current from the USB bus), the power consumption of the application must be set in

the Max Power field in the internal FT234XD MTP memory. A high-power bus powered application

uses the descriptor in the internal FT234XD MTP memory to inform the system of its power

requirements.

v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered

down using the external logic. In this case use the +3V3OUT.

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7 Application Examples

The following sections illustrate possible applications of the FT234XD.

7.1 USB to RS232 Converter

VBUS

C1

C2

R1

R5

10k

U2

C8 0.1uF

4.7uF 0.1uF 10k

C9

0.1uF

2

4

5

6

19

3

7

C1+

VCC

V+

V-

C11 0.1uF

C1-

C2+

C2-

GND

C3

C12 0.1uF GND

TXD_RS232

RTS_RS232

RXD_RS232

CTS_RS232

C10

FB1

600R/0.5A

U1

0.1uF

3

7

TXD

10 RXD

RTS#

11 CTS#

13

12

15

10

17

8

3V3OUT

TXD

RXD

RTS#

CTS#

CN1

VBUS

D-

D+

GND

1

2

3

4

GND

R2

R3

8

27R

1

12

USBDM

USBDP

16

9

2

6

SLEEP#

RESET#

CBUS0

USB

FT234XD

1

11

18

20

14

EN

NC

GND

SHDN

NC

C4

C5

C6

C7

10nF

47pF 47pF

10nF

ZT3222F

GND

GND GND

GND

Figure 7.1 Application Example showing USB to RS232 Converter

An example of using the FT234XD as a USB to RS232 converter is illustrated in Figure 7.1. In this

application, a 3V3 TTL to RS232 Level Converter IC is used on the serial UART interface of the FT234XD

to convert the 3V3 levels of the FT234XD to RS232 levels. This level shift can be done using line drivers

from a variety of vendors e.g. Zywyn. A useful feature on some of these devices is the SHDN# pin which

can be used to power down the device to a low quiescent current during USB suspend mode.

A suitable level shifting device is the Zywyn ZT3222F which is capable of RS232 communication at up to

1000k baud.

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7.2 USB to RS485 Coverter

VBUS

C1

C2

R1

4.7uF 0.1uF 10k

C8

0.1uF

GND

C3

FB1

600R/0.5A

U1

GND

0.1uF

3

7

TXD

U2

3V3OUT

TXD

RXD

RTS#

CTS#

CN1

VBUS

D-

D+

GND

10 RXD

8

11

1

8

RO

VCC

1

2

3

4

GND

R2

R3

R

1

12

2

3

7

6

Data -

Data +

USBDM

USBDP

RE

DE

27R

D

2

6

TXDEN

4

5

RESET#

CBUS0

DI

GND

ZT485EEN

USB

FT234XD

C4

C5

C6

C7

10nF

47pF 47pF

10nF

GND

GND GND

GND

Figure 7.2 Application Example Showing USB to RS485 Converter

An example of using the FT234XD as a USB to RS485 converter is shown in Figure 7.2. In this

application, a 3V3-TTL to RS485 level converter IC is used on the serial UART interface of the FT234XD to

convert the TTL levels of the FT234XD to RS485 levels.

This example uses the Zywyn ZT485EEN device. Equivalent devices are available from Maxim and

Analogue Devices. The ZT485EEN is a RS485 device in a compact 8 pin SOP package. It has separate

enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a

character is being transmitted from the UART

The TXDEN signal CBUS pin option on the FT234XD is provided for exactly this purpose and so the

transmitter enable is wired to CBUS which has been configured as TXDEN. Note that the TXDEN is

activated 1 bit period before the start bit. TXDEN is deactivated at the same time as the stop bit. This is

not configurable.

RS485 is a multi-drop network; so many devices can communicate with each other over a two wire cable

interface. The RS485 cable requires to be terminated at each end of the cable. A link (which provides the

120Ω termination) allows the cable to be terminated if the ZT3485 is physically positioned at either end

of the cable.

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7.3 USB to RS422 Converter

Q1

VBUS

IRLML6402

C1

C2

R1

R5

10k

C8

4.7uF 0.1uF 10k

0.1uF

U2

1

3

6

5

8

7

TxD-

TxD+

RxD+

RxD-

VCC

DI

Z

Y

A

B

R4

2k

GND

D

C3

FB1

600R/0.5A

R

U1

2

4

0.1uF

RO

GND

3

7

TXD

10 RXD

RTS#

11 CTS#

3V3OUT

TXD

RXD

RTS#

CTS#

CN1

VBUS

D-

D+

GND

R6

R7

120R

1

2

3

4

GND

R2

R3

8

GND

ZT490E

27R

1

12

U3

USBDM

USBDP

1

3

6

5

8

7

RTS-

RTS+

CTS+

CTS-

VCC

Z

Y

A

B

D

DI

2

6

PWREN#

RESET#

CBUS0

R

2

4

USB

RO

GND

FT234XD

C4

C5

C6

C7

10nF

C9

0.1uF

ZT490E

47pF 47pF

10nF

GND

GND GND

GND

Figure 7.3 USB to RS422 Converter Configuration

An example of using the FT234XD as a USB to RS422 converter is shown in Figure 7.3. In this

application, two TTL to RS422 Level Converter ICs are used on the serial UART interface of the FT234XD

to convert the TTL levels of the FT234XD to RS422 levels. There are many suitable level converter

devices available. This example uses Zywyn ZT490E devices. P-Channel MOSFET connected in the VCC

line of ZT490E ensures that USB standby current of 2.5mA is not exceeded.

The ZT490E is specified to transmit and receive data at a rate of up to 10 Mbaud. In this example the

maximum data rate is limited to 3 Mbaud by the FT234XD.

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7.4 USB Battery Charging Detection

A recent addition to the USB specification (http://www.usb.org/developers/docs/devclass_docs/BCv1.2_070312.zip)

is to allow for additional charging profiles to be used for charging batteries in portable devices. These

charging profiles do not enumerate the USB port of the peripheral. The FT234XD device will detect that a

USB compliant dedicated charging port (DCP) is connected. Once detected while in suspend mode, a

battery charge detection signal is provided to allow external logic to switch to charging mode as opposed

to operation mode.

VBUS

3V3OUT

VBUS 3V3OUT

VBUS

3V3OUT

0.1uF

600R/2A

3V3OUT

CN USB

VBUS

1

2

3

4

5

GND

D-

D+

ID

DM

DP

27R

GND

RESET#

10nF

N.F.

BCD

0.1uF

CBUS0

FT234XD

0R

SLD GND

GND

VBUS VBUS

VBUS

VBATT

4.7uF

0.1uF

1

2

3

4

5

10

9

8

7

6

CHRG

VCC

FAULT

TIMER

GND

ACPR

GND GND

BAT

SHDN

PROG

NTC

1

+

NCT

-

BCD

NTC

TB3.5mm

LTC4053EDD

0.1uF

1uF

1R

2K2

1K5

GND

GND GND

1A when connected to a dedicated charger port

0A when enumerated

0A when not enumerated and not in sleep

0A when in sleep

EEPROM Setting

VBUS

Battery Options

X-Chip Pin

CBUS0

Function

BCD

Battery Charger Enable

Force Power Enable

X

NTC

JP1

NCT Available

4K32 1%

De-acticate Sleep

1-2 NCT Enabled

2-3 NCT Disabled (Default)

JP1

SIP-3

JUMPER-2mm

GND

Figure 7.4 USB Battery Charging Detection

To use the FT234XD with battery charging detection the CBUS0 pin must be reprogrammed to allow for

the BCD Charger output to switch the external charger circuitry on. The CBUS0 pin is configured in the

internal MTP memory with the free utility FT_PROG. If the charging circuitry requires an active low signal

to enable it, the CBUS0 pin can be programmed to BCD Charger# as an alternative.

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When connected to a USB compliant dedicated charging port (DCP, as opposed to a standard USB host)

the device USB signals will be shorted together and the device suspended. The BCD charger signal will

bring the LTC4053 out of suspend and allow battery charging to start. The charge current in the example

above is 1A as defined by the resistance on the PROG pin.

To calculate the equivalent resistance on the PROG pin select a charge current, then Res = 1500V/Ichg

For more configuration options of the LTC4053 refer to:

AN_175_Battery Charging Over USB

Note: If the FT234XD is connected to a standard host port such that the device is enumerated the battery

charge detection signal is inactive as the device will not be in suspend.

7.5 LED Interface

The CBUS0 I/O pin can be configured to drive an LED. The FT234XD has 3 configuration options for

driving LEDs from the CBUS. These are TXLED#, RXLED#, and TX&RXLED#. Refer to Section 3.2 for

configuration options.

VCCIO

270R

FT234XD

TX &

RXLED#

CBUS0

Figure 7.5 Single LED Configuration

An example of using the FT234XD to drive an LED is shown in Figure 7.57. In this example the CBUS0 pin

is used to indicate when data is being transmitted or received by the device (TX&RXLED). In this

configuration the FT234XD will drive only a single LED.

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8 Internal MTP Memory Configuration

The FT234XD includes an internal MTP memory which holds the USB configuration descriptors, other

configuration data for the chip and also user data areas. Following a power-on reset or a USB reset the

FT234XD will scan its internal MTP memory and read the USB configuration descriptors stored there.

In many cases, the default values programmed into the MTP memory will be suitable and no re-

programming will be necessary. The defaults can be found in Section 8.1.

The MTP memory in the FT234XD can be programmed over USB if the values need to be changed for a

particular application. Further details of this are provided from section 8.2 onwards.

Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their

design can apply to FTDI for a free block of unique PIDs. See TN_100 – USB Vendor ID/Product ID

Guidelines for more details.

8.1 Default Values

The default factory programmed values of the internal MTP memory are shown in Table 8.1.

Parameter

Value

Notes

USB Vendor ID (VID)

USB Product UD (PID)

Serial Number Enabled?

0403h

6015h

Yes

FTDI default VID (hex)

FTDI default PID (hex)

A unique serial number is generated and

programmed into the MTP memory during device

final test.

Serial Number

See Note

Enabling this option will make the device pull down

on the UART interface lines when in USB suspend

mode (PWREN# is high).

Pull down I/O Pins in USB

Suspend

Disabled

FTDI

Manufacturer Name

Product Description

FT234XD BASIC

UART

Max Bus Power Current

Power Source

90mA

Bus Powered

FT234XD

Device Type

Returns USB 2.0 device description to the host.

Note: The device is a USB 2.0 Full Speed device

(12Mb/s) as opposed to a USB 2.0 High Speed

device (480Mb/s).

USB Version

0200

Taking RI# low will wake up the USB host controller

from suspend in approximately 20 ms.

Remote Wake Up

Disabled

4mA

DBUS Drive Current

Strength

Options are 4mA, 8mA, 12mA, 16mA

DBUS slew rate

Slow

Options are slow or fast

Normal

Options are normal or Schmitt

DBUS Schmitt Trigger

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Parameter

Value

Notes

Enable

CBUS Drive Current

Strength

4mA

Slow

Options are 4mA, 8mA, 12mA, 16mA

Options are slow or fast

CBUS slew rate

CBUS Schmitt Trigger

Enable

Normal

Options are normal or Schmitt

Makes the device load the VCP driver interface for

the device.

Load VCP Driver

CBUS0

Enabled**

TXDEN

Default configuration of CBUS0 – Transmit data

enable for RS485

Invert TXD

Invert RXD

Invert RTS#

Invert CTS#

Disabled

Signal on this pin becomes TXD# if enable.

Signal on this pin becomes RXD# if enable.

Signal on this pin becomes RTS if enable.

Signal on this pin becomes CTS if enable.

Table 8.1 Default Internal MTP Memory Configuration

8.2 Methods of Programming the MTP Memory

8.2.1 Programming the MTP memory over USB

The MTP memory on all FT-X devices can be programmed over USB. This method is the same as for the

EEPROM on other FTDI devices such as the FT232R. No additional hardware, connections or programming

voltages are required. The device is simply connected to the host computer in the same way that it would

be for normal applications, and the FT_Prog utility is used to set the required options and program the

device.

The FT_Prog utility is provided free-of-charge from the FTDI website, and can be found at the link below.

The user guide is also available at this link.

http://www.ftdichip.com/Support/Utilities.htm#FT_Prog

Additionally, D2XX commands can be used to program the MTP memory from within user applications.

For more information on the commands available, please see the D2XX Programmers Guide below.

http://www.ftdichip.com/Support/Documents/ProgramGuides/D2XX_Programmer's_Guide(FT_000071).p

df

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8.3 Memory Map

The FT-X family MTP memory has various areas which come under three main categories:



User Memory Area

Configuration Memory Area (writable)

Configuration Memory Area (non-writable)

Memory Area Description

Word Address

0x3FF - 0x80

User Memory Area 2

Accessible via USB

Configuration Memory Area

Accessible via USB

0x7E - 0x50

0x4E - 0x40

0x3E - 0x12

0x10 - 0x00

Configuration Memory Area

Cannot be written

User Memory Area 1

Accessible via USB

Configuration Memory Area

Accessible via USB

Figure 8.1: Simplified memory map for the FT-X

User Memory Area

The User Memory Areas are highlighted in Green on the memory map. They can be read and written via

USB on the FT234XD. All locations within this range are freely programmable; no areas have special

functions and there is no checksum for the user area.

Note that the application should take into account the specification for the number of write cycles in

Section 5.3 if it will be writing to the MTP memory multiple times.

Configuration Memory Area (writable)

This area stores the configuration data for the device, including the data which is returned to the host in

the configuration descriptors (e.g. the VID, PID and string descriptions) and also values which set the

hardware configuration (the signal assigned to each CBUS pin for example).

These values can have a significant effect on the behaviour of the device. Steps must be taken to ensure

that these locations are not written to un-intentionally by an application which is intended to access only

the user area.

This area is included in a checksum which covers configuration areas of the memory, and so changing

any value can also cause this checksum to fail.

Configuration Memory Area (non-writable)

This is a reserved area and the application should not write to this area of memory. Any attempt to write

these locations will fail

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9 Package Parameters

The FT234XD is available in a DFN-12 package. The solder reflow profile is described in Section 9.2.

9.1 DFN-12 Package Mechanical Dimensions

Figure 9.1 DFN-12 Package Dimensions

The FT234XD is supplied in a RoHS compliant leadless DFN-12 package. The package is lead (Pb) free,

and uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.

This package is nominally 3.00mm x 3.00mm. The solder pads are on a 0.45mm pitch. The above

mechanical drawing shows the DFN-12 package. Refer to the WDFN column in Figure 9.13. All

dimensions are in millimetres.

The centre pad on the base of the FT234XD is internally connected to ground.

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9.2 DFN-12 Package Markings

1

12

FTDI

XXXXXXXXXX

FT234XD

Q

YYWW-B

6

7

Figure 9.2 DFN-12 Package Markings

The date code format is YYWW where XX = 2 digit week number, WW = 2 digit year number. This is

followed by the revision number.

The code XXXXXXX is the manufacturing LOT code.

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9.3 Solder Reflow Profile

The FT234XD is supplied in a Pb free DFN-12 package. The recommended solder reflow profile is shown

in Figure 9.35.

t_p

T

p

Critical Zone: when

T is in the range

Ramp Up

T to T

p

L

T

L

t_L

T Max

S

Ramp

Down

T Min

S

t_S

Preheat

25

T = 25º C to T_P

Time, t (seconds)

Figure 9.3 FT234XD Solder Reflow Profile

The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both

a completely Pb free solder process (i.e. the FT234XD is used with Pb free solder), and for a non-Pb free

solder process (i.e. the FT234XD is used with non-Pb free solder).

Profile Feature

Pb Free Solder Process

Non-Pb Free Solder Process

Average Ramp Up Rate (T_sto T_p)

3°C / second Max.

3°C / Second Max.

Preheat

- Temperature Min (T_sMin.)

- Temperature Max (T_sMax.)

- Time (t_sMin to t_sMax)

100°C

150°C

200°C

60 to 120 seconds

Time Maintained Above Critical Temperature

T_L:

217°C

183°C

- Temperature (T_L)

- Time (t_L)

60 to 150 seconds

Peak Temperature (T_p)

260°C

240°C

Time within 5°C of actual Peak Temperature

(t_p)

20 to 40 seconds

Ramp Down Rate

6°C / second Max.

8 minutes Max.

6°C / second Max.

6 minutes Max.

Time for T= 25°C to Peak Temperature, T_p

Table 9.1 Reflow Profile Parameter Values

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10 Contact Information

Head Office – Glasgow, UK

Branch Office – Tigard, Oregon, USA

Unit 1, 2 Seaward Place, Centurion Business Park

Glasgow G41 1HH

United Kingdom

Tel: +44 (0) 141 429 2777

Fax: +44 (0) 141 429 2758

7130 SW Fir Loop,

Tigard, OR 97223

USA

Tel: +1 (503) 547 0988

Fax: +1 (503) 547 0987

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries) admin1@ftdichip.com

sales1@ftdichip.com

support1@ftdichip.com

E-Mail (Sales)

E-Mail (Support)

E-Mail (General Enquiries)

us.sales@ftdichip.com

us.support@ftdichip.com

us.admin@ftdichip.com

Branch Office – Taipei, Taiwan

Branch Office – Shanghai, China

2F, No. 516, Sec. 1, NeiHu Road

Taipei 114

Taiwan , R.O.C.

Room 408, 317 Xianxia Road,

Shanghai, 200051

China

Tel: +886 (0) 2 8791 3570

Fax: +886 (0) 2 8791 3576

Tel: +86 21 62351596

Fax: +86 21 62351595

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries) tw.admin1@ftdichip.com

tw.sales1@ftdichip.com

tw.support1@ftdichip.com E-mail (Support)

E-mail (Sales)

cn.sales@ftdichip.com

cn.support@ftdichip.com

cn.admin@ftdichip.com

E-mail (General Enquiries)

Web Site

http://ftdichip.com

System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology

Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level

performance requirements. All application-related information in this document (including application descriptions, suggested

FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this

information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications

assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the

user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from

such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is

implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product

described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent

of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,

Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640

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Appendix A – References

Useful Application Notes

http://www.ftdichip.com/Support/Documents/AppNotes/AN_232R-

01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_

000067).pdf

http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility.

pdf

http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf

http://www.ftdichip.com/Documents/InstallGuides.htm

http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_100_USB_VID-PID_Guidelines.pdf

http://www.ftdichip.com/Support/Documents/AppNotes/AN_175_Battery%20Charging%20Over%20USB

%20with%20FTEX%20Devices.pdf

http://www.ftdichip.com/Support/Documents/ProgramGuides/D2XX_Programmer's_Guide(FT_000071).p

df

http://www.usb.org/developers/docs/devclass_docs/BCv1.2_070312.zip

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Appendix B - List of Figures and Tables

List of Figures

Figure 2.1 FT234XD Block Diagram.................................................................................................4

Figure 3.1 DFN Schematic Symbol ..................................................................................................7

Figure 6.1 Bus Powered Configuration ........................................................................................... 20

Figure 6.2 Self Powered Configuration........................................................................................... 21

Figure 6.3 Bus Powered with Power Switching Configuration ............................................................ 22

Figure 7.1 Application Example showing USB to RS232 Converter..................................................... 23

Figure 7.2 Application Example Showing USB to RS485 Converter .................................................... 24

Figure 7.3 USB to RS422 Converter Configuration........................................................................... 25

Figure 7.4 USB Battery Charging Detection.................................................................................... 26

Figure 7.5 Single LED Configuration .............................................................................................. 27

Figure 8.1: Simplified memory map for the FT-X ............................................................................ 30

Figure 9.1 DFN-12 Package Dimensions......................................................................................... 31

Figure 9.2 DFN-12 Package Markings ............................................................................................ 32

Figure 9.3 FT234XD Solder Reflow Profile ...................................................................................... 33

List of Tables

Table 3.1 Power and Ground ..........................................................................................................7

Table 3.2 Common Function pins....................................................................................................8

Table 3.3 UART Interface and CBUS Group (see note 1) ....................................................................8

Table 3.4 CBUS Configuration Control ........................................................................................... 10

Table 5.1 Absolute Maximum Ratings............................................................................................ 14

Table 5.2 Operating Voltage and Current ....................................................................................... 15

Table 5.3 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins)........................................... 16

Table 5.4 I/O Pin Characteristics VCCIO = +2.5V (except USB PHY pins)........................................... 17

Table 5.5 I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins)........................................... 18

Table 5.6 USB I/O Pin (USBDP, USBDM) Characteristics .................................................................. 19

Table 5.7 MTP Memory Characteristics........................................................................................... 19

Table 5.8 Internal Clock Characteristics......................................................................................... 19

Table 8.1 Default Internal MTP Memory Configuration ..................................................................... 29

Table 9.1 Reflow Profile Parameter Values ..................................................................................... 33

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FT234XD USB TO BASIC UART IC

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Appendix C - Revision History

Document Title:

USB to BASIC UART IC FT234XD

Document Reference No.:

Clearance No.:

FT_000753

FTDI#324

Product Page:

http://www.ftdichip.com/FT-X.htm

Send Feedback

Document Feedback:

Version 1.0

Version 1.1

Version 1.2

First release

Updated TID info. Added clarification that we are 5V tolerant February 2013

Added reference to WDFN chip dimensions Aug 2015

January 2013

37


型号：	FT234XD
厂家：	FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD.
描述：	The FT234XD is a USB to serial UART interface with optimised packaging (3mm x 3mm 12 pin DFN) for smaller PCB designs and the following advanced features PC
文件：	总37页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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