FTD5830B18 [FS]

3A Low Drop Regulaotr With Enable;


型号：	FTD5830B18
厂家：	First Silicon Co., Ltd
描述：	3A Low Drop Regulaotr With Enable
文件：	总16页 (文件大小：1375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SEMICONDUCTOR

FTD5830B

TECHNICAL DATA

3A Low Drop Regulaotr With Enable

General Description

Features

The FTD5830 is a high performance positive voltage

� Adjustable Output Low to 0.8V

regulator designed for use in applications requiring very � Input Voltage as Low as 1.6V and VPP Voltage 5V

low Input voltage and very low dropout voltage at up to 3 � 240mV Dropout @ 3A

amps. It operates with a V as low as 1.6V and VPP

� Over Current and Over Temperature Protection

voltage 5V with output voltage programmable as low as � Enable Pin

0.8V. The FTD5830 features ultra low dropout, ideal for � Low Reverse Leakage (Output to Input )

applications where V is very close to V .

� Power SOP8 –E Packages with Thermal Pad

� ±2% Output Voltage

OUT

Additionally, the FTD5830 has an enable pin to further

reduce power dissipation while shutdown. The FTD5830 � VO Power OK Signal

provides excellent regulation over variations in line,

� 1.2V, 1.5V, 1.8V, 2.5V Options and Adjustable

load and temperature. The FTD5830 provides a power OK � Externally Using Resistors

signal to indicate if the voltage level of VO reaches

92% of its rating value.

� VO Pull Low Resistance when Disable

The FTD5830 is available in the power SOP-8E pack-

age. It is available with 1.2V, 1.5V, 1.8V and 2.5V in-

ternally preset outputs that are also adjustable using

external resistors.

Applications

� Motherboards

� Peripheral Cards

� Network Cards

� Set Top Boxes

� Notebook Computers

Package Types

SOP-8E

Figure 1. Package Types of FTD5830

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FTD5830B

Pin Assignments

PIN NAME

PGOOD Assert high once VO reaches 92% of

its rating voltage. Open-drain output.

Enable Input. (Active High)

Input voltage. Large bulk capacitance

should be placed closely to this pin. A

10µF ceramic capacitor is

VIN

recommended at this pin.

VDD

Input voltage for controlling circuit.

Not connected.

VOUT

The power output of the device. A pull

low resistance exists when deactivate

device by VEN.

ADJ

This pin, FTD5830B when grounded,

sets the output voltage by the internal

feedback resistors.If external feedback

resistors are used, the output voltage

will be

VO = 0.8(R1+R2)/R2 Volts.

Reference ground.

GND

Ordering Information

FTD5830A/B

□

Circuit Type

Output Versions

Blank：Adj

12：1.2V

15：1.5V

18：1.8V

25：2.5V

Enable Pin Function&ADJ Pin Function

A:Enable Pin Internal Pull High, Active High

ADJ Pin grounded output voltage by the internal feedback resistors

B:Enable Pin Internal Pull Low, Active High

ADJ Pin grounded output voltage by the internal feedback resistors

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FTD5830B

Functional Block Diagram

Figure2: Functional Block Diagram of FTD5830

Absolute Maximum Ratings

Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated i

periods may affect reliability.

n the operation is not implied. Exposure to absolute maximum rating conditions for extended

Parameter

VCNTL Supply Voltage (VCNTL to GND)

VIN Supply Voltage (VIN to GND)

VOUT to GND Voltage

Rating

Unit

-0.3 ~ 6

-0.3 ~ VIN+0.3

-0.3 ~ 7

POK to GND Voltage

EN, FB to GND Voltage

-0.3 ~ VCNTL+0.3

Internally Limited

150

Power Dissipation

Maximum Junction Temperature

Storage Temperature Range

ºC

-65°C ≤T ≤+150

Reflow Temperature (soldering, 10sec)

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Operating Temperature Range

Storage Temperature

260

ºC

°C/W

ºC

-40 to +125

-65 to +150

260

ºC

Lead Temperature (Soldering, 10 sec)

ESD Rating (Human Body Model)

ºC

2000

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FTD5830B

Recommended Operating Conditions

Symbol

VDD

VIN

Parameter

Range

Unit

VCNTL Supply Voltage

VIN Supply Voltage

3.0 ~ 5.5

1.2 ~ 5.5

0.8 ~ VIN – VDROP

0 ~ 3

VOUT

IOUT

VOUT Output Voltage (when VCNTL-VOUT>1.7V)

VOUT Output Current

ADJ to GND

1k ~ 24k

8~770

IOUT = 3A at 25% nominal VOUT

COUT

VOUT Output Capacitance

IOUT = 1.5A at 25% nominal VOUT 8~1400

IOUT = 0.5A at 25% nominal VOUT 8~1700

ESRCOUT ESR of VOUT Output Capacitor

0 ~ 200

mΩ

ºC

Ambient Temperature

Junction Temperature

-40 ~ 85

-40 ~ 125

ºC

Electrical Characteristics

Note:Refer to the typical application circuits. These specifications apply over VCNTL=5V, vN=1.8v, VOUT=1.2V, and TA= -40 ~ 85oC, unless otherwise specified.

Typical values are at T^J=25oC.

Symbol

Parameter

Test Conditions

Min.

2.4

0.15

Typ.

2.7

Max. Unit

POR Threshold

POR Hysteresis

0.2

V_{TH_ADJ}

V_ADJ

Adjustable Pin Threshold

Reference Voltage

Fixed Output Voltage Range

I_OUT=1mA

0.2

0.4

0.816

0.6

FB=V_outI_OUT=1mA T_J=25 ºC

0.784 0.8

Δ V_OUT

-2

Δ V_{LINE_IN}Line Regulation(V_IN)

V_IN=V_OUT+0.5V TO 5V

I_OUT=1mA

0.2

Δ V_LOAD

Load Regulation

V_IN=V_OUT+1V

I_OUT=1mA TO 3A

I_OUT= 3A

0.1

V_DROP

I_Q

Dropout Voltage

210

0.6

4.5

1.8

0.6

150

350

1.2

Quiescent Current

Current Limit

V_DD=5.5V

I_LIM

3.2

0.5

Short Circuit Current

In-rush Current

V_OUT<0.2V

C_OUT=10uF,Enable Start-up

V_EN=0V

V_OUTPull-Low Resistance

Chip Enable

V_EN=0V

IEN

EN Input Bias Current

VDD Shutdown Current

ISHDN

FTD5830A

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FTD5830B

V_ENL

V_ENH

EN Threshold

Logic-Low Voltage

Logic-High Voltage

0.2

1.2

Power Good

PGOOD Rising Threshold

PGOOD Hysteresis

PGOOD Sink Capability

PGOOD Delay

I_PGOOD=10mA

0.2

1.5

0.4

0.5

Thermal Protection

T_SD

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

160

ºC

Δ T_SD

Thermal Shutdown Temperature V_OUT<0.4V

Fold-back

110

Typical Operating Characteristics

Current-Limit vs.

Short Current-Limit vs.

Junction Temperature

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FTD5830B

Typical Operating Characteristics (Cont.)

Dropout Voltage vs. Output Current

Droput Voltage vs. Output Current

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FTD5830B

Typical Operating Characteristics (Cont.)

Reference Voltage vs.

Droput Voltage vs. Output Current

Junction Temperature

VCNTL Power Supply Rejection

Ratio (PSRR)

VIN Power Supply Rejection

Ratio (PSRR)

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FTD5830B

Operating Waveforms

Refer to the typical applicaꢀon circuit. The test condiꢀon is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise speciﬁed

Power On

Power Off

COUT=10�F, CIN=10�F, RL=0.6��TIME: 5ms/Div

COUT=10�F, CIN=10�F, RL=0.6��TIME: 10ms/Div

CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC

CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC

CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC

CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC

Load Transient Response

Over Current Protection

COUT=10mF, CIN=10mF, IOUT=1A to 5.1A

IOUT=10mA to 3A to 15mA (rise / fall ꢀme = 1�s) COUT=10�F, CIN=10�F

CH1: VOUT, 50mV/Div, AC/CH4: IOUT, 1.5A/Div, DC/ TIME: 20�s/Div

CH1: VOUT, 1V/Div, DC/ CH4: IOUT, 1.5A/Div, DC/ TIME: 0.2ms/Div

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FTD5830B

OperatingWaveforms (Cont.)

Refer to the typical applicaꢀon circuit. The test condiꢀon is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise speciﬁed

Shutdown

Enable

COUT=10mF, CIN=10mF, RL=0.6W/ TIME: 5us/Div

CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC

CH3: VPOK, 5V/Div, DC/CH4: IOUT, 3A/Div, DC

COUT=10mF, CIN=10mF, RL=0 6W/ TIME: 0.5ms/Div

CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC

CH3: VPOK, 5V/Div, DC/CH4: IOUT, 3A/Div, DC

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FTD5830B

Typical Application Circuit

FTD5830B

Figure3:Fixed Voltage Regulator Application Circuit of FTD5830B

FTD5830B

Figure4:Adjustable Voltage Regulator Application Circuit of FTD5830B

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FTD5830B

Function Description

Power-On-Reset

Short Current-Limit Protection

A Power-On-Reset (POR) circuit monitors both of supply The short current-limit function reduces the current-limit

voltages on VCNTL and VIN pins to prevent wrong logic level down to 0.8A (typical) when the voltage on FB pin

controls. The POR function initiates a soft-start process

falls below 0.2V (typical) during current overload or

after both of the supply voltages exceed their rising POR shortcircuit conditions.

voltage thresholds during powering on. The POR

The short current-limit function is disabled for successful

function also pulls low the POK voltage regardless of the start-up during soft-start.

output status when one of the supply voltages falls below

its falling POR voltage threshold.

Thermal Shutdown

Internal Soft-Start

A thermal shutdown circuit limits the junction

temperature of FTD5830. When the junction temperature

exceeds +170 ºC, a thermal sensor turns off the output

NMOS, allowing the device to cool down. The regulator

regulates the output again through initiation of a new

soft-start process after the junction temperature cools by

50oC, resulting in a pulsed output during continuous

thermal overload conditions. The thermal shutdown is

designed with a 50 ºC hysteresis to lower the average

junction temperature during continuous thermal overload

conditions, extending lifetime of the device.

An internal soft-start function controls rise rate of the

output voltage to limit the current surge during start-up.

The typical soft-start interval is about 0.6ms.

Output Voltage Regulation

An error amplifier working with a temperature

compensated 0.8V reference and an output NMOS

regulates output to the preset voltage. The error amplifier

is designed with high bandwidth and DC gain provides

very fast transient response and less load regulation. It

compares the reference with the feedback voltage and

amplifies the difference to drive the output NMOS which

provides load current from VIN to VOUT.

For normal operation, the device power dissipation

should be externally limited so that junction temperatures

will not exceed +125 ºC.

Enable Control

The FTD5830A/B has a dedicated enable pin (EN).

FTD5830A:A logic low signal applied to this pin shuts

down the output. Following a shutdown, a logic high

signal re-enables the output through initiation of a new

soft-start cycle. When left open, this pin is pulled up by

an internal current source (5uA typical) to enable normal

operation. It’s not necessary to use an external transisto

Current-Limit Protection

The FTD5830 monitors the current flowing through the

output NMOS and limits the maximum current to prevent

load and FTD5830 from damages during current overload

conditions.

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FTD5830B

Function Description (Cont.)

to save cost.

FTD5830B:A logic low signal applied to this pin shuts

down the output. Following a shutdown, a logic high

signal re-enables the output through initiation of a new

soft-start cycle. When left open, this pin is pulled up by

an internal current source (5uA typical) to turn off

operation.

Power-OK and Delay

The FTD5830 indicates the status of the output voltage by

monitoring the feedback voltage (VFB) on FB pin. As the

VFB rises and reaches the rising Power-OK voltage

threshold(VTHPOK), an internal delay function starts to

work. At the end of the delay time, the IC turns off the

internal NMOS of the POK to indicate the output is ok. As

the VFB falls and reaches the falling Power-OK voltage

threshold, the IC turns on the NMOS of the POK ( after a

debounce time of 10ms typical ).

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FTD5830B

Application Information

Ultra-low-ESR capacitors (such as ceramic chip

capacitors) and low-ESR bulk capacitors (such as solid

tantalum, POSCap, and Aluminum electrolytic

capacitors) can all be used as output capacitors.

During load transients, the output capacitors which is

depending on the stepping amplitude and slew rate of

load current, are used to reduce the slew rate of the

current seen by the FTD5830 and help the device to

minimize the variations of output voltage for good

transient response. For the applications with large

stepping load current, the low-ESR bulk capacitors are

normally recommended.

Power Sequencing

The power sequencing of VIN and VCNTL is not

necessary to be concerned. However, do not apply a

voltage to VOUT for a long time when the main voltage

applied at VIN is not present. The reason is the internal

parasitic diode from VOUT to VIN conducts and

dissipates power without protections due to the

forward-voltage.

Decoupling ceramic capacitors must be placed at the

load and ground pins as close as possible and the

impedance of the layout must be minimized.

Output Capacitor

The FTD5830 requires a proper output capacitor to

maintain stability and improve transient response. The

output capacitor selection is dependent upon ESR

(equivalent series resistance) and capacitance of the

output capacitorover the operating temperature.

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FTD5830B

Application Information (Cont.)

Input Capacitor

Setting The Output Voltage

The FTD5830 requires proper input capacitors to supply The output voltage is programmed by the resistor divider

current surge during stepping load transients to prevent

the input voltage rail from dropping. Because the

parasitic inductor from the voltage sources or other bulk

capacitors to the VIN pin limit the slew rate of the surge

currents, more parasitic inductance needs more input

capacitance.

connected to FB pin. The preset output voltage is

calculated by the following equation :

where R1 is the risistor connected from VOUT to FB with

Kelvin sensing connection and R2 is the risistor

Ultra-low-ESR capacitors (such as ceramic chip

capacitors) and low-ESR bulk capacitors (such as solid

connected from FB to GND. A bypass capacitor(C1) may

tantalum, POSCap, and Aluminum electrolytic capacitors be connected with R1 in parallel to improve load

can all be used as an input capacitor of VIN. For most

applications, the recommended input capacitance of VIN

is 10uF at least. However, if the drop of the input voltage

is not cared, the input capacitance can be less than

10uF. More capacitance reduces the variations of the

supply voltage on VIN pin.

transient response and stability.

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FTD5830B

Layout Consideration (See Figure A)

1. Please solder the Exposed Pad on the system ground

pad on the top-layer of PCBs. The ground pad must have

Thermal Consideration

wide size to conduct heat into the ambient air through the

system ground plane and PCB as a heat sink.

2. Please place the input capacitors for VIN and VCNTL

pins near the pins as close as possible for decoupling

high-frequency ripples.

Refer to the figure B, the SOP-8E is a cost-effective

package featuring a small size like a standard SOP-8 and

a bottom exposed pad to minimize the thermal resistance

of the package, being applicable to high current

3. Ceramic decoupling capacitors for load must be placed

near the load as close as possible for decoupling

high-frequency ripples.

applications. The exposed pad must be soldered to the

top-layer ground plane. It is recommended to connect the

top-layer ground pad to the internal ground plan by using

vias. The copper of the ground plane on the top-layer

conducts heat into the PCB and ambient air. Please

enlarge the area of the top-layer pad and the ground

plane to reduce the case-to-ambient resistance (θ CA).

4. To place FTD5830 and output capacitors near the load

reduces parasitic resistance and inductance for excellent

load transient response.

5. The negative pins of the input and output capacitors

and the GND pin must be connected to the ground plane

of the load.

6. Large current paths, shown by bold lines on the figure

1, must have wide tracks.

7. Place the R1, R2, and C1 (option) near the FTD5830 as

close as to avoid noise coupling.

8. Connect the ground of the R2 to the GND pin by using

a dedicated track.

9. Connect the one pin of the R1 to the load for Kelvin

sensing.

10. Connect one pin of the C1 (option) to the VOUT pin

Figure B

Figure A

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FTD5830B

Package Information

SOP8-E Package Outline Dimensions

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FTD5830B18 [FS]

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