SPC5705BEMLQR [FREESCALE]
Microcontroller; 微控制器
| 型号： | SPC5705BEMLQR |
| 厂家： | 
Freescale |
| 描述： | Microcontroller |
| 文件： | 总92页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5607B
Rev. 3, 01/2010
MPC5607B
MPC5607B Microcontroller
Data Sheet
208 MAPBGA (17 x 17
)
100 LQFP (14 x 14 )
144 LQFP (20 x 20 )
176LQFP (24 x 24)
Features
•
•
Up to 6 serial peripheral interface (DSPI) modules
Up to 10 serial communication interface (LINFlex)
modules
•
Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture™
embedded category
•
Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
— Enhanced instruction set allowing variable
length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed
16-bit and 32-bit instructions, it is possible to
achieve significant code size footprint
reduction.
2
•
•
1 inter-integrated circuit (I C) interface module
Up to 149 configurable general purpose pins
supporting input and output operations (package
dependent)
•
Real-Time Counter (RTC)
•
Up to 1.5 Mbytes on-chip Flash supported with the
Flash controller
— Clock source from internal 128 kHz or 16 MHz
oscillator supporting autonomous wakeup with
1 ms resolution with maximum timeout of 2
seconds
•
•
Up to 96 Kbytes on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity on certain
family members
— Optional support for RTC with clock source
from external 32 kHz crystal oscillator,
supporting wakeup with 1 sec resolution and
maximum timeout of 1 hour
•
Interrupt controller (INTC) capable of handling 204
selectable-priority interrupt sources
•
•
•
Up to 8 periodic interrupt timers (PIT) with 32-bit
counter resolution
•
•
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or RAM from multiple bus
masters
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus
Device/board boundary scan testing supported per
Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
•
•
•
16-channel eDMA controller with multiple transfer
request sources using DMA multiplexer
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
•
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
Timer supports I/O channels providing a range of
16-bit input capture, output compare, and pulse
width modulation functions (eMIOS)
•
•
2 analog-to-digital converters (ADC): one 10-bit and
one 12-bit
Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or PIT
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 40
3.11 Electromagnetic compatibility (EMC) characteristics. . 40
3.11.1 Designing hardened software to avoid
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 176LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .8
2.2 144LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .9
2.3 208MAPBGA pin configuration . . . . . . . . . . . . . . . . . . .10
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .11
3.2.2 NVUSRO[OSCILLATOR_MARGIN] field
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.2 Electromagnetic interference (EMI) . . . . . . . . . 41
3.11.3 Absolute maximum ratings (electrical sensitivity)41
3.12 Fast external crystal oscillator (4 to 16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.13 Slow external crystal oscillator (32 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 48
3.15 Fast internal RC oscillator (16 MHz)
3
description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2.3 NVUSRO[WATCHDOG_EN] field description . .12
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .13
3.4 Recommended operating conditions . . . . . . . . . . . . . .14
3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .17
3.5.1 External ballast resistor recommendations . . . .17
3.5.2 Package thermal characteristics . . . . . . . . . . . .17
3.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .18
3.6 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .18
3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6.2 I/O input DC characteristics. . . . . . . . . . . . . . . .19
3.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .21
3.6.4 Output pin transition times. . . . . . . . . . . . . . . . .23
3.6.5 I/O pad current specification . . . . . . . . . . . . . . .24
3.7 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .27
3.8 Power management electrical characteristics. . . . . . . .30
3.8.1 Voltage regulator electrical characteristics . . . .30
3.8.2 Voltage monitor electrical characteristics. . . . . .33
3.9 Low voltage domain power consumption . . . . . . . . . . .35
3.10 Flash memory electrical characteristics . . . . . . . . . . . .37
3.10.1 Program/Erase characteristics. . . . . . . . . . . . . .37
3.10.2 Flash power supply DC characteristics . . . . . . .38
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.16 Slow internal RC oscillator (128 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 50
3.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.17.2 Input impedance and ADC accuracy . . . . . . . . 51
3.17.3 ADC electrical characteristics . . . . . . . . . . . . . 56
3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 64
3.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 66
3.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 73
3.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 74
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 75
4.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1.2 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.1.3 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1.4 208MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4
5
6
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
2
Freescale Semiconductor
General description
1
General description
The MPC5607B is a new family of next generation microcontrollers built on the Power Architecture™ embedded category.
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device.
The MPC5607B family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5607B automotive controller
family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding)
APU (Auxillary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high
performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of
current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist
with users implementations.
1
Table 1. MPC5607B Family Comparison
MPC5605B
MPC5606B
MPC5607B
Feature
Package
CPU
100
LQFP
144
LQFP
176
LQFP
144
LQFP
176
LQFP
176
LQFP
208 MAP
BGA2
e200z0h
Execution speed3
Code Flash
Data Flash
RAM
Up to 64 MHz
768 KB
64 KB
1 MB
1.5 MB
64 (4 x 16) Kbyte
80 KB
8-entry
16 ch
96 KB
MPU
DMA
10-bit ADC
Yes
dedicated4
shared with 12-bit ADC
12-bit ADC
7 ch
15 ch
29 ch
15 ch
29 ch
19 ch
Yes
dedicated5
5 ch
shared with 10-bit ADC
19 ch
Total timer I/O6
eMIOS
37 ch,
16-bit
64 ch,
16-bit
Counter / OPWM / ICOC7
10 ch
7 ch
O(I)PWM / OPWFMB /
OPWMCB / ICOC8
O(I)PWM / ICOC9
OPWM / ICOC10
7 ch
13 ch
4
14 ch
33 ch
SCI (LINFlex)
6
5
8
6
6
5
6
8
10
SPI (DSPI)
3
6
CAN (FlexCAN)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3
General description
1
Table 1. MPC5607B Family Comparison (continued)
MPC5605B
MPC5606B
MPC5607B
Feature
I2C
1
32 kHz oscillator
GPIO11
Yes
121
77
121
149
149
149
Debug
JTAG
N2+
1
2
3
4
5
6
7
Feature set dependent on selected peripheral multiplexing; table shows example.
208 MAPBGA package is for debug use only.
Based on 105 °C ambient operating temperature.
Not shared with 12-bit ADC, but possibly shared with other alternate functions.
Not shared with 10-bit ADC, but possibly shared with other alternate functions.
Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output
Compare.
8
9
Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output
Compare.
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and
Pulse width measurement.
10 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
11 Maximum I/O count based on multiplexing with peripherals.
1.1
Block diagram
Figure 1 shows a top-level block diagram of the MPC5607B.
MPC5607B Microcontroller Data Sheet, Rev. 3
4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
General description
RAM
96 KB
Code Flash DataFlash
1.5 MB 64 KB
JTAG
eDMA
(Master)
JTAG Port
Nexus Port
Instructions
SRAM
Controller
Flash
Controller
e200z0h
Nexus 2+
(Master)
Nexus
Data
NMI
(Slave)
(Master)
SIUL
Voltage
Regulator
(Slave)
Interrupt requests
from peripheral
blocks
(Slave)
NMI
MPU
Registers
INTC
WKPU
Clocks
CMU
FMPLL
RTC
MC_RGM MC_CGM MC_ME MC_PCU
Peripheral Bridge
SSCM
STM
PIT
BAM
SWT
ECSM
SIUL
10 x
LINFlex
64 ch
eMIOS
6 x
DSPI
6 x
FlexCAN
29 ch 10-bit
ADC
19 ch 10bit/12bit
ADC
2
CTU
I C
Reset Control
Interrupt
Request
External
Interrupt
Request
IMUX
GPIO &
Pad Control
. . .
. . .
. . .
. . .
. . .
I/O
Legend:
MC_ME
MPU
Nexus
NMI
Mode Entry Module
Memory Protection Unit
NexuS Development Interface (NDI) Level
Non-Maskable Interrupt
ADC
BAM
CAN
CMU
CTU
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network (FlexCAN)
Clock Monitor Unit
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
Cross Triggering Unit
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
Deserial Serial Peripheral Interface
PIT
RTC
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
SIUL
SRAM
SSCM
STM
SWT
JTAG controller
Serial Communication Interface (LIN support)
Software Watchdog Timer
MC_CGM Clock Generation Module
Figure 1. MPC5607B block diagram
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
5
General description
Table 2 summarizes the functions of the blocks present on the MPC5607B.
Table 2. MPC5607B series block summary
Block
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
Generates high-speed system clocks and supports programmable frequency
phase-locked loop (FMPLL)
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Periodic interrupt timer (PIT)
Real-time counter (RTC)
Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
MPC5607B Microcontroller Data Sheet, Rev. 3
6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts
Table 2. MPC5607B series block summary (continued)
Function
Block
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System timer module (STM)
Provides a set of output compare events to support AutoSAR and operating
system tasks
2
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Package pinouts
2.1
176LQFP pin configuration
LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3]
LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]
EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15]
E1UC[18]/SCK_5/GPIO[148]/PJ[4]
VDD_HV
1
2
3
4
5
6
7
8
PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3]
PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2]
PA[9]/GPIO[9]/E0UC[9]/CS2_1/FAB
PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX
PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1]
PE[13]/GPIO[77]/SOUT_2/E1UC[20]
PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX
PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX
VDD_HV
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VSS_HV
E1UC[17]/SOUT_5/GPIO[127]/PH[15]
E1UC[26]/CS0_3/SOUT_4/GPIO[125]/PH[13]
E1UC[27]/CS1_3/SCK_4/GPIO[126]/PH[14]
CS0_4/E1UC[30]/GPIO[134]/PI[6]
CS1_4/E1UC[31]/GPIO[135]/PI[7]
SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5]
SCK_3/E1UC[13]/GPIO[100]/PG[4]
WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3]
SOUT_3/E1UC[11]/GPIO[98]/PG[2]
MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2]
CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0]
WKUP[2]/NMI/E0UC[1]/GPIO[1]/PA[1]
CAN5TX/E0UC[17]/GPIO[65]/PE[1]
CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]
CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9]
EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10]
WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]
LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11]
VSS_HV
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSS_HV
PG[0]/GPIO[96]/CAN5TX/E1UC[23]
PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX
PH[3]/GPIO[115]/E1UC[5]/CS0_1
PH[2]/GPIO[114]/E1UC[4]/SCK_1
PH[1]/GPIO[113]/E1UC[3]/SOUT_1
PH[0]/GPIO[112]/E1UC[2]/SIN_1
PG[12]/GPIO[108]/E0UC[26]/SOUT_4
PG[13]/GPIO[109]/E0UC[27]/SCK_4
PA[3]/GPIO[3]/E0UC[3]/LIN5TX/CS4_1/EIRQ[0]/ADC1_S[0]
PI[13]/GPIO[141]/CS1_3/ADC0_S[21]
PI[12]/GPIO[140]/CS0_3/ADC0_S20]
PI[11]/GPIO[139]/ANS[19]/SIN_3
176 LQFP
Top view
PI[10]/GPIO[138]/ADC0_S[18]
PI[9]/GPIO[137]/ADC0_S[17]
PI[8]/GPIO[136]/ADC0_S[16]
PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]
PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]
PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]
PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]
PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]
PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]
PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0]
PD[12]/GPIO[60]/CS5_0/E0UC[24]/ADC0_S[4]
VDD_HV_ADC1
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
LIN7RX/WKUP[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9]
EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8]
CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11]
MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]
LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7]
LIN6TX/E1UC[15]/GPIO[102]/PG[6]
LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0]
CAN0RX/WKUP[4]/LIN0RX/E0UC[31]/GPIO[17]/PB[1]
CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9]
CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]
VSS_HV_ADC1
98
97
96
95
94
93
92
91
PB[11]/GPIO[27]/E0UC[3]/CS0_0/ADC0_S[3]
PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15]
PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14]
PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13]
PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3]
PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2]
PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1]
VDD_HV_ADC0
LIN5TX/E1UC[25]/GPIO[92]/PF[12]
E1UC[28]/LIN1TX/GPIO[38]/PC[6]
90
89
VSS_HV_ADC0
Note:
Availability of port pin alternate functions depends on product selection.
Figure 2. 176 LQFP pin configuration (top view)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
8
Freescale Semiconductor
Package pinouts
2.2
144LQFP pin configuration
LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3]
LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]
EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15]
SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5]
SCK_3/E1UC[13]/GPIO[100]/PG[4]
WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3]
SOUT_3/E1UC[11]/GPIO[98]/PG[2]
MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2]
CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0]
WKUP[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1]
CAN5TX/E0UC[17]/GPIO[65]/PE[1]
CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]
CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9]
EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10]
WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]
LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11]
VSS_HV
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3]
PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2]
PA[9]/GPIO[9]/E0UC[9]/FAB/CS2_1
PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX
PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1]
PE[13]/GPIO[77]/SOUT_2/E1UC[20]
PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX
PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX
VDD_HV
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS_HV
PG[0]/GPIO[96]/CAN5TX/E1UC[23]
PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX
PH[3]/GPIO[115]/E1UC[5]/CS0_1
PH[2]/GPIO[114]/E1UC[4]/SCK_1
PH[1]/GPIO[113]/E1UC[3]/SOUT_1
PH[0]/GPIO[112]/E1UC[2]/SIN_1
PG[12]/GPIO[108]/E0UC[26]/SOUT_4
PG[13]/GPIO[109]/E0UC[27]/SCK_4
PA[3]/GPIO[3]/E0UC[3]/LIN5TX/EIRQ[0]/CS4_1/ADC1_S[0]
PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]
PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]
PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]
PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]
PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]
PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]
/GPIO[28]/E0UC[4]/CS1_0
144 LQFP
Top view
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
LIN7RX/EIRQ[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9]
EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8]
CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11]
MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]
LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7]
LIN6TX/E1UC[15]/GPIO[102]/PG[6]
E0UC[30]/CAN0TX/GPIO[16]/PB[0]
LIN0RX/CAN0RX/WKUP[4]/E0UC[31]/GPIO[17]/PB[1]
CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9]
CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]
LIN5TX/E1UC[25]/GPIO[92]/PF[12]
E1UC[28]/LIN1TX/GPIO[38]/PC[6]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15]
PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14]
PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13]
PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3]
PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2]
PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1]
VDD_HV_ADC0
74
73
VSS_HV_ADC0
Note:
Availability of port pin alternate functions depends on product selection.
Figure 3. 144 LQFP pin configuration (top view)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
9
Package pinouts
2.3
208MAPBGA pin configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[8] PC[1 PH[1 PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[1 PH[1 NC
3] 5] 5] 1]
NC
A
B
C
D
A
B
C
D
PC[9] PB[2] PH[1 PC[1 PE[6] PH[5] PC[4] PH[9] PH[1 PI[2] PC[3] PG[1 PG[1 PG[1 PA[1 PA[1
3] 2] 0] 1] 5] 4] 1] 0]
PC[14 VDD_ PB[3] PE[7] PH[7] PE[5] PE[3] VSS_ PC[1] PI[3] PA[5] PI[5] PE[1 PE[1 PA[9] PA[8]
LV 4] 2]
]
HV
PH[14 PI[6] PC[1 PI[7] PH[6] PE[4] PE[2] VDD VDD NC PA[6] PH[1 PG[1 PF[1 PE[1 PA[7]
]
5]
_LV _HV
2]
0]
4]
3]
PG[4] PG[5] PG[3] PG[2]
PE[0] PA[2] PA[1] PE[1]
PG[1] PG[0] PF[1 VDD
E
F
E
F
5] _HV
PH[0] PH[1] PH[3] PH[2]
PE[9] PE[8] PE[1 PA[0]
0]
VSS_ VSS_ VSS_ VSS_
VDD PI[12 PI[13 MSE
G
G
HV
HV
HV
HV
_HV
]
]
O
VSS_ PE[1 VDD NC
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
MDO MDO MDO MDO
H
J
H
J
HV
1]
_HV
3
2
0
1
RESE VSS_ NC
NC
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
PI[8] PI[9] PI[10 PI[11
T
LV
]
]
EVTI NC VDD VDD
_BV _LV
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
VDD PG[1 PA[3] PG[1
_HV_ 2]
3]
K
K
ADC
1
PG[9] PG[8] NC EVT
O
PB[1 PD[1 PD[1 PB[1
5] 5] 4] 4]
L
L
PG[7] PG[6] PC[1 PC[1
PB[1 PD[1 PD[1 PB[1
3] 3] 2] 2]
M
M
0]
1]
_HV
PB[1] PF[9] PB[0] VDD PJ[0] PA[4] VSS_ EXTA VDD PF[0] PF[4] VSS_ PB[1 PD[1 PD[9] PD[1
LV
L
_HV
HV_
ADC
1
1]
0]
1]
N
P
N
P
PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[1 VDD XTAL PB[1 PF[1] PF[5] PD[0] PD[3] VDD PB[6] PB[7]
4]
_LV
0]
_HV_
ADC
0
PF[12 PC[6] PF[1 PF[1 VDD PA[1 PA[1 PI[14 XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_ PB[5]
]
0]
1]
_HV
5]
3]
]
HV_
ADC
0
R
T
R
T
NC
NC
NC MCK NC PF[1 PA[1 PI[15 EXTA PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4]
O
3]
2]
]
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTE: The 208 MAPBGA is available only as development package for Nexus 2+.
= Not connected
NC
Figure 4. 208 MAPBGA configuration
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
10
Freescale Semiconductor
Electrical characteristics
3
Electrical characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 3. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
3.2.1
NVUSRO[PAD3V5V] field description
Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
11
Preliminary—Subject to Change Without Notice
Electrical characteristics
1
Table 4. PAD3V5V field description
Value2
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
2
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.2.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
1
Table 5. OSCILLATOR_MARGIN field description
Value2
Description
0
1
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
1
2
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The main external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
3.2.3
NVUSRO[WATCHDOG_EN] field description
Table 5 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.
1
Table 6. WATCHDOG_EN field description
Value2
Description
0
1
Disable after reset
Enable after reset
1
2
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
12
Freescale Semiconductor
Electrical characteristics
3.3
Absolute maximum ratings
Table 7. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR
SR
Digital ground
on VSS_HV
pins
—
0
0
V
VDD
Voltage on
VDD_HV pins
with respect to
—
—
-0.3
6.0
V
ground (VSS
)
VSS_LV
VDD_BV
VSS_ADC
SR
SR
SR
Voltage on
VSS-0.1
VSS+0.1
V
V
V
VSS_LV (low
voltage digital
supply) pins
with respect to
ground (VSS
)
Voltage on
VDD_BV pin
(regulator
supply) with
respect to
—
-0.3
-0.3
6.0
Relative to VDD
VDD+0.3
ground (VSS
)
Voltage on
VSS_HV_ADC
0,
—
VSS-0.1
VSS+0.1
VSS_HV_ADC
1 (ADC
reference) pin
with respect to
ground (VSS
)
VDD_ADC
SR
Voltage on
—
-0.3
6.0
V
VSS_HV_ADC
0,
Relative to VDD
VDD −0.3
VDD+0.3
VSS_HV_ADC
1 (ADC
reference) with
respect to
ground (VSS
)
VIN
SR
Voltage on any
GPIO pin with
respect to
—
-0.3
6.0
V
Relative to VDD
VDD −0.3
VDD+0.3
ground (VSS
)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
13
Electrical characteristics
Table 7. Absolute maximum ratings (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
IINJPAD
SR
SR
SR
Injected input
current on any
pin during
overload
condition
—
-10
10
mA
IINJSUM
Absolute sum
of all injected
input currents
duringoverload
condition
—
-50
50
IAVGSEG
Sum of all the VDD = 5.0 V ±
static I/O 10%,PAD3V5V
current within a = 0
supply
70
64
mA
V
DD = 3.3 V ±
10%,PAD3V5V
= 1
segment
TSTORAGE
SR
Storage
—
-55
150
°C
temperature
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
3.4
Recommended operating conditions
Table 8. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect
3.0
3.6
to ground (VSS
)
2
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
VSS−0.1 VSS+0.1
V
V
(VSS
)
3
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
—
3.0
3.6
)
Relative to VDD
VDD−0.1 VDD+0.1
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Electrical characteristics
Table 8. Recommended operating conditions (3.3 V) (continued)
Value
Unit
Symbol
Parameter
Conditions
Min
Max
VSS_ADC SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) pin
—
VSS−0.1 VSS+0.1
V
V
with respect to ground (VSS
)
4
VDD_ADC
SR Voltage on VSS_HV_ADC0,
—
3.05
VDD−0.1 VDD+0.1
3.6
VSS_HV_ADC1 (ADC reference) with
Relative to VDD
respect to ground (VSS
)
VIN
SR Voltage on any GPIO pin with respect
—
VSS−0.1
—
—
VDD+0.1
5
V
to ground (VSS
)
Relative to VDD
IINJPAD
IINJSUM
SR Injected input current on any pin
during overload condition
—
—
—
−5
mA
SR Absolute sum of all injected input
currents during overload condition
−50
50
TVDD
TA
SR VDD slope to ensure correct power up6
SR Ambient temperature under bias
SR Junction temperature under bias
—
0.25 V/µs
fCPU < 64 MHz
−40
−40
125
150
°C
TJ
—
1
2
3
100 nF capacitance needs to be provided between each VDD/VSS pair
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4
5
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL
device is reset.
,
6
Guaranteed by device validation
Table 9. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect to ground (VSS
)
—
Voltage drop2
—
4.5
3.0
5.5
5.5
3
VSS_LV
SR Voltage on VSS_LV (low voltage digital supply) pins with
respect to ground (VSS
VSS-0.1 VSS+0.1
V
V
)
4
VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect
—
4.5
3.0
5.5
5.5
to ground (VSS
)
Voltage drop2
Relative to VDD VDD-0.1 VDD+0.1
SS-0.1 VSS+0.1
VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
reference) pin with respect to ground (VSS
—
V
V
)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
15
Electrical characteristics
Table 9. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
5
VDD_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
—
4.5
3.0
5.5
5.5
V
reference) with respect to ground (VSS
)
Voltage drop2
Relative to VDD VDD-0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to ground (VSS
)
—
Relative to VDD
—
VSS-0.1
-
VDD+0.1
5
V
-
IINJPAD SR Injected input current on any pin during overload
condition
-5
mA
IINJSUM SR Absolute sum of all injected input currents during
overload condition
—
-50
50
TVDD
SR VDD slope to ensure correct power up6
—
—
—
3
0.25
—
V/µs
V/s
°C
TA C-Grade SR Ambient temperature under bias
fCPU < 64 MHz
−40
85
Part
TJ C-Grade SR Junction temperature under bias
—
fCPU < 64 MHz
—
−40
−40
−40
−40
−40
110
105
130
125
150
Part
TA V-Grade SR Ambient temperature under bias
Part
TJ V-Grade SR Junction temperature under bias
Part
TA M-Grade SR Ambient temperature under bias
fCPU < 60 MHz
—
Part
TJ M-Grade SR Junction temperature under bias
Part
1
2
100 nF capacitance needs to be provided between each VDD/VSS pair
Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3
4
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). This decoupling need to be increased as recommended in
Section 3.5.1, “External ballast resistor recommendations incase external ballast resistor is planned to be used.
5
6
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair
Guaranteed by device validation
NOTE
RAM data retention is guaranteed wi‘th V
not below 1.08 V.
DD_LV
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
16
Freescale Semiconductor
Electrical characteristics
3.5
Thermal characteristics
3.5.1
External ballast resistor recommendations
External ballast resistor on V
pin helps in reducing the overall power dissipation inside the device. This resistor is
DD_BV
required only when maximum power consumption exceeds the limit imposed by package thermal characteristics.
As stated in Table 10 LQFP thermal characteristics, considering thermal resistance of LQFP144 as 48.3 °C/W, at ambient T =
A
125 °C, the junction temp T will cross 150 °C if total power dissipation > (150 - 125)/48.3 = 517 mW. Therefore, total device
j
current I
at 125 °C/5.5V must not exceed 94.1 mA (i.e. PD/VDD). Assuming an average I (V
) of 15-20 mA
DDMAX
DD DD_HV
consumption typically during device RUN mode, the LV domain consumption I (V
) is thus limited to I
-
DD DD_BV
DDMAX
I
(V
) i.e. 80 mA.
DD DD_HV
Therefore, respecting the maximum power allowed as explained in Section 3.5.2, “Package thermal characteristics, it is
recommended to use this resistor only in the 125 °C/5.5V operating corner as per the following guidelines:
•
•
•
If I (V
) < 80 mA, then no resistor is required.
DD DD_BV
If 80 mA < I (V
) < 90 mA, then 4 Ohm resistor can be used along with 14.7 µf decoupling.
DD DD_BV
If I (V
) > 90 mA, then 8 Ohm resistor can be used along with 33 µf decoupling.
DD DD_BV
Using resistance in the range of 4-8 Ohm, the gain will be around 10-20% of total consumption on V
. For example, if 8
DD_BV
Ohm resistor is used, then power consumption when I (V
) is 110 mA is equivalent to power consumption when
DD DD_BV
I
(V
) is 90 mA (approximately) when resistor not used.
DD DD_BV
3.5.2
Package thermal characteristics
1
Table 10. LQFP thermal characteristics
Value3
Typ
Symbol
C
Parameter Conditions2 Pin count
Unit
Min
Max
RθJA
CC
D
Thermal
resistance, board—1s
junction-to-
Single-layer
100
144
176
—
—
—
—
—
—
64
64
64
°C/W
ambient
natural
convection4
Four-layer
board—2s2p
100
144
176
—
—
—
—
—
—
49.7
48.3
47.3
1
2
3
4
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
All values need to be confirmed during device validation.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA
.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
17
Preliminary—Subject to Change Without Notice
Electrical characteristics
1
Table 11. 208 MAPBGA thermal characteristics
Symbol
C
Parameter
Thermal
Conditions
Value
Unit
RθJA
CC
—
Single-layer
board—1s
TBD
°C/W
resistance,
junction-to-am
bient natural
convection2
Four-layer
board—2s2p
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA
and RthJMA
.
3.5.3
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:
J
T = T + (P x R )
θJA
Eqn. 1
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
θJA
P is the sum of P
and P (P = P
+ P ).
D
INT
I/O
D
INT I/O
P
P
is the product of I and V , expressed in watts. This is the chip internal power.
DD DD
INT
I/O
represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, P < P
and may be neglected. On the other hand, P may be significant, if the device
I/O
INT
I/O
is configured to continuously drive external modules and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273 °C)
Eqn. 2
Eqn. 3
D
J
Therefore, solving equations 1 and 2:
Where:
2
K = P x (T + 273 °C) + R
x P
D
D
A
θJA
K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2
A.
D
J
iteratively for any value of T .
A
3.6
I/O pad electrical characteristics
I/O pad types
3.6.1
The device provides four main I/O pad types depending on the associated alternate functions:
•
Slow pads - are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
•
Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce
electromagnetic emission.
MPC5607B Microcontroller Data Sheet, Rev. 3
18
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Fast pads - provide maximum speed. These are used for improved Nexus debugging capability.
•
•
Input only pads - are associated with ADC channels and 32 kHz low power external crystal oscillator providing low
input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 5.
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
Table 12. I/O input DC electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
VIL SR P Input low level CMOS (Schmitt
Trigger)
−0.4
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
0.1VDD
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
19
Electrical characteristics
Table 12. I/O input DC electrical characteristics (continued)
Value2
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
ILKG CC P Digital input leakage
No injection
on adjacent
pin
TA = −40 °C
TA = 25 °C
TA = 105 °C
TA = 125 °C
—
—
—
—
—
2
—
—
nA
P
D
P
2
12
70
—
500
1000
40
WFI SR P Width of input pulse surely filtered
by analog filter3
—
—
ns
ns
WNFI SR P Width of input pulse surely not
filtered by analog filter3
1000
—
—
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Analog filters are available on all wakeup lines.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
20
Freescale Semiconductor
Electrical characteristics
3.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 15 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 14 provides output driver characteristics for I/O pads when in FAST configuration.
Table 13. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
|IWPU
|
CC
P
C
P
Weak
VIN = VIL, PAD3V5V
10
—
150
µA
pull-up
current
absolute
value
VDD
=
= 0
5.0 V ±
10%
PAD3V5V
= 12
10
10
—
—
250
150
VIN = VIL, PAD3V5V
VDD = 1
=
3.3 V ±
10%
|IWPD
|
CC
P
C
P
Weak
pull-down VDD
current
absolute
value
VIN = VIH, PAD3V5V
10
10
10
—
—
—
150
250
150
µA
=
= 0
5.0 V ±
10%
PAD3V5V
= 1
VIN = VIH, PAD3V5V
VDD = 1
=
3.3 V ±
10%
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
21
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 14. FAST configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH
CC
P
Output
high level
FAST
Push Pull IOH
−14mA,
VDD
=
0.8VDD
—
—
V
=
configurati
on
5.0 V ±
10%,
PAD3V5V
= 0
(recomme
nded)
C
C
IOH
−7mA,
VDD
5.0 V ±
10%,
=
0.8VDD
—
—
—
—
=
PAD3V5V
= 12
IOH
−11mA,
VDD
=
VDD−0.8
=
3.3 V ±
10%,
PAD3V5V
= 1
(recomme
nded)
VOL
CC
P
Output low Push Pull IOL
=
—
—
0.1VDD
V
level
14mA,
VDD
5.0 V ±
10%,
FAST
configurati
on
=
PAD3V5V
= 0
(recomme
nded)
C
C
IOL = 7mA,
—
—
—
—
0.1VDD
VDD
=
5.0 V ±
10%,
PAD3V5V
= 12
IOL
11mA,
VDD
=
0.5
=
3.3 V ±
10%,
PAD3V5V
= 1
(recomme
nded)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
22
Freescale Semiconductor
Electrical characteristics
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
3.6.4
Output pin transition times
Table 15. Output pin transition times
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
Ttr
CC
D
T
Output
transition 25 pF
CL =
VDD
5.0 V ±
10%,
PAD3V5V
= 0
=
—
—
50
ns
time output
CL =
50 pF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
125
50
pin3
SLOW
configurati
on
D
D
T
CL =
100 pF
CL =
25 pF
VDD =
3.3 V ±
10%,
PAD3V5V
= 1
CL =
50 pF
100
125
10
D
D
T
CL =
100 pF
Ttr
CC
Output
transition 25 pF
CL =
VDD
5.0 V ±
10%,
PAD3V5V
= 0
SIUL.PCR
x.SRC = 1
=
ns
time output
CL =
50 pF
20
pin3
MEDIUM
configurati
on
D
D
T
CL =
100 pF
40
CL =
25 pF
VDD
3.3 V ±
10%,
PAD3V5V
= 1
SIUL.PCR
x.SRC = 1
=
12
CL =
50 pF
25
D
CL =
100 pF
40
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
23
Electrical characteristics
Table 15. Output pin transition times (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
Ttr
CC
D
Output
CL =
VDD
=
—
—
4
ns
transition 25 pF
5.0 V ±
10%,
PAD3V5V
= 0
time output
CL =
50 pF
—
—
—
—
—
—
—
—
—
—
6
12
4
pin3
FAST
configurati
on
CL =
100 pF
CL =
25 pF
VDD =
3.3 V ±
10%,
PAD3V5V
= 1
CL =
50 pF
7
CL =
12
100 pF
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
CL includes device and package capacitances (CPKG < 5 pF).
3.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 16.
Table 17 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the I
maximum value.
DYNSEG
Table 16. I/O supply segments
Supply segment
Package
1
2
3
4
5
6
7
8
208
Equivalent to 176 LQFP segment pad distribution
MCKO
MDOn
/MSEO
MAPBGA1
176 LQFP pin7– pin27 pin28 –
pin59 –
pin85
pin86 –
pin123
pin124 –
pin150
pin151 –
pin6
pin57
144 LQFP
100 LQFP
pin20 –
pin49
pin51 –
pin99
pin100 –
pin122
pin 123 –
pin19
—
—
—
—
—
—
—
—
pin16 –
pin37 –
pin70 –
pin84 –
pin35
pin69
pin83
pin15
1
208 MAPBGA available only as development package for Nexus2+
MPC5607B Microcontroller Data Sheet, Rev. 3
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 17. I/O consumption
Value2
Symbol
C
Parameter
Conditions1
Unit
Max
Min
Typ
IDYNSEG
SR
D
Sum of all VDD = 5.0 V ± 10%,
—
—
110
mA
the
PAD3V5V = 0
dynamic
and static
I/O current
within a
supply
V
DD = 3.3 V ± 10%,
—
—
65
PAD3V5V = 1
segment
,3
ISWTSLW
CC
D
D
D
Dynamic
CL =
VDD
=
5.0 V ±
10%,
—
—
—
—
—
—
—
—
—
—
—
—
20
16
mA
I/O current 25 pF
for SLOW
configurati
on
PAD3V5V
= 0
VDD
3.3 V ±
10%,
PAD3V5V
= 1
=
3
ISWTMED
CC
Dynamic
I/O current 25 pF
for
MEDIUM
configurati
on
CL =
VDD
5.0 V ±
10%,
PAD3V5V
= 0
=
29
mA
VDD
3.3 V ±
10%,
PAD3V5V
= 1
=
17
3
ISWTFST
CC
Dynamic
I/O current 25 pF
for FAST
configurati
on
CL =
VDD
5.0 V ±
10%,
PAD3V5V
= 0
=
110
50
mA
VDD
=
3.3 V ±
10%,
PAD3V5V
= 1
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
25
Electrical characteristics
Table 17. I/O consumption (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
IRMSSLW
CC
D
Root
CL =
VDD
=
—
—
2.3
mA
medium
square I/O MHz
25 pF, 2
5.0 V ±
10%,
current for
SLOW
configurati
on
PAD3V5V
= 0
CL =
25 pF, 4
MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.2
6.6
1.6
2.3
4.7
6.6
13.4
18.3
5
CL =
100 pF, 2
MHz
CL =
25 pF, 2
MHz
VDD =
3.3 V ±
10%,
PAD3V5V
= 1
CL =
25 pF, 4
MHz
CL =
100 pF, 2
MHz
IRMSMED
CC
D
Root
medium
square I/O MHz
current for
MEDIUM
configurati
on
CL =
VDD
=
mA
25 pF, 13 5.0 V ±
10%,
PAD3V5V
= 0
CL =
25 pF, 40
MHz
CL =
100 pF, 13
MHz
CL =
VDD =
25 pF, 13 3.3 V ±
MHz
10%,
PAD3V5V
= 1
CL =
25 pF, 40
MHz
8.5
11
CL =
100 pF, 13
MHz
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
26
Freescale Semiconductor
Electrical characteristics
Table 17. I/O consumption (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit
Max
Min
Typ
IRMSFST
CC
D
Root
medium
square I/O MHz
current for
FAST
configurati
on
CL =
VDD
=
—
—
22
33
56
14
20
35
mA
25 pF, 40 5.0 V ±
10%,
PAD3V5V
= 0
CL =
25 pF, 64
MHz
—
—
—
—
—
—
—
—
—
—
CL =
100 pF, 40
MHz
CL =
VDD =
25 pF, 40 3.3 V ± 10
MHz
%,
PAD3V5V
= 1
CL =
25 pF, 64
MHz
CL =
100 pF, 40
MHz
IAVGSEG
SR
D
Sum of all VDD = 5.0 V ± 10%,
the static PAD3V5V = 0
I/O current
—
—
—
—
70
65
mA
V
DD = 3.3 V ± 10%,
within a
supply
PAD3V5V = 1
segment
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
3.7
nRSTIN electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
27
Preliminary—Subject to Change Without Notice
Electrical characteristics
V
DD
V
DDMIN
nRSTIN
V
IH
V
IL
device reset forced by nRSTIN
device start-up phase
Figure 6. Start-up reset requirements
VRSTIN
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 7. Noise filtering on reset signal
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
28
Freescale Semiconductor
Electrical characteristics
Table 18. Reset electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input High Level CMOS
(Schmitt Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
V
V
V
VIL SR P Input low Level CMOS
(Schmitt Trigger)
−0.4
0.1VDD
—
—
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
VOL CC P Output low level
Push Pull, IOL = 2mA,
0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
Push Pull, IOL = 1mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 13
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
Ttr
CC D Output transition time
output pin4
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
40
—
ns
MEDIUM configuration
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
WFRST SR P nRSTIN input filtered
pulse
—
—
ns
ns
µA
WNFRST SR P nRSTIN input not filtered
pulse
—
1000
|IWPU
|
CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 5.0 V ± 10%, PAD3V5V = 15
10
10
10
—
—
—
150
150
250
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
4
5
CL includes device and package capacitance (CPKG < 5 pF).
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
29
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply V
from the high voltage
DD_LV
ballast supply V
. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:
DD_BV
DD
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through V
power pin.
DD
BV: High voltage external power supply for internal ballast module. This must be provided externally through V
DD_BV
power pin. Voltage values should be aligned with V
.
DD
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also `used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
C
(LV_COR/LV_CFLA)
REG2
GND
V
DD
V
V
DD_LV
SS_LV
V
DD_BV
DD_LVn
SS_LVn
V
REF
V
DD_BV
V
DD_LV
DEVICE
V
Voltage Regulator
I
V
SS_LV
GND
V
V
V
V
V
DD
SS_LV
DD_LV
SS
DEVICE
GND
(LV_COR/LV_PLL)
GND
C
(supply/IO decoupling)
C
DEC2
REG3
Figure 8. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (C
) to be connected to the device in order to provide a stable
REGn
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5607B Microcontroller Data Sheet, Rev. 3
30
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Each decoupling capacitor must be placed between each of the three V
Section 3.4, “Recommended operating conditions).
/V
supply pairs to ensure stable voltage (see
DD_LV SS_LV
Table 19. Voltage regulator electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CREGn
RREG
SR — Internal voltage regulator external
capacitance
—
—
200
—
330
nF
W
SR — Stability capacitor equivalent serial
resistance
—
—
0.2
CDEC1
CDEC2
SR — Decoupling capacitance3,4 ballast
VDD_BV/VSS_LV pair
VDD/VSS pair
400
10
4705
100
—
—
nF
nF
SR — Decoupling capacitance regulator
supply
VMREG
CC P Main regulator output voltage
Before trimming
After trimming
—
—
—
—
1.32
1.28
—
—
—
V
IMREG
SR — Main regulator current provided to
VDD_LV domain
150
mA
mA
IMREGINT CC D Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
—
—
2
1
VLPREG
ILPREG
CC P Low power regulator output voltage After trimming
1.23
—
—
15
V
SR — Low power regulator current provided
to VDD_LV domain
mA
—
ILPREGINT CC D Low power regulator module current ILPREG = 15 mA;
—
—
—
—
—
—
—
—
5
600
TBD
—
µA
consumption
TA = 55 °C
—
ILPREG = 0 mA;
TA = 55 °C
VULPREG CC P Ultra low power regulator output
voltage
Post trimming
1.23
—
—
2
V
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
—
5
mA
µA
IULPREGINT CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
100
TBD
—
IULPREG = 0 mA;
TA = 55 °C
IVREGREF CC D Main LVDs and reference current
consumption (low power and main
regulator switched off)
TA = 55 °C
17
µA
IVREDLVD12 CC D Main LVD current consumption
(switch-off during standby)
TA = 55 °C
—
—
—
2
TBD µA
4006 mA
IDD_BV
CC D In-rush current on VDD_BV during
power-up
—
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
31
Preliminary—Subject to Change Without Notice
Electrical characteristics
3
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
4
In case external ballast resistor is planned to be used, then to avoid a LVD reset during standby mode exit, the
following configuration need to be respected.
- for 8 ohm ballast resistor, decoupling cap of 33 µf is required.
- for 4 ohm ballast resistor, decoupling cap of 14.7µf is required.
These values are only after preliminary validation and are subject to change.
5
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
6
In-rush current is seen only for short time during power-up and on standby exit (max 20µs, depending on external
capacitances to be load)
MPC5607B Microcontroller Data Sheet, Rev. 3
32
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.8.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the V and the V voltage while device is supplied:
DD
DD_LV
•
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP.
V
DD
V
V
LVDHVxH
LVDHVxL
RESET
Figure 9. Low voltage monitor vs reset
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
33
Electrical characteristics
Table 20. Low voltage monitor electrical characteristics
Condition
Symbol
C
Parameter
Value2
Unit
Symbol
s1
VPORUP
SR
P
Supply for TA = 25 °C,
functional after
1.0
—
5.5
V
VPORUP
POR
trimming
module
VPORH
CC
CC
P
T
Power-on
reset
threshold
1.5
—
—
—
2.6
VPORH
VLVDHV3H
LVDHV3
lowvoltage
detector
high
2.95
VLVDHV3H
threshold
VLVDHV3L
VLVDHV3BH
VLVDHV3BL
CC
CC
CC
P
P
P
LVDHV3
lowvoltage
detector
low
2.7
—
—
—
—
2.9
2.95
2.9
VLVDHV3L
VLVDHV3BH
VLVDHV3BL
threshold
LVDHV3B
lowvoltage
detector
high
threshold
LVDHV3B
L low
2.7
voltage
detector
low
threshold
VLVDHV5H
CC
CC
CC
T
P
P
LVDHV5
lowvoltage
detector
high
—
3.8
—
—
—
4.5
4.4
VLVDHV5H
threshold
VLVDHV5L
LVDHV5
lowvoltage
detector
low
VLVDHV5L
threshold
VLVDLVCOR
LVDLVCO
R low
1.07
1.11
VLVDLVCOR
L
L
voltage
detector
low
threshold
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
34
Freescale Semiconductor
Electrical characteristics
2
All values need to be confirmed during device validation.
3.9
Low voltage domain power consumption
Table 21 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 21. Low voltage power domain electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
2
IDDMAX
CC
CC
D
RUN mode
maximum
average
—
—
115
1403
mA
current
4
IDDRUN
T
P
RUN mode
typical
—
—
—
—
80
100
mA
TBD
TBD
average
current5
IDDHALT
CC
CC
P
HALT
—
—
8
TBD
mA
µA
mode
current6
IDDSTOP
P
D
D
D
P
P
D
D
D
P
STOP
mode
Slow
internal
RC
oscillator
(128 kHz)
running
TA = 25 °
C
—
—
—
—
—
—
—
—
—
—
350
750
2
9008
—
current7
TA = 55 °
C
TA = 85 °
C
—
mA
TA = 105 °
C
4
—
TA = 125 °
C
9
TBD8
100
—
IDDSTDBY2
CC
STANDBY Slow
TA = 25 °
C
30
TBD
µA
2 mode
internal
RC
oscillator
(128 kHz)
running
current9
TA = 55 °
C
TA = 85 °
C
—
TA = 105 °
C
—
TA = 125 °
C
TBD
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
35
Electrical characteristics
Table 21. Low voltage power domain electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
IDDSTDBY1
CC
T
D
D
D
D
STANDBY Slow
TA = 25 °
C
—
20
60
µA
1 mode
internal
current10 RC
TA = 55 °
C
—
—
—
—
TBD
—
—
oscillator
(128 kHz)
running
TA = 85 °
C
TA = 105 °
C
—
TA = 125 °
C
280
TBD
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value
with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to
be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default),
reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode
when possible.
3
Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on
Table 19.
4
5
RUN current measured with typical application with accesses on both flash and RAM.
Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master,
PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic
SW/WDG timer reset enabled.
6
Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON
(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0
(clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue
watchdog
7
8
Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances , it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched-off.
10 ULPreg on, HP/LPVreg off, 8KB RAM on, device configured for minimum consumption, all possible modules
switched-off.
MPC5607B Microcontroller Data Sheet, Rev. 3
36
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.10 Flash memory electrical characteristics
3.10.1 Program/Erase characteristics
Table 22 shows the program and erase characteristics.
Table 22. Program and erase specifications
Value
Symbol
C
Parameter
Unit
Initial
max2
Min
Typ1
Max3
Tdwprogram
CC
C
Double
word (64
bits)
—
22
TBD
500
µs
program
time4
T16Kpperase
16 KB block
pre-progra
m and
—
—
—
300
400
800
500
600
5000
5000
7500
ms
ms
ms
erase time
T32Kpperase
32 KB block
pre-progra
m and
erase time
T128Kpperas
128 KB
block
1300
e
pre-progra
m and
erase time
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
37
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 23. Flash module life
Conditions
Value
Symbol
C
Parameter
Unit
Min
Typ
P/E
CC C Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
—
—
100,000
10,000
1,000
—
cycles
P/E
P/E
CC C Number of program/erase cycles per
block for 32 Kbyte blocks over the
operating temperature range (TJ)
100,0001 cycles
100,0001 cycles
CC C Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
Retention CC C Minimum data retention at 85 °C
average ambient temperature2
Blocks with 0–1,000 P/E
cycles
20
10
5
—
—
—
years
years
years
Blocks with 10,000 P/E
cycles
Blocks with 100,000 P/E
cycles
1
To be confirmed
2
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 24. Flash read access timing
Symbol
C
Parameter
Conditions1
Max
Unit
fREAD
CC
P
C
C
Maximum
frequency for
Flash reading
2 wait states
1 wait state
0 wait states
64
40
20
MHz
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3.10.2 Flash power supply DC characteristics
Table 25 shows the power supply DC characteristics on external supply.
MPC5607B Microcontroller Data Sheet, Rev. 3
38
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 25. Flash power supply DC electrical characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Max
Min
Typ
3
ICFREAD
CC
CC
Sum of the Flash
Code Flash
33
33
mA
current
module
3
IDFREAD
Data Flash
consumptio read
n on VDDHV fCPU = 64
and VDDBV MHz4
on read
access
3
ICFMOD
Sum of the Program/
Code Flash
Data Flash
52
33
mA
current
Erase
3
IDFMOD
consumptio on-going
n on VDDHV while
and VDDBV reading
on matrix
Flash
modificatio registers
n
fCPU = 64
(program/er MHz4
ase)
3
3
ICFLPW
IDFLPW
CC
Sum of the
current
consumptio
n on VDDHV
and VDDBV
during
Code Flash
Data Flash
1.1
mA
µA
900
Flash low
power
mode
3
ICFPWD
CC
Sum of the
current
consumptio
n on VDDHV
and VDDBV
during
Code Flash
Data Flash
150
150
µA
3
IDFPWD
Flash
power
down mode
1
2
3
4
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Data based on characterization results, not tested in production
fCPU 64 MHz can be achieved only at up to 105 °C
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
39
Electrical characteristics
3.10.3 Start-up/Switch-off timings
Table 26. Start-up time/Switch-off time
Value
Symbol
C
Parameter Conditions1
Unit
Min
Typ
Max
TFLARSTEXI CC
T
T
Delay for
Flash
module to
exit reset
mode
—
—
—
—
125
µs
T
TFLALPEXIT CC
Delay for
Flash
module to
exit
low-power
mode
—
—
—
—
—
—
—
—
0.5
30
TFLAPDEXIT CC
T
T
T
Delay for
Flash
module to
exit
power-dow
n mode
—
—
—
TFLALPENTR CC
Delay for
Flash
module to
enter
low-power
mode
0.5
1.5
Y
TFLAPDENT CC
Delay for
RY
Flash mod-
ule to enter
power-dow
n mode
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3.11 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.11.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for the application.
•
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
MPC5607B Microcontroller Data Sheet, Rev. 3
40
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
3.11.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1
standard, which specifies the general conditions for EMI measurements.
1,2
Table 27. EMI radiated emission measurement
Value
Paramete
Symbol
C
Conditions
Unit
r
Min
Typ
Max
—
SR
SR
SR
—
—
—
Scan
range
—
—
—
0.150
1000
MHz
MHz
V
fCPU
Operating
frequency
—
—
64
—
—
VDD_LV
LV
1.28
operating
voltages
SEMI
CC
T
Peak level VDD
5 V,
=
No PLL
frequency
—
—
—
—
18
dBµV
dBµV
TA = 25 ° modulatio
C,
n
LQFP144
package
Test
conformin
g to IEC
61967-2,
fOSC = 8
MHz/fCPU
= 64 MHz
± 2% PLL
frequency
modulatio
n
143
1
2
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3
All values need to be confirmed during device validation
3.11.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
41
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.11.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts×(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
1,2
Table 28. ESD absolute maximum ratings
Symbol
Ratings
Conditions
TA = 25 °C
Class
Max value3
Unit
VESD(HBM) Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production
3.11.3.2 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 29. Latch-up results
Symbol
Parameter
Static latch-up class
Conditions
Class
LU
TA = 125 °C
II level A
conforming to JESD 78
3.12 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure describes a simple model of the internal oscillator driver and provides
an example of a connection for an oscillator or a resonator.
Table 30 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
MPC5607B Microcontroller Data Sheet, Rev. 3
42
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
EXTAL
C1
EXTAL
R
P
XTAL
C2
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
Figure 10. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 30. Crystal description
Shunt
capacitance
between
xtalout
Crystal
equivalent
series
resistance
ESR Ω
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
Nominal
frequency
(MHz)
NDK crystal
reference
xtalin/xtalout
C1 = C2
(pF)1
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
1
2
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
43
Preliminary—Subject to Change Without Notice
Electrical characteristics
S_MTRANS bit (ME_GS register)
1
0
V
XTAL
1/f
MXOSC
V
MXOSC
90%
10%
V
MXOSCOP
T
valid internal clock
MXOSCSU
Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
oscillator
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
transconductance
CC P
CC C
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
VFXOSC
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC P Oscillation operating point
—
—
—
—
0.95
2
V
,3
IFXOSC
CC T Fast external crystal
oscillator consumption
3
mA
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
44
Freescale Semiconductor
Electrical characteristics
Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
TFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
ms
f
OSC = 16 MHz,
—
—
—
—
1.8
OSCILLATOR_MARGIN = 1
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
−0.4
VDD+0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
3.13 Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL
OSC32K_EXTAL
C1
R
P
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
45
Preliminary—Subject to Change Without Notice
Electrical characteristics
l
C0
Crystal
Rm
Lm
Cm
C1
C2
C1
C2
Figure 13. Equivalent circuit of a quartz crystal
1
Table 32. Crystal motional characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
Motional capacitance
—
—
—
—
—
18
11.796
—
—
28
KH
fF
Cm
2
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
—
pF
AC coupled @ C0 = 2.85 pF4
AC coupled @ C0 = 4.9 pF4
AC coupled @ C0 = 7.0 pF4
AC coupled @ C0 = 9.0 pF4
—
—
—
—
—
—
—
—
65
50
35
30
kW
3
Rm
Motional resistance
1
2
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3
4
Maximum ESR (Rm) of the crystal is 50 kΩ
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
MPC5607B Microcontroller Data Sheet, Rev. 3
46
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
1/f
LPXOSC32K
V
LPXOSC32K
90%
10%
T
valid internal clock
LPXOSC32KSU
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
Table 33. Slow external crystal oscillator (32 kHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator
frequency
—
32
32.768
40
kHz
gmSXOSC CC — Slow external crystal oscillator
transconductance
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
TBD
TBD
TBD
mA/V
VDD = 5.0 V ± 10%
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VSXOSC
CC T Oscillation amplitude
—
—
—
—
2.1
TBD
—
—
V
ISXOSCBIAS CC T Oscillation bias current
µA
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
8
TSXOSCSU CC T Slow external crystal oscillator
start-up time
—
—
23
s
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
47
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.14 FMPLL electrical characteristics
The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 34. FMPLL electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fPLLIN SR — FMPLL reference clock3
—
—
4
—
—
64
60
MHz
%
ΔPLLIN SR — FMPLL reference clock duty
40
cycle3
fPLLOUT CC P FMPLL output clock frequency
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
tLOCK CC P FMPLL lock time
—
16
—
20
—
—
—
40
—
64
MHz
—
644 MHz
—
150 MHz
Stable oscillator (fPLLIN = 16 MHz)
100
10
µs
ns
ΔtLTJIT CC — FMPLL long term jitter
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
—
IPLL
CC C FMPLL consumption
TA = 25 °C
—
4
mA
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN
fCPU 64 MHz can be achieved only at up to 105 °C
.
4
3.15 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics
Value2
Symbol
fFIRC
3,
C
Parameter
Conditions1
Unit
Min
Typ
Max
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
—
12
—
16
—
20
MHz
SR —
—
IFIRCRUN
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
—
200
µA
µA
frequency current in running
mode
IFIRCPWD CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
—
TBD
10
—
TA = 55 °C
TBD TBD
down mode
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
48
Freescale Semiconductor
Electrical characteristics
Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value2
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C sysclk = off
frequency and system clock
—
—
—
—
—
—
—
—
—
−1
500
600
700
900
1250
1.1
1.2
—
—
—
µA
sysclk = 2 MHz
current in stop mode
sysclk = 4 MHz
sysclk = 8 MHz
—
—
sysclk = 16 MHz
—
TFIRCSU CC C Fast internal RC oscillator
TA = 55 °C VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
2.0
TBD
2.0
TBD
+1
µs
%
start-up time
—
—
—
TA = 125 °C VDD = 5.0 V ± 10%
VDD = 3.3 V ± 10%
—
ΔFIRCPRE CC C Fast internal RC oscillator
precision after software
TA = 25 °C
—
trimming of fFIRC
ΔFIRCTRIM CC C Fast internal RC oscillator
TA = 25 °C
—
1.6
—
%
%
trimming step
ΔFIRCVAR CC C Fast internal RC oscillator
variation over temperature and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
—
−5
+5
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
3.16 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
—
100
—
128
—
—
150
5
kHz
frequency
SR —
3,
ISIRC
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
µA
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
49
Electrical characteristics
Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
TSIRCSU CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
%
ΔSIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C
−2
—
2.7
—
+2
after software trimming of fSIRC
ΔSIRCTRIM CC C Slow internal RC oscillator trimming
—
—
—
step
ΔSIRCVAR CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
−10
+10
%
respect to fSIRC at TA = 55 °C in high
frequency configuration
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
3.17 ADC electrical characteristics
3.17.1 Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).
MPC5607B Microcontroller Data Sheet, Rev. 3
50
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 15. ADC0 characteristic and error definitions
3.17.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
51
Preliminary—Subject to Change Without Notice
Electrical characteristics
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 kΩ is obtained (R
S
EQ
= 1 / (fc*C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
S
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 4:
Eqn. 4
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V •
< -- LSB
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 16. Input equivalent circuit (precise channels)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
52
Freescale Semiconductor
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
Pin Capacitance (three contributions, C , C and C )
Sampling Capacitance
P1
P2
P3
S
Figure 17. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon
A
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 18. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
53
Electrical characteristics
Eqn. 5
C • C
P
S
--------------------
) •
τ
= (R
+ R
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
Eqn. 6
τ < (R
+ R
) • C « T
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
Eqn. 7
V
• (C + C + C ) = V • (C + C
)
A1
S
P1
P2
A
P1
P2
2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 8
τ < R • (C + C + C
P1 P2
)
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
Eqn. 9
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 10
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
MPC5607B Microcontroller Data Sheet, Rev. 3
54
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Analog source bandwidth (VA)
Noise
T
C < 2 RFCF (Conversion rate vs. filter pole)
fF = f0 (Anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = Conversion rate)
fF
f0
fC
f
f
Figure 19. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
ADC0 (10-bit)
> 2048 • C
Eqn. 12
Eqn. 13
C
F
S
ADC1 (12-bit)
> 8192 • C
C
F
S
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
55
Electrical characteristics
3.17.3 ADC electrical characteristics
Table 37. ADC input leakage current
Value
Typ
Symbol C
Parameter
Conditions
Unit
Min
Max
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
—
—
—
—
1
1
—
—
nA
C
C
P
TA = 25 °C
TA = 105 °C
TA = 125 °C
8
200
400
45
Table 38. ADC conversion characteristics (10-bit ADC0)
Value
Paramete
Symbol
C
Conditions1
Unit
r
Min
Typ
Max
VSS_ADC0
SR
—
Voltageon
VSS_HV_
ADC0
—
−0.1
—
0.1
V
(ADC0
reference)
pin with
respect to
ground
2
(VSS
)
VDD_ADC0
SR
—
Voltageon
VDD_HV_
ADC pin
(ADC
—
VDD−0.1
—
VDD+0.1
V
reference)
with
respect to
ground
(VSS
)
VAINx
SR
SR
SR
—
—
—
Analog
input
—
—
VSS_ADC0
—
—
—
VDD_ADC0
+0.1
V
MHz
%
−0.1
voltage3
fADC0
ADC0
analog
frequency
6
32 + 4%
55
ΔADC0_SY
ADC0
ADCLKSEL = 14
45
digital
S
clock duty
cycle
(ipg_clk)
tADC0_PU
SR
—
ADC0
—
—
—
1.5
µs
power up
delay
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
56
Freescale Semiconductor
Electrical characteristics
Table 38. ADC conversion characteristics (continued)(10-bit ADC0)
Value
Paramete
r
Symbol
C
Conditions1
Unit
Min
Typ
Max
tADC0_S
CC
T
Sample
time5
fADC = 32 MHz,
ADC0_conf_sample_i
nput = 17
0.5
—
µs
f
ADC = 6 MHz,
—
—
—
42
3
INPSAMP = 255
tADC0_C
CS
CC
CC
P
D
Conversio fADC = 32 MHz,
0.625
—
µs
n time6
ADC_conf_comp = 2
ADC0
input
—
pF
sampling
capacitan
ce
CP1
CC
CC
CC
CC
CC
CC
SR
D
D
D
D
D
D
—
ADC0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
1
1
3
2
2
pF
pF
pF
kΩ
kΩ
kΩ
mA
input pin
capacitan
ce 1
CP2
ADC0
input pin
capacitan
ce 2
CP3
ADC0
input pin
capacitan
ce 3
RSW1
RSW2
RAD
IINJ
Internal
resistance
of analog
source
Internal
resistance
of analog
source
Internal
resistance
of analog
source
Input
current
Injection on one
ADC0
Current
VDD
=
−5
−5
—
—
5
5
injection 3.3 V ±
10%
VDD
5.0 V ±
10%
=
input,
different
from the
converted
one
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
57
Electrical characteristics
Table 38. ADC conversion characteristics (continued)(10-bit ADC0)
Value
Paramete
r
Symbol
C
Conditions1
Unit
Min
Typ
Max
| INL |
CC
T
Absolute No overload
—
0.5
1.5
LSB
value for
integral
non-linear
ity
| DNL |
| OFS |
CC
CC
T
T
Absolute No overload
—
—
0.5
0.5
1.0
—
LSB
LSB
differential
non-linear
ity
Absolute
offset
—
error
| GNE |
TUEP
CC
CC
T
P
T
Absolute
gain error
—
—
−2
−3
0.6
0.6
—
2
LSB
LSB
Total
Without current
unadjuste injection
derror7 for
With current injection
3
precise
channels,
input only
pins
TUEX
CC
T
T
Total
Without current
−3
−4
1
3
4
LSB
unadjuste injection
derror7 for
With current injection
extended
channel
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4
5
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
6
7
This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5607B Microcontroller Data Sheet, Rev. 3
58
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
V
(LSB
)
in(A)
ideal
Offset Error OSE
Figure 20. ADC1 characteristic and error definitions
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
59
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1)
Value
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
VSS_ADC1
SR
Voltage on
VSS_HV_A
DC1(ADC1
reference)
pin with
—
-0.1
0.1
V
respect to
ground
2
(VSS
)
VDD_ADC1
SR
Voltage on
VDD_HV_
ADC1 pin
(ADC1
—
VDD-0.1
VDD+0.1
V
reference)
with
respect to
ground
(VSS
)
VAINx
SR
SR
SR
CC
Analog
input
—
VSS_ADC1-0
.1
VDD_ADC1
0.1
+
V
MHz
µs
voltage3
fADC1
ADC1
analog
frequency
—
—
32 + 3%
32 + 4%
tADC1_PU
ADC1
power up
delay
1.5
tADC1_S
Sample
time4
VDD=3.3 V ut = 20
f
ADC1= 32 MHz,
ADC1_conf_sample_inp
600
500
ns
Sample
time4
f
ADC1= 32 MHz,
ADC1_conf_sample_inp
VDD =5.0 V ut = 17
Sample
time4
VDD=3.3 V ut = 255
f
ADC1= 3.33 MHz,
76.2
76.2
µs
ADC1_conf_sample_inp
Sample
time4
fADC1= 3.33 MHz,
ADC1_conf_sample_inp
VDD =5.0 V ut = 255
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
60
Freescale Semiconductor
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1) (continued)
Value
Symbol
Parameter
Conditions1
Unit
Max
Min
Typ
tADC1_C
CC
Conversion fADC1 = 20MHz,
2.4
µs
µs
µs
µs
time5
ADC1_conf_comp = 0
VDD=3.3 V
Conversion fADC 1= 13.33 MHz,
1.5
3.6
3.6
time5
ADC1_conf_comp = 0
VDD =5.0 V
Conversion fADC 1= 13.33 MHz,
time5
ADC1_conf_comp = 0
VDD=3.3 V
Conversion fADC1 = 32 MHz,
time5
ADC1_conf_comp = 0
VDD =5.0 V
ΔADC0_SYS
SR
CC
CC
CC
CC
CC
CC
CC
ADC1
digital clock
duty cycle
(ipg_clk)
ADCLKSEL = 16
45
—
5
55
%
CS
ADC1 input
sampling
capacitanc
e
—
—
—
—
—
—
—
pF
pF
pF
pF
kΩ
kΩ
kΩ
CP1
ADC1 input
pin
capacitanc
e 1
3
CP2
ADC1 input
pin
capacitanc
e 2
1
CP3
ADC1 input
pin
capacitanc
e 3
1.5
RSW1
RSW2
RAD
Internal
1
2
resistance
of analog
source
Internal
resistance
of analog
source
Internal
0.3
resistance
of analog
source
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
61
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1) (continued)
Value
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
IINJ
SR
Input
Current
VDD = 3.3 V
-5
—
5
mA
current
Injection
injection on ± 10%
one ADC1
VDD = 5.0 V
-5
—
5
input,
± 10%
different
from the
converted
one
INLP
INLX
DNL
CC
CC
CC
Absolute
Integral
non-linearit
y-Precise
channels
No overload
No overload
No overload
1
3
5
1
LSB
LSB
LSB
Absolute
Integral
non-linearit
y-Extended
channels
1.5
0.5
Absolute
Differential
non-linearit
y
OFS
GNE
CC
CC
CC
Absolute
Offset error
—
2
2
LSB
LSB
Absolute
Gain error
—
TUEP7
Total
Unadjusted
Error for
precise
channels,
input only
pins
Without current injection
With current injection
-6
-8
6
8
TUEX7
CC
Total
Unadjusted
Error for
extended
channel
Without current injection
With current injection
-10
-12
10
12
LSB
LSB
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the
end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC1_S depend on programming.
MPC5607B Microcontroller Data Sheet, Rev. 3
62
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
5
6
7
This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
63
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.18 On-chip peripherals
3.18.1 Current consumption
1
Table 40. On-chip peripherals current consumption
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
IDD_BV(CAN
CC
T
CAN
500 Kbps Total(static
7.652 * fperiph + 84.73
µA
(FlexCAN)
supply
+ dynamic)
consumpti
)
125 Kbps
8.0743 * fperiph + 26.757
current on
VDD_BV
on:
• FlexCAN
in
loop-ba
ckmode
• XTAL@8
MHz
used as
CAN
engine
clock
source
• Message
sending
periodis
580 µs
IDD_BV(eMI
CC
T
eMIOS
supply
Static consumption:
• eMIOS channel OFF
28.7 * fperiph
OS)
current on • Global prescaler
VDD_BV
enabled
Dynamic consumption:
• It does not change
varying the
3
frequency (0.003
mA)
IDD_BV(SCI)
CC
CC
T
T
SCI
Total (static + dynamic)
4.7804 * fperiph + 30.946
(LINFlex) consumption:
supply • LIN mode
current on • Baudrate: 20 Kbps
VDD_BV
IDD_BV(SPI)
SPI (DSPI) Ballast static
1
supply
consumption (only
current on clocked)
VDD_BV
Ballast dynamic
16.3 * fperiph
consumption
(continuus
communication):
• Baudrate: 2 Mbit
• Trasmission every 8
µs
• Frame: 16 bits
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
64
Freescale Semiconductor
Electrical characteristics
1
Table 40. On-chip peripherals current consumption (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
IDD_BV(ADC
CC
T
ADC
supply
V
DD = 5.5
Ballast
static
0.0409 * fperiph
mA
V
)
current on
VDD_BV
consumpti
on (no
conversion
)
VDD = 5.5
V
Ballast
dynamic
consumpti
on
0.0049 * fperiph
(continuus
conversion
)
IDD_HV_AD
CC
T
ADC
supply
V
DD = 5.5
Analog
static
0.0017 * fperiph
V
C(ADC)
current on
VDD_HV_AD
consumpti
on (no
conversion
)
C
VDD = 5.5
V
Analog
dynamic
consumpti
on
0.075 * fperiph + 0.032
(continuus
conversion
)
IDD_HV(FLA
CC
CC
T
T
CFlash +
DFlash
supply
current on
VDD_HV_AD
VDD = 5.5
V
-
13.25
SH)
C
IDD_HV(PLL)
PLLsupply
current on
VDD_HV
VDD = 5.5
-
0.0031 * fperiph
V
1
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
65
Electrical characteristics
3.18.2 DSPI characteristics
Table 41. DSPI characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
tSCK
SR
SR
D
D
SCK cycle time
64
—
—
—
—
ns
—
fDSPI
DSPI digital controller
frequency
fCPU
MHz
—
ΔtCSC
CC
D
Internal delay
between pad
associated to SCK
and pad associated to
CSn in master mode
—
—
1201
ns
ns
2
2
3
4
tCSCext
CC
SR
CC
SR
CC
SR
SR
D
D
D
D
D
D
D
CS to
Master
tCSCext = tCSC + ΔtCSC
SCK delay mode
Slave
mode
32
—
—
3
tASCext
After SCK Master
tASCext = tASC + ΔtCSC
ns
ns
ns
delay
mode
Slave
mode
1/fDSPI + 5
—
tSCK/2
—
—
ns
tSDC
SCK duty Master
—
—
—
—
cycle
mode
Slave
mode
tSCK/2
27
5
6
tA
Slave
access
time
—
—
ns
ns
tDI
SR
SR
D
D
Slave
SOUT
disable
time
—
0
—
—
—
—
7
tSUI
Data
Master
35
ns
setup time (MTFE =
for inputs 0)
Slave
5
—
—
—
—
Master
(MTFE =
1)
35
8
tHI
SR
D
Data hold Master
0
—
—
ns
time for
inputs
(MTFE =
0)
Slave
24
0
—
—
—
—
Master
(MTFE =
1)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
66
Freescale Semiconductor
Electrical characteristics
Table 41. DSPI characteristics (continued)
Value
No.
Symbol
C
Parameter
Unit
Max
Min
Typ
5
9
tSUO
CC
D
Data valid Master
—
—
32
ns
after SCK (MTFE =
edge
0)
Slave
—
—
—
—
34
32
Master
(MTFE =
1)
5
10
tHO
CC
D
Data hold Master
2
—
—
ns
time for
outputs
(MTFE =
0)
Slave
5.5
2
—
—
—
—
Master
(MTFE =
1)
1
2
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtCSC to ensure
positive tCSCext
.
3
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtASC to ensure positive
tASCext
.
4
5
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
SCK and SOUT configured as MEDIUM pad
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
67
Preliminary—Subject to Change Without Notice
Electrical characteristics
Figure 21. DSPI classic SPI timing - master, CPHA = 0
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: Numbers shown reference Table 41.
Figure 22. DSPI classic SPI timing - master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
68
Freescale Semiconductor
Electrical characteristics
Figure 23. DSPI classic SPI timing - slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
11
12
Data
6
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 41.
Figure 24. DSPI classic SPI timing - slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
69
Electrical characteristics
Figure 25. DSPI modified transfer format timing - master, CPHA = 0
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Note: Numbers shown reference Table 41.
Figure 26. DSPI modified transfer format timing - master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
70
Freescale Semiconductor
Electrical characteristics
Figure 27. DSPI modified transfer format timing - slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 41.
Figure 28. DSPI modified transfer format timing - slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
71
Preliminary—Subject to Change Without Notice
Electrical characteristics
Figure 29. DSPI PCS strobe (PCSS) timing
8
7
PCSS
PCSx
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
72
Freescale Semiconductor
Electrical characteristics
3.18.3 Nexus characteristics
Table 42. Nexus characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Max
Min
1
2
3
4
5
6
tTCYC
tMCYC
tMDOV
tMSEOV CC D MCKO low to MSEO_b data valid
CC D TCK cycle time
64
32
—
—
—
15
15
5
—
—
—
—
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC D MCKO cycle time
CC D MCKO low to MDO data valid
8
tEVTOV
tNTDIS
CC D MCKO low to EVTO data valid
CC D TDI data setup time
8
—
—
—
—
—
—
tNTMSS CC D TMS data setup time
tNTDIH CC D TDI data hold time
tNTMSH CC D TMS data hold time
7
5
8
9
tTDOV
tTDOI
CC D TCK low to TDO data valid
CC D TCK low to TDO data invalid
35
6
Figure 30. Nexus TDI, TMS, TDO timing
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 42.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
73
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.18.4 JTAG characteristics
Table 43. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
4
5
6
7
tJCYC
tTDIS
CC D TCK cycle time
CC D TDI setup time
CC D TDI hold time
64
15
5
—
—
—
—
—
—
—
—
—
—
—
—
33
—
ns
ns
ns
ns
ns
ns
ns
tTDIH
tTMSS
tTMSH
tTDOV
tTDOI
CC D TMS setup time
CC D TMS hold time
CC D TCK low to TDO valid
CC D TCK low to TDO invalid
15
5
6
Figure 31. Timing diagram - JTAG boundary scan
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
7
Note: Numbers shown reference Table 43.
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
74
Freescale Semiconductor
Package characteristics
4
Package characteristics
Package mechanical data
176 LQFP
4.1
4.1.1
Figure 32. 176 LQFP package mechanical drawing (Part 1 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
75
Package characteristics
Figure 33. 176 LQFP package mechanical drawing (Part 2 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
76
Freescale Semiconductor
Package characteristics
Figure 34. 176 LQFP package mechanical drawing (Part 3 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
77
Package characteristics
1
Table 44. LQFP176 mechanical data
mm
inches2
Typ
Symbol
Min
Typ
Max
Min
Max
A
1.400
0.050
1.350
0.170
0.090
23.900
23.900
1.600
0.150
1.450
0.270
0.200
24.100
24.100
0.063
A1
0.002
0.053
0.007
0.004
0.941
0.941
A2
0.057
0.011
0.008
0.949
0.949
b
C
D
E
e
HD
0.500
0.020
25.900
25.900
0.450
26.100
26.100
0.750
1.020
1.020
0.018
1.028
1.028
0.030
HE
L3
L1
1.000
1.250
1.250
0.039
0.049
0.049
ZD
ZE
q
0 °
7 °
0 °
7 °
Tolerance
mm
inches
0.0031
ccc
0.080
1
Controlling dimension: millimeter
2
3
Values in inches are converted from mm and rounded to 4 decimal digits.
L dimension is measured at gauge plane at 0.25 mm above the seating plane
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
78
Freescale Semiconductor
Package characteristics
4.1.2
144 LQFP
Figure 35. 144 LQFP package mechanical drawing (Part 1 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
79
Package characteristics
Figure 36. 144 LQFP package mechanical drawing (Part 2 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
80
Freescale Semiconductor
Package characteristics
Table 45. LQFP144 mechanical data
mm
inches1
Typ
Symbol
Min
Typ
Max
Min
Max
A
1.600
0.150
1.450
0.270
0.200
22.200
20.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
A1
0.050
1.350
0.170
0.090
21.800
19.800
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
A2
1.400
0.220
0.0551
0.0087
b
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5 °
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
0.0 °
D1
D3
E
21.800
19.800
22.200
20.200
0.8583
0.7795
0.8740
0.7953
E1
E3
e
L
0.450
0.0 °
0.750
7.0°
0.0177
3.5 °
0.0295
7.0 °
L1
k
Tolerance
ccc
mm
inches
0.0031
0.080
1
Values in inches are converted from mm and rounded to 4 decimal digits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
81
Preliminary—Subject to Change Without Notice
Package characteristics
4.1.3
100 LQFP
Figure 37. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
82
Freescale Semiconductor
Package characteristics
Figure 38. 100 LQFP package mechanical drawing (Part 2 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
83
Package characteristics
Figure 39. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
84
Freescale Semiconductor
Package characteristics
Table 46. LQFP100 mechanical data
mm
inches1
Typ
Symbol
Min
Typ
Max
Min
Max
A
1.600
0.150
1.450
0.270
0.200
16.200
14.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
A1
0.050
1.350
0.170
0.090
15.800
13.800
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
A2
1.400
0.220
0.0551
0.0087
b
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5 °
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5 °
D1
D3
E
15.800
13.800
16.200
14.200
0.6220
0.5433
0.6378
0.5591
E1
E3
e
L
0.450
0.0 °
0.750
7.0 °
0.0177
0.0 °
0.0295
7.0 °
L1
k
Tolerance
ccc
mm
inches
0.0031
0.080
1
Values in inches are converted from mm and rounded to 4 decimal digits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
85
Preliminary—Subject to Change Without Notice
Package characteristics
4.1.4
208MAPBGA
Figure 40. 208 MAPBGA package mechanical drawing (Part 1 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
86
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 41. 208 MAPBGA package mechanical drawing (Part 2 of 2)
Table 47. LBGA208 mechanical data
inches1
mm
Symbol
Notes
Min
Typ
Max
Min
Typ
Max
2
A
1.70
0.0669
A1
A2
A3
A4
b
0.30
0.0118
1.085
0.30
0.0427
0.0118
0.80
0.70
0.0315
0.0276
3
0.50
0.60
0.0197
0.0236
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
87
Package characteristics
Table 47. LBGA208 mechanical data (continued)
mm
Typ
inches1
Typ
Symbol
Notes
Min
Max
Min
Max
D
D1
E
16.80
17.00
15.00
17.00
15.00
1.00
17.20
0.6614
0.6693
0.5906
0.6693
0.5906
0.0394
0.0394
0.6772
16.80
17.20
0.6614
0.6772
E1
e
F
1.00
ddd
eee
fff
0.20
0.25
0.10
0.0079
0.0098
0.0039
4
5
1
2
Values in inches are converted from mm and rounded to 4 decimal digits.
LBGA stands for Low profile Ball Grid Array.
- Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A2 Typ+A1 Typ +√ (A12+A32+A42 tolerance values)
- Low profile: 1.20mm < A < 1.70mm
3
4
The typical ball diameter before mounting is 0.60mm.
The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with
respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this
tolerance zone.
5
The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as
defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
MPC5607B Microcontroller Data Sheet, Rev. 3
88
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Ordering information
5
Ordering information
Figure 42. Commercial product code structure
Example code:
M
PC
56
0
7
B
E
M
LL
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
Qualification Status
M = MC status
Flash Size (z0 core)
5 = 768 KB
Temperature spec.
C = –40° C to 85°C
V = –40° C to 105°C
M = –40° C to 125°C
S = Auto qualified
P = PC status
6 = 1024 KB
7 = 1.5 MB
Automotive Platform
56 = PPC in 90nm
Product
B = Body
Package Code
LL = 100 LQFP
LQ = 144 LQFP
LU= 176 LQFP
57 = PPC in 65nm
C = Gateway
1
208 MAPBGA available only as development package for Nexus2+
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
89
Revision history
6
Revision history
Table 48 summarizes revisions to this document.
Table 48. Revision history
Substantive changes
Revision
Date
1
2
12-Jan-2009 Initial release
09 Nov-2009 Updated Features
-Replaced 27 IRQs in place of 23
-ADC features
-External Ballast resistor support conditions
-updated device summary-added 208 BGA details
-updated block diagram to include WKUP
-updated block diagram to include 5 ch ADC 12 -bit
-updated Block summary table
-updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC
signals as ADCx_P[x] and ADCx_S[x]
Section 1, “General description
-updated Bolero 1.5M device comparison table
-updated block diagram-aligned with 512k
-updated block summary-aligned with 512k
Section 2, “Package pinouts
-updated 100,144,176,208 packages according to cut2.0 changes
Added Section 3.5.1, “External ballast resistor recommendations
Added NVUSRO [WATCHDOG_EN] field description
updated Absolute maximum ratings
updated LQFP thermal characteristics
updated I/O supply segments
updated Voltage regulator capacitance connection
updated Low voltage monitor electrical characteristics
updated Low voltage power domain electrical characteristics
updated DC electrical characteristics
updated Program/Erase specifications
updated Conversion characteristics (10 bit ADC)
updated FMPLL electrical characteristics
updated Fast RC oscillator electrical characteristics-aligned with Bolero 512K
updated On-chip peripherals current consumption
updated ADC characteristics and error definitions diagram
updated ADC conversion characteristics (10 bit and 12 bit)
Added ADC characteristics and error definitions diagram for 12 bit ADC
3
25 Jan-2010 Updated Features
Updated block diagram to connect peripherals to pad I/O
Updated block summary to include ADC 12-bit
Updated 144, 176 and 100 pinouts to adjust format issues
Table 26 Flash module life-retention value changed from 1-5 to 5 yrs
Minor editing changes
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
90
Freescale Semiconductor
Abbreviations
Appendix A
Abbreviations
Table 49 lists abbreviations used but not defined elsewhere in this document.
Table 49. Abbreviations
Abbreviation
Meaning
CMOS
CPHA
CPOL
CS
Complementary metal–oxide–semiconductor
Clock phase
Clock polarity
Peripheral chip select
Event out
EVTO
LED
Light emitting diode
Message clock out
Message data out
Message start/end out
Modified timing format enable
Serial communications clock
Serial data out
MCKO
MDO
MSEO
MTFE
SCK
SOUT
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5607B Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
91
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MPC5607B
Rev. 3
01/2010
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