PPXS3015VMS1R [FREESCALE]
PXS30 Microcontroller; PXS30微控制器
| 型号： | PPXS3015VMS1R |
| 厂家： | 
Freescale |
| 描述： | PXS30 Microcontroller |
| 文件： | 总139页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXS30
Rev. 1, 09/2011
PXS30
PXS30 Microcontroller Data
Sheet
473 MAPBGA
(19 x 19 mm)
257 MAPBGA
(14 x 14 mm)
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 19
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 70
3.3 Recommended operating conditions . . . . . . . . . . . . . . 71
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73
3.5 Electromagnetic interference (EMI) characteristics . . . 74
3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 75
3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8 Power Management Controller (PMC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 78
3.10 Temperature sensor electrical characteristics . . . . . . . 78
3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 79
3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 79
3.13 16 MHz RC oscillator electrical characteristics . . . . . . 81
3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 81
3.15 Flash memory electrical characteristics . . . . . . . . . . . . 87
3.16 SRAM memory electrical characteristics . . . . . . . . . . . 89
3.17 GP pads specifications. . . . . . . . . . . . . . . . . . . . . . . . . 89
3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 91
3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . . 96
3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 102
3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 110
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 132
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 138
The PXS30 family represents a new generation of
32-bit microcontrollers based on the Power
Architecture . These devices provide a
®
cost-effective, single chip display solution for the
industrial market. An integrated TFT driver with
digital video input ability from an external video
source, significant on-chip memory, and low power
design methodologies provide flexibility and
reliability in meeting display demands in rugged
environments. The advanced processor core offers
high performance processing optimized for low
power consumption, operating at speeds as high as
64 MHz. The family itself is fully scalable from
512 KB to 1 MB internal flash memory. The
memory capacity can be further expanded via the
on-chip QuadSPI serial flash controller module.
2
3
The PXS30 family platform has a single level of
memory hierarchy supporting on-chip SRAM and
flash memories. The 1 MB flash version features
160 KB of on-chip graphics SRAM to buffer cost
effective color TFT displays driven via the on-chip
Display Control Unit (DCU). See Table 1 for
specific memory size and feature sets of the product
family members.
4
5
6
7
The PXS30 family benefits from the extensive
development infrastructure for Power Architecture
devices, which is already well established. This
includes full support from available software
drivers, operating systems, and configuration code
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Preliminary—Subject to Change Without Notice
Introduction
to assist with users’ implementations. See Section 3, Developer support, for more information.
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and
highlights important electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS30
series of microcontroller units (MCUs). For functional characteristics, see the PXS30 Microcontroller
Reference Manual.
1.2
Device comparison
Table 1. PXS30 Family Feature Set
Features
PXS3010 PXS3015
PXS3020
CPU
Type
2 × e200z7d (SoR1) in lock-step or decoupled operation
Harvard
Architecture
Execution speed
0–150 MHz (+2% FM) 0–180 MHz (+2% FM) 0–180 MHz (+2% FM)
Nominal platform
frequency (in 1:1, 1:2,
and 1:3 modes)
0–75 MHz (+2% FM)
0–90 MHz (+2% FM)
0–90 MHz (+2% FM)
MMU
64 entries (SoR)
Yes
Instruction set PPC
Instruction set VLE
Instruction cache
Data cache
Yes
16 KB, 4-way with EDC (SoR)
16 KB, 4-way with EDC (SoR)
Yes (SoR)
MPU
Buses
Core bus
32-bit address, 64-bit data
32-bit address, 32-bit data
Yes (SoR)
Internal periphery bus
Master slave ports
Static RAM (SRAM)
Code Flash memory
Data Flash memory
XBAR
Memory
256 KB (ECC)
1 MB2
384 KB (ECC)
512 KB (ECC)
2 MB2
1.5 MB2
64 KB2
PXS30 Microcontroller Data Sheet, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
Table 1. PXS30 Family Feature Set (continued)
PXS3010 PXS3015
257 pin pkg: 4 × 12 bit (22 external channels)
Features
PXS3020
Modules
Analog-to-Digital
Converter (ADC)
473 pin pkg: 4 12 bit (up to 34 external channels)
×
CRC unit
2 (3 contexts each)
2 modules
Cross Triggering Unit
(CTU)
Serial Peripheral
Interface (SPI)
2 modules
(3 chip selects)
3 modules
(3 chip selects)
Digital I/Os
16
DRAM Controller
(DRAMC)
No
Yes3
Enhanced Direct
2 modules, 32 channels each
Memory Access (eDMA)
eTimer
3 modules, 6 channels each
1 module3
External Bus Interface
(EBI)
16-bit Data + Address or 32-bit Data with Address bus muxed4
Fast Ethernet Controller
(FEC)
1 module
Fault Collection and
Control Unit (FCCU)
1 module
CAN
4 modules (32 message buffers each)
3 modules (each 4 × 3 channels)
Optional
PWM
FlexRay
I2C
2 modules
3 modules
3 modules
Interrupt Controller
(INTC)
Yes (SoR)
1 module4
UART/LIN
4 modules
Parallel Data Interface
(PDI)
Periodic Interrupt Timer
(PIT)
1 module, 4 channels
Yes (SoR)
Software Watchdog
Timer (SWT)
System Timer Module
(STM)
Yes (SoR)
Temperature sensor
Wakeup Unit (WKPU)
Crossbar switch (XBAR)
1 module
Yes
3 modules, 2 are user-configurable
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Introduction
Table 1. PXS30 Family Feature Set (continued)
Features
PXS3010
PXS3015
PXS3020
Clocking
Clock monitor unit
(CMU)
3 modules
Clock output
2 modules
Frequency-modulated
phase-locked loop
(FMPLL)
2 modules (system and auxiliary)
IRCOSC – 16 MHz
1
1
XOSC 4 MHz – 40 MHz
Supply
Power management unit
(PMU)
Yes
1.2 V low-voltage
detector (LVD12)
1
1
4
1.2 V high-voltage
detector (HVD12)
2.7 V low-voltage
detector (LVD27)
Debug
Nexus
Class 3+ (for cores and SRAM ports)
473 pins
Packages
MAPBGA
257 pins
473 pins
Temperature Ambient
NOTES:
See the TA recommended operating condition in the device data sheet
1
Sphere of Replication.
2
3
4
Does not include Test or Shadow Flash memory space.
Available only on 473-pin package.
DDR available only on 473 package. Other modules available as follows:
EBI or DDR on 473 package.
EBI + PDI on 473 package.
DDR + PDI on 473 package
PDI only on 257 package.
1.3
Block diagram
Figure 1 shows a top-level block diagram of the PXS30 device.
PXS30 Microcontroller Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
PXS30 Block Diagram
Debug
JTAG
e200z7
e200z7
PMU
SWT
MCM
STM
PMU
SWT
MCM
STM
Nexus
SPE2
VLE
SPE2
VLE
FlexRay™
MMU
Cache
MMU
Cache
Ethernet
PDI
INTC
eDMA
INTC
eDMA
Redundancy
Checker
Crossbar Switch (XBAR)
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Memory Protection Unit (MPU)
PBRIDGE
EBI
Redundancy Checker
2 MB Flash (ECC)
Redundancy Checker
512 KB SRAM (ECC)
MDDR
PBRIDGE
Redundancy Checker
Communications
I/O System
ADC
BAM
CAN
CMU
CRC
CTU
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Clock monitoring unit
– Cyclic redundancy check unit
– Cross triggering unit
– External bus interface
mDDR
– Mobile double data rate dynamic RAM
PBRIDGE – Peripheral I/O bridge
PDI
PIT
PMU
PWM
RC
– Parallel data interface
– Periodic interrupt timer
– Power management unit
– Pulse width modulator module
– Redundancy checker
EBI
ECC
ECSM
eDMA
FCCU
FEC
– Error correction code
RTC
– Real time clock
– Semaphore unit
– Error correction status module
– Enhanced direct memory access controller
– Fault collection and control unit
– Fast Ethernet controller
– Frequency-modulated phase-locked loop
– Inter-integrated circuit controller
SEMA4
SIUL
SPI
SSCM
STM
SWT
TSENS
– System integration unit Lite
– Serial peripheral interface controller
– System status and configuration module
– System timer module
– Software watchdog timer
– Temperature sensor
FMPLL
I2C
IRCOSC – Internal RC oscillator
INTC
JTAG
MC
– Interrupt controller
– Joint Test Action Group interface
– Mode entry, clock, reset, & power modules
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
XOSC
– Crystal oscillator
Figure 1. PXS30 block diagram
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Introduction
1.4
Feature list
•
High-performance e200z7d dual core
— 32-bit Power Architecture technology CPU
— Up to 180 MHz core frequency
— Dual-issue core
— Variable length encoding (VLE)
— Memory management unit (MMU) with 64 entries
— 16 KB instruction cache and 16 KB data cache
Memory available
•
•
— Up to 2 MB Code flash memory with ECC
— 64 KB Data flash memory with ECC
— Up to 512 KB on-chip SRAM with ECC
SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection
— Sphere of replication (SoR) for key components
— Redundancy checking units on outputs of the SoR connected to FCCU
— Fault collection and control unit (FCCU)
— Boot-time built-in self-test for memory (MBIST) and logic (LBIST) triggered by hardware
— Boot-time built-in self-test for ADC and flash memory
— Replicated safety-enhanced watchdog timer
— Junction temperature sensor
— Non-maskable interrupt (NMI)
— 16-region memory protection unit (MPU)
— Clock monitoring units (CMU)
— Power management unit (PMU)
— Cyclic redundancy check (CRC) units
Decoupled Parallel mode for high-performance use of replicated cores
Nexus Class 3+ interface
•
•
•
Interrupts
— Replicated 16-priority interrupt controller
— Replicated 32-channel eDMA controller
GPIOs individually programmable as input, output, or special function
3 general-purpose eTimer units (6 channels each)
3 FlexPWM units with four 16-bit channels per module
Communications interfaces
•
•
•
•
— 4 LINFlex modules
— 3 DSPI modules with automatic chip select generation
— 4 FlexCAN interfaces (2.0B Active) with 32 message objects
PXS30 Microcontroller Data Sheet, Rev. 1
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
— FlexRay module (V2.1) with dual channel, up to 128 message objects and up to 10 Mbit/s
— Fast Ethernet Controller (FEC)
2
— 3 I C modules
•
Four 12-bit analog-to-digital converters (ADCs)
— 22 input channels
— Programmable cross triggering unit (CTU) to synchronize ADC conversion with timer and
PWM
•
•
•
•
•
External bus interface
16-bit external DDR memory controller
Parallel digital interface (PDI)
On-chip CAN/UART bootstrap loader
Capable of operating on a single 3.3 V voltage supply
— 3.3 V-only modules: I/O, oscillators, flash memory
— 3.3 V or 5 V modules: ADCs, supply to internal VREG
— 1.8–3.3 V supply range: DRAM/PDI
Operating junction temperature range –40 to 150 °C
•
1.5
Feature details
1.5.1
High-performance e200z7d core processor
•
•
•
•
•
Dual 32-bit Power Architecture processor core
Loose or tight core coupling
Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction
Thirty-two 64-bit general-purpose registers (GPRs)
Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer
(TLB)
•
•
•
Branch processing unit
Fully pipelined load/store unit
16 KB Instruction and 16 KB Data caches per core with line locking
— Four way set associative
— Two 32-bit fetches per clock
— Eight-entry store buffer
— Way locking
— Supports tag and data parity
Vectored interrupt support
•
•
Signal processing engine 2 (SPE2) auxiliary processing unit (APU) operating on 64-bit general
purpose registers
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Introduction
•
Floating point
— IEEE 754 compatible with software wrapper
— Single precision in hardware; double precision with software library
— Conversion instructions between single precision floating point and fixed point
•
Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the
PXS30
•
•
To reduce latency, long cycle time instructions are aborted upon interrupt requests
Extensive system development support through Nexus debug module
1.5.2
Crossbar switch (XBAR)
•
•
32-bit address bus, 64-bit data bus
Simultaneous accesses from different masters to different slaves (there is no clock penalty when a
parked master accesses a slave)
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA,
FlexRay, CPU) can be assigned different access rights to each region.
•
•
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
1.5.4
Enhanced Direct Memory Access (eDMA) controller
•
•
•
32 channels support independent 8-, 16-, 32-bit single value or block transfers
Supports variable-sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain
constant
•
•
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
1.5.5
Interrupt Controller (INTC)
•
•
•
•
•
208 peripheral interrupt requests
8 software settable sources
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resources
PXS30 Microcontroller Data Sheet, Rev. 1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
1.5.6
Frequency-Modulated Phase-Locked Loop (FMPLL)
Two FMPLLs are available on each device.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of
4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor and output clock divider ratio are software configurable. The
FMPLLs have the following major features:
•
•
•
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
Option to switch modulation on and off via software interface
Reduced frequency divider (RFD) for reduced frequency operation without re-lock
2 modes of operation
•
•
•
— Normal PLL mode with crystal reference (default)
— Normal PLL mode with external reference
•
•
•
•
Lock monitor circuitry with lock status
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
Auxiliary FMPLL
— Used for FlexRay due to precise symbol rate requirement by the protocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow
independent frequencies of operation for PWM and timers as well as jitter-free control
— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential
unadjusted error in electric motor control loop
— Allows running motor control periphery at different (precisely lower, equal, or higher ,as
required) frequency than the system to ensure higher resolution
1.5.7
External Bus Interface (EBI)
•
•
Available on 473-pin devices
Data and address options:
— 16-bit data and address (non-muxed)
— 32-bit data and address (bus-muxed)
•
•
MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default
ADDR[8:31], but configurable to 26-bit address bus.
Memory controller with support for various memory types
— Non-burst and burst mode SDR flash and SRAM
— Asynchronous/legacy flash and SRAM
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Introduction
•
•
•
Configurable bus speed modes
Support for 2 MB address space
Chip select and write/byte enable options as presented in the pin-muxing table in Section 2,
Package pinouts and signal descriptions
•
•
Configurable wait states (via chip selects)
Optional automatic CLKOUT gating to save power and reduce EMI
1.5.8
On-chip flash memory
•
•
•
•
Up to 2 MB Code flash memory with ECC
64 KB Data flash memory with ECC
Censorship protection scheme to prevent flash content visibility
Multiple block sizes to support features such as boot block, operating system block, and EEPROM
emulation
•
•
•
Read-while-write with multiple partitions
Parallel programming mode to support rapid end of line programming
Hardware programming state machine
1.5.9
Cache memory
•
•
•
Harvard architecture cache
16 KB instruction / 16 KB data
Four-way set-associative Harvard (instruction and data) 256-bit long cache
— Two 32-bit fetches per clock
— Eight-entry store buffer
— Way locking
— Supports tag and data parity
1.5.10 On-chip internal static RAM (SRAM)
•
•
Up to 512 KB general-purpose SRAM
ECC performs single-bit correction, double-bit error detection
— Address included in ECC checkbase
1.5.11 DRAM controller
The DRAM controller (available only on 473-pin devices) is a multi-port controller that monitors
incoming requests on the three AHB slave ports and decides (at each rising clock edge) what command
needs to be sent to the external DRAM.
The DRAM controller on this device supports the following types of memories:
•
Mobile DDR (mDDR)
PXS30 Microcontroller Data Sheet, Rev. 1
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
•
•
•
DDR 1
DDR 2 (optional)
SDR
The controller has the following features:
•
•
•
•
•
•
Optimized timing for 32-byte bursts and single read accesses on the AHB interface
Optimized timing for 8-byte and 16-byte bursts on the DRAMC interface
Supports priority elevation on the slave ports for single accesses
16-bit wide DRAM interface
One chip select (CS)
mDDR memory controller
— 16-bit external interface
— Address range up to 8 MB
1.5.12 Boot Assist Module (BAM)
•
•
•
•
Enables booting via serial mode (FlexCAN, LINFlex)
Handles static mode in case of an erroneous boot procedure
Implemented in 8 KB ROM
Supports Lock Step Mode (LSM) and Decoupled Parallel Mode (DPM)
1.5.13 Parallel Data Interface (PDI)
•
•
•
•
•
•
Support for external ADC and CMOS image sensors
Parallel interface operation up to MCU system bus frequency
Selectable data capture from rising or falling edge
Receive FIFO with adjustable trigger thresholds
Data width for 8, 10, 12, 14, and 16 bits
Data Packing Unit to pack input data on 64-bit words — data packed on 8- or 16- bit boundary,
depending on input data width
•
•
Binary increasing channel select that allows as many as eight channels to be selected
Frame synchronization through Vsync, Hsync, PIXCLK
1.5.14 Deserial Serial Peripheral Interface (DSPI) modules
•
Three Serial Peripheral Interfaces
— Full duplex communication ports with interrupt and eDMA request support
— Support for all functional modes from QSPI submodule of QSMCM (MPC5xx family)
— Support for queues in RAM
— Six chip selects, expandable to 64 with external demultiplexers
— Programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Introduction
— Modified SPI mode for interfacing to peripherals with longer setup time requirements
Support for up to 60 Mbit/s in Slave Only Rx mode
•
1.5.15 Serial communication interface module (LINFlex)
The LINFlex on this device features the following:
•
•
•
•
Supports LIN Master mode, LIN Slave mode, and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Manages LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store as many as 8 data bytes
— Supports messages as long as 64 bytes
— Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum
and time-out errors)
— Classic or extended checksum calculation
— Configurable break duration of up to 36-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features (Loop back, LIN bus stuck dominant detection)
— Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
•
•
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit, 9-bit, or 16-bit words)
— Configurable parity scheme: none, odd, even, always 0
— Speed as fast as 2 Mbit/s
— Error detection and flagging (parity, noise, and framing errors)
— Interrupt-driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
•
Support for DMA-enabled transfers
PXS30 Microcontroller Data Sheet, Rev. 1
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
1.5.16 FlexCAN
•
•
•
•
•
•
•
•
•
•
•
Thirty-two message buffers each
Full implementation of the CAN protocol specification, Version 2.0B
Programmable acceptance filters
Individual Rx filtering per message buffer
Short latency time for high priority transmit messages
Arbitration scheme according to message ID or message buffer number
Listen-only mode capabilities
Programmable clock source: system clock or oscillator clock
Reception queue possible by setting more than one Rx message buffer with the same ID
Backwards compatible with previous FlexCAN modules
Safety CAN features on 1 CAN module as implemented on MPC5604P
1.5.17 Dual-channel FlexRay controller
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1
Sixty-four configurable message buffers can be handled
Message buffers configurable as Tx, Rx, or RxFIFO
Message buffer size configurable
Message filtering for all message buffers based on FrameID, cycle count, and message ID
Programmable acceptance filters for RxFIFO message buffers
Dual channel, each at up to 10 Mbit/s data rate
1.5.18 Periodic Interrupt Timer (PIT)
The PIT module implements the features below:
•
•
•
•
•
Four general-purpose interrupt timers
32-bit counter resolution
Clocked by system clock frequency
32-bit counter for real time interrupt, clocked from main external oscillator
Can be used for software tick or DMA trigger operation
1.5.19 System Timer Module (STM)
The STM implements the features below:
•
•
•
Duplicated periphery to guarantee that safety targets (SIL3) are achieved
Up-counter with four output compare registers
OS task protection and hardware tick implementation as per current state-of-the-art AUTOSAR
requirement
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Introduction
1.5.20 Motor control (MOTC) peripherals
The peripherals in this section can be used for general-purpose applications, but are specifically designed
for motor control (MOTC) applications.
1.5.20.1 FlexPWM
The pulse width modulator module (FlexPWM) contains three PWM channels, each of which is
configured to control a single half-bridge power stage. There may also be one or more fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM), Permanent Magnet
AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable
reluctance motors (VRM), and stepper motors.
A FlexPWM module implements the following features:
•
•
•
•
•
•
•
•
•
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
Maximum operating frequency lower than or equal to platform frequency
Clock source not modulated and independent from system clock (generated via auxiliary PLL)
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM is supported
Double-buffered PWM registers
— Integral reload rates from 1 to 16
— Half-cycle reload capability
•
•
•
•
•
•
•
•
•
•
•
•
•
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual-edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
PXS30 Microcontroller Data Sheet, Rev. 1
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
— External ADC input, taking into account values set in ADC high and low limit registers
DMA support
•
1.5.20.2 Cross Triggering Unit (CTU)
The CTU provides automatic generation of ADC conversion requests on user selected conditions without
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
•
•
Cross triggering between ADC, FlexPWM, eTimer, and external pins
Double-buffered trigger generation unit with as many as eight independent triggers generated from
external triggers
•
•
•
•
Maximum operating frequency lower than or equal to platform
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low-pass filter
Double-buffered global trigger unit allowing eTimer synchronization and/or ADC command
generation
•
•
•
•
Double-buffered ADC command list pointers to minimize ADC-trigger unit update
Double-buffered ADC conversion command list with as many as twenty-four ADC commands
Each trigger has the capability to generate consecutive commands
ADC conversion command allows controlling ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
•
DMA support with safety features
1.5.20.3 Analog-to-Digital Converter (ADC)
•
•
•
•
•
Four independent ADCs with 12-bit A/D resolution
Common mode conversion range of 0–5 V or 0–3.3 V
Twenty-two single-ended input channels
Supports eight FIFO queues with fixed priority
Queue modes with priority-based preemption; initiated by software command, internal, or external
triggers
•
DMA and interrupt request support
1.5.20.4 eTimer module
Three 16-bit general purpose up/down timer/counters per module are implemented with the following
features:
•
•
Ability to operate up to platform frequency
Individual channel capability
— Input capture trigger
— Output compare
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Introduction
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
•
— Equals peripheral clock/2 for external event counting
— Equals peripheral clock for internal clock counting
Cascadeable counters
•
•
•
•
•
•
•
•
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
1.5.21 Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the
following features:
•
•
Duplicated module to guarantee highest possible diagnostic coverage (check of checker)
Replicated IP to be used as checkers on the PBRIDGE output, flash controller output, SRAM
Output, DMA Channel Mux inputs
1.5.22 Software Watchdog Timer (SWT)
This module implements the features below:
•
•
•
•
•
•
Duplicated periphery to guarantee that safety targets (SIL3) are achieved
Fault-tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows high level of safety (SIL3 monitor)
1.5.23 Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
•
•
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on the device
PXS30 Microcontroller Data Sheet, Rev. 1
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
•
•
Collection of test results
Configurable and graded fault control
— Internal reactions (no internal reaction, NMI, reset, or safe mode)
— External reaction (failure is reported to the outside world via configurable output pins)
1.5.24 System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O
(GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block
contains the external pin boot configuration logic. The pad configuration block controls the static electrical
characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O
pins of the MCU.
The SIUL provides the following features:
•
Centralized pad control on per-pin basis
— Pin function selection
— Configurable weak pullup/pulldown
— Configurable slew rate control (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
Input filtering for external interrupts
•
1.5.25 Cyclic Redundancy Checker (CRC) unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to
an input register.
The CRC unit has the following features:
•
•
•
Three sets of registers to allow three concurrent contexts with possibly different CRC
computations, each with a selectable polynomial and seed
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores the result in an
internal register
Implements the following standard CRC polynomials:
16
12
5
— x + x + x + 1 [16-bit CRC-CCITT]
32
26
23
22
16
12
11
10
8
7
5
4
2
— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
[32-bit CRC-ethernet(32)]
•
•
Key engine to be coupled with communication periphery where CRC application is added to allow
implementation of safe communication protocol
Offloads the core from cycle-consuming CRC and helps in checking the configuration signature
for safe start-up or periodic procedures
•
•
Connected as a peripheral on the internal peripheral bus
Provides DMA support
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Introduction
1.5.26 Non-maskable interrupt (NMI)
The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions.
1.5.27 System Status and Configuration Module (SSCM)
The SSCM on the PXS30 features the following:
•
•
•
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset
Configuration Half Word
•
Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code
(default) or as Freescale VLE code out of flash
•
•
•
Supports serial bootloading of either Classic PowerPC Book E code (default) or Freescale VLE code
Detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
1.5.28 Nexus Development Interface (NDI)
•
•
Per IEEE-ISTO 5001-2008
Real-time development support for Power Architecture core through Nexus class 3 (some class 4
support)
•
•
•
•
•
•
Nexus support to snoop system SRAM traffic
Data trace of FlexRay accesses
Read and write access
Configured via the IEEE 1149.1 (JTAG) port
High bandwidth mode for fast message transmission
Reduced bandwidth mode for reduced pin usage
1.5.29 IEEE 1149.1 JTAG controller (JTAGC)
•
•
IEEE 1149.1-2001 Test Access Port (TAP) interface
JCOMP input that provides the ability to share the TAP —selectable modes of operation include
JTAGC/debug or normal system operation
•
•
•
5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
5-bit instruction register that supports additional public instructions
Three test data registers:
— Bypass register
— Boundary scan register
— Device identification register
•
TAP controller state machine that controls the operation of the data registers, instruction register,
and associated circuitry
PXS30 Microcontroller Data Sheet, Rev. 1
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
Figure 2 shows the PXS30 in the 257 MAPBGA package. Figure 3 through Figure 6 show the PXS30 in
the 473 MAPBGA package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
flexray
CA_TR_
EN
fec
RX_
CLK
A
B
C
D
E
F
A
B
C
D
E
F
VSS_
HV_IO
VSS_
HV_IO
VDD_
nexus
nexus
nexus
flexray
VDD_
HV_IO
fec
RXD[2]
fec
RXD[0]
fec
MDIO
fec
TX_EN
fec
TXD[3]
VSS_
HV_IO
VSS_
HV_IO
HV_IO MDO[5] MDO[7] MDO[9] CB_TX
nexus
MDO
[14]
flexray
CB_TR_
EN
fec
TX_
CLK
VSS_
HV_IO
VSS_
HV_IO
mc_cgl
clk_out
can1
TXD
dspi2
CS1
flexray
CA_TX
VSS_
HV_IO
fec
fec
fec
fec
can0
TXD
VDD_
HV_IO
VSS_
HV_IO
RXD[3] RX_ER RXD[1] TX_ER
nexus
MDO
[15]
pdi
DATA
[5]
VDD_
HV_IO
VSS_
HV_IO
FCCU_
F[1]
flexray
CB_RX ETC[0]
etimer0 etimer0 etimer0 etimer0
fec
CRS
fec
TXD[0]
fec
COL
can0
RXD
VSS_
HV_PDI
pdi
CLOCK
JCOMP
ETC[1]
ETC[2]
ETC[3]
nexus
MDO
[2]
nexus
MDO
[3]
pdi
DATA
[0]
pdi
DATA
[1]
can1
RXD
dspi0 RESERV etimer0 etimer0
SOUT
VDD_
VSS_
fec
fec
fec
fec
MDC
VDD_
HV_PDI HV_IO
VSS_
ED
ETC[5]
ETC[4] HV_FLA HV_FLA TXD[2]
TXD[1] RX_DV
nexus
MDO
[0]
nexus
MDO
[1]
pdi
pdi
DATA
[3]
pdi
DATA
[4]
flexray
CA_RX
pdi
DATA
LINE_V
[2]
NMI
nexus
MDO
[11]
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
pdi
mc_cgl
DATA
pdi
DATA
[7]
pdi
DATA
[8]
nexus
MDO[6]
dspi1
SOUT
dspi1
SIN
clk_out
[6]
nexus
MDO
[4]
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
[9]
pdi
DATA
[10]
pdi
pdi
G
H
J
G
H
J
VDD_
HV_IO
dspi0
SCK
dspi1
SCK
DATA FRAME_
[11]
V
nexus
MDO
[10]
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
[12]
pdi
DATA
[13]
VDD_
HV_
PDI
flexpwm
0
X[0]
VSS_
HV_IO
dspi0
CS0
dspi1
CS0
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
[14]
pdi
DATA
[15]
VSS_
HV_
PDI
flexpwm
0
X[1]
nexus
MCKO MDO[8]
nexus
dspi2
CS0
dspi2
CS2
nexus
MSEO_ MSEO_
B[0]
nexus
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
flexpwm flexpwm flexpwm flexpwm
K
L
nexus
RDY_B
dspi0
SIN
K
L
0
X[2]
0
X[3]
0
A[1]
0
B[0]
B[1]
nexus
MDO
[13]
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
VDD_HV
_DRAM_
VREF
flexpwm
0
B[1]
nexus
EVTO_B EVTI_B
nexus
dspi2
SCK
TCK
TDI
TDO
VDD_
VDD_
HV_
nexus
MDO
[12]
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
flexpwm
0
flexpwm
1
M
N
P
R
T
M
N
P
R
T
dspi1
CS2
TMS
HV_IO
OSC
B[2]
A[1]
flexpwm flexpwm flexpwm flexpwm
VSS_
XTALIN
dspi0
CS3
VSS_
LV_PLL
0
B[3]
0
A[2]
1
A[0]
1
B[0]
HV_IO
VSS_
HV_
OSC
adc0_
adc1
AN[14]
flexpwm flexpwm flexpwm
dspi0
CS2
VDD_
LV_PLL ETC[1]
etimer1 etimer1
adc0
AN[0]
etimer1
ETC[3]
VSS_
HV_IO
VDD_
HV_IO
etimer1 etimer1
ETC[4]
VDD_
HV_IO
RESET
0
0
A[0]
1
B[1]
ETC[2]
ETC[5]
A[3]
VDD_
HV_
adc2_
adc3
VDD_
HV_
adc0_
adc1
AN[13]
flexpwm flexpwm
XTAL
OUT
FCCU_ VSS_HV
F[0]
dspi1
CS3
adc2
AN[0]
adc2
AN[3]
adc0
AN[2]
adc1
AN[1]
VREG_C
TRL
lin0
TXD
VSS_
HV_IO
1
1
B[2]
_IO
ADR_13 AN[14] ADR_02
A[2]
VSS_
HV_
adc2_
adc3
VSS_
HV_
adc0_
adc1
AN[12]
VSS_
HV_IO
VDD_
HV_IO
dspi2
SOUT
adc3
AN[0]
adc3
AN[3]
adc2
AN[2]
adc0
AN[1]
adc1
AN[0]
adc1
AN[2]
lin0
RXD
etimer1
ETC[0]
VDD_
HV_IO
VSS_
HV_IO
ADR_13 AN[13] ADR_02
adc2_
adc3
AN[11]
adc2_
adc3
AN[12]
VDD_
HV_
ADV
VSS_
HV_
ADV
adc0_
adc1
AN[11]
VREG_
INT_EN
ABLE
VSS_
HV_
PMU
U
U
VSS_
HV_IO
VSS_
HV_IO
dspi2
SIN
adc3
AN[1]
adc3
AN[2]
adc2
AN[1]
RESET_ VDD_HV
VSS_
HV_IO
VSS_
HV_IO
SUP
_PMU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Figure 2. PXS30 257 MAPBGA pinout (top view)
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
VSS_
HV_IO
VSS_
HV_IO
VDD_
HV_IO
nexus
MDO[5]
nexus
MDO[7]
nexus
MDO[9]
flexray
CB_TX
flexray
CA_TR_EN
fec
RX_DV
fec
MDIO
fec
TX_CLK
fec
TX_EN
A
B
C
D
E
F
VSS_
HV_IO
VSS_
HV_IO
mc_cgl
clk_out
can1
TXD
nexus
MDO[14]
dspi2
CS1
flexray
CB_TR_EN
flexray
CA_TX
fec
RXD[3]
fec
RX_ER
fec
TXD[0]
fec
RXD[0]
VDD_
HV_IO
nexus
MDO[15]
VSS_
HV_IO
FCCU_
F[1]
flexray
CB_RX
etimer0
ETC[4]
etimer0
ETC[1]
etimer0
ETC[2]
etimer0
ETC[3]
fec
TXD[2]
fec
TXD[1]
fec
CRS
nexus
MDO[1]
nexus
MDO[3]
can1
RXD
dspi0
SOUT
etimer0
ETC[5]
etimer0
ETC[0]
VDD_
HV_IO
VSS_
HV_IO
VSS_
HV_IO
VSS_
HV_FLA
RESERVED
JCOMP
nexus
MDO[0]
nexus
MDO[2]
flexray
CA_RX
NMI
nexus
MDO[10]
nexus
MDO[11]
nexus
MDO[6]
nexus
MDO[4]
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
nexus
MCKO
VDD_
HV_IO
nexus
MDO[8]
nexus
MSEO_B[1]
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
G
H
J
nexus
EVTO_B
VSS_
HV_IO
nexus
MSEO_B[0]
nexus
EVTI_B
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
nexus
RDY_B
nexus
MDO[13]
nexus
MDO[12]
dspi1
SIN
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
dspi0
SCK
dspi1
CS0
dspi1
SCK
dspi1
SOUT
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
K
L
dspi0
CS0
dspi2
CS2
dspi2
CS0
VSS_
HV_IO
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
flexpwm0
X[0]
VDD_
HV_IO
dspi0
SIN
VDD_
HV_IO
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
M
Figure 3. PXS30 473 MAPBGA pinout (northwest, viewed from above)
flexpwm0
A[0]
VSS_
HV_IO
flexpwm0
X[1]
flexpwm0
B[2]
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
N
P
R
T
flexpwm0
B[0]
flexpwm0
B[1]
flexpwm0
A[2]
flexpwm0
A[3]
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
flexpwm0
X[2]
flexpwm0
X[3]
flexpwm0
A[1]
VSS_
HV_IO
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
flexpwm0
B[3]
flexpwm1
A[0]
flexpwm1
A[1]
VDD_
HV_IO
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
flexpwm1
B[0]
flexpwm1
B[1]
flexpwm1
A[2]
dspi2
SCK
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
U
V
W
Y
VDD_
HV_OSC
VDD_
HV_IO
flexpwm1
B[2]
dspi1
CS2
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VSS_
HV_IO
dspi0
CS3
VSS_
LV_PLL
XTALIN
VSS_
HV_OSC
dspi0
CS2
VDD_
LV_PLL
flexpwm1
X[0]
adc3
AN[0]
adc2_adc3 adc2_adc3
AN[11]
etimer1
ETC[1]
etimer1
ETC[2]
etimer1
ETC[3]
VSS_
HV_IO
RESET
AN[14]
FCCU_
F[0]
VSS_
HV_IO
dspi1
CS3
flexpwm1
X[1]
adc3
AN[1]
adc2_adc3
AN[12]
adc2
AN[0]
VDD_
HV_ADV
VSS_
HV_ADV
adc0
AN[2]
adc0
AN[5]
AA XTALOUT
VSS_
AB
VDD_
HV_IO
dspi2
SOUT
flexpwm1
X[2]
flexpwm1
X[3]
adc3
AN[2]
adc2_adc3
AN[13]
adc2
AN[1]
adc2
AN[2]
adc0
AN[0]
adc0
AN[4]
adc0
AN[6]
HV_IO
VSS_
AC
VSS_
HV_IO
dspi2
SIN
flexpwm1
A[3]
flexpwm1
B[3]
adc3
AN[3]
VDD_HV_
ADR_23
VSS_HV_
ADR_23
adc2
AN[3]
adc0
AN[1]
adc0
AN[3]
VDD_
HV_ADR_0
HV_IO
1
2
3
4
5
6
7
8
9
10
11
12
Figure 4. PXS30 473 MAPBGA pinout (southwest, viewed from above)
PXS30 Microcontroller Data Sheet, Rev. 1
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package pinouts and signal descriptions
13
14
15
16
17
18
19
20
21
22
23
fec
TXD[3]
VDD_
HV_IO
pdi
DATA[3]
pdi
DATA[1]
pdi
CLOCK
pdi
DATA[7]
pdi
DATA[10]
pdi
DATA[13]
pdi
DATA[15]
VSS_
HV_IO
VSS_
HV_IO
A
B
C
D
E
F
fec
TX_ER
VSS_
HV_IO
pdi
DATA[6]
pdi
DATA[4]
pdi
DATA[0]
pdi
LINE_V
pdi
DATA[9]
pdi
DATA[14]
can0
TXD
VDD_
HV_IO
VSS_
HV_IO
fec
RX_CLK
fec
RXD[1]
fec
COL
pdi
DATA[5]
pdi
DATA[2]
pdi
DATA[8]
pdi
DATA[12]
can0
RXD
VSS_
HV_PDI
siul
GPIO[197]
dramc
CAS
VDD_
HV_FLA
fec
RXD[2]
fec
MDC
VDD_
HV_PDI
VSS_
HV_PDI
pdi
DATA[11]
pdi
FRAME_V
VDD_
HV_PDI
dramc
BA[1]
siul
GPIO[195]
dramc
BA[0]
mc_cgl
clk_out
siul
GPIO[149]
dramc
CS0
dramc
BA[2]
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
dramc
RAS
siul
GPIO[194]
siul
GPIO[148]
dramc
D[5]
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
siul
GPIO[196]
dramc
DQS[0]
dramc
DM[0]
dramc
D[7]
G
H
J
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
D[2]
VDD_HV_
DRAM_VTT
VDD_HV_
DRAM
VSS_HV_
DRAM
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
D[0]
dramc
D[1]
dramc
D[3]
dramc
D[6]
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VSS_
HV_IO
dramc
D[4]
dramc
D[8]
dramc
D[9]
K
L
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VDD_
HV_IO
VDD_HV_
DRAM_VTT
VSS_HV_
DRAM
VDD_HV_
DRAM
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
ODT
dramc
WEB
dramc
D[11]
dramc
D[10]
M
Figure 5. PXS30 473 MAPBGA pinout (northeast, viewed from above)
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
DQS[1]
dramc
DM[1]
dramc
D[13]
dramc
D[12]
N
P
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
D[14]
dramc
D[15]
VSS_HV_
DRAM
VDD_HV_
DRAM
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VDD_HV_
DRAM_VREF
dramc
ADD[3]
dramc
CKE
dramc
CLKB
R
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
ADD[8]
dramc
ADD[9]
dramc
ADD[1]
dramc
CLK
T
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
dramc
ADD[6]
dramc
ADD[12]
VDD_HV_
DRAM
dramc
ADD[0]
U
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
lin0
TXD
dramc
ADD[13]
VSS_HV_
DRAM
dramc
ADD[2]
V
lin0
RXD
dramc
ADD[14]
dramc
ADD[7]
dramc
ADD[4]
W
Y
VDD_
HV_IO
adc0_adc1
AN[11]
etimer1
ETC[5]
etimer1
ETC[4]
adc1
AN[8]
adc1
AN[6]
dramc
ADD[15]
dramc
ADD[11]
dramc
ADD[5]
TCK
TDI
VDD_HV_IO
adc0
AN[8]
adc0_adc1
AN[12]
adc1
AN[0]
adc1
AN[2]
adc1
AN[5]
adc1
AN[7]
etimer1
ETC[0]
lin1
TXD
dramc
ADD[10]
VSS_HV_IO
AA
AB
AC
adc0
AN[7]
adc0_adc1
AN[13]
adc1
AN[1]
adc1
AN[3]
adc1
AN[4]
lin1
RXD
VDD_
HV_IO
VSS_
HV_IO
TDO
VREG_CTRL
18
TMS
RESERVED
VSS_
HV_ADR_0
adc0_adc1
AN[14]
VDD_
HV_ADR_1
VSS_
HV_ADR_1
VDD_
HV_PMU
VSS_
HV_PMU
RESET_
SUP
VREG_INT_
ENABLE
VSS_
HV_IO
VSS_
HV_IO
13
14
15
16
17
19
20
21
22
23
Figure 6. PXS30 473 MAPBGA pinout (southeast, viewed from above)
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Package pinouts and signal descriptions
2.2
Pin descriptions
The following sections provide signal descriptions and related information about the functionality and
configuration for this device.
2.2.1
Pad types
Table 2 lists the pad types used on the PXS30.
Table 2. Pad types
Pad Type
GP Slow
Description
Slow buffer with CMOS Schmitt trigger and pullup/pulldown.
GP Slow/Fast
Programmable slow/fast buffer with CMOS Schmitt trigger, pullup/pulldown.
GP Slow/Medium
Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown.
Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown
and Injection proof analog switch.
GP Slow/Symmetric Programmable slow/symmetric buffer with CMOS Schmitt trigger,
pullup/pulldown.
PDI Medium
Medium slew-rate output with four selectable slew rates. Contains an input buffer
and weak pullup/pulldown.
PDI Fast
Fast slew-rate output with four selectable slew rates. Contains an input buffer and
weak pullup/pulldown.
DRAM ACC
Bidirectional DDR pad. Can be configured to support LPDDR half strength,
LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR.
DRAM CLK
DRAM DQ
Differential clock driver
Bidirectional DDR pad with integrated ODT. Can be configured to support
LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full
strength, and SDR.
DRAM ODT CTL
Analog
Enable On Die Termination control
CMOS Schmitt trigger cell with injection proof analog switch.
CMOS Schmitt trigger cell with two injection-proof analog switches.
Analog Shared
2.2.2
Power supply and reference voltage pins
Table 3 shows the supply pins for the PXS30 in the 257 MAPBGA package. Table 5 shows the supply pins
for the PXS30 in the 473 MAPBGA package.
Table 4 and Table 6 show the pins not populated on the PXS30 257 MAPBGA and 473 MAPBGA
packages, respectively.
PXS30 Microcontroller Data Sheet, Rev. 1
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 257 MAPBGA supply pins
Ball
Number
Ball
Pad Type
Ball Name
Ball Name
Pad Type
Number
VDD
A3
A9
VDD_HV_IO
VDD_HV_IO
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV_A
VDD_HV_A
VDD_HV_A
VDD_LV
F9
F10
F11
F12
G6
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_PLL
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
B16
C1
VDD_HV_IO
VDD_HV_IO
G2
M2
P10
P14
T2
VDD_HV_IO
VDD_HV_IO
G12
H6
VDD_HV_IO
VDD_HV_IO
H12
J6
VDD_HV_IO
T16
L14
D8
VDD_HV_IO
J12
K6
VDD_HV_DRAM_VREF
VDD_HV_FLA
VDD_HV_OSC
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PMU
VDD_HV_ADR_13
VDD_HV_ADR_02
VDD_HV_ADV
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
K12
L6
M1
D14
H16
U14
R7
L12
M6
M7
M8
R9
M9
U9
M10
M11
M12
P4
F6
F7
VDD_LV
F8
VDD_LV
VSS
A1
A2
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
G7
G8
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
A16
A17
B1
G9
G10
G11
H7
B2
B9
H8
B17
C3
H9
H10
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Package pinouts and signal descriptions
Table 3. 257 MAPBGA supply pins (continued)
Ball
Number
Ball
Number
Ball Name
Pad Type
Ball Name
Pad Type
D15
H2
VSS_HV_IO
VSS_HV_IO
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV_A
VSS_HV_A
VSS_HV_A
H11
J7
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_PLL
VSS_HV_PMU
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
N2
VSS_HV_IO
J8
P9
VSS_HV_IO
J9
R3
VSS_HV_IO
J10
J11
K7
R15
T1
VSS_HV_IO
VSS_HV_IO
T17
U1
VSS_HV_IO
K8
VSS_HV_IO
K9
U2
VSS_HV_IO
K10
K11
L7
U16
U17
D9
VSS_HV_IO
VSS_HV_IO
VSS_HV_FLA
VSS_HV_OSC
VSS_HV_PDI
VSS_HV_PDI
VSS_HV_ADR_02
VSS_HV_ADR_13
VSS_HV_ADV
L8
P1
L9
C15
J16
T9
L10
L11
N4
U15
T7
U10
Table 4. 257 MAPBGA Balls not populated on package
E5
E13
J13
N6
E6
F5
K5
N7
E7
F13
K13
N8
E8
G5
L5
E9
E10
H5
E11
H13
M13
N12
E12
J5
G13
L13
N10
M5
N5
N9
N11
N13
Table 5. 473 MAPBGA supply pins
Ball
Number
Ball
Pad Type
Ball Name
Ball Name
Pad Type
Number
VDD
A3
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV
VDD_HV
VDD_HV
F15
F16
F17
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV
VDD_LV
VDD_LV
A14
B22
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
24
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. 473 MAPBGA supply pins (continued)
Ball
Number
Ball
Number
Ball Name
Pad Type
Ball Name
Pad Type
C1
D8
VDD_HV_IO
VDD_HV_IO
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV_A
VDD_HV_A
VDD_HV_A
VDD_HV_A
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_HV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
F18
G6
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
G2
VDD_HV_IO
G18
H6
L20
M2
VDD_HV_IO
VDD_HV_IO
H18
J6
M4
VDD_HV_IO
T4
VDD_HV_IO
J18
K6
V2
VDD_HV_IO
Y13
Y20
AB2
AB22
AC12
AC15
AC7
AA9
H22
L23
P23
U22
R20
H21
L21
D13
V1
VDD_HV_IO
K18
L6
VDD_HV_IO
VDD_HV_IO
L18
M6
VDD_HV_IO
VDD_HV_ADR_0
VDD_HV_ADR_1
VDD_HV_ADR_23
VDD_HV_ADV
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM_VREF
VDD_HV_DRAM_VTT
VDD_HV_DRAM_VTT
VDD_HV_FLA
VDD_HV_OSC
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PMU
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
M18
N6
N18
P6
P18
R6
R18
T6
T18
U6
U18
V6
V7
D16
D20
AC17
F6
V8
V9
V10
V11
V12
V13
V14
V15
V16
F7
F8
F9
F10
F11
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Package pinouts and signal descriptions
Table 5. 473 MAPBGA supply pins (continued)
Ball
Number
Ball
Number
Ball Name
Pad Type
Ball Name
Pad Type
F12
F13
F14
VDD_LV_COR
VDD_LV_COR
VDD_LV_COR
VDD_LV
VDD_LV
VDD_LV
V17
V18
Y4
VDD_LV_COR
VDD_LV_COR
VDD_LV_PLL
VDD_LV
VDD_LV
VDD_LV
VSS
A2
A22
A23
B1
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_IO
VSS_HV_ADR_0
VSS_HV_ADR_1
VSS_HV_ADR_23
VSS_HV_ADV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV_A
VSS_HV_A
VSS_HV_A
VSS_HV_A
L7
L8
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
L9
L10
L11
L12
L13
L14
L15
L16
L17
M7
B2
B14
B23
C3
D9
D11
H2
K20
L4
M8
N2
M9
A1
M10
M11
M12
M13
M14
M15
M16
M17
N7
R4
W2
Y12
AA3
AA21
AB1
AB23
AC1
AC2
AC22
AC23
AC13
AC16
AC8
AA10
N8
N9
N10
N11
N12
N13
N14
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
26
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. 473 MAPBGA supply pins (continued)
Ball
Number
Ball
Number
Ball Name
Pad Type
Ball Name
Pad Type
H23
L22
P22
V22
D12
Y1
VSS_HV_DRAM
VSS_HV_DRAM
VSS_HV_DRAM
VSS_HV_DRAM
VSS_HV_FLA
VSS_HV_OSC
VSS_HV_PDI
VSS_HV_PDI
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
N15
N16
N17
P7
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
P8
P9
C21
D17
G7
P10
P11
P12
P13
P14
P15
P16
P17
R7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
H7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
J7
T8
T9
T10
T11
T12
T13
T14
T15
J8
J9
J10
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Package pinouts and signal descriptions
Table 5. 473 MAPBGA supply pins (continued)
Ball
Number
Ball
Number
Ball Name
Pad Type
Ball Name
Pad Type
J11
J12
J13
J14
J15
J16
J17
K7
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
T16
T17
U7
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_COR
VSS_LV_PLL
VSS_HV_PMU
RESERVED
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_HV
VSS_HV
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
W4
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
AC19
D5
AB20
RESERVED
Table 6. 473 MAPBGA Balls not populated on package
E5
E13
F19
K19
P19
V19
W12
E6
E14
G5
E7
E15
G19
L19
R19
W6
E8
E16
H5
E9
E17
H19
M19
T19
W8
E10
E18
J5
E11
E19
J19
E12
F5
K5
L5
M5
N5
N19
U19
W10
W18
P5
R5
T5
U5
V5
W5
W13
W7
W15
W9
W17
W11
W19
W14
W16
2.2.3
System pins
Table 7 shows the system pins for the PXS30 in the 257 MAPBGA package. Table 8 shows the system
pins for the PXS30 in the 473 MAPBGA package.
PXS30 Microcontroller Data Sheet, Rev. 1
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package pinouts and signal descriptions
Table 7. 257 MAPBGA system pins
Ball
Number
Weak pull
during reset default condition
Safe Mode
Ball Name
FCCU_F[1]
Pad Type
Power Domain
C4
C10
E1
disabled
pull down
—
not available
not available
not available
not available
not available
not available
not available
not available
not available
not available
—
GP Slow/Medium
GP Slow
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_REG
JCOMP
Nexus MDO[0]1
GP Slow/Fast
E4
NMI
pull up
pull up
pull up
—
GP Slow
L15
M16
N1
TCK
GP Slow
TMS
GP Slow
XTALIN
Analog Feedthrough
Reset
P2
RESET
pull down
—
R1
XTALOUT
FCCU_F[0]
VREG_CTRL
VREG_INT_ENABLE
RESET_SUP
Analog Feedthrough
GP Slow/Medium
Analog Feedthrough
Analog Feedthrough
Analog Feedthrough
R2
disabled
—
R13
U12
U13
—
—
VDD_HV_IO
VDD_HV_IO
pull down
—
NOTES:
1
Do not connect pin directly to a power supply or ground.
Table 8. 473 MAPBGA system pins
Ball
Number
Weak pull
during reset default condition
Safe Mode
Ball Name
FCCU_F[1]
Pad Type
Power Domain
C4
D10
E1
disabled
pull down
—
not available
not available
not available
not available
—
GP Slow/Medium
GP Slow
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_REG
JCOMP
Nexus MDO[0]1
GP Slow/Fast
E4
NMI
pull up
—
GP Slow
R23
T23
W1
Y2
dramc CLKB
dramc CLK
XTALIN
DRAM CLK
disabled
—
—
DRAM CLK
not available
not available
not available
not available
not available
not available
—
Analog Feedthrough
Reset
RESET
pull down
pull up
—
Y19
TCK
GP Slow
AA1 XTALOUT
Analog Feedthrough
GP Slow/Medium
GP Slow
AA2 FCCU_F[0]
AB19 TMS
disabled
pull up
—
AC18 VREG_CTRL
AC20 RESET_SUP
AC21 VREG_INT_ENABLE
Analog Feedthrough
Analog Feedthrough
Analog Feedthrough
pull down
—
—
VDD_HV_IO
VDD_HV_IO
—
NOTES:
1
Do not connect pin directly to a power supply or ground.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
2.2.4
Multiplexed pins
Table 9 shows the pin multiplexing for the PXS30 in the 257 MAPBGA package. Table 10 shows the pin multiplexing for the PXS30
in the 473 MAPBGA package.
Table 9. 257 MAPBGA pin multiplexing
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
A4
A5
GPIO nexus
A0: siul_GPIO[114]
A1: _
A2: npc_wrapper_MDO[5]
A3: _
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
MDO[5]1
GPIO nexus
MDO[7]1
A0: siul_GPIO[112]
A1: _
A2: npc_wrapper_MDO[7]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
GP Slow/
Fast
A6
GPIO nexus
MDO[9]1
A0: siul_GPIO[110]
A1: _
A2: npc_wrapper_MDO[9]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
A7
GPIO flexray
A0: siul_GPIO[51]
A1: flexray_CB_TX
A2: _
I: _
I: _
I: _
GP Slow/
Symmetric
CB_TX
A3: _
A8
GPIO flexray
A0: siul_GPIO[47]
I: ctu0_EXT_IN
I: flexpwm0_EXT_SYNC
I: _
GP Slow/
Symmetric
CA_TR_EN A1: flexray_CA_TR_EN
A2: _
A3: _
A10
A11
GPIO fec
RXD[2]
A0: siul_GPIO[213]
A1: _
A2: _
I: fec_RXD[2]
I: _
I: siul_EIRQ[21]
GP Slow/
Medium
A3: dspi2_SOUT
GPIO fec
RX_CLK
A0: siul_GPIO[209]
A1: flexray_DBG2
A2: etimer2_ETC[2]
A3: dspi0_CS6
I: fec_RX_CLK
I: _
I: siul_EIRQ[25]
GP Slow/
Medium
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
A12
A13
A14
A15
B3
GPIO fec
A0: siul_GPIO[211]
A1: i2c1_clock
A2: _
I: fec_RXD[0]
I: _
I: siul_EIRQ[27]
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
RXD[0]
A3: _
GPIO fec
MDIO
A0: siul_GPIO[198]
A1: fec_MDIO
A2: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
I: siul_EIRQ[28]
A3: dspi2_CS0
GPIO fec
TX_EN
A0: siul_GPIO[200]
A1: fec_TX_EN
A2: _
I: _
I: _
I: _
GP Slow/
Medium
A3: lin0_TXD
GPIO fec
A0: siul_GPIO[204]
A1: fec_TXD[3]
A2: _
I: flexpwm1_FAULT[2]
I: _
I: siul_EIRQ[29]
GP Slow/
Medium
TXD[3]
A3: dspi2_CS2
GPIO mc_cgl
A0: siul_GPIO[22]
A1: mc_cgl_clk_out
A2: etimer2_ETC[5]
A3: _
I: _
I: _
GP Slow/
Fast
clk_out
I: siul_EIRQ[18]
B4
GPIO can1
A0: siul_GPIO[14]
A1: can1_TXD
A2: _
I: _
I: _
GP Slow/
Medium
TXD
I: siul_EIRQ[13]
A3: _
B5
GPIO nexus
A0: siul_GPIO[219]
A1: _
A2: npc_wrapper_MDO[14]
A3: can3_TXD
I: _
I: _
I: _
GP Slow/
Fast
MDO[14]1
B6
GPIO dspi2
A0: siul_GPIO[9]
A1: dspi2_CS1
A2: _
I: flexpwm0_FAULT[0]
I: lin3_RXD
I: can2_RXD
GP Slow/
Medium
CS1
A3: _
B7
GPIO flexray
A0: siul_GPIO[52]
I: _
I: _
I: _
GP Slow/
Symmetric
CB_TR_EN A1: flexray_CB_TR_EN
A2: _
A3: _
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
B8
B10
B11
B12
B13
B14
B15
C2
GPIO flexray
A0: siul_GPIO[48]
A1: flexray_CA_TX
A2: _
A3: _
I: ctu1_EXT_IN
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Symmetric
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
CA_TX
GPIO fec
RXD[3]
A0: siul_GPIO[214]
A1: i2c1_data
A2: _
I: fec_RXD[3]
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
A3: _
GPIO fec
RX_ER
A0: siul_GPIO[215]
A1: _
A2: _
I: fec_RX_ER
I: _
I: _
GP Slow/
Medium
A3: dspi0_CS1
GPIO fec
RXD[1]
A0: siul_GPIO[212]
A1: dspi1_CS1
A2: etimer2_ETC[5]
A3: _
I: fec_RXD[1]
I: _
I: _
GP Slow/
Medium
GPIO fec
TX_ER
A0: siul_GPIO[205]
A1: fec_TX_ER
A2: dspi2_CS3
A3: _
I: flexpwm1_FAULT[3]
I: lin0_RXD
I: _
GP Slow/
Medium
GPIO fec
TX_CLK
A0: siul_GPIO[207]
A1: flexray_DBG0
A2: etimer2_ETC[4]
A3: dspi0_CS4
I: fec_TX_CLK
I: _
I: _
GP Slow/
Medium
GPIO can0
A0: siul_GPIO[16]
A1: can0_TXD
A2: _
I: _
I: _
GP Slow/
Medium
TXD
I: siul_EIRQ[15]
A3: sscm_DEBUG[0]
GPIO nexus
A0: siul_GPIO[220]
A1: _
A2: npc_wrapper_MDO[15]
A3: _
I: can3_RXD
I: can2_RXD
I: _
GP Slow/
Fast
MDO[15]1
C5
GPIO flexray
A0: siul_GPIO[50]
A1: _
A2: ctu1_EXT_TGR
A3: _
I: flexray_CB_RX
I: _
I: _
GP Slow/
Medium
CB_RX
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
C6
C7
GPIO etimer0
A0: siul_GPIO[0]
A1: etimer0_ETC[0]
A2: _
A3: _
I: dspi2_SIN
I: _
I: siul_EIRQ[0]
—
disabled
disabled
disabled
pull down
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
ETC[0]
GPIO etimer0
A0: siul_GPIO[1]
A1: etimer0_ETC[1]
A2: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
ETC[1]
I: siul_EIRQ[1]
A3: _
C8
GPIO etimer0
A0: siul_GPIO[2]
A1: etimer0_ETC[2]
A2: _
I: _
I: _
GP Slow/
Medium
ETC[2]
I: siul_EIRQ[2]
A3: _
C9
GPIO etimer0
A0: siul_GPIO[3]
A1: etimer0_ETC[3]
A2: _
I: _
GP Slow/
Medium
ETC[3]
I: mc_rgm_ABS[2]
I: siul_EIRQ[3]
A3: _
C11
C12
C13
C14
C16
GPIO fec
A0: siul_GPIO[208]
A1: flexray_DBG1
A2: etimer2_ETC[3]
A3: dspi0_CS5
I: fec_CRS
I: _
I: _
GP Slow/
Medium
CRS
GPIO fec
A0: siul_GPIO[201]
A1: fec_TXD[0]
A2: etimer2_ETC[1]
A3: _
I: _
I: _
I: _
GP Slow/
Medium
TXD[0]
GPIO fec
A0: siul_GPIO[206]
A1: fec_COL
A2: _
I: _
I: _
I: _
GP Slow/
Medium
COL
A3: lin1_TXD
GPIO can0
A0: siul_GPIO[17]
A1: _
A2: _
I: can0_RXD
I: can1_RXD
I: siul_EIRQ[16]
GP Slow/
Medium
RXD
A3: sscm_DEBUG[1]
GPIO pdi
A0: siul_GPIO[136]
A1: flexpwm2_A[0]
A2: _
I: pdi_DATA[5]
I: _
I: _
PDI
Medium
DATA[5]
A3: etimer1_ETC[0]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
C17
D1
GPIO pdi
A0: siul_GPIO[128]
A1: flexpwm2_B[1]
A2: _
I: pdi_CLOCK
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
pull down
disabled
disabled
PDI
Medium
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
CLOCK
A3: etimer1_ETC[3]
GPIO nexus
MDO[2]1
A0: siul_GPIO[85]
A1: _
A2: npc_wrapper_MDO[2]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
D2
GPIO nexus
MDO[3]1
A0: siul_GPIO[84]
A1: _
A2: npc_wrapper_MDO[3]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
D3
GPIO can1
A0: siul_GPIO[15]
I: can1_RXD
I: can0_RXD
I: siul_EIRQ[14]
GP Slow/
Medium
RXD
A1: _
A2: _
A3: _
D4
GPIO dspi0
A0: siul_GPIO[38]
A1: dspi0_SOUT
A2: _
I: _
I: _
GP Slow/
Medium
SOUT
I: siul_EIRQ[24]
A3: sscm_DEBUG[6]
D6
GPIO etimer0
A0: siul_GPIO[44]
A1: etimer0_ETC[5]
A2: _
I: _
I: _
I: _
GP Slow/
Medium
ETC[5]
A3: _
D7
GPIO etimer0
A0: siul_GPIO[43]
A1: etimer0_ETC[4]
A2: _
I: _
GP Slow/
Medium
ETC[4]
I: mc_rgm_ABS[0]
I: _
A3: _
D10
D11
GPIO fec
A0: siul_GPIO[203]
A1: fec_TXD[2]
A2: _
I: flexpwm1_FAULT[1]
I: _
I: _
GP Slow/
Medium
TXD[2]
A3: _
GPIO fec
A0: siul_GPIO[202]
A1: fec_TXD[1]
A2: _
I: flexpwm1_FAULT[0]
I: _
I: _
GP Slow/
Medium
TXD[1]
A3: dspi2_SCK
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
D12
D13
D16
D17
E2
GPIO fec
A0: siul_GPIO[210]
A1: flexray_DBG3
A2: etimer2_ETC[0]
A3: dspi0_CS7
I: fec_RX_DV
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
RX_DV
GPIO fec
MDC
A0: siul_GPIO[199]
A1: fec_MDC
A2: _
I: _
I: lin1_RXD
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
A3: _
GPIO pdi
DATA[0]
A0: siul_GPIO[131]
A1: _
A2: lin3_TXD
A3: _
I: pdi_DATA[0]
I: _
I: flexpwm2_FAULT[2]
PDI
Medium
GPIO pdi
A0: siul_GPIO[132]
A1: flexpwm2_B[3]
A2: _
I: pdi_DATA[1]
I: _
I: _
PDI
Medium
DATA[1]
A3: _
GPIO nexus
A0: siul_GPIO[86]
A1: _
A2: npc_wrapper_MDO[1]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
MDO[1]1
E3
GPIO flexray
A0: siul_GPIO[49]
A1: _
A2: ctu0_EXT_TGR
A3: _
I: flexray_CA_RX
I: _
I: _
GP Slow/
Medium
CA_RX
E14
E15
E16
GPIO pdi
A0: siul_GPIO[129]
A1: _
A2: lin2_TXD
A3: _
I: pdi_LINE_V
I: _
I: flexpwm2_FAULT[0]
PDI
Medium
LINE_V
GPIO pdi
A0: siul_GPIO[133]
A1: flexpwm2_A[1]
A2: _
I: pdi_DATA[2]
I: _
I: _
PDI
Medium
DATA[2]
A3: etimer1_ETC[2]
GPIO pdi
A0: siul_GPIO[134]
A1: flexpwm2_X[1]
A2: _
I: pdi_DATA[3]
I: _
I: _
PDI
Medium
DATA[3]
A3: _
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
E17
F1
GPIO pdi
A0: siul_GPIO[135]
A1: flexpwm2_A[2]
A2: _
I: pdi_DATA[4]
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
PDI
Medium
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
DATA[4]
A3: etimer1_ETC[4]
GPIO nexus
MDO[6]1
A0: siul_GPIO[113]
A1: _
A2: npc_wrapper_MDO[6]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
F2
GPIO nexus
MDO[11]1
A0: siul_GPIO[108]
A1: _
A2: npc_wrapper_MDO[11]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
F3
GPIO dspi1
A0: siul_GPIO[7]
A1: dspi1_SOUT
A2: _
I: _
I: _
GP Slow/
Medium
SOUT
I: siul_EIRQ[7]
A3: _
F4
GPIO dspi1
A0: siul_GPIO[8]
A1: _
A2: _
I: dspi1_SIN
I: _
I: siul_EIRQ[8]
GP Slow/
Medium
SIN
A3: _
F14
F15
F16
F17
GPIO mc_cgl
A0: siul_GPIO[233]
A1: mc_cgl_clk_out
A2: etimer2_ETC[5]
A3: _
I: _
I: _
I: _
PDI Fast
clk_out
GPIO pdi
A0: siul_GPIO[137]
A1: flexpwm2_B[0]
A2: _
I: pdi_DATA[6]
I: _
I: _
PDI
Medium
DATA[6]
A3: etimer1_ETC[1]
GPIO pdi
A0: siul_GPIO[138]
A1: flexpwm2_B[2]
A2: _
I: pdi_DATA[7]
I: _
I: _
PDI
Medium
DATA[7]
A3: etimer1_ETC[5]
GPIO pdi
A0: siul_GPIO[139]
A1: flexpwm2_A[3]
A2: _
I: pdi_DATA[8]
I: _
I: _
PDI
Medium
DATA[8]
A3: _
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
G1
G3
GPIO nexus
A0: siul_GPIO[115]
A1: _
A2: npc_wrapper_MDO[4]
A3: _
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
MDO[4]1
GPIO dspi0
A0: siul_GPIO[37]
A1: dspi0_SCK
A2: _
I: flexpwm0_FAULT[3]
I: _
I: siul_EIRQ[23]
—
—
—
—
—
—
—
—
GP Slow/
Medium
SCK
A3: sscm_DEBUG[5]
G4
GPIO dspi1
A0: siul_GPIO[6]
A1: dspi1_SCK
A2: _
I: _
I: _
GP Slow/
Medium
SCK
I: siul_EIRQ[6]
A3: _
G14
G15
G16
G17
H1
GPIO pdi
A0: siul_GPIO[140]
A1: flexpwm2_X[2]
A2: _
I: pdi_DATA[9]
I: _
I: _
PDI
Medium
DATA[9]
A3: _
GPIO pdi
DATA[10]
A0: siul_GPIO[141]
A1: flexpwm2_X[3]
A2: _
I: pdi_DATA[10]
I: _
I: _
PDI
Medium
A3: _
GPIO pdi
DATA[11]
A0: siul_GPIO[142]
A1: flexpwm2_X[0]
A2: _
I: pdi_DATA[11]
I: _
I: _
PDI
Medium
A3: _
GPIO pdi
A0: siul_GPIO[130]
I: pdi_FRAME_V
I: lin2_RXD
I: flexpwm2_FAULT[1]
PDI
Medium
FRAME_V A1: _
A2: _
A3: _
GPIO nexus
A0: siul_GPIO[109]
A1: _
A2: npc_wrapper_MDO[10]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
MDO[10]1
H3
GPIO dspi0
A0: siul_GPIO[36]
A1: dspi0_CS0
A2: _
I: _
I: _
GP Slow/
Medium
CS0
I: siul_EIRQ[22]
A3: sscm_DEBUG[4]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
H4
H14
H15
H17
J1
GPIO dspi1
CS0
A0: siul_GPIO[5]
A1: dspi1_CS0
A2: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
I: siul_EIRQ[5]
A3: dspi0_CS7
GPIO pdi
DATA[12]
A0: siul_GPIO[143]
I: pdi_DATA[12]
I: lin3_RXD
I: flexpwm2_FAULT[3]
—
—
—
—
—
—
—
—
PDI
Medium
A1: _
A2: _
A3: _
GPIO pdi
A0: siul_GPIO[144]
A1: pdi_SENS_SEL[2]
A2: ctu1_EXT_TGR
A3: _
I: pdi_DATA[13]
I: _
I: _
PDI
Medium
DATA[13]
GPIO flexpwm0
A0: siul_GPIO[194]
A1: flexpwm0_X[0]
A2: ebi_D28
I: _
I: _
I: _
DRAM
ACC
X[0]
A3: _
GPIO nexus
A0: siul_GPIO[87]
A1: _
A2: npc_wrapper_MCKO
A3: _
I: _
I: _
I: _
GP Slow/
Fast
MCKO
J2
GPIO nexus
A0: siul_GPIO[111]
A1: _
A2: npc_wrapper_MDO[8]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
MDO[8]1
J3
GPIO dspi2
A0: siul_GPIO[10]
A1: dspi2_CS0
A2: _
I: _
I: _
GP Slow/
Medium
CS0
I: siul_EIRQ[9]
A3: can3_TXD
J4
GPIO dspi2
A0: siul_GPIO[42]
A1: dspi2_CS2
A2: lin3_TXD
I: flexpwm0_FAULT[1]
I: _
I: _
GP Slow/
Medium
CS2
A3: can2_TXD
J14
GPIO pdi
A0: siul_GPIO[145]
A1: pdi_SENS_SEL[1]
A2: i2c2_clock
A3: _
I: pdi_DATA[14]
I: _
I: _
PDI
Medium
DATA[14]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
J15
J17
K1
GPIO pdi
A0: siul_GPIO[146]
A1: pdi_SENS_SEL[0]
A2: i2c2_data
I: pdi_DATA[15]
I: ctu1_EXT_IN
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
PDI
Medium
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
DATA[15]
A3: _
GPIO flexpwm0
A0: siul_GPIO[195]
A1: flexpwm0_X[1]
A2: ebi_D29
I: _
I: _
I: _
—
—
—
—
—
—
—
—
DRAM
ACC
X[1]
A3: _
GPIO nexus
A0: siul_GPIO[89]
I: _
I: _
GP Slow/
Fast
MSEO_B[0]1 A1: _
A2: npc_wrapper_MSEO_B[0] I: _
A3: _
K2
GPIO nexus
A0: siul_GPIO[88]
I: _
I: _
GP Slow/
Fast
MSEO_B[1]1 A1: _
A2: npc_wrapper_MSEO_B[1] I: _
A3: _
K3
GPIO nexus
A0: siul_GPIO[216]
A1: _
A2: nexus_RDY_B
A3: _
I: _
I: _
I: _
GP Slow/
Fast
RDY_B
K4
GPIO dspi0
A0: siul_GPIO[39]
A1: _
A2: _
I: dspi0_SIN
I: _
I: _
GP Slow/
Medium
SIN
A3: sscm_DEBUG[7]
K14
K15
K16
GPIO flexpwm0
A0: siul_GPIO[196]
A1: flexpwm0_X[2]
A2: ebi_D30
I: _
I: _
I: _
DRAM
ACC
X[2]
A3: _
GPIO flexpwm0
A0: siul_GPIO[197]
A1: flexpwm0_X[3]
A2: ebi_D31
I: _
I: _
I: _
DRAM
ACC
X[3]
A3: _
GPIO flexpwm0
A0: siul_GPIO[149]
A1: _
A2: ebi_RD_WR
A3: flexpwm0_A[1]
I: _
I: _
I: _
DRAM
ACC
A[1]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
K17
L1
GPIO flexpwm0
A0: siul_GPIO[148]
A1: _
A2: ebi_CLKOUT
A3: flexpwm0_B[0]
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
DRAM
ACC
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
B[0]
GPIO nexus
A0: siul_GPIO[90]
A1: _
A2: npc_wrapper_EVTO_B
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
EVTO_B
L2
GPIO nexus
A0: siul_GPIO[91]
A1: _
A2: leo_sor_proxy_EVTI_B
A3: _
I: _
I: _
I: _
GP Slow/
Medium
EVTI_B
L3
GPIO dspi2
A0: siul_GPIO[11]
A1: dspi2_SCK
A2: _
I: can3_RXD
I: _
I: siul_EIRQ[10]
GP Slow/
Medium
SCK
A3: _
L4
GPIO nexus
A0: siul_GPIO[218]
A1: _
A2: npc_wrapper_MDO[13]
A3: _
I: can2_RXD
I: can3_RXD
I: _
GP Slow/
Fast
MDO[13]1
L16
L17
M3
M4
GPIO flexpwm0
A0: siul_GPIO[150]
A1: dramc_CS0
A2: ebi_TS
I: _
I: _
I: _
DRAM
ACC
B[1]
A3: flexpwm0_B[1]
GPIO TDO
A0: siul_GPIO[20]
A1: jtagc_TDO
A2: _
I: _
I: _
I: _
GP Slow/
Fast
A3: _
GPIO dspi1
A0: siul_GPIO[56]
A1: dspi1_CS2
A2: _
I: flexpwm0_FAULT[3]
I: lin2_RXD
I: _
GP Slow/
Medium
CS2
A3: dspi0_CS5
GPIO nexus
A0: siul_GPIO[217]
A1: _
A2: npc_wrapper_MDO[12]
A3: can2_TXD
I: _
I: _
I: _
GP Slow/
Fast
MDO[12]1
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
M14
M15
M17
N3
GPIO flexpwm0
A0: siul_GPIO[152]
A1: dramc_CAS
A2: ebi_WE_BE_1
A3: flexpwm0_B[2]
I: _
I: _
I: _
—
disabled
DRAM
ACC
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
B[2]
GPIO TDI
A0: siul_GPIO[21]
I: jtagc_TDI
I: _
I: _
—
—
—
—
—
—
—
—
pull up
GP Slow/
Medium
A1: _
A2: _
A3: _
GPIO flexpwm1
A0: siul_GPIO[157]
A1: dramc_ODT
A2: ebi_CS1
I: _
I: _
I: _
disabled
disabled
disabled
disabled
disabled
disabled
disabled
DRAM
ACC
A[1]
A3: flexpwm1_A[1]
GPIO dspi0
A0: siul_GPIO[53]
A1: dspi0_CS3
A2: i2c2_clock
A3: _
I: flexpwm0_FAULT[2]
I: _
I: _
GP Slow/
Medium
CS3
N14
N15
N16
N17
P3
GPIO flexpwm0
A0: siul_GPIO[154]
A1: dramc_BA[0]
A2: ebi_WE_BE_3
A3: flexpwm0_B[3]
I: _
I: _
I: _
DRAM
ACC
B[3]
GPIO flexpwm0
A0: siul_GPIO[151]
A1: dramc_RAS
A2: ebi_WE_BE_0
A3: flexpwm0_A[2]
I: _
I: _
I: _
DRAM
ACC
A[2]
GPIO flexpwm1
A0: siul_GPIO[155]
A1: dramc_BA[1]
A2: ebi_BDIP
I: _
I: _
I: _
DRAM
ACC
A[0]
A3: flexpwm1_A[0]
GPIO flexpwm1
A0: siul_GPIO[156]
A1: dramc_BA[2]
A2: ebi_CS0
I: _
I: _
I: _
DRAM
ACC
B[0]
A3: flexpwm1_B[0]
GPIO dspi0
A0: siul_GPIO[54]
A1: dspi0_CS2
A2: i2c2_data
A3: _
I: flexpwm0_FAULT[1]
I: _
I: _
GP Slow/
Medium
CS2
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
P5
P6
GPIO etimer1
A0: siul_GPIO[45]
A1: etimer1_ETC[1]
A2: _
A3: _
I: ctu0_EXT_IN
I: flexpwm0_EXT_SYNC
I: ctu1_EXT_IN
—
disabled
GP Slow/
Medium
VDD_HV_IO
ETC[1]
GPIO etimer1
ETC[2]
A0: siul_GPIO[46]
A1: etimer1_ETC[2]
A2: ctu0_EXT_TGR
A3: _
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
P7
P8
ANA adc0
—
siul_GPI[23]
lin0_RXD
AN: adc0_AN[0]
Analog
VDD_HV_ADR02
VDD_HV_IO
AN[0]
GPIO etimer1
A0: siul_GPIO[92]
A1: etimer1_ETC[3]
A2: _
I: ctu1_EXT_IN
I: mc_rgm_FAB
I: siul_EIRQ[30]
—
pull down
GP Slow/
Medium
ETC[3]
A3: _
P11
P12
ANA adc0_adc1
—
siul_GPI[28]
AN: adc0_adc1_AN[14]
Analog
Shared
VDD_HV_ADR02
VDD_HV_IO
AN[14]
GPIO etimer1
A0: siul_GPIO[93]
A1: etimer1_ETC[4]
A2: ctu1_EXT_TGR
A3: _
I: _
I: _
—
disabled
disabled
disabled
disabled
GP Slow/
Medium
ETC[4]
I: siul_EIRQ[31]
P13
P15
P16
GPIO etimer1
A0: siul_GPIO[78]
A1: etimer1_ETC[5]
A2: _
I: _
I: _
—
—
—
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
ETC[5]
I: siul_EIRQ[26]
A3: _
GPIO flexpwm0
A0: siul_GPIO[153]
A1: dramc_WEB
A2: ebi_WE_BE_2
A3: flexpwm0_A[3]
I: _
I: _
I: _
DRAM
ACC
A[3]
GPIO flexpwm0
A0: siul_GPIO[147]
A1: dramc_CKE
A2: ebi_OE
I: _
I: _
I: _
DRAM
ACC
A[0]
A3: flexpwm0_A[0]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
P17
R4
GPIO flexpwm1
A0: siul_GPIO[163]
A1: dramc_ADD[5]
A2: ebi_ADD13
I: _
I: _
I: _
—
disabled
DRAM
ACC
VDD_HV_IO
B[1]
A3: flexpwm1_B[1]
GPIO dspi1
A0: siul_GPIO[55]
A1: dspi1_CS3
A2: lin2_TXD
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
CS3
A3: dspi0_CS4
R5
R6
ANA adc2
—
—
—
—
—
—
siul_GPI[221]
siul_GPI[224]
siul_GPI[228]
siul_GPI[33]
siul_GPI[27]
AN: adc2_AN[0]
—
—
—
—
—
—
Analog
Analog
VDD_HV_ADR02
VDD_HV_ADR02
VDD_HV_ADR13
VDD_HV_ADR02
VDD_HV_ADR02
VDD_HV_ADR13
AN[0]
ANA adc2
AN: adc2_AN[3]
AN[3]
R8
ANA adc2_adc3
AN: adc2_adc3_AN[14]
AN: adc0_AN[2]
Analog
Shared
AN[14]
R10
R11
R12
ANA adc0
Analog
AN[2]
ANA adc0_adc1
AN: adc0_adc1_AN[13]
AN: adc1_AN[1]
Analog
Shared
AN[13]
ANA adc1
siul_GPI[30]
Analog
AN[1]
etimer0_ETC[4]
siul_EIRQ[19]
R14
R16
GPIO lin0
A0: siul_GPIO[18]
A1: lin0_TXD
A2: i2c0_clock
I: _
I: _
—
—
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
TXD
I: siul_EIRQ[17]
A3: sscm_DEBUG[2]
GPIO flexpwm1
A0: siul_GPIO[164]
A1: dramc_ADD[6]
A2: ebi_ADD14
I: _
I: _
I: _
DRAM
ACC
A[2]
A3: flexpwm1_A[2]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
R17
T3
GPIO flexpwm1
A0: siul_GPIO[165]
A1: dramc_ADD[7]
A2: ebi_ADD15
I: _
I: _
I: _
—
disabled
DRAM
ACC
VDD_HV_IO
B[2]
A3: flexpwm1_B[2]
GPIO dspi2
A0: siul_GPIO[12]
A1: dspi2_SOUT
A2: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
SOUT
I: siul_EIRQ[11]
A3: _
T4
T5
ANA adc3
—
—
—
—
—
—
—
—
siul_GPI[229]
AN: adc3_AN[0]
—
—
—
—
—
—
—
—
Analog
Analog
Analog
VDD_HV_ADR13
VDD_HV_ADR13
VDD_HV_ADR02
VDD_HV_ADR02
VDD_HV_ADR02
VDD_HV_ADR02
VDD_HV_ADR13
VDD_HV_ADR13
AN[0]
ANA adc3
siul_GPI[232]
siul_GPI[223]
siul_GPI[227]
AN: adc3_AN[3]
AN[3]
T6
ANA adc2
AN: adc2_AN[2]
AN[2]
T8
ANA adc2_adc3
AN: adc2_adc3_AN[13]
AN: adc0_AN[1]
Analog
Shared
AN[13]
T10
T11
T12
T13
ANA adc0
siul_GPI[24]
etimer0_ETC[5]
Analog
AN[1]
ANA adc0_adc1
siul_GPI[26]
siul_GPI[29]
AN: adc0_adc1_AN[12]
AN: adc1_AN[0]
Analog
Shared
AN[12]
ANA adc1
Analog
Analog
AN[0]
lin1_RXD
ANA adc1
siul_GPI[31]
AN: adc1_AN[2]
AN[2]
siul_EIRQ[20]
Table 9. 257 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
T14
T15
U3
GPIO lin0
RXD
A0: siul_GPIO[19]
A1: _
A2: i2c0_data
A3: sscm_DEBUG[3]
I: lin0_RXD
I: _
I: _
—
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
GPIO etimer1
A0: siul_GPIO[4]
A1: etimer1_ETC[0]
A2: _
I: _
I: _
—
—
GP Slow/
Medium
ETC[0]
I: siul_EIRQ[4]
A3: _
GPIO dspi2
A0: siul_GPIO[13]
I: dspi2_SIN
I: flexpwm0_FAULT[0]
I: siul_EIRQ[12]
GP Slow/
Medium
SIN
A1: _
A2: _
A3: _
U4
U5
U6
U7
U8
U11
ANA adc3
—
—
—
—
—
—
siul_GPI[230]
siul_GPI[231]
siul_GPI[222]
siul_GPI[225]
siul_GPI[226]
siul_GPI[25]
AN: adc3_AN[1]
—
—
—
—
—
—
Analog
Analog
Analog
VDD_HV_ADR13
VDD_HV_ADR13
VDD_HV_ADR02
VDD_HV_ADR13
VDD_HV_ADR13
VDD_HV_ADR02
AN[1]
ANA adc3
AN: adc3_AN[2]
AN[2]
ANA adc2
AN: adc2_AN[1]
AN[1]
ANA adc2_adc3
AN: adc2_adc3_AN[11]
AN: adc2_adc3_AN[12]
AN: adc0_adc1_AN[11]
Analog
Shared
AN[11]
ANA adc2_adc3
Analog
Shared
AN[12]
ANA adc0_adc1
Analog
Shared
AN[11]
END OF 257 MAPBGA PIN MULTIPLEXING TABLE
NOTES:
1
Do not connect pin directly to a power supply or ground.
Table 10. 473 MAPBGA pin multiplexing
Additional Inputs Analog Inputs
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Pad Type Power Domain
A4
A5
A6
A7
A8
A9
GPIO nexus
A0: siul_GPIO[114]
A1: _
A2: npc_wrapper_MDO[5]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
MDO[5]1
GPIO nexus
MDO[7]1
A0: siul_GPIO[112]
A1: _
A2: npc_wrapper_MDO[7]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
GPIO nexus
MDO[9]1
A0: siul_GPIO[110]
A1: _
A2: npc_wrapper_MDO[9]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
GPIO flexray
A0: siul_GPIO[51]
A1: flexray_CB_TX
A2: _
I: _
I: _
I: _
GP Slow/
Symmetric
CB_TX
A3: _
GPIO flexray
A0: siul_GPIO[47]
I: ctu0_EXT_IN
I: flexpwm0_EXT_SYNC
I: _
GP Slow/
Symmetric
CA_TR_EN A1: flexray_CA_TR_EN
A2: _
A3: _
GPIO fec
RX_DV
A0: siul_GPIO[210]
A1: flexray_DBG3
A2: etimer2_ETC[0]
A3: dspi0_CS7
I: fec_RX_DV
I: _
I: _
GP Slow/
Medium
A10 GPIO fec
MDIO
A0: siul_GPIO[198]
A1: fec_MDIO
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[28]
A3: dspi2_CS0
A11
GPIO fec
TX_CLK
A0: siul_GPIO[207]
A1: flexray_DBG0
A2: etimer2_ETC[4]
A3: dspi0_CS4
I: fec_TX_CLK
I: _
I: _
GP Slow/
Medium
A12 GPIO fec
TX_EN
A0: siul_GPIO[200]
A1: fec_TX_EN
A2: _
I: _
I: _
I: _
GP Slow/
Medium
A3: lin0_TXD
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
A13 GPIO fec
TXD[3]
A0: siul_GPIO[204]
A1: fec_TXD[3]
A2: _
I: flexpwm1_FAULT[2]
I: _
I: siul_EIRQ[29]
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
A3: dspi2_CS2
A15 GPIO pdi
DATA[3]
A0: siul_GPIO[134]
A1: flexpwm2_X[1]
A2: _
I: pdi_DATA[3]
I: _
I: _
—
—
—
—
—
—
—
—
PDI
Medium
A3: _
A16 GPIO pdi
DATA[1]
A0: siul_GPIO[132]
A1: flexpwm2_B[3]
A2: _
I: pdi_DATA[1]
I: _
I: _
PDI
Medium
A3: _
A17 GPIO pdi
CLOCK
A0: siul_GPIO[128]
A1: flexpwm2_B[1]
A2: _
I: pdi_CLOCK
I: _
I: _
PDI
Medium
A3: etimer1_ETC[3]
A18 GPIO pdi
DATA[7]
A0: siul_GPIO[138]
A1: flexpwm2_B[2]
A2: _
I: pdi_DATA[7]
I: _
I: _
PDI
Medium
A3: etimer1_ETC[5]
A19 GPIO pdi
DATA[10]
A0: siul_GPIO[141]
A1: flexpwm2_X[3]
A2: _
I: pdi_DATA[10]
I: _
I: _
PDI
Medium
A3: _
A20 GPIO pdi
DATA[13]
A0: siul_GPIO[144]
A1: pdi_SENS_SEL[2]
A2: ctu1_EXT_TGR
A3: _
I: pdi_DATA[13]
I: _
I: _
PDI
Medium
A21 GPIO pdi
DATA[15]
A0: siul_GPIO[146]
A1: pdi_SENS_SEL[0]
A2: i2c2_data
I: pdi_DATA[15]
I: ctu1_EXT_IN
I: _
PDI
Medium
A3: _
B3
GPIO mc_cgl
clk_out
A0: siul_GPIO[22]
A1: mc_cgl_clk_out
A2: etimer2_ETC[5]
A3: _
I: _
I: _
GP Slow/
Fast
I: siul_EIRQ[18]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[14]
A1: can1_TXD
A2: _
Additional Inputs
Analog Inputs
Pad Type Power Domain
B4
B5
B6
B7
B8
B9
GPIO can1
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
TXD
I: siul_EIRQ[13]
A3: _
GPIO nexus
A0: siul_GPIO[219]
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
MDO[14]1 A1: _
A2: npc_wrapper_MDO[14]
A3: can3_TXD
GPIO dspi2
CS1
A0: siul_GPIO[9]
A1: dspi2_CS1
A2: _
I: flexpwm0_FAULT[0]
I: lin3_RXD
I: can2_RXD
GP Slow/
Medium
A3: _
GPIO flexray
A0: siul_GPIO[52]
I: _
I: _
I: _
GP Slow/
Symmetric
CB_TR_EN A1: flexray_CB_TR_EN
A2: _
A3: _
GPIO flexray
CA_TX
A0: siul_GPIO[48]
A1: flexray_CA_TX
A2: _
I: ctu1_EXT_IN
GP Slow/
Symmetric
I: _
I: _
A3: _
GPIO fec
RXD[3]
A0: siul_GPIO[214]
A1: i2c1_data
A2: _
I: fec_RXD[3]
GP Slow/
Medium
I: _
I: _
A3: _
B10 GPIO fec
RX_ER
A0: siul_GPIO[215]
A1: _
A2: _
I: fec_RX_ER
GP Slow/
Medium
I: _
I: _
A3: dspi0_CS1
B11
GPIO fec
TXD[0]
A0: siul_GPIO[201]
A1: fec_TXD[0]
A2: etimer2_ETC[1]
A3: _
I: _
I: _
I: _
GP Slow/
Medium
B12 GPIO fec
RXD[0]
A0: siul_GPIO[211]
A1: i2c1_clock
A2: _
I: fec_RXD[0]
I: _
I: siul_EIRQ[27]
GP Slow/
Medium
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
B13 GPIO fec
TX_ER
A0: siul_GPIO[205]
A1: fec_TX_ER
A2: dspi2_CS3
A3: _
I: flexpwm1_FAULT[3]
I: lin0_RXD
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
VDD_HV_IO
B15 GPIO pdi
DATA[6]
A0: siul_GPIO[137]
A1: flexpwm2_B[0]
A2: _
I: pdi_DATA[6]
I: _
I: _
—
—
—
—
—
—
—
—
PDI
Medium
A3: etimer1_ETC[1]
B16 GPIO pdi
DATA[4]
A0: siul_GPIO[135]
A1: flexpwm2_A[2]
A2: _
I: pdi_DATA[4]
I: _
I: _
PDI
Medium
A3: etimer1_ETC[4]
B17 GPIO pdi
DATA[0]
A0: siul_GPIO[131]
A1: _
A2: lin3_TXD
A3: _
I: pdi_DATA[0]
I: _
I: flexpwm2_FAULT[2]
PDI
Medium
B18 GPIO pdi
LINE_V
A0: siul_GPIO[129]
A1: _
A2: lin2_TXD
A3: _
I: pdi_LINE_V
I: _
I: flexpwm2_FAULT[0]
PDI
Medium
B19 GPIO pdi
DATA[9]
A0: siul_GPIO[140]
A1: flexpwm2_X[2]
A2: _
I: pdi_DATA[9]
I: _
I: _
PDI
Medium
A3: _
B20 GPIO pdi
DATA[14]
A0: siul_GPIO[145]
A1: pdi_SENS_SEL[1]
A2: i2c2_clock
A3: _
I: pdi_DATA[14]
I: _
I: _
PDI
Medium
B21 GPIO can0
A0: siul_GPIO[16]
A1: can0_TXD
A2: _
I: _
I: _
GP Slow/
Medium
TXD
I: siul_EIRQ[15]
A3: sscm_DEBUG[0]
C2
GPIO nexus
A0: siul_GPIO[220]
I: can3_RXD
I: can2_RXD
I: _
GP Slow/
Fast
MDO[15]1 A1: _
A2: npc_wrapper_MDO[15]
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[50]
A1: _
A2: ctu1_EXT_TGR
A3: _
Additional Inputs
Analog Inputs
Pad Type Power Domain
C5
C6
C7
C8
C9
GPIO flexray
I: flexray_CB_RX
—
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
CB_RX
I: _
I: _
GPIO etimer0
A0: siul_GPIO[43]
A1: etimer0_ETC[4]
A2: _
I: _
—
—
—
—
—
—
—
—
pull down GP Slow/
Medium
ETC[4]
I: mc_rgm_ABS[0]
I: _
A3: _
GPIO etimer0
ETC[1]
A0: siul_GPIO[1]
A1: etimer0_ETC[1]
A2: _
I: _
I: _
disabled
disabled
GP Slow/
Medium
I: siul_EIRQ[1]
A3: _
GPIO etimer0
ETC[2]
A0: siul_GPIO[2]
A1: etimer0_ETC[2]
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[2]
A3: _
GPIO etimer0
ETC[3]
A0: siul_GPIO[3]
A1: etimer0_ETC[3]
A2: _
I: _
pull down GP Slow/
Medium
I: mc_rgm_ABS[2]
I: siul_EIRQ[3]
A3: _
C10 GPIO fec
TXD[2]
A0: siul_GPIO[203]
A1: fec_TXD[2]
A2: _
I: flexpwm1_FAULT[1]
disabled
disabled
disabled
disabled
GP Slow/
Medium
I: _
I: _
A3: _
C11
GPIO fec
TXD[1]
A0: siul_GPIO[202]
A1: fec_TXD[1]
A2: _
I: flexpwm1_FAULT[0]
GP Slow/
Medium
I: _
I: _
A3: dspi2_SCK
C12 GPIO fec
CRS
A0: siul_GPIO[208]
A1: flexray_DBG1
A2: etimer2_ETC[3]
A3: dspi0_CS5
I: fec_CRS
I: _
GP Slow/
Medium
I: _
C13 GPIO fec
RX_CLK
A0: siul_GPIO[209]
A1: flexray_DBG2
A2: etimer2_ETC[2]
A3: dspi0_CS6
I: fec_RX_CLK
I: _
I: siul_EIRQ[25]
GP Slow/
Medium
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
I: fec_RXD[1]
I: _
I: _
Analog Inputs
Pad Type Power Domain
C14 GPIO fec
RXD[1]
A0: siul_GPIO[212]
A1: dspi1_CS1
A2: etimer2_ETC[5]
A3: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
C15 GPIO fec
COL
A0: siul_GPIO[206]
A1: fec_COL
A2: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
VDD_HV_IO
A3: lin1_TXD
C16 GPIO pdi
DATA[5]
A0: siul_GPIO[136]
A1: flexpwm2_A[0]
A2: _
I: pdi_DATA[5]
I: _
I: _
PDI
Medium
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_PDI
VDD_HV_IO
A3: etimer1_ETC[0]
C17 GPIO pdi
DATA[2]
A0: siul_GPIO[133]
A1: flexpwm2_A[1]
A2: _
I: pdi_DATA[2]
I: _
I: _
PDI
Medium
A3: etimer1_ETC[2]
C18 GPIO pdi
DATA[8]
A0: siul_GPIO[139]
A1: flexpwm2_A[3]
A2: _
I: pdi_DATA[8]
I: _
I: _
PDI
Medium
A3: _
C19 GPIO pdi
DATA[12]
A0: siul_GPIO[143]
I: pdi_DATA[12]
I: lin3_RXD
I: flexpwm2_FAULT[3]
PDI
Medium
A1: _
A2: _
A3: _
C20 GPIO can0
A0: siul_GPIO[17]
A1: _
I: can0_RXD
I: can1_RXD
I: siul_EIRQ[16]
GP Slow/
Medium
RXD
A2: _
A3: sscm_DEBUG[1]
C22 GPIO siul
A0: siul_GPIO[197]
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
GPIO[197] A1: flexpwm0_X[3]
A2: ebi_D31
A3: _
C23 GPIO dramc
CAS
A0: siul_GPIO[152]
A1: dramc_CAS
A2: ebi_WE_BE_1
A3: flexpwm0_B[2]
I: _
I: _
I: _
DRAM
ACC
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[86]
Additional Inputs
Analog Inputs
Pad Type Power Domain
D1
D2
D3
D4
D6
D7
GPIO nexus
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_PDI
MDO[1]1
A1: _
A2: npc_wrapper_MDO[1]
A3: _
GPIO nexus
MDO[3]1
A0: siul_GPIO[84]
A1: _
A2: npc_wrapper_MDO[3]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
GPIO can1
A0: siul_GPIO[15]
I: can1_RXD
I: can0_RXD
I: siul_EIRQ[14]
GP Slow/
Medium
RXD
A1: _
A2: _
A3: _
GPIO dspi0
SOUT
A0: siul_GPIO[38]
A1: dspi0_SOUT
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[24]
A3: sscm_DEBUG[6]
GPIO etimer0
ETC[5]
A0: siul_GPIO[44]
A1: etimer0_ETC[5]
A2: _
I: _
I: _
I: _
GP Slow/
Medium
A3: _
GPIO etimer0
ETC[0]
A0: siul_GPIO[0]
A1: etimer0_ETC[0]
A2: _
I: dspi2_SIN
I: _
I: siul_EIRQ[0]
GP Slow/
Medium
A3: _
D14 GPIO fec
RXD[2]
A0: siul_GPIO[213]
A1: _
A2: _
I: fec_RXD[2]
I: _
I: siul_EIRQ[21]
GP Slow/
Medium
A3: dspi2_SOUT
D15 GPIO fec
MDC
A0: siul_GPIO[199]
A1: fec_MDC
A2: _
I: _
GP Slow/
Medium
I: lin1_RXD
I: _
A3: _
D18 GPIO pdi
DATA[11]
A0: siul_GPIO[142]
A1: flexpwm2_X[0]
A2: _
I: pdi_DATA[11]
PDI
I: _
I: _
Medium
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
D19 GPIO pdi
A0: siul_GPIO[130]
I: pdi_FRAME_V
I: lin2_RXD
I: flexpwm2_FAULT[1]
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
PDI
Medium
VDD_HV_PDI
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
FRAME_V A1: _
A2: _
A3: _
D21 GPIO dramc
A0: siul_GPIO[155]
A1: dramc_BA[1]
A2: ebi_BDIP
I: _
I: _
I: _
—
—
—
—
—
—
—
—
DRAM
ACC
BA[1]
A3: flexpwm1_A[0]
D22 GPIO siul
A0: siul_GPIO[195]
I: _
I: _
I: _
DRAM
ACC
GPIO[195] A1: flexpwm0_X[1]
A2: ebi_D29
A3: _
D23 GPIO dramc
A0: siul_GPIO[154]
A1: dramc_BA[0]
A2: ebi_WE_BE_3
A3: flexpwm0_B[3]
I: _
I: _
I: _
DRAM
ACC
BA[0]
E2
E3
GPIO nexus
A0: siul_GPIO[85]
A1: _
A2: npc_wrapper_MDO[2]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
MDO[2]1
GPIO flexray
CA_RX
A0: siul_GPIO[49]
A1: _
A2: ctu0_EXT_TGR
A3: _
I: flexray_CA_RX
I: _
I: _
GP Slow/
Medium
VDD_HV_IO
E20 GPIO mc_cgl
A0: siul_GPIO[233]
A1: mc_cgl_clk_out
A2: etimer2_ETC[5]
A3: _
I: _
I: _
I: _
PDI Fast
VDD_HV_PDI
clk_out
E21 GPIO siul
A0: siul_GPIO[149]
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
GPIO[149] A1: _
A2: ebi_RD_WR
A3: flexpwm0_A[1]
E22 GPIO dramc
A0: siul_GPIO[150]
A1: dramc_CS0
A2: ebi_TS
I: _
I: _
I: _
DRAM
ACC
CS0
A3: flexpwm0_B[1]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
E23 GPIO dramc
A0: siul_GPIO[156]
A1: dramc_BA[2]
A2: ebi_CS0
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
DRAM
ACC
VDD_HV_DRAM
BA[2]
A3: flexpwm1_B[0]
F1
F2
GPIO nexus
GPIO nexus
GPIO nexus
A0: siul_GPIO[109]
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
VDD_HV_IO
MDO[10]1 A1: _
A2: npc_wrapper_MDO[10]
A3: _
A0: siul_GPIO[108]
I: _
I: _
I: _
GP Slow/
Fast
VDD_HV_IO
MDO[11]1 A1: _
A2: npc_wrapper_MDO[11]
A3: _
F3
A0: siul_GPIO[113]
A1: _
A2: npc_wrapper_MDO[6]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
VDD_HV_IO
MDO[6]1
F4
GPIO nexus
MDO[4]1
A0: siul_GPIO[115]
A1: _
A2: npc_wrapper_MDO[4]
A3: _
I: _
I: _
I: _
GP Slow/
Fast
VDD_HV_IO
F20
F21
F22
F23
GPIO dramc
RAS
A0: siul_GPIO[151]
A1: dramc_RAS
A2: ebi_WE_BE_0
A3: flexpwm0_A[2]
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
GPIO siul
A0: siul_GPIO[194]
I: _
I: _
I: _
DRAM
ACC
GPIO[194] A1: flexpwm0_X[0]
A2: ebi_D28
A3: _
GPIO siul
A0: siul_GPIO[148]
I: _
I: _
I: _
DRAM
ACC
GPIO[148] A1: _
A2: ebi_CLKOUT
A3: flexpwm0_B[0]
GPIO dramc
D[5]
A0: siul_GPIO[179]
A1: dramc_D[5]
A2: ebi_D13
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
A3: ebi_ADD29
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[87]
Additional Inputs
Analog Inputs
Pad Type Power Domain
G1
GPIO nexus
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
MCKO
A1: _
A2: npc_wrapper_MCKO
A3: _
G3
GPIO nexus
MDO[8]1
A0: siul_GPIO[111]
A1: _
A2: npc_wrapper_MDO[8]
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Fast
VDD_HV_IO
G4
GPIO nexus
A0: siul_GPIO[88]
I: _
I: _
GP Slow/
Fast
VDD_HV_IO
MSEO_B[1]1 A1: _
A2: npc_wrapper_MSEO_B[1] I: _
A3: _
G20 GPIO siul
A0: siul_GPIO[196]
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
GPIO[196] A1: flexpwm0_X[2]
A2: ebi_D30
A3: _
G21 GPIO dramc
A0: siul_GPIO[190]
A1: dramc_DQS[0]
A2: ebi_D24
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
DQS[0]
A3: _
G22 GPIO dramc
A0: siul_GPIO[192]
A1: dramc_DM[0]
A2: ebi_D26
A3: _
I: _
I: _
I: _
DM[0]
G23 GPIO dramc
A0: siul_GPIO[181]
A1: dramc_D[7]
A2: ebi_D15
I: _
I: _
I: _
D[7]
A3: ebi_ADD31
H1
H3
GPIO nexus
EVTO_B
A0: siul_GPIO[90]
A1: _
A2: npc_wrapper_EVTO_B
A3: _
I: _
I: _
I: _
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
GPIO nexus
A0: siul_GPIO[89]
I: _
I: _
I: _
GP Slow/
Fast
MSEO_B[0]1 A1: _
A2: npc_wrapper_MSEO_B[0]
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[91]
Additional Inputs
Analog Inputs
Pad Type Power Domain
H4
GPIO nexus
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
EVTI_B
A1: _
A2: leo_sor_proxy_EVTI_B
A3: _
H20 GPIO dramc
A0: siul_GPIO[176]
A1: dramc_D[2]
A2: ebi_D10
I: _
I: _
I: _
—
—
—
—
—
—
—
—
disabled DRAM DQ VDD_HV_DRAM
D[2]
A3: ebi_ADD26
J1
J2
GPIO nexus
RDY_B
A0: siul_GPIO[216]
A1: _
A2: nexus_RDY_B
A3: _
I: _
I: _
I: _
disabled
disabled
disabled
disabled
GP Slow/
Fast
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
GPIO nexus
A0: siul_GPIO[218]
I: can2_RXD
I: can3_RXD
I: _
GP Slow/
Fast
MDO[13]1 A1: _
A2: npc_wrapper_MDO[13]
A3: _
J3
GPIO nexus
A0: siul_GPIO[217]
I: _
I: _
I: _
GP Slow/
Fast
MDO[12]1 A1: _
A2: npc_wrapper_MDO[12]
A3: can2_TXD
J4
GPIO dspi1
SIN
A0: siul_GPIO[8]
A1: _
A2: _
I: dspi1_SIN
I: _
I: siul_EIRQ[8]
GP Slow/
Medium
A3: _
J20
J21
J22
GPIO dramc
D[0]
A0: siul_GPIO[174]
A1: dramc_D[0]
A2: ebi_D8
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
A3: ebi_ADD24
GPIO dramc
D[1]
A0: siul_GPIO[175]
A1: dramc_D[1]
A2: ebi_D9
I: _
I: _
I: _
A3: ebi_ADD25
GPIO dramc
D[3]
A0: siul_GPIO[177]
A1: dramc_D[3]
A2: ebi_D11
I: _
I: _
I: _
A3: ebi_ADD27
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
J23
K1
K2
K3
K4
GPIO dramc
A0: siul_GPIO[180]
A1: dramc_D[6]
A2: ebi_D14
I: _
I: _
I: _
—
disabled DRAM DQ VDD_HV_DRAM
D[6]
A3: ebi_ADD30
GPIO dspi0
A0: siul_GPIO[37]
A1: dspi0_SCK
A2: _
I: flexpwm0_FAULT[3]
I: _
I: siul_EIRQ[23]
—
—
—
—
—
—
—
—
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
SCK
A3: sscm_DEBUG[5]
GPIO dspi1
CS0
A0: siul_GPIO[5]
A1: dspi1_CS0
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[5]
A3: dspi0_CS7
GPIO dspi1
SCK
A0: siul_GPIO[6]
A1: dspi1_SCK
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[6]
A3: _
GPIO dspi1
SOUT
A0: siul_GPIO[7]
A1: dspi1_SOUT
A2: _
I: _
I: _
GP Slow/
Medium
I: siul_EIRQ[7]
A3: _
K21 GPIO dramc
A0: siul_GPIO[178]
A1: dramc_D[4]
A2: ebi_D12
I: _
I: _
I: _
DRAM DQ VDD_HV_DRAM
D[4]
A3: ebi_ADD28
K22 GPIO dramc
A0: siul_GPIO[182]
A1: dramc_D[8]
A2: ebi_D16
A3: _
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
D[8]
K23 GPIO dramc
A0: siul_GPIO[183]
A1: dramc_D[9]
A2: ebi_D17
A3: _
I: _
I: _
I: _
D[9]
L1
GPIO dspi0
CS0
A0: siul_GPIO[36]
A1: dspi0_CS0
A2: _
I: _
I: _
disabled
GP Slow/
Medium
VDD_HV_IO
I: siul_EIRQ[22]
A3: sscm_DEBUG[4]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[42]
A1: dspi2_CS2
A2: lin3_TXD
A3: can2_TXD
Additional Inputs
Analog Inputs
Pad Type Power Domain
L2
L3
GPIO dspi2
I: flexpwm0_FAULT[1]
—
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
CS2
I: _
I: _
GPIO dspi2
A0: siul_GPIO[10]
A1: dspi2_CS0
A2: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
VDD_HV_IO
CS0
I: siul_EIRQ[9]
A3: can3_TXD
M1
M3
GPIO flexpwm0
X[0]
A0: siul_GPIO[57]
A1: flexpwm0_X[0]
A2: lin2_TXD
A3: _
I: _
I: _
I: _
GP Slow/
Medium
VDD_HV_IO
GPIO dspi0
SIN
A0: siul_GPIO[39]
A1: _
A2: _
I: dspi0_SIN
GP Slow/
Medium
VDD_HV_IO
I: _
I: _
A3: sscm_DEBUG[7]
M20 GPIO dramc
A0: siul_GPIO[157]
A1: dramc_ODT
A2: ebi_CS1
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
ODT
A3: flexpwm1_A[1]
M21 GPIO dramc
A0: siul_GPIO[153]
A1: dramc_WEB
A2: ebi_WE_BE_2
A3: flexpwm0_A[3]
I: _
I: _
I: _
DRAM
ACC
WEB
M22 GPIO dramc
A0: siul_GPIO[185]
A1: dramc_D[11]
A2: ebi_D19
A3: _
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
D[11]
M23 GPIO dramc
A0: siul_GPIO[184]
A1: dramc_D[10]
A2: ebi_D18
A3: _
I: _
I: _
I: _
D[10]
N1
GPIO flexpwm0
A[0]
A0: siul_GPIO[58]
A1: flexpwm0_A[0]
A2: _
I: _
disabled
GP Slow/
Medium
VDD_HV_IO
I: etimer0_ETC[0]
I: _
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[60]
A1: flexpwm0_X[1]
A2: _
A3: _
Additional Inputs
I: lin2_RXD
I: _
I: _
Analog Inputs
Pad Type Power Domain
N3
N4
GPIO flexpwm0
X[1]
—
disabled
GP Slow/
Medium
VDD_HV_IO
GPIO flexpwm0
B[2]
A0: siul_GPIO[100]
A1: flexpwm0_B[2]
A2: _
I: _
—
—
—
—
—
—
—
—
disabled
GP Slow/
Medium
VDD_HV_IO
I: etimer0_ETC[5]
I: _
A3: _
N20 GPIO dramc
A0: siul_GPIO[191]
A1: dramc_DQS[1]
A2: ebi_D25
I: _
I: _
I: _
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
DQS[1]
A3: _
N21 GPIO dramc
A0: siul_GPIO[193]
A1: dramc_DM[1]
A2: ebi_D27
A3: _
I: _
I: _
I: _
DM[1]
N22 GPIO dramc
A0: siul_GPIO[187]
A1: dramc_D[13]
A2: ebi_D21
A3: _
I: _
I: _
I: _
D[13]
N23 GPIO dramc
A0: siul_GPIO[186]
A1: dramc_D[12]
A2: ebi_D20
A3: _
I: _
I: _
I: _
D[12]
P1
P2
P3
GPIO flexpwm0
B[0]
A0: siul_GPIO[59]
A1: flexpwm0_B[0]
A2: _
I: _
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
I: etimer0_ETC[1]
I: _
A3: _
GPIO flexpwm0
B[1]
A0: siul_GPIO[62]
A1: flexpwm0_B[1]
A2: _
I: _
GP Slow/
Medium
I: etimer0_ETC[3]
I: _
A3: _
GPIO flexpwm0
A[2]
A0: siul_GPIO[99]
A1: flexpwm0_A[2]
A2: _
I: _
GP Slow/
Medium
I: etimer0_ETC[4]
I: _
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
P4
GPIO flexpwm0
A[3]
A0: siul_GPIO[102]
A1: flexpwm0_A[3]
A2: _
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
A3: _
P20 GPIO dramc
A0: siul_GPIO[188]
A1: dramc_D[14]
A2: ebi_D22
A3: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
disabled DRAM DQ VDD_HV_DRAM
disabled DRAM DQ VDD_HV_DRAM
D[14]
P21 GPIO dramc
A0: siul_GPIO[189]
A1: dramc_D[15]
A2: ebi_D23
A3: _
I: _
I: _
I: _
D[15]
R1
R2
R3
GPIO flexpwm0
X[2]
A0: siul_GPIO[98]
A1: flexpwm0_X[2]
A2: lin3_TXD
A3: _
I: _
I: _
I: _
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
GPIO flexpwm0
X[3]
A0: siul_GPIO[101]
A1: flexpwm0_X[3]
A2: _
I: lin3_RXD
I: _
I: _
GP Slow/
Medium
A3: _
GPIO flexpwm0
A[1]
A0: siul_GPIO[80]
A1: flexpwm0_A[1]
A2: _
I: _
GP Slow/
Medium
VDD_HV_IO
I: etimer0_ETC[2]
I: _
A3: _
R21 GPIO dramc
A0: siul_GPIO[161]
A1: dramc_ADD[3]
A2: ebi_ADD11
A3: ebi_TEA
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
ADD[3]
R22 GPIO dramc
A0: siul_GPIO[147]
A1: dramc_CKE
A2: ebi_OE
I: _
I: _
I: _
DRAM
ACC
CKE
A3: flexpwm0_A[0]
T1
GPIO flexpwm0
B[3]
A0: siul_GPIO[103]
A1: flexpwm0_B[3]
A2: _
I: _
I: _
I: _
GP Slow/
Medium
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
T2
T3
GPIO flexpwm1
A[0]
A0: siul_GPIO[117]
A1: flexpwm1_A[0]
A2: _
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
A3: can2_TXD
GPIO flexpwm1
A[1]
A0: siul_GPIO[120]
A1: flexpwm1_A[1]
A2: _
I: _
I: _
I: _
—
—
—
—
—
—
—
—
GP Slow/
Medium
VDD_HV_IO
A3: can3_TXD
T20
T21
T22
U1
GPIO dramc
ADD[8]
A0: siul_GPIO[166]
A1: dramc_ADD[8]
A2: ebi_D0
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
A3: ebi_ADD16
GPIO dramc
ADD[9]
A0: siul_GPIO[167]
A1: dramc_ADD[9]
A2: ebi_D1
I: _
I: _
I: _
DRAM
ACC
A3: ebi_ADD17
GPIO dramc
ADD[1]
A0: siul_GPIO[159]
A1: dramc_ADD[1]
A2: ebi_ADD9
I: _
I: _
I: _
DRAM
ACC
A3: ebi_CS3
GPIO flexpwm1
B[0]
A0: siul_GPIO[118]
A1: flexpwm1_B[0]
A2: _
I: can2_RXD
I: can3_RXD
I: _
GP Slow/
Medium
A3: _
U2
GPIO flexpwm1
B[1]
A0: siul_GPIO[121]
A1: flexpwm1_B[1]
A2: _
I: can3_RXD
I: can2_RXD
I: _
GP Slow/
Medium
VDD_HV_IO
A3: _
U3
GPIO flexpwm1
A[2]
A0: siul_GPIO[123]
A1: flexpwm1_A[2]
A2: _
I: _
I: _
I: _
GP Slow/
Medium
VDD_HV_IO
A3: _
U4
GPIO dspi2
SCK
A0: siul_GPIO[11]
A1: dspi2_SCK
A2: _
I: can3_RXD
I: _
I: siul_EIRQ[10]
GP Slow/
Medium
VDD_HV_IO
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
U20 GPIO dramc
A0: siul_GPIO[164]
A1: dramc_ADD[6]
A2: ebi_ADD14
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
ADD[6]
A3: flexpwm1_A[2]
U21 GPIO dramc
A0: siul_GPIO[170]
A1: dramc_ADD[12]
A2: ebi_D4
I: _
I: _
I: _
—
—
—
—
—
—
—
—
DRAM
ACC
ADD[12]
A3: ebi_ADD20
U23 GPIO dramc
A0: siul_GPIO[158]
A1: dramc_ADD[0]
A2: ebi_ADD8
I: _
I: _
I: _
DRAM
ACC
ADD[0]
A3: ebi_CS2
V3
V4
GPIO flexpwm1
B[2]
A0: siul_GPIO[124]
A1: flexpwm1_B[2]
A2: _
I: _
I: _
I: _
GP Slow/
Medium
A3: _
GPIO dspi1
CS2
A0: siul_GPIO[56]
A1: dspi1_CS2
A2: _
I: flexpwm0_FAULT[3]
I: lin2_RXD
I: _
GP Slow/
Medium
VDD_HV_IO
A3: dspi0_CS5
V20 GPIO lin0
A0: siul_GPIO[18]
A1: lin0_TXD
A2: i2c0_clock
I: _
I: _
GP Slow/
Medium
VDD_HV_IO
TXD
I: siul_EIRQ[17]
A3: sscm_DEBUG[2]
V21 GPIO dramc
A0: siul_GPIO[171]
A1: dramc_ADD[13]
A2: ebi_D5
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
ADD[13]
A3: ebi_ADD21
V23 GPIO dramc
A0: siul_GPIO[160]
A1: dramc_ADD[2]
A2: ebi_ADD10
A3: ebi_TA
I: _
I: _
I: _
DRAM
ACC
ADD[2]
W3
GPIO dspi0
CS3
A0: siul_GPIO[53]
A1: dspi0_CS3
A2: i2c2_clock
A3: _
I: flexpwm0_FAULT[2]
I: _
I: _
GP Slow/
Medium
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[19]
A1: _
A2: i2c0_data
A3: sscm_DEBUG[3]
Additional Inputs
I: lin0_RXD
I: _
I: _
Analog Inputs
Pad Type Power Domain
W20 GPIO lin0
RXD
—
disabled
disabled
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
W21 GPIO dramc
ADD[14]
A0: siul_GPIO[172]
A1: dramc_ADD[14]
A2: ebi_D6
I: _
I: _
I: _
—
—
—
—
—
DRAM
ACC
A3: ebi_ADD22
W22 GPIO dramc
A0: siul_GPIO[165]
A1: dramc_ADD[7]
A2: ebi_ADD15
I: _
I: _
I: _
DRAM
ACC
ADD[7]
A3: flexpwm1_B[2]
W23 GPIO dramc
A0: siul_GPIO[162]
A1: dramc_ADD[4]
A2: ebi_ADD12
A3: ebi_ALE
I: _
I: _
I: _
DRAM
ACC
ADD[4]
Y3
Y5
GPIO dspi0
CS2
A0: siul_GPIO[54]
A1: dspi0_CS2
A2: i2c2_data
A3: _
I: flexpwm0_FAULT[1]
I: _
I: _
GP Slow/
Medium
GPIO flexpwm1
X[0]
A0: siul_GPIO[116]
A1: flexpwm1_X[0]
A2: etimer2_ETC[0]
A3: dspi0_CS1
I: ctu0_EXT_IN
I: ctu1_EXT_IN
I: _
GP Slow/
Medium
VDD_HV_IO
Y6
Y7
Y8
ANA adc3
AN[0]
—
—
—
siul_GPI[229]
siul_GPI[225]
siul_GPI[228]
AN: adc3_AN[0]
—
—
—
Analog VDD_HV_ADR23
ANA adc2_adc3
AN[11]
AN: adc2_adc3_AN[11]
AN: adc2_adc3_AN[14]
Analog VDD_HV_ADR23
Shared
ANA adc2_adc3
AN[14]
Analog VDD_HV_ADR23
Shared
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
A0: siul_GPIO[45]
A1: etimer1_ETC[1]
A2: _
A3: _
Additional Inputs
Analog Inputs
Pad Type Power Domain
Y9
GPIO etimer1
I: ctu0_EXT_IN
I: flexpwm0_EXT_SYNC
I: ctu1_EXT_IN
—
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
ETC[1]
Y10 GPIO etimer1
A0: siul_GPIO[46]
A1: etimer1_ETC[2]
A2: ctu0_EXT_TGR
A3: _
I: _
I: _
I: _
—
—
disabled
GP Slow/
Medium
ETC[2]
Y11
GPIO etimer1
ETC[3]
A0: siul_GPIO[92]
A1: etimer1_ETC[3]
A2: _
I: ctu1_EXT_IN
I: mc_rgm_FAB
I: siul_EIRQ[30]
pull down GP Slow/
Medium
A3: _
Y14 ANA adc0_adc1
—
siul_GPI[25]
AN: adc0_adc1_AN[11]
—
Analog
Shared
VDD_HV_ADR0
VDD_HV_IO
AN[11]
Y15 GPIO etimer1
A0: siul_GPIO[78]
A1: etimer1_ETC[5]
A2: _
I: _
I: _
—
disabled
GP Slow/
Medium
ETC[5]
I: siul_EIRQ[26]
A3: _
Y16 GPIO etimer1
A0: siul_GPIO[93]
A1: etimer1_ETC[4]
A2: ctu1_EXT_TGR
A3: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
ETC[4]
I: siul_EIRQ[31]
Y17 ANA adc1
—
siul_GPI[74]
siul_GPI[76]
AN: adc1_AN[8]
AN: adc1_AN[6]
—
—
—
Analog
Analog
VDD_HV_ADR1
VDD_HV_ADR1
VDD_HV_DRAM
AN[8]
Y18 ANA adc1
—
AN[6]
Y21 GPIO dramc
A0: siul_GPIO[173]
A1: dramc_ADD[15]
A2: ebi_D7
I: _
I: _
I: _
disabled
DRAM
ACC
ADD[15]
A3: ebi_ADD23
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
Y22 GPIO dramc
ADD[11]
A0: siul_GPIO[169]
A1: dramc_ADD[11]
A2: ebi_D3
I: _
I: _
I: _
—
disabled
disabled
disabled
disabled
DRAM
ACC
VDD_HV_DRAM
VDD_HV_DRAM
VDD_HV_IO
A3: ebi_ADD19
Y23 GPIO dramc
A0: siul_GPIO[163]
A1: dramc_ADD[5]
A2: ebi_ADD13
I: _
I: _
I: _
—
—
—
DRAM
ACC
ADD[5]
A3: flexpwm1_B[1]
AA4 GPIO dspi1
A0: siul_GPIO[55]
A1: dspi1_CS3
A2: lin2_TXD
I: _
I: _
I: _
GP Slow/
Medium
CS3
A3: dspi0_CS4
AA5 GPIO flexpwm1
A0: siul_GPIO[119]
A1: flexpwm1_X[1]
A2: etimer2_ETC[1]
A3: dspi0_CS4
I: _
I: _
I: _
GP Slow/
Medium
VDD_HV_IO
X[1]
AA6 ANA adc3
—
—
—
—
—
—
siul_GPI[230]
siul_GPI[226]
siul_GPI[221]
siul_GPI[33]
siul_GPI[66]
siul_GPI[69]
AN: adc3_AN[1]
AN: adc2_adc3_AN[12]
AN: adc2_AN[0]
AN: adc0_AN[2]
AN: adc0_AN[5]
AN: adc0_AN[8]
—
—
—
—
—
—
Analog VDD_HV_ADR23
AN[1]
AA7 ANA adc2_adc3
Analog VDD_HV_ADR23
Shared
AN[12]
AA8 ANA adc2
Analog VDD_HV_ADR23
AN[0]
AA11 ANA adc0
Analog
Analog
Analog
VDD_HV_ADR0
VDD_HV_ADR0
VDD_HV_ADR0
AN[2]
AA12 ANA adc0
AN[5]
AA13 ANA adc0
AN[8]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
siul_GPI[26]
Analog Inputs
Pad Type Power Domain
AA14 ANA adc0_adc1
—
AN: adc0_adc1_AN[12]
—
—
—
Analog
Shared
VDD_HV_ADR0
VDD_HV_ADR1
VDD_HV_ADR1
AN[12]
AA15 ANA adc1
—
—
siul_GPI[29]
AN: adc1_AN[0]
AN: adc1_AN[2]
Analog
Analog
AN[0]
lin1_RXD
AA16 ANA adc1
siul_GPI[31]
AN[2]
siul_EIRQ[20]
siul_GPI[64]
AA17 ANA adc1
—
—
AN: adc1_AN[5]
AN: adc1_AN[7]
—
—
—
Analog
Analog
VDD_HV_ADR1
VDD_HV_ADR1
VDD_HV_IO
AN[5]
AA18 ANA adc1
siul_GPI[73]
AN[7]
AA19 GPIO TDI
A0: siul_GPIO[21]
I: jtagc_TDI
I: _
I: _
pull up
GP Slow/
Medium
A1: _
A2: _
A3: _
AA20 GPIO etimer1
A0: siul_GPIO[4]
A1: etimer1_ETC[0]
A2: _
I: _
I: _
—
—
—
—
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
ETC[0]
I: siul_EIRQ[4]
A3: _
AA22 GPIO lin1
A0: siul_GPIO[94]
A1: lin1_TXD
A2: i2c1_clock
A3: _
I: _
I: _
I: _
GP Slow/
Medium
TXD
AA23 GPIO dramc
A0: siul_GPIO[168]
A1: dramc_ADD[10]
A2: ebi_D2
I: _
I: _
I: _
DRAM
ACC
VDD_HV_DRAM
VDD_HV_IO
ADD[10]
A3: ebi_ADD18
AB3 GPIO dspi2
A0: siul_GPIO[12]
A1: dspi2_SOUT
A2: _
I: _
I: _
GP Slow/
Medium
SOUT
I: siul_EIRQ[11]
A3: _
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
Analog Inputs
Pad Type Power Domain
AB4 GPIO flexpwm1
A0: siul_GPIO[122]
A1: flexpwm1_X[2]
A2: etimer2_ETC[2]
A3: dspi0_CS5
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
X[2]
AB5 GPIO flexpwm1
A0: siul_GPIO[125]
A1: flexpwm1_X[3]
A2: etimer2_ETC[3]
A3: dspi0_CS6
I: _
I: _
I: _
—
disabled
GP Slow/
Medium
VDD_HV_IO
X[3]
AB6 ANA adc3
—
—
—
—
—
—
—
—
—
siul_GPI[231]
siul_GPI[227]
siul_GPI[222]
siul_GPI[223]
siul_GPI[23]
AN: adc3_AN[2]
AN: adc2_adc3_AN[13]
AN: adc2_AN[1]
—
—
—
—
—
—
—
—
—
Analog VDD_HV_ADR23
AN[2]
AB7 ANA adc2_adc3
Analog VDD_HV_ADR23
Shared
AN[13]
AB8 ANA adc2
Analog VDD_HV_ADR23
Analog VDD_HV_ADR23
AN[1]
AB9 ANA adc2
AN: adc2_AN[2]
AN[2]
AB10 ANA adc0
AN: adc0_AN[0]
Analog
Analog
Analog
Analog
VDD_HV_ADR0
VDD_HV_ADR0
VDD_HV_ADR0
VDD_HV_ADR0
VDD_HV_ADR0
AN[0]
lin0_RXD
AB11 ANA adc0
siul_GPI[70]
AN: adc0_AN[4]
AN[4]
AB12 ANA adc0
siul_GPI[71]
siul_GPI[68]
siul_GPI[27]
AN: adc0_AN[6]
AN[6]
AB13 ANA adc0
AN: adc0_AN[7]
AN[7]
AB14 ANA adc0_adc1
AN: adc0_adc1_AN[13]
Analog
Shared
AN[13]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
siul_GPI[30]
Analog Inputs
Pad Type Power Domain
AB15 ANA adc1
—
AN: adc1_AN[1]
—
Analog
VDD_HV_ADR1
AN[1]
etimer0_ETC[4]
siul_EIRQ[19]
siul_GPI[32]
AB16 ANA adc1
—
—
AN: adc1_AN[3]
AN: adc1_AN[4]
—
—
—
Analog
Analog
VDD_HV_ADR1
VDD_HV_ADR1
VDD_HV_IO
AN[3]
AB17 ANA adc1
siul_GPI[75]
AN[4]
AB18 GPIO TDO
A0: siul_GPIO[20]
A1: jtagc_TDO
A2: _
I: _
I: _
I: _
disabled
GP Slow/
Fast
A3: _
AB21 GPIO lin1
A0: siul_GPIO[95]
A1: _
A2: i2c1_data
A3: _
I: lin1_RXD
I: _
I: _
—
—
—
—
disabled
disabled
disabled
disabled
GP Slow/
Medium
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
VDD_HV_IO
RXD
AC3 GPIO dspi2
A0: siul_GPIO[13]
I: dspi2_SIN
I: flexpwm0_FAULT[0]
I: siul_EIRQ[12]
GP Slow/
Medium
SIN
A1: _
A2: _
A3: _
AC4 GPIO flexpwm1
A0: siul_GPIO[126]
A1: flexpwm1_A[3]
A2: etimer2_ETC[4]
A3: dspi0_CS7
I: _
I: _
I: _
GP Slow/
Medium
A[3]
AC5 GPIO flexpwm1
A0: siul_GPIO[127]
A1: flexpwm1_B[3]
A2: etimer2_ETC[5]
A3: _
I: _
I: _
I: _
GP Slow/
Medium
B[3]
AC6 ANA adc3
—
siul_GPI[232]
siul_GPI[224]
AN: adc3_AN[3]
AN: adc2_AN[3]
—
—
GP Slow/ VDD_HV_ADR23
Medium
AN[3]
AC9 ANA adc2
—
Analog VDD_HV_ADR23
AN[3]
Table 10. 473 MAPBGA pin multiplexing (continued)
Ball
Number Type
Ball
Weak pull
during reset
Ball Name
Alternate I/O
Additional Inputs
siul_GPI[24]
Analog Inputs
Pad Type Power Domain
AC10 ANA adc0
—
AN: adc0_AN[1]
—
—
—
Analog
Analog
VDD_HV_ADR0
VDD_HV_ADR0
VDD_HV_ADR0
AN[1]
etimer0_ETC[5]
AC11 ANA adc0
—
—
siul_GPI[34]
AN: adc0_AN[3]
AN[3]
AC14 ANA adc0_adc1
siul_GPI[28]
AN: adc0_adc1_AN[14]
Analog
Shared
AN[14]
END OF 473 MAPBGA PIN MULTIPLEXING TABLE
NOTES:
1
Do not connect pin directly to a power supply or ground.
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for this device.
The “Symbol” column of the electrical parameter and timings tables may contain an additional column
containing “SR”, “CC”, “P”, “C”, “T” or “D”.
•
“SR” identifies system requirements—conditions that must be provided to ensure normal device
operation. An example is the input voltage of a voltage regulator.
•
“CC” identifies specifications that define normal device operation. Where available, the letters
“P”, “C”, “T” or “D” replace the letter “CC” and apply to these controller characteristics. They
specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a
statistically relevant sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values are shown in the typical
(“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
1
Table 11. Absolute maximum ratings
No.
Symbol
Parameter
Conditions
Min
Max2
Unit
1
2
VDD_HV_PMU SR Voltage regulator supply voltage
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
5.53
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VSS_HV_PMU
VDD_HV_IO
VSS_HV_IO
SR Voltage regulator supply ground
SR Input/output supply voltage
SR Input/output supply ground
SR Flash supply voltage
0.1
3
3.64,5
0.1
4
5
VDD_HV_FLA
VSS_HV_FLA
3.64,5
6
SR Flash supply ground
0.1
7
VDD_HV_OSC SR Crystal oscillator amplifier supply voltage
3.64,5
0.1
8
VSS_HV_OSC
VDD_HV_PDI
VSS_HV_PDI
SR Crystal oscillator amplifier supply ground
SR PDI interface supply voltage
9
3.64,5
10
SR PDI interface supply ground
0.1
11 VDD_HV_DRAM SR DRAM interface supply voltage
3.64,5
0.1
12 VSS_HV_DRAM SR DRAM interface supply ground
6
13 VDD_HV_ADRx
14
SR ADCx high reference voltage
6.0
VSS_HV_ADRx SR ADCx low reference voltage
0.1
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
70
Freescale Semiconductor
Electrical characteristics
1
Table 11. Absolute maximum ratings (continued)
No.
Symbol
Parameter
SR ADC supply voltage
Conditions
Min
Max2
Unit
15
16
17
18
19
20
21
VDD_HV_ADV
VSS_HV_ADV
VDD_LV_COR
VSS_LV_COR
VDD_LV_PLL
VSS_LV_PLL
TVDD
—
—
—
—
—
—
—
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
—
3.64,5
V
SR ADC supply ground
0.1
V
SR Core supply voltage digital logic
SR Core supply voltage ground digital logic
SR PLL supply voltage
1.327
0.1
V
V
V
1.4
SR PLL reference voltage
0.1
V
SR Slope characteristics on all VDD during power
up
25
mV/µs
22
23
24
25
VIN
SR Voltage on any pin with respect to its supply rail Relative to
–0.3
–10
–3
V
V
DD_HV_xxx
VDD_HV_xxx
VDD_HV_xxx
+ 0.38
IINJPAD
IINJPADA
IINJSUM
SR Injected input current on any pin during
overload condition (incl. analog pins TBD)
—
10
mA
mA
mA
SR Injected input current on any analog pin during
overload condition
—
—
3
SR Absolute sum of all injected input currents
during overload condition
–50
–55
50
150
26
27
TSTG
TSDR
SR Storage temperature
—
—
°C
°C
SR Maximum Solder Temperature9
Pb-free package
—
—
260
245
SnPb package
28
MSL
SR Moisture Sensitivity Level10
—
—
3
—
NOTES:
1
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3
4
5
6
7
8
9
TBD V for 10 hours cumulative time, 5.0 V + 10% for time remaining.
5.3 V for 10 hours cumulative over lifetime of device, 3.63 V for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
All VDD_HV_ADRx rails must be operated at the same supply voltage.
2.0 V for 10 hours cumulative time, 1.2 V + 10% for time remaining.
Only when VDD_HV_xxx < 5.2 V.
Solder profile per CDF-AEC-Q100.
10 Moisture sensitivity per JEDEC test method A112.
3.3
Recommended operating conditions
1
Table 12. Recommended operating conditions
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
VDD_HV_PMU SR Voltage regulator supply voltage
—
3.0
5.5
V
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
71
Electrical characteristics
1
Table 12. Recommended operating conditions (continued)
No.
Symbol
Parameter
Conditions
Min
Max
Unit
2
3
VSS_HV_PMU
VDD_HV_IO
SR Voltage regulator supply ground
SR Input/output supply voltage
SR Input/output supply ground
SR Flash supply voltage
—
—
—
—
—
—
—
—
—
—
—
—
0
3.0
0
0
3.6
0
V
V
V
V
V
V
V
V
V
V
V
V
4
VSS_HV_IO
5
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_OSC
VSS_HV_OSC
VDD_HV_PDI
VSS_HV_PDI
3.0
0
3.6
0
6
SR Flash supply ground
7
SR Crystal oscillator amplifier supply voltage
SR Crystal oscillator amplifier supply ground
SR PDI interface supply voltage
SR PDI interface supply ground
3.0
0
3.6
0
8
9
1.62
0
3.6
0
10
11 VDD_HV_DRAM SR DRAM interface supply voltage
1.62
0
3.6
0
12
13
VSS_HV_DRAM SR DRAM interface supply ground
VDD_HV_ADRx SR ADCx high reference voltage
3.0
4.5
3.6
5.5
Alternate input
voltage
14
15
16
17
VSS_HV_ADRx SR ADCx low reference voltage
—
—
—
0
3.0
0
0
3.6
0
V
V
V
V
VDD_HV_ADV
VSS_HV_ADV
VDD_LV_COR
SR ADC supply voltage
SR ADC supply ground
SR Core supply voltage digital logic2
ExternalVREG
mode
1.14
1.32
17a
CC
Internal VREG
Mode
1.14
1.32
V
18
19
VSS_LV_COR
VDD_LV_PLL
SR Core supply voltage ground digital logic
SR PLL supply voltage2
—
0
0
V
V
ExternalVREG
mode
1.14
1.32
19a
CC
Internal VREG
Mode
1.14
1.32
V
20
21
VSS_LV_PLL
TA
SR PLL reference voltage
—
0
0
V
SR Ambient temperature under bias3
257 MAPBGA
473 MAPBGA
257 MAPBGA
473 MAPBGA
–40
–40
–40
–40
1054
125
150
150
°C
°C
°C
22
TJ
SR Junction temperature under bias
NOTES:
1
These specifications are design targets and are subject to change per device characterization.
2
The jitter specifications for both PLLs holds true only up to 50 mV noise (peak to peak) on VDD_LV_COR and
VDD_LV_PLL
.
3
4
See Table 1 for available frequency and package options.
Preliminary data.
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
72
Freescale Semiconductor
Electrical characteristics
3.4
Thermal characteristics
1
Table 13. Thermal characteristics for package options
Value
No.
Symbol
Parameter
Conditions
Unit
BGA BGA
257
473
1
2
3
4
RJA CC Thermal resistance junction-to-ambient Single layer board – 1s
40 34 °C/W
22 20 °C/W
32 26 °C/W
18 17 °C/W
10 10 °C/W
natural convection2
RJA CC Thermal resistance junction-to-ambient Four layer board – 2s2p
natural convection2
RJMA CC Thermal resistance
junction-to-moving-air ambient2
@ 200 ft./min.,
single layer board – 1s
RJMA CC Thermal resistance
junction-to-moving-air ambient2
@ 200 ft./min.,
four layer board – 2s2p
5
6
7
RJB CC Thermal resistance junction-to-board3
RJC CC Thermal resistance junction-to-case4
—
—
—
6
2
6 °C/W
2 °C/W
JT
CC Junction-to-package-top natural
convection5
NOTES:
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2
3
4
5
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
× P )
Eqn. 1
J
A
JA
D
where:
o
T
= ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
JA
P
= power dissipation in the package (W)
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single layer
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
73
Electrical characteristics
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case
thermal resistance and a case to ambient thermal resistance:
R
= R
+ R
CA
Eqn. 2
JA
JC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
JA
JC
CA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to
JC
change the case to ambient thermal resistance, R
. For instance, the user can change the size of the heat
CA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter ( ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using Equation 3:
T = T + ( × P )
Eqn. 3
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
JT
P
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
See [6] to [10] in Section 6, Reference documents, for more information.
3.5
Electromagnetic interference (EMI) characteristics
3.5.1
Test Setup
Electromagnetic emission tests are performed by TEM cell [2] and via direct coupling [3] (150 Ohm)
measurements.
Electromagnetic immunity are measured by DPI [4].
PXS30 Microcontroller Data Sheet, Rev. 1
74
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
See Section 6, Reference documents, for more information.
3.5.2
Test parameters
The following test parameters shall be used:
Table 14. EMC test parameters
Receiver
Method
Frequency Range
BW
Step Size
150 Ohm
TEM
1 MHz to 1000 MHz
1 MHz
500 kHz
In case of only narrow band disturbances the maximum of the results will not change. In case of broadband
signals the emission has to be below the limits.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of
each sample according to each pin combination. The sample size depends on the number of supply pins in
the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
1, 2
Table 15. ESD ratings
No.
Symbol
Parameter
Conditions
Class Max value3
Unit
1
VESD(HBM)
SR Electrostatic discharge TA = 25 °C
H1C
2000
V
(Human Body Model)
conforming to AEC-Q100-002
2
3
VESD(MM)
SR Electrostatic discharge TA = 25 °C
M2
200
V
V
(Machine Model)
conforming to AEC-Q100-003
VESD(CDM)
SR Electrostatic discharge TA = 25 °C
C3A 750 (corners)
500
(Charged Device Model) conforming to AEC-Q100-011
NOTES:
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply over voltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
75
Electrical characteristics
Table 16. Latch-up results
Parameter
CC Static latch-up class
No.
Symbol
LU
Conditions
Class
1
TA = 125 °C conforming to JESD 78
II level A
3.8
Power Management Controller (PMC) electrical characteristics
3.8.1
PMC electrical specifications
This section contains electrical characteristics for the PMC.
Table 17. PMC electrical specifications
No.
Symbol
Parameter
Min
Typ
Max
Unit
2
VDD_LV_COR CC Nominal VRC regulated 1.2 V output
—
1.28
—
V
V
DD_HV_PMU
3
4
PorC
LvdC
CC POR rising VDD 1.2 V
• POR VDD variation
—
PorC – 30%
—
0.7
PorC
75
—
PorC + 30%
—
V
V
mV
• POR 1.2 V hysteresis
CC Nominal LVD 1.2 V
—
—
1.1751
1.2151
LvdC1
LvdC1
15
—
—
V
V
V
V
mV
• LVD 1.2 V at reset (LVDCR)
• LVD 1.2 V variation at reset
• LVD 1.2 V variation after reset
• LVD 1.2 V hysteresis
LvdC – 3.5%
LvdC – 3%
10
LvdC + 3.5%
LvdC + 3%
20
5
HvdC
CC Nominal HVD 1.2 V
—
—
1.321
1.441
—
—
• HVD 1.2 V at reset (HVDCR)
• HVD 1.2 V variation at reset
• HVD 1.2 V variation after reset
• HVD 1.2 V hysteresis
V
V
V
HvdC – 3.5%
HvdC – 3%
10
HvdC1 HvdC + 3.5%
HvdC1
15
HvdC + 3%
20
mV
6
7
VddStepC CC Trimming step LVD 1.2 V, HVD 1.2 V,
—
5
—
mV
VRC 1.2 V
PorReg
LvdReg
CC POR rising on VDDREG
• POR VDDREG variation
• POR VDDREG hysteresis
—
2.00
—
V
V
mV
PorReg – 30% PorReg PorReg + 30%
—
250
—
8
CC Nominal rising LVD 3.3 V on VDDREG
VDDIO, VDDFLASH, and VDDADC
• LVD 3.3 V variation at reset
• LVD 3.3 V variation after reset
• LVD 3.3 V hysteresis
,
—
2.865
—
V
V
V
LvdReg – 3.5% LvdReg1 LvdReg + 3.5%
LvdReg – 3% LvdReg1 LvdReg + 3%
—
—
—
30
50
25
—
—
—
mV
mV/ms
mV/µs
• Minimum slew rate
• Maximum slew rate
9
LvdStepReg CC Trimming step LVD 3.3 V
—
30
—
mV
NOTES:
1
Rising VDD
.
PXS30 Microcontroller Data Sheet, Rev. 1
76
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.8.2
PMC board schematic and components
Figure 7 shows a sample application for the PMC.
VDD_HV_PMU
VSS_HV_PMU
Ca
Cb
Cd
R
Q
VREG_CTRL
VDD_LV_COR
L
Cl
Ce
D
VSS_LV_COR
Figure 7. PMU mandatory external components
Table 18. VRC SMPS recommended external devices
Reference
Designator
Part Description
Part Type Nominal
Description
Ca
Cb
Cd
—
—
—
capacitor 20 µF, 20 V Filter capacitor
capacitor 0.1 µF, 20 V Filter capacitor
capacitor 20 µF, 20 V Supply decoupling cap, ESR < 50 m,
as close to p-MOS source as possible
Ce
Cl
—
—
capacitor 0.1 µF, 16 V Ceramic
capacitor 20 µF, 16 V Buck capacitor, total ESR < 100 m,
as close to the coil as possible
D
L
SS8P3L
—
Schottky
inductor 4 µH, 1.5 A Buck shielded coil low ESR
Vishay low threshold p-MOS, Vth <
—
Vishay low Vf Schottky diode
Q
SUD50P04/SQD50P04 pMOS 2 A, 40 V
2.5 V, Rdson@4.5 V < 20 m, Cg
< 5 nF
R
—
resistor 50–100 k Pull up for power p-MOS gate
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
77
Electrical characteristics
3.9
Supply current characteristics
1
Table 19. Current consumption characteristics
No.
Symbol
Parameter
Conditions
VDD_LV = 1.36 V, fCore = 180 MHz, 1:2
Min Typ Max Unit
1
IDD_LV
CC Maximum run IDD
—
600 900 mA
(incl. digital core logic Mode, DPM, both cores executing EMC test
and analog block of code, internal VREG mode, all caches
the LV rail)
enabled, code execution of core 0 from
code flash 0, code execution of core 1 from
code flash 1, FMPLL_1 active at 120 MHz.
2
3
IDD_LV_PLL CC Maximum run IDD for VDD_LV_PLL = 1.36 V, fVCO running at
—
—
1.5
20
2
mA
each PLL2
maximum frequency.
IDD_HV_FLA CC Maximum run IDD
VDD_HV_FLA = 3.6 V, DPM, both cores
executing EMC test code, code execution of
core 0 from code flash 0, code execution of
core 1 from code flash 1.
30 mA
Flash
4
5
6
IDD_HV_OSC CC Maximum run IDD
fOSC 4 MHz to 40 MHz,
VDD_HV_OSC 3.6 V
—
—
1
2
3
4
2
mA
mA
mA
OSC
IDD_HV_ADV CC Maximum run IDD for VDD_HV_ADV = 3.6 V
each ADC3
IDD_HV_ADR02 CC Maximum reference ADC0 powered on6
—
—
—
—
—
—
—
—
—
—
4
5
IDD
ADC2 powered on
1.2 mA
1.2 mA
1.2 mA
4
7
IDD_HV_ADR13 CC Maximum reference ADC1 powered on
5
IDD
ADC3 powered on
7
8
9
IDD_HV_ADR0 CC Maximum reference ADC0 powered on6
2
mA
IDD
7
IDD_HV_ADR1 CC Maximum reference ADC1 powered on
—
—
1.2 mA
IDD
7
10 IDD_HV_ADR23 CC Maximum reference ADC2 powered on
—
—
—
—
1.2 mA
1.2 mA
5
IDD
ADC3 powered on
NOTES:
1
Applies to TJ = –40 °C to 150 °C.
2
Total current on IDD_LV_PLL needs to be multiplied with the number of active PLLs.
3
Total current on IDD_HV_ADV needs to be multiplied with the number of active ADCs.
4
257 MAPBGA only.
5
Total current on IDD_HV_ADRxx is the sum of both references if both ADCs are powered on.
6
ADC0 includes 0.7 mA dissipation for the temperature sensor (TSENS).
7
473 MAPBGA only.
3.10 Temperature sensor electrical characteristics
Table 20. Temperature sensor electrical characteristics
Symbol
Parameter
Conditions
Min
Max
10
Unit
1
—
P Accuracy
TJ = –40 °C to TA = 125 °C
–10
°C
PXS30 Microcontroller Data Sheet, Rev. 1
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 20. Temperature sensor electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
2
TS
D Minimum sampling period
—
4
—
µs
3.11 Main oscillator electrical characteristics
The PXS30 provides an oscillator/resonator driver.
×
Table 21. Main oscillator electrical characteristics
Value
No.
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
1
2
3
FXOSCHS SR Oscillator frequency
—
4.0
—
—
TBD
—
40.0
TBD
MHz
µs
TXOSCHSSU CC Oscillator start-up time fOSC = 4 MHz to 40 MHz
VIH
SR Input high level CMOS Oscillator bypass mode 0.65 × VDD
VDD + 0.4
V
Schmitt Trigger
4
VIL
SR Input low level CMOS Oscillator bypass mode
–0.4
—
0.35 × VDD
V
Schmitt Trigger
NOTES:
1
VDD = 3.0 V to 3.6 V, TJ = –40 to 150 °C, unless otherwise specified.
3.12 FMPLL electrical characteristics
Table 22. FMPLL electrical characteristics
Symbol
Parameter
Conditions
Crystal reference
Min
Typ
Max Unit
fREF_CRYSTAL D FMPLL reference frequency
fREF_EXT
TBD
TBD
16
—
TBD MHz
range1
fPLL_IN
D Phase detector input frequency
range (after pre-divider)
—
—
TBD MHz
256 MHz
fFMPLLOUT D Clock frequency range in normal See Chapter 30,
—
mode
“Frequency-Modulated
Phase-Locked Loop (FMPLL),” in
the PXS30 Reference Manual
(PXS30RM) for more details on
PLL configuration.
fFREE
P Free running frequency
Measured using clock division
TBD
—
TBD MHz
(typically 16)
fsys
D On-chip FMPLL frequency2
D System clock period
—
TBD
—
—
—
—
—
—
TBD MHz
1 / fsys ns
TBD MHz
TBD
tCYC
—
Lower limit
Upper limit
—
fLORL
fLORH
D Loss of reference frequency
window2
TBD
TBD
TBD
fSCM
D Self-clocked mode frequency3,4
TBD MHz
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79
Electrical characteristics
Symbol
Table 22. FMPLL electrical characteristics (continued)
Parameter
Conditions
Min
Typ
Max Unit
tLOCK
P Lock time
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
—
—
200
µs
tlpll
tdc
D FMPLL lock time 5, 6
—
—
—
—
—
—
TBD
60
s
%
D Duty cycle of reference
40
CJITTER T CLKOUT period jitter7,8,9,10
Peak-to-peak (clock edge to clock TBD
TBD
ps
edge), fSYS maximum
Long-term jitter (avg. over 2 ms
interval), fSYS maximum
TBD
—
—
—
—
—
—
TBD
ns
tPKJIT T Single period jitter (peak to peak) PHI @ 16 MHz,
±500 ps
Input clock @ 4 MHz
tLTJIT
T Long term jitter
PHI @ 16 MHz,
Input clock @ 4 MHz
—
±6
ns
fLCK
D Frequency LOCK range
D Frequency un-LOCK range
D Modulation Depth
—
TBD
TBD
TBD
TBD
%
fsys
fUL
—
%
fsys
fCS
fDS
Center spread
Down Spread
—
TBD
TBD
TBD
—
—
—
TBD
TBD
%
fsys
fMOD
D Modulation frequency11
TBD kHz
NOTES:
1
Considering operation with FMPLL not bypassed.
2
3
4
“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self
clocked mode.
Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls
outside the fLOR window.
fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS = fVCOODF
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this FMPLL, load capacitors should not exceed these limits.
5
6
This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control
bits in the synthesizer control register (SYNCR).
7
8
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
f
SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
9
Proper PC board layout procedures must be followed to achieve specifications.
10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
11 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
PXS30 Microcontroller Data Sheet, Rev. 1
80
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.13 16 MHz RC oscillator electrical characteristics
Table 23. RC oscillator electrical characteristics
No.
Symbol
Parameter
Conditions
Min Typ Max Unit
1
2
fRC
CC RC oscillator frequency
27 °C, 1.2 V trimmed
—
—
16
—
—
MHz
%
RCMVAR CC Frequency spread: The variation in
—
±5
output frequency from PTF1 across
temperature and supply voltage range
3
IRCTRIM CC Internal RC oscillator trimming step
TA = 25 °C
—
1.6
—
%
NOTES:
1
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature.
3.14 ADC electrical characteristics
The PXS30 provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3 V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = ±6 LSB = ±4.84 mV
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 40904091 40924093 40944095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 8. ADC characteristics and error definitions
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
81
Electrical characteristics
3.14.1 Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC
impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can
be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to
attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when
the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple
RC filter). The RC filtering may be limited according to the value of source impedance of the transducer
or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking
into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input
impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling
capacitance: C being substantially a switched capacitance, with a frequency equal to the conversion rate
S
of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz,
with C equal to 3 pF, a resistance of 330 k is obtained (R = 1 / (f C ), where f represents the
S
EQ
C
S
C
conversion rate at the considered channel). To minimize the error induced by the voltage partitioning
between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external
S
S
F
L
SW
AD
circuit must be designed to respect the Equation 9:
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V
-- LSB
Eqn. 9
A
R
EQ
Equation 9 generates a constraint for external network design, in particular on resistive path. Internal
switch resistances (R and R ) can be neglected with respect to external resistances.
SW
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
C
V
C
C
P1
C
S
A
F
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 10. Input equivalent circuit
PXS30 Microcontroller Data Sheet, Rev. 1
82
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances
C , C , and C are initially charged at the source voltage V (please see the equivalent circuit in
F
P1
P2
A
Figure 10): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch is
closed).
Voltage Transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << TS
V
A1
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 11. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance C and C to the sampling
P1
P2
capacitance C occurs (C is supposed initially completely discharged): considering a worst case
S
S
(since the time constant in reality would be faster) in which C is reported in parallel to C (call
P2
P1
C = C + C ), the two capacitances C and C are in series, and the time constant is:
P
P1
P2
P
S
C C
P
S
--------------------
= R
+ R
Eqn. 12
1
SW
AD
C + C
P
S
Equation 12 can again be simplified considering only C as an additional worst condition. In
S
reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in
the very worst case: the sampling time T is always much longer than the internal time constant:
S
R
+ R
C « T
Eqn. 13
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V
P1
P2
S
A1
on the capacitance according to Equation 14:
V
C + C + C = V C + C
P1 P2 P1 P2
Eqn. 14
A1
S
A
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance)
F
through the resistance R : again considering the worst case in which C and C were in parallel
L
P2
S
to C (since the time constant in reality would be faster), the time constant is:
P1
R C + C + C
P1 P2
Eqn. 15
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the
transient is completed well before the end of sampling time T , a constraints on R sizing is
S
L
obtained:
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
83
Electrical characteristics
10 = 10 R C + C + C T
P1 P2 S
Eqn. 16
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination
L
with R (source impedance) and R (filter resistance). Being C definitively bigger than C , C
S
F
F
P1 P2
and C , then the final voltage V (at the end of the charge transfer transient) will be much higher
S
A2
than V . Equation 17 must be respected (charge balance assuming now C already charged at
A1
S
V ):
A1
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
Eqn. 17
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C
F F
filter, is not able to provide the extra charge to compensate the voltage drop on C with respect to the ideal
S
source V ; the time constant R C of the filter is very high with respect to the sampling time (T ). The
A
F F
S
filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (V )
A
T
f
2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
f (Anti-aliasing Filtering Condition)
F
0
2 f f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 18. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the
0
anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at least 2f ; it
F
C
0
means that the constant time of the filter is greater than or at least equal to twice the conversion period
(T ). Again the conversion period T is longer than the sampling time T , which is just a portion of it,
C
C
S
even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific
channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher
F F
than the sampling time T , so the charge level on C cannot be modified by the analog signal source during
S
S
the time in which the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy
error due to the voltage drop on C ; from the two charge balance equations above, it is simple to derive
S
Equation 19 between the ideal and real sampled voltage on C :
S
Eqn. 19
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
PXS30 Microcontroller Data Sheet, Rev. 1
84
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept
A
a maximum error of half a count, a constraint is evident on C value:
F
C
8192 C
Eqn. 20
F
S
Table 24. ADC conversion characteristics
Conditions1
No. Symbol
Parameter
Min Typ Max Unit
1
fCK SR ADC clock frequency (depends on ADC
configuration)
—
3
—
60 MHz
(The duty cycle depends on AD_CK2 frequency)
2
3
4
5
6
7
8
9
fs
SR Sampling frequency
—
—
383
600
—
—
—
—
—
—
959 kHz
tADC_S D Sample time3
60 MHz
TBD
—
—
ns
ns
tADC_E P Evaluation time4
5
CS
D ADC input sampling capacitance
—
—
—
7.32 pF
2.5 pF
5
5
CP1
CP2
D ADC input pin capacitance 1
D ADC input pin capacitance 2
—
—
— TBD pF
5
RSW1 D Channel selection switch resistance
VREF range = 4.5 to 5.5 V
VREF range = 3.0 to 3.6 V
—
—
—
—
—
—
1.0 k
1.2 k
—
5
10 RAD
11
D Sample switching resistance
T Current injection
—
825
3
IINJ
Currentinjection on one ADC –3
input channel, different from
the converted one. Other
parameters stay within
mA
specified limits as long as the
ADC supply stays within its
specified limits due to the
current injection.
12
INL
P Integral non linearity
—
—
—
—
—
—
—
—
—
—
–3
–1.0
–4
—
—
—
—
—
3
LSB
13 DNL P Differential non linearity6
1.0 LSB
14 OFS T Offset error
4
4
6
LSB
LSB
LSB
15 GNE T Gain error
–4
16 TUE P Total unadjusted error
17 TUE T Total unadjusted error with current injection
18 SNR T Signal-to-noise ratio
19 THD T Total harmonic distortion
20 SINAD T Signal-to-noise and distortion
21 ENOB T Effective number of bits
–6
TBD — TBD LSB
69
TBD
65
—
—
—
—
—
—
—
—
dB
dB
dB
bits
10.5
NOTES:
1
VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF
.
2
AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
85
Electrical characteristics
3
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of
the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC_S depend on programming.
4
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time
to load the result register with the conversion result.
5
See Figure 10.
6
No missing codes.
PXS30 Microcontroller Data Sheet, Rev. 1
86
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.15 Flash memory electrical characteristics
3.15.1 Program/Erase characteristics
Table 25 shows the Code flash memory program and erase characteristics.
Table 25. Code flash program and erase electrical specifications
Initial Lifetime
No.
Symbol
Parameter
Min Typ1
Unit
Max2
Max3
1
3
4
5
6
TDWPROGRAM CC Double Word (64 bits) program time4
—
—
—
—
—
18
50
500
µs
ms
ms
ms
ms
T16KPPERASE
T32KPPERASE
T64KPPERASE
CC 16 KB block pre-program and erase time
CC 32 KB block pre-program and erase time
CC 64 KB block pre-program and erase time
200
300
400
500
600
900
5000
5000
5000
7500
T128KPPERASE CC 128 KB block pre-program and erase time
600 1300
NOTES:
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100
program/erase cycles, nominal supply values and operation at TJ = 25 °C. These values are verified at production
test.
3
4
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life.
These values are characterized, but not tested.
Actual hardware programming times. This does not include software overhead.
Table 26 shows the Data flash memory program and erase characteristics.
Table 26. Data flash program and erase electrical specifications
Initial Lifetime
No.
Symbol
Parameter
Min Typ1
Unit
Max2
Max3
1
3
TDWPROGRAM CC Double Word (64 bits) program time4
T16KPPERASE CC 16 KB block pre-program and erase time
—
—
30
70
300
µs
700
800
1500
ms
NOTES:
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100
program/erase cycles, nominal supply values and operation at TJ = 25 °C. These values are verified at production
test.
3
4
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life.
These values are characterized, but not tested.
Actual hardware programming times. This does not include software overhead.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
87
Electrical characteristics
Table 27. Flash module life
Value
No.
Symbol
Parameter
Condition
Unit
Min
Typ1
Max
1a
1b
1c
2
P/E
CC Number of program/erase
cycles per block for over the
operating temperature range
(TJ)
16 KB blocks
100,000
—
—
—
—
—
cycles
cycles
cycles
years
32 KB and 64 KB blocks
128 KB blocks
10,000 100,000
1,000 100,000
Retention CC Minimum data retention at
85 °C average ambient
Blocks with 0–1,000
P/E cycles
20
10
5
—
—
—
temperature2
Blocks with 1,001–10,000
P/E cycles
—
—
years
years
Blocks with 10,001–100,000
P/E cycles
NOTES:
1
Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For
additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619,
Typical Endurance for Nonvolatile Memory.
2
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
3.15.2 Read access timing
Table 28. Code flash read access timing
Value
Max
No.
Symbol
Parameter
Condition
Unit
2
3
fREAD
CC Maximum frequency for Flash reading
4 wait states
3 wait states
90
60
MHz
MHz
(system clock frequency SYS_CLK)
Table 29. Data flash read access timing
Value
Max
No.
Symbol
Parameter
Condition
Unit
2
3
fREAD
CC Maximum frequency for Flash reading
12 wait states
8 wait states
90
60
MHz
MHz
(system clock frequency SYS_CLK)
3.15.3 Write access timing
Table 30. Code flash write access timing
Value
Max
No.
Symbol
Parameter
Condition
Unit
2
3
fWRITE
CC Maximum frequency for Flash writing
TBD
TBD
90
60
MHz
MHz
(system clock frequency SYS_CLK)
PXS30 Microcontroller Data Sheet, Rev. 1
88
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 31. Data flash write access timing
Value
Unit
No.
Symbol
Parameter
Condition
Max
2
3
fWRITE
CC Maximum frequency for Flash writing
TBD
TBD
90
60
MHz
MHz
(system clock frequency SYS_CLK)
3.16 SRAM memory electrical characteristics
3.16.1 Read access timing
Table 32. System SRAM memory read access timing
Value
Max
No.
Symbol
Parameter
Condition
Unit
2
3
sREAD
CC Maximum frequency for system SRAM
reading (system clock frequency
SYS_CLK)
1 wait state
1 wait state
90
60
MHz
MHz
3.16.2 Write access timing
Table 33. System SRAM memory write access timing
Value
Max
No.
Symbol
Parameter
Condition
Unit
2
3
sWRITE CC Maximum frequency for system SRAM
writing (system clock frequency
SYS_CLK)
TBD
TBD
90
60
MHz
MHz
3.17 GP pads specifications
This section specifies the electrical characteristics of the GP pads. Please refer to the tables in Section 2.2,
Pin descriptions,” for a cross reference between package pins and pad types.
3.17.1 GP pads DC specifications
Table 34 gives the DC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V).
DD_HV_IO
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
89
Electrical characteristics
1,2
Table 34. GP pads DC electrical characteristics
No.
Symbol
Parameter
Conditions
Min
–0.13
Max
Unit
1
2
3
4
5
6
7
8
9
VIL
VIH
SR Low level input voltage
SR High level input voltage
CC Schmitt trigger hysteresis
—
0.35 VDD_HV_IO
V
V
—
—
0.65 VDD_HV_IO VDD_HV_IO + 0.13
VHYS
0.1 VDD_HV_IO
—
—
0.5
—
V
VOL_S CC Slow, low level output voltage
VOH_S CC Slow, high level output voltage
VOL_M CC Medium, low level output voltage
VOH_M CC Medium, high level output voltage
VOL_F CC Fast, high level output voltage
VOH_F CC Fast, high level output voltage
IOL = 1.5 mA
V
IOH = –1.5 mA VDD_HV_IO – 0.8
IOL = 2 mA
IOH = –2 mA VDD_HV_IO – 0.8
IOL = 11 mA
IOH = –11 mA VDD_HV_IO – 0.8
IOL = 5 mA
IOH = –5 mA VDD_HV_IO – 0.8
V
—
0.5
—
V
V
—
0.5
—
V
V
10 VOL_SYM CC Symmetric, high level output voltage
11 VOH_SYM CC Symmetric, high level output voltage
—
0.5
—
V
V
12
IPU
CC Equivalent pull-up current
VIN = VIL
IN = VIH
–130
—
—
µA
V
–10
—
13
IPD
CC Equivalent pull-down current
VIN = VIL
VIN = VIH
10
µA
—
130
1
14
15
IIL
IIL
CC Input leakage current
TA = –40 to
125 °C
—
µA
µA
(all bidirectional ports)
CC Input leakage current
TA = –40 to
125 °C
—
0.5
(all ADC input-only ports)
16
17
VILR
VIHR
SR RESET, low level input voltage
SR RESET, high level input voltage
—
—
–0.43
0.35 VDD_HV_IO
V
V
0.65 VDD_HV_IO VDD_HV_IO+0.43
18 VHYSR CC RESET, Schmitt trigger hysteresis
—
0.1 VDD_HV_IO
—
0.5
—
V
19
20
VOLR
IPD
CC RESET, low level output voltage
IOL = 2 mA
VIN = VIL
—
10
—
V
CC RESET, equivalent pull-down current
µA
V
IN = VIH
130
NOTES:
1
These specifications are design targets and subject to change per device characterization.
The values provided in this table are not applicable for PDI and EBI/DRAM interface.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 11.
2
3
PXS30 Microcontroller Data Sheet, Rev. 1
90
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.17.2 GP pads AC specifications
1
Table 35. GP pads AC electrical characteristics
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
3
3
3
3
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
40
15
15
15
15
6
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
50
75
100
12
25
40
70
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
0.01
0.01
0.01
0.01
2.5
2.5
2.5
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
25
50
2
10
14
2
2
2
100
200
25
2
2
2
3
Medium
40
20
13
7
7
4
7
50
8
7
100
200
25
14
1
7
Fast
72
55
40
25
50
—
40
40
40
40
25
—
6
1.5
3
7
7
50
6
12
18
5
7
100
200
25
6
5
7
4
5
Symmetric
8
1
3
Pull Up/Down
(3.6 V max)
—
—
7500
—
50
NOTES:
1
The values provided in this table are not applicable for PDI and EBI/DRAM interface.
2
3
Slope at rising/falling edge.
Data based on characterization results, not tested in production.
3.18 PDI pads specifications
This section specifies the electrical characteristics of the PDI pads. Please refer to the tables in Section 2.2,
Pin descriptions,” for a cross reference between package pins and pad types.
PDI pads feature list:
•
•
Direction
— Input
— Output
— Bidirectional
Driver
— Push/Pull/Open Drain
— Configurable Four Drive Strengths on Fast driver pads
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
91
Electrical characteristics
— Configurable No Slew-Rate, Slow Slew-Rate, and Fast Slew-Rate on Slow, Medium, and SLR
driver pads
— VDD_HV_PDI NOTE: All pads are NOT 5 V TOLERANT. Pads are not capable of driving to
or from voltages above their respective VDD_HV_PDI. In other words, you cannot connect a
3.3V external device to a pad supplied with 2.5 V. If a pad must be connected to a 3.3V device,
its local VDD_HV_PDI must be 3.3 V. Injection current is then handled by the intrinsic diodes
from the pad transistors and by the ESD diodes.
— VDD_HV_PDI range
– 1.8 V nominal
– 2.5 V nominal
– 3.3 V nominal
•
Receiver
— Selectable hysteresis Input Buffer.
— CMOS Input Buffer
The electrical data provided in Section 3.18, PDI pads specifications,” applies to the pads listed in
Table 36.
Table 36. PDI I/O pads
No.
Name
Volt.
Used For
Notes
1
PDI Fast 1.62 V-3.6 V
I/O
Enhanced operating voltage range fast slew-rate output with four selectable
slew-rates. Contains an input buffer and weak pullup/pulldown.
2
PDI
Medium
1.62 V-3.6 V
I/O
Enhanced operating voltage range medium slew-rate output with four
selectable slew-rates. Contains an input buffer and weak pullup/pulldown.
3.18.1 PDI pads electrical specifications (VDD_HV_PDI = 3.3 V)
Table 37. PDI pads DC electrical characteristics (V
= 3.3 V)
DD_HV_PDI
No.
Symbol
Parameter
Min
Max
Unit
1
2
VDD_HV_PDI SR I/O supply voltage
3.0
3.6
V
V
VIH_C
VIH_C
VIL_C
VIL_C
CC CMOS input buffer high voltage
0.65 × VDD_HV_PDI VDD_HV_PDI + 0.3
(hysteresis enabled)
3
4
5
CC CMOS input buffer high voltage
0.51 × VDD_HV_PDI VDD_HV_PDI + 0.3
V
V
V
(hysteresis disabled)
CC CMOS input buffer low voltage
VSS – 0.3
VSS – 0.3
0.35 × VDD_HV_PDI
0.42 × VDD_HV_PDI
(hysteresis enabled)
CC CMOS input buffer low voltage
(hysteresis disabled)
6
7
VHYS_C CC CMOS input buffer hysteresis
0.1 × VDD_HV_PDI
V
µA
V
IACT_S
VOH
CC Selectable weak pullup/pulldown current3
25
0.8 × VDD_HV_PDI
—
150
—
9
CC Output high voltage
10
VOL
CC Output low voltage
0.2 × VDD_HV_PDI
V
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
92
Freescale Semiconductor
Electrical characteristics
Table 38. Drive Current, V
= 3.3 V (±10%)
DD_HV_PDI
Pad
Drive Mode
All
All
Minimum IOH (mA)1
84.4
61.9
Minimum IOL (mA)2
PDI Fast
137
PDI Medium
83.6
NOTES:
1
IOH is defined as the current sourced by the pad to drive the output to VOH
.
2
IOL is defined as the current sunk by the pad to drive the output to VOL
.
Table 39. PDI pads AC electrical characteristics (V
= 3.3 V)
DD_HV_PDI
Prop. Delay (ns)
Rise/Fall Edge
(ns)
Drive/Slew
Rate Select
L H/H L1
Drive Load
(pF)
No.
Name
Min
Max
Min
Max
MSB, LSB
1
PDI Medium
—
4.0/4.5
7.3/8.3
24/22
33/31
49/44
60/53
332/302
362/325
5/5
—
1.02/1.4
3.5/4.2
9.1/10.3
14/15
18/21
24/25
126/151
136/158
1.1/1.1
2.6/2.6
2.4/2.4
5/5
50
200
50
11
10
01
00
11
10
01
00
200
50
200
50
200
50
2
PDI Fast
—
—
8/8
200
50
8/8
12/12
13/13
19/19
40/40
50/50
200
50
5/5
8/8
200
50
16/16
21/21
200
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.18.2 PDI pads electrical specifications (VDD_HV_PDI = 2.5 V)
Table 40. PDI pads DC electrical specifications (V
= 2.5 V)
DD_HV_PDI
Min
No.
Symbol
VDD_HV_PDI SR I/O supply voltage
VIH_C CC CMOS input buffer high voltage (hysteresis
Parameter
Max
Unit
1
2
2.3
2.7
V
0.65 × VDD_HV_PDI VDD_HV_PDI + 0.3
V
enabled)
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
93
Electrical characteristics
Table 40. PDI pads DC electrical specifications (V
= 2.5 V) (continued)
DD_HV_PDI
No.
Symbol
Parameter
Min
Max
Unit
3
VIH_C
CC CMOS input buffer high voltage (hysteresis
0.54 × VDD_HV_PDI VDD_HV_PDI + 0.3
V
disabled)
4
5
VIL_C
VIL_C
CC CMOS input buffer low voltage (hysteresis
Vss – 0.3
Vss – 0.3
0.35 × VDD_HV_PDI
0.42 × VDD_HV_PDI
V
V
enabled)
CC CMOS input buffer low voltage (hysteresis
disabled)
6
7
VHYS_C CC CMOS input buffer hysteresis
0.1 × VDD_HV_PDI
V
µA
V
IACT_S
VOH
CC Selectable weak pullup/pulldown current1
25
0.8 × VDD_HV_PDI
—
150
—
9
CC Output high voltage
10
VOL
CC Output low voltage
0.2 × VDD_HV_PDI
V
Table 41. Drive Current @ V
= 2.5 V (±10%)
DD_HV_PDI
Pad
Drive Mode
All
All
Minimum IOH (mA)1
51.5
52.6
Minimum IOL (mA)2
PDI Fast
111
PDI Medium
78.1
NOTES:
1
IOH is defined as the current sourced by the pad to drive the output to VOH
.
2
IOL is defined as the current sunk by the pad to drive the output to VOL. PDI
Table 42. PDI pads AC electrical specifications (V
= 2.5 V)
DD_HV_PDI
Prop. Delay (ns)
Drive/Slew
Rate Select
Rise/Fall Edge (ns)
L H/H L1
Drive Load
(pF)
No.
Name
Min
Max
Min
Max
MSB, LSB
1
PDI Medium
0.8/0.7
--------
1.1/1.08
4.5/4
9/7
1.3/1
4.8/3.2
10.5/7.9
16.3/12
21/16
—
50
200
50
11
34/19
44/26
70/38
83/45
491/254
528/279
10
01
00
200
50
28/20
200
50
142/115
154/122
200
PXS30 Microcontroller Data Sheet, Rev. 1
94
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
= 2.5 V) (continued)
Table 42. PDI pads AC electrical specifications (V
DD_HV_PDI
Prop. Delay (ns)
Drive/Slew
Rate Select
Rise/Fall Edge (ns)
L H/H L1
Drive Load
(pF)
No.
Name
Min
Max
Min
Max
MSB, LSB
2
PDI Fast
0.8/0.7
--------
1.1/1.08
5/5
8.4/8.4
8.6/8.6
14/14
1.5/1.5
3.5/3.5
3/3
—
50
200
50
11
10
01
00
5.6/5.6
5.7/5.7
9.5/9.5
19/19
25/25
200
50
15.5/15.5
22/22
200
50
48/48
60/60
200
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.18.3 PDI pads electrical specifications (VDD_HV_PDI = 1.8 V)
Table 43. PDI pads DC electrical specifications (V
= 1.8 V)
DD_HV_PDI
Min
No.
Symbol
Parameter
Max
Unit
1
2
VDD_HV_PDI SR I/O supply voltage
1.62
1.98
V
VIH_C
VIH_C
VIL_C
VIL_C
CC CMOS input buffer high voltage
0.65 × VDD_HV_PDI VDD_HV_PDI + 0.3
V
V
V
V
(hysteresis enabled)
3
4
5
CC CMOS input buffer high voltage
0.58 × VDD_HV_PDI VDD_HV_PDI + 0.3
(hysteresis disabled)
CC CMOS input buffer low voltage
Vss – 0.3
Vss – 0.3
0.35 × VDD_HV_PDI
0.44 × VDD_HV_PDI
(hysteresis enabled)
CC CMOS input buffer low voltage
(hysteresis disabled)
6
7
VHYS_C CC CMOS input buffer hysteresis
0.1 × VDD_HV_PDI
—
V
µA
V
IACT_S
VOH
CC Selectable weak pullup/pulldown current1
25
0.8 × VDD_HV_PDI
—
150
—
9
CC Output high voltage
10
VOL
CC Output low voltage
0.2 × VDD_HV_PDI
V
Table 44. Drive current @ VDD_HV_PDI = 1.8 V (±10%)
Pad
Drive Mode
Minimum IOH (mA)1
Minimum IOL (mA)2
84.8
52.1
PDI Fast
All
All
26.2
19.2
PDI Medium
NOTES:
1
IOH is defined as the current sourced by the pad to drive the output to VOH
.
2
IOL is defined as the current sunk by the pad to drive the output to VOL
.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
95
Electrical characteristics
Table 45. PDI pads AC electrical specifications (V
= 1.8 V)
DD_HV_PDI
Prop. Delay (ns)
Rise/Fall Edge
(ns)
Drive/Slew
Rate Select
L H/H L1
Drive Load
(pF)
No.
Name
Min
Max
Min
Max
MSB, LSB
1
PDI Medium
—
5.5/3.5
12/5.5
49/17
2/1
—
50
200
50
11
7.2/2.3
13/6
10
01
00
11
10
01
00
60/23
21/9.2
26/12
35/16
172/85
191/90
2/2
200
50
102/32
119/39
722/216
772/237
10/10
200
50
200
50
2
PDI Fast
—
—
15/15
6.2/6.2
4.5/4.5
7.1/7.1
7.5/7.5
12/12
24/24
31/31
200
50
15/15
22/22
200
50
24/24
33/33
200
50
66/66
84/84
200
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.19 DRAM pad specifications
This section specifies the electrical characteristics of the DRAM pads. Please refer to the tables in
Section 2.2, Pin descriptions,” for a cross reference between package pins and pad types.
DRAM pads feature list:
•
Driver
— Configurable to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half
strength, DDR2 full strength, and SDR modes.
— VDD_HV_DRAM Range of
– 1.8 V nominal
– 2.5 V nominal
– 3.3 V nominal
•
Receiver
— Differential or pseudo-differential input buffer in all DRAM pads
PXS30 Microcontroller Data Sheet, Rev. 1
96
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
— All inputs are tolerant up to their VDD_HV_DRAM Absolute Maximum Rating
— Data and strobe pads can be configured to support four signal termination options
– Infinite/no termination
– 50 Ohms
– 75 Ohms
– 150 Ohms
The electrical data provided in Section 3.19, DRAM pad specifications,” applies to the pads listed in
Table 46.
Table 46. DRAM pads
Name
Voltage
Used For
Notes1
DRAM ACC 1.62 V–3.6 V
DRAM CLK 1.62 V–3.6 V
DRAM DQ 1.62 V–3.6 V
I/O
O
Bidirectional DDR pad
Output only differential clock driver pad
Bidirectional DDR pad with integrated ODT
I/O
NOTES:
1
All pads can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half
strength, DDR2 full strength, and SDR.
All three pad types can be configured to support SDR, DDR, DDR2 half and full strength, and LPDDR
half and full strength modes, according to Table 47.
Table 47. Mode configuration for DRAM pads
Configuration1
Mode
000
001
010
011
100
101
110
111
1.8 V LPDDR Half Strength
1.8 V LPDDR Full Strength
1.8 V DDR2 Half Strength
2.5 V DDR
Not supported
Not supported
1.8 V DDR2 Full Strength
SDR
NOTES:
1
Configuration is selected in the corresponding PCR registers of the SIUL.
3.19.1 DRAM pads electrical specifications (V
= 3.3 V)
= 3.3 V)
Max
DD_HV_DRAM
Table 48. DRAM pads DC electrical specifications (V
DD_HV_DRAM
No.
Symbol
Parameter
Condition
Min
Unit
1
2
VDD_HV_DRAM SR I/O supply voltage
—
—
3.0
1.3
3.6
1.7
V
V
V
CC Input reference
DD_HV_DRAM_VREF
voltage
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
97
Electrical characteristics
Table 48. DRAM pads DC electrical specifications (V
(continued) = 3.3 V)
DD_HV_DRAM
No.
Symbol
Parameter
Condition
Min
Max
Unit
3
V
CC Termination voltage1
—
VDD_HV_DRAM_VREF
× 0.05
VDD_HV_DRAM_VREF
+ 0.05
V
DD_HV_DRAM_VTT
4
5
6
VIH
VIL
CC Input high voltage
CC Input low voltage
CC Output high voltage
—
—
VDD_HV_DRAM_VREF
0.20
+
—
V
V
V
V
V
V
VDD_HV_DRAM_VREF
× 0.2
VOH
ODT
VDD_HV_DRAM_VTT
+ 0.8
—
enabled2
ODT
0.8 × VDD_HV_DRAM
—
disabled3
7
VOL
CC Output low voltage
ODT
—
—
VDD_HV_DRAM_VTT
× 0.8
enabled2
ODT
VDD_HV_DRAM
× 0.2
disabled3
NOTES:
1
BGA473: Termination voltage can be supplied via package pins. BGA257 Termination voltage internally tied as the
BGA257 does not provide DRAM interface. Disable ODT
2
3
Termination voltage is supplied by VDD_HV_DRAM_VTT
.
Tie VDD_HV_DRAM_VTT to VSS and disable ODT
Table 49. Output drive current @ V
= 3.3 V (±10%)
DDE
1
2
No.
Pad Name
Drive Mode
Minimum I (mA)
Minimum I (mA)
OH
OL
1
2
3
DRAM ACC
DRAM DQ
DRAM CLK
111
–16
16
NOTES:
1
IOH is defined as the current sourced by the pad to drive the output to VOH
.
2
IOL is defined as the current sunk by the pad to drive the output to VOL
.
Table 50. DRAM pads AC electrical specifications (V
= 3.3 V)
DD_HV_DRAM
Prop. Delay (ns)
Output Slew rate
Rise/Fall (V/ns)
Drive/Slew
Rate Select
L H/H L1
Drive Load
(pF)
No.
1
Pad Name
DRAM ACC
DRAM DQ
DRAM CLK
Min
Max
Min
Max
MSB, LSB
1.4/1.4
1.7/1.7
1.4/1.4
1.7/1.7
1.4/1.4
1.6/1.6
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.4/2.4
2.6/2.6
3.1/2.5
0.9/1.1
3.1/2.5
0.9/1.1
3.1/2.5
1.1/1.3
5.6/5.4
1.7/2.0
5.6/5.4
1.7/2.0
5.7/5.7
2.3/2.3
5
20
5
111
111
111
111
111
111
2
20
5
3
20
PXS30 Microcontroller Data Sheet, Rev. 1
98
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.19.2 DRAM pads electrical specification (V
= 2.5 V)
DD_HV_DRAM
Table 51. DRAM pads DC electrical specifications (V
= 2.5 V)
DD_HV_DRAM
Symbol
Parameter
Condition
Min
Max
Unit
No.
1
2
3
VDD_HV_DRAM
SR I/O supply voltage
—
—
—
2.3
2.7
V
V
V
VDD_HV_DRAM_VREF CC Input reference voltage
VDD_HV_DRAM_VTT CC Termination voltage1
0.49 × V
0.51 × V
DD_HV_DRAM
DD_HV_DRAM
VDD_HV_DRAM_VREF VDD_HV_DRAM_VREF
- 0.04
+ 0.04
4
5
6
VIH
VIL
CC Input high voltage
CC Input low voltage
CC Output high voltage
—
—
VDD_HV_DRAM_VREF
+ 0.15
—
V
V
V
V
V
V
—
VDD_HV_DRAM_VREF
– 0.15
VOH
ODT
VDD_HV_DRAM_VTT
+ 0.81
—
enabled2
ODT
0.8 × VDD_HV_DRAM
—
disabled3
7
VOL
CC Output low voltage
ODT
—
—
VDD_HV_DRAM_VTT
– 0.81
enabled2
ODT
0.2 × VDD_HV_DRAM
disabled3
NOTES:
1
473 MAPBGA: Termination voltage can be supplied via package pins. 257 MAPBGA Termination voltage internally
tied as the 257 MAPBGA does not provide DRAM interface. Disable ODT
2
3
Termination voltage is supplied by VDD_HV_DRAM_VTT.
Tie VDD_HV_DRAM_VTT to VSS and disable ODT
Table 52. Output drive current @ V
= 2.5 V (±200 mV)
DDE
Pad Name
Drive Mode
Minimum IOH (mA)1
Minimum IOL (mA)2
DRAM ACC
DRAM DQ
DRAM CLK
011
011
011
–16.2
16.2
NOTES:
1
2
IOH is defined as the current sourced by the pad to drive the output to VOH
.
IOL is defined as the current sunk by the pad to drive the output to VOL
.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
99
Electrical characteristics
Table 53. DRAM pads AC electrical specifications (V
= 2.5 V)
DD_HV_DRAM
Prop. Delay (ns)
Drive/Slew
Rate Select
Rise/Fall Edge (ns)
Drive
Load
(pF)
L H/H L1
No.
1
Pad Name
DRAM ACC
DRAM DQ
DRAM CLK
Min
Max
Min
Max
MSB, LSB
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.4
1.6/1.6
2.5/2.4
2.8/2.7
2.5/2.4
2.8/2.7
2.4/2.4
2.7/2.7
2.1/2.1
0.6/0.7
2.1/2.1
0.6/0.7
2.1/2.1
0.6/0.7
4.3/4.1
1.1/1.3
4.3/4.1
1.1/1.3
4.4/4.1
1.6/1.8
5
20
5
011
2
011
011
20
5
3
20
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.19.3 DRAM pads electrical specification (V
= 1.8 V)
DD_HV_DRAM
Table 54. DRAM pads DC electrical specifications (V
= 1.8 V)
DD_HV_DRAM
No.
Symbol
Parameter
Condition
Min
Max
Unit
1
2
3
VDD_HV_DRAM
SR I/O supply voltage
—
—
—
1.7
1.9
V
V
VDD_HV_DRAM_VREF CC Input reference voltage
VDD_HV_DRAM_VTT CC Termination voltage1
0.49 × V
0.51 × V
DD_HV_DRAM
DD_HV_DRAM
VDD_HV_DRAM_VREF VDD_HV_DRAM_VREF
V
V
V
V
V
V
V
– 0.04
+ 0.04
4
5
6
VIH
VIL
CC Input high voltage
CC Input low voltage
CC Output high voltage
—
—
VDD_HV_DRAM_VREF
+ 0.125
—
—
VDD_HV_DRAM_VREF
– 0.125
VOH
ODT
VDD_HV_DRAM_VTT
+ 0.81
—
enabled2
ODT
0.8 × VDD_HV_DRAM
—
disabled3
7
VOL
CC Output low voltage
ODT
—
—
VDD_HV_DRAM_VTT
– 0.81
enabled2
ODT
0.2 × VDD_HV_DRAM
disabled3
NOTES:
1
BGA473: Termination voltage can be supplied via package pins. BGA257 Termination voltage internally tied as the
BGA257 does not provide DRAM interface. Disable ODT
2
3
Termination voltage is supplied by VDD_HV_DRAM_VTT.
Tie VDD_HV_DRAM_VTT to VSS and disable ODT
PXS30 Microcontroller Data Sheet, Rev. 1
100
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 55. Output drive current @ V
= 1.8 V (±100 mV)
DDE
No.
Pad Name
Drive Mode
Minimum IOH (mA)1
Minimum IOL (mA)2
1
DRAM ACC
000
001
010
110
000
001
010
110
000
001
010
110
–3.57
–7.84
–5.36
–13.4
–3.57
–7.84
–5.36
–13.4
–3.57
–7.84
–5.36
–13.4
3.57
7.84
5.36
13.4
3.57
7.84
5.36
13.4
3.57
7.84
5.36
13.4
2
3
DRAM DQ
DRAM CLK
NOTES:
1
IOH is defined as the current sourced by the pad to drive the output to VOH
.
2
IOL is defined as the current sunk by the pad to drive the output to VOL
.
Table 56. DRAM pads AC electrical specifications (V
= 1.8 V)
DD_HV_DRAM
Prop. Delay (ns)
Rise/Fall Edge
(ns)
Drive/Slew
Rate Select
L H/H L1
Drive Load
(pF)
No.
Pad Name
Min
Max
Min
Max
MSB, LSB
1
DRAM ACC
1.4/1.4
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.8
2.4/2.4
2.8/2.7
2.4/2.5
2.8/2.8
2.4/2.4
2.8/2.7
2.5/2.5
2.8/2.8
0.6/1.0
0.2/0.4
1.1/1.1
0.4/0.4
1.0/1.1
0.3/0.4
1.5/1.1
0.4/0.4
2.7/2.6
0.5/0.6
3.0/2.7
0.7/0.7
2.9/2.7
0.6/0.7
3.1/2.6
0.7/0.6
5
20
5
000
001
010
110
20
5
20
5
20
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
101
Electrical characteristics
Table 56. DRAM pads AC electrical specifications (V
(continued) = 1.8 V)
DD_HV_DRAM
Prop. Delay (ns)
Rise/Fall Edge
(ns)
Drive/Slew
Rate Select
L H/H L1
Drive Load
(pF)
No.
Pad Name
Min
Max
Min
Max
MSB, LSB
2
DRAM DQ
1.4/1.4
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.8
1.4/1.4
1.6/1.6
1.4/1.4
1.7/1.7
1.4/1.4
1.6/1.6
1.4/1.4
1.7/1.7
2.4/2.4
2.8/2.7
2.4/2.5
2.8/2.8
2.4/2.4
2.8/2.7
2.5/2.5
2.8/2.8
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.5/2.5
2.7/2.7
0.6/1.0
0.2/0.4
1.1/1.1
0.4/0.4
1.0/1.1
0.3/0.4
1.5/1.1
0.4/0.4
0.4/0.6
0.7/0.9
1.1/1.1
0.3/0.4
0.9/1.1
0.3/0.4
1.5/1.2
0.4/0.4
2.7/2.6
0.5/0.6
3.0/2.7
0.7/0.7
2.9/2.7
0.6/0.7
3.1/2.6
0.7/0.6
2.7/2.7
1.8/3.4
3.0/2.8
1.0/1.1
3.0/2.8
0.9/1.0
3.2/2.6
1.1/1.2
5
20
5
000
001
010
110
000
001
010
110
20
5
20
5
20
5
3
DRAM CLK
20
5
20
5
20
5
20
NOTES:
1
L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay.
3.20 RESET characteristics
3.20.1 RESET pin characteristics
Table 57. RESET pin characteristics
No.
Symbol
WFRST
WNFRST
Parameter
Conditions
Min Max Unit
1
2
SR RESET pulse is sure to be filtered
SR RESET pulse is sure not to be filtered
—
—
—
70
—
ns
ns
400
3.21 Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and
it specifies the start conditions and the end indication for the reset sequences depending on internal or
external VREG mode.
PXS30 Microcontroller Data Sheet, Rev. 1
102
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.21.1 Reset sequence duration
Table 58 specifies the minimum and the maximum reset sequence duration for the five different reset
sequences described in Section 3.21.2, Reset sequence description.”
Table 58. RESET sequences
TReset
No.
Symbol
Parameter
Unit
Min
Typ
Max1
1
2
3
4
5
TDRB
TDR
CC
CC
Destructive Reset Sequence, BIST enabled
Destructive Reset Sequence, BIST disabled
External Reset Sequence Long, BIST enabled
Functional Reset Sequence Long
60
40
60
40
1
65
400
65
70
1000
70
ms
µs
ms
µs
µs
TERLB CC
TFRL
TFRS
CC
CC
300
3
600
10
Functional Reset Sequence Short
NOTES:
1
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of
RESET by an external reset generator.
3.21.2 Reset sequence description
The figures in this section show the internal states of the PXS30 during the five different reset sequences.
The doted lines in the figures indicate the starting point and the end point for which the duration is
specified in Table 58. The start point and end point conditions as well as the reset trigger mapping to the
different reset sequences is specified in Section 3.21.3, Reset sequence trigger mapping.”
With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application
execution starts and the internal reset sequence is finished.
The following figures show the internal states of the PXS30 during the execution of the reset sequence and
the possible states of the RESET signal pin.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be
driven low by an external reset generator or by the PXS30 internal reset
circuitry. A high level on this pin can only be generated by an external pull
up resistor which is strong enough to overdrive the weak internal pull down
resistor. The rising edge on RESET in the following figures indicates the
time when the device stops driving it low. The reset sequence durations
given in Table 58 are applicable only if the internal reset sequence is not
prolonged by an external reset generator keeping RESET asserted low
beyond the last PHASE3.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
103
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Establish
IRC and
PWR
Flash
Init
Flash
Init
Device
Config
Self
Device
Config
Application
Execution
MBIST
LBIST
Test
Setup
TDRB, min < TRESET < TDRB, max
Figure 21. Destructive reset sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
DRUN
Establish
IRC and
PWR
Flash
Init
Device
Config
Application
Execution
TDR, min < TRESET < TDR, max
Figure 22. Destructive reset sequence, BIST disabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Flash
Init
Flash
Init
Device
Config
Self
Test
Setup
Device
Config
Application
Execution
MBIST
LBIST
TERLB, min < TRESET < TERLB, max
Figure 23. External reset sequence long, BIST enabled
PXS30 Microcontroller Data Sheet, Rev. 1
104
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
DRUN
Flash
Init
Device
Config
Application
Execution
TFRL, min < TRESET < TFRL, max
Figure 24. Functional reset sequence long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TRESET < TFRS, max
Figure 25. Functional reset sequence short
The reset sequences shown in Figure 24 and Figure 25 are triggered by functional reset events. RESET is
driven low during these two reset sequences only if the corresponding functional reset source (which
triggered the reset sequence) was enabled to drive RESET low for the duration of the internal reset
sequence. See the RGM_FBRE register in the PXS30 Reference Manual (PXS30RM) for more
information.
3.21.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences, depending on the
VREG mode (external or internal). It specifies the reset sequence start conditions as well as the reset
sequence end indications that are the basis for the timing data provided in Table 58.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
105
Electrical characteristics
Table 59. Reset sequence trigger—reset sequence
Reset Sequence
Reset
Sequence Sequence
Start End
Condition Indication
Reset
Destructive
Reset
Destructive
Reset
External
Reset
Sequence
Long,
Functional
Reset
Sequence
Long
Functional
Reset
Sequence
Short
Reset
Sequence
Trigger
Sequence,
BIST
Sequence,
BIST
2
2
enabled
disabled
BIST
enabled
All active
internal
I
Section 3.
21.4.1,
Release of
RESET
triggers
cannot
trigger
cannot
trigger
cannot
trigger
3
destructive
reset sources
(LVDs or
Internal
VREG
mode
”
internal HVD
during
power-upand
during
E
Section 3.
21.4.2,
External
VREG
cannot
trigger
cannot
trigger
cannot
trigger
operation)
mode
”
Assertion of
RESET_SUP4
Assertion of
RESET5
I/E
I/E
I/E
Section 3.
21.4.3,
external
Reset via
cannot trigger
cannot trigger
cannot trigger
triggers6
triggers7
triggers
triggers8
RESET
”
All internal
functional
resetsources
configured
for long reset
Sequence
starts with
internal
reset
Release of
RESET
cannot
trigger
cannot
trigger
9
trigger
All internal
functional
resetsources
configured
for short
cannot
trigger
cannot
trigger
triggers
reset
NOTES:
1
VREG Mode: I = Internal VREG Mode, E = External VREG Mode.
2
3
Whether BIST is executed or not depends on device configuration data stored in the shadow sector of the NVM.
End of the internal reset sequence (as specified in Table 58) can only be observed by release of RESET if it is not held low
externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 until RESET is released
externally.
4
5
In external VREG mode only.
The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
6
If RESET is configured for long reset (default) and if BIST is enabled via device configuration data stored in the
shadow sector of the NVM.
PXS30 Microcontroller Data Sheet, Rev. 1
106
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
If RESET is configured for long reset (default) and if BIST is disabled via device configuration data stored in the
7
shadow sector of the NVM.
8
9
If RESET is configured for short reset.
Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the functional
reset source which triggered the reset sequence.
3.21.4 Reset sequence—start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming
important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset
sequence duration.
3.21.4.1 Internal VREG mode
Figure 26 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST
enabled and the start for the Destructive Reset Sequence, BIST disabled. The last voltage rail crossing the
levels shown in Figure 26 determines the start of the reset times specified in Table 58.
Supply Rail
V
V
max
V
min
T
starts here
Reset, max
t
T
starts here
Reset, min
Figure 26. Reset sequence start in internal VREG mode
Table 60. Voltage thresholds
Variable name
Value
Vmin
Vmax
LvdReg – 3.5%
LvdReg + 3.5%
Supply Rail
VDD_HV_PMU
VDD_HV_IO
VDD_HV_FLASH
VDD_HV_ADV
3.21.4.2 External VREG mode
Figure 27 and Figure 28 show the voltage thresholds that determine the start of the Destructive Reset
Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.
NOTE
RESET_SUP must not be released unless V
range of operation.
is within its valid
DD_LV_xxx
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
107
Electrical characteristics
VDD_HV_PMU
VDD_HV_IO
V
VDD_HV_FLASH
VDD_HV_ADV
t
V
RESET_SUP
0.8 × VDD_HV_IO
0.2 × VDD_HV_IO
T
starts here
Reset, max
t
T
starts here
Reset, min
Figure 27. External VREG mode, RESET_SUP rises after V
are stable
DD_HV_xxx
VDD_HV_PMU
VDD_HV_IO
V
VDD_HV_FLASH
VDD_HV_ADV
LvdReg + 3.5%
LvdReg – 3.5%
t
V
RESET_SUP
T
starts here
Reset, max
t
T
starts here
Reset, min
Figure 28. External VREG mode, RESET_SUP rises with V
DD_HV_xxx
NOTE
In case RESET_SUP has reached a valid high level before V
is
DD_HV_IO
stable, the reset sequence will start as documented in Figure 28 as the
RESET_SUP input circuitry needs a valid V
a high level on RESET_SUP.
rail in order to detect
DD_HV_IO
PXS30 Microcontroller Data Sheet, Rev. 1
108
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.21.4.3 external Reset via RESET
Figure 29 shows the voltage thresholds that determine the start of the reset sequences initiated by the
assertion of RESET as specified in Table 59.
V
RESET_SUP
0.65 × VDD_HV_IO
0.352 × VDD_HV_IO
T
starts here
t
Reset, max
T
starts here
Reset, min
Figure 29. Reset sequence start via RESET assertion
3.21.5 External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.21, Reset
sequence can be used to determine the correct positioning of the trigger window for the external watchdog.
Figure 30 shows the relationships between the minimum and the maximum duration of a given reset
sequence and the position of an external watchdog trigger window.
Watchdog needs to be triggered within this window
T
WDStart, min
External Watchdog window closed
T
WDStart, max
External Watchdog window closed
Watchdog Trigger
Basic Application Init
T
Reset, min
Application Running
Basic Application Init
T
Reset, max
Application Running
Latest
Application
Start
Earliest
Application
Start
Application time required
to prepare watchdog trigger
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 30. Reset sequence—external watchdog trigger window position
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
109
Electrical characteristics
3.22 Peripheral timing characteristics
3.22.1 SDRAM (DDR)
The PXS30 memory controller supports three types of DDR devices:
•
•
•
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR/Mobile-DDR (1.8V I/O supply voltage)
JEDEC standards define the minimum set of requirements for compliant memory devices:
•
•
•
JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006
JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005
JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4,
May 2006
The PXS30 supports the configuration of two output drive strengths for DDR2 and LPDDR:
•
•
Full drive strength
Half drive strength (intended for lighter loads or point-to-point environments)
The PXS30 memory controller supports dynamic on-die termination in the host device and in the DDR2
memory device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the
Section 3.19, DRAM pad specifications.”
3.22.1.1 DDR and DDR2 SDRAM AC timing specifications
Table 61. DDR and DDR2 (DDR2-400) SDRAM timing specifications
At recommended operating conditions with VDD_MEM_IO of 5%
No.
Symbol
Parameter
CC Clock cycle time, CL = x
Min
Max
Unit
1
2
tCK
—
90
MHz
V
VIX-AC
CC MCK AC differential crosspoint voltage1
VDD_MEM_IO
× 0.5 – 0.1
VDD_MEM_IO
× 0.5 + 0.1
3
4
5
8
tCH
tCL
tDQSS
tOS(base)
CC CK HIGH pulse width1, 2
0.47
0.47
0.53
0.53
0.25
tCK
tCK
tCK
ps
CC CK LOW pulse width1, 2
CC Skew between MCK and DQS transitions2, 3
0.25
CC Address and control output setup time relative to
MCK rising edge2, 3
(tCK/2 – 750)
9
tOH(base)
CC Address and control output hold time relative to
MCK rising edge2, 3
(tCK/2 – 750)
—
ps
11
12
tDS1(base)
tDH1(base)
CC DQ and DM output setup time relative to DQS2, 3
CC DQ and DM output hold time relative to DQS2, 3
(tCK/4 – 500)
(tCK/4 – 500)
—
—
ps
ps
PXS30 Microcontroller Data Sheet, Rev. 1
110
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 61. DDR and DDR2 (DDR2-400) SDRAM timing specifications (continued)
At recommended operating conditions with VDD_MEM_IO of 5%
No.
Symbol
Parameter
Min
Max
Unit
14
15
tDQSQ
CC DQS-DQ skew for DQS and associated DQ inputs2 –(tCK/4 – 600) (tCK/4 – 600) ps
tDQSEN
CC DQS window start position related to CAS read
command1, 2, 3, 4, 5
TBD
TBD
ps
NOTES:
1
Measured with clock pin loaded with differential 100 ohm termination resistor.
2
3
4
All transitions measured at mid-supply (VDD_MEM_IO/2).
Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDD_MEM_IO/2.
In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS
should be low.
5
Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.
Figure 31 shows the DDR SDRAM write timing.
tCL
tCH
MCK
DQS
tCK
tDQSS
DQ, DM (out)
tDS
tDH
Figure 31. DDR write timing
Figure 32 and Figure 33 show the DDR SDRAM read timing.
DQS (in)
Any DQ (in)
tDQSQ
tDQSQ
Figure 32. DDR read timing, DQ vs. DQS
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
111
Electrical characteristics
MCK
Command
Address
Read
tOH
tOS
DQS (in)
tDQSEN (min)
tDQSEN
Figure 33. DDR read timing, DQSEN
Figure 34 provides the AC test load for the DDR bus.
VDD_MEM_IO/2
Output
Z0 = 50
RL = 50
Figure 34. DDR AC test load
3.22.2 IEEE 1149.1 (JTAG) interface timing
Table 62. JTAG pin AC electrical characteristics
No.
Symbol
Parameter Conditions
Min Max Unit
100
40 60
1
2
tJCYC
tJDC
D
D
D
D
D
D
D
D
D
D
D
D
D
TCK cycle time 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width (measured at VDDE/2)
TCK rise and fall times (40%–70%)
TMS, TDI data setup time
3
tTCKRISE
—
5
3
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
—
—
20
—
20
50
50
50
—
—
5
t
TMS, TDI data hold time
25
—
0
6
TCK low to TDO data valid
7
TCK low to TDO data invalid
8
TCK low to TDO high impedance
—
—
—
—
50
50
11
12
13
14
15
TCK falling edge to output valid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
PXS30 Microcontroller Data Sheet, Rev. 1
112
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
NOTES:
1
fTCK = 1/tTCK. fTCK needs to be smaller than or equal to the system clock (SYS_CLK).
TCK
2
3
3
2
1
Figure 35. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 36. JTAG test access port timing
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
113
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 37. JTAG boundary scan timing
3.22.3 Nexus timing
1
Table 63. Nexus debug port timing
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
2
tMCKO
tMDC
CC MCKO cycle time
CC MCKO duty cycle
—
—
—
—
—
—
—
—
—
—
—
15.75
33
—
ns
%
66
3
tMDOV
tEVTIPW
tEVTOPW
tTCYC
CC MCKO Low to MDO, MSEO, EVTO data valid2
(–0.1)tMCKO (0.2)tMCKO ns
4
CC EVTI pulse width
4.0
1
—
—
—
60
—
—
18
—
tTCYC
tMCYC
ns
5
CC EVTO pulse width
6
CC TCK cycle time3
60
40
12
6
7
tTDC
CC TCK duty cycle
%
8
tNTDIS, NTMSS
t
CC TDI, TMS data setup time
CC TDI, TMS data hold time
CC TCK low to TDO data valid
CC TCK low to TDO data invalid
ns
9
tNTDIH, NTMSH
t
ns
10
11
tJOV
0
ns
tJOIV
6
ns
PXS30 Microcontroller Data Sheet, Rev. 1
114
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
NOTES:
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal.
2
3
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The system clock frequency needs to be three times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
4
EVTI
Figure 38. Nexus output timing
3.22.4 External interrupt timing (IRQ pins)
Table 64. External interrupt timing (NMI IRQ)
No.
Symbol
Parameter Conditions
Min Max Unit
1
2
3
tIPWL SR IRQ pulse width low
tIPWH SR IRQ pulse width high
tICYC SR IRQ edge to edge time1
—
—
—
TBD
TBD
TBD
—
—
—
ns
ns
ns
NOTES:
1
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
Table 65. External interrupt timing (GPIO IRQ)
No.
Symbol
Parameter
Conditions
Min Max Unit
1
2
3
tIPWL SR IRQ pulse width low
tIPWH SR IRQ pulse width high
tICYC SR IRQ edge to edge time1
—
—
—
TBD
TBD
TBD
—
—
—
ns
ns
ns
NOTES:
1
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
115
Electrical characteristics
CLKOUT
IRQ
1
2
3
Figure 39. External interrupt timing
3.22.5 FlexCAN timing
Table 66. FlexCAN timing
No.
Symbol
Parameter
Conditions Min
Max
Unit
1
2
fCAN_TX CC FlexCAN design target transmit data rate
fCAN_RX CC FlexCAN design target receive data rate
—
—
10
10
—
—
MBit/s
MBit/s
3.22.6 DSPI timing
Table 67. DSPI timing
Conditions
No. Symbol
Parameter
Min
Max
Unit
1
tSCK CC DSPI cycle time
Master (MTFE = 0)
62
62
16
16
16
—
—
—
—
—
ns
Slave (MTFE = 0)
Slave receive only mode1
2
3
4
5
6
7
8
tCSC CC PCS to SCK delay
tASC CC After SCK delay
tSDC CC SCK duty cycle
—
ns
ns
—
—
0.4 × tSCK 0.6 × tSCK ns
tA
CC Slave access time
SS active to SOUT valid
—
—
13
13
40
10
—
—
ns
ns
ns
ns
tDIS CC Slave SOUT disable time
tPCSC CC PCSx to PCSS time
tPASC CC PCSS to PCSx time
SS inactive to SOUT High-Z or invalid
—
—
PXS30 Microcontroller Data Sheet, Rev. 1
116
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 67. DSPI timing (continued)
No. Symbol
Parameter
Conditions
Master (MTFE = 0)
Min
Max
Unit
9
tSUI CC Data setup time for inputs
20
2
—
—
—
—
—
—
—
—
4
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
5
20
–5
4
10
tHI
CC Data hold time for inputs
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
11
–5
—
—
—
—
–2
6
11 tSUO CC Data valid (after SCK edge)
12 tHO CC Data hold time for outputs
13 tDT CC Delay after Transfer
Slave
23
11
5
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
—
—
—
—
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Continuous mode
6
–2
62
134
—
—
(minimum CS negation time) Non-continuos mode2
NOTES:
1
Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. Note that in this mode, the DSPI can
receive data on SIN, but no valid data is transmitted on SOUT.
2
In non-continuous mode, this value is always tSCK × DSPI_CTARn[DT] × DSPI_CTARn[PDT]. The minimum
permissible value of DT is 2 and the minimum permissible value of PDT is 1. See the DSPI chapter of the PXS30
Reference Manual (PXS30RM) for more information.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
117
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Figure 40. DSPI classic SPI timing—master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 41. DSPI classic SPI timing—master, CPHA = 1
PXS30 Microcontroller Data Sheet, Rev. 1
118
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 42. DSPI classic SPI timing—slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 43. DSPI classic SPI timing—slave, CPHA = 1
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
119
Electrical characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Figure 44. DSPI modified transfer format timing—master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 45. DSPI modified transfer format timing—master, CPHA = 1
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
120
Freescale Semiconductor
Electrical characteristics
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 46. DSPI modified transfer format timing—slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
Data
Data
SOUT
9
10
SIN
First Data
Last Data
Figure 47. DSPI modified transfer format timing—slave, CPHA = 1
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
121
Electrical characteristics
(CPOL = 0)
(CPOL = 1)
SCK
SCK
Master SOUT
Master SIN
PCSx
3
2
2
13
Figure 48. Example of non-continuous format (CPHA = 1, CONT = 0)
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
2
3
2
Figure 49. Example of continuous transfer (CPHA = 1, CONT = 1)
8
7
PCSS
PCSx
Figure 50. DSPI PCS strobe (PCSS) timing
Table 68. PDI electrical characteristics
3.22.7 PDI timing
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
tPDI_CLOCK SR PDI clock period
—
15
—
ns
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
122
Freescale Semiconductor
Electrical characteristics
Table 68. PDI electrical characteristics (continued)
No.
Symbol
Parameter
Conditions
Min
Max
Unit
2
3
tPDI_IS
tPDI_IH
SR Input setup time1
SR Input hold time1
—
—
3
3
—
—
ns
ns
NOTES:
1
Data can be captured at both launching and capturing edge of PDI_CLK.
PDI_CLOCK
1
2
3
PDI_DATA[15:0]
PDI_LINE_V
Input Data Valid
PDI_FRAME_V
PDI timing
3.22.8 Fast ethernet interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals
are not TTL compatible. They follow the CMOS electrical characteristics.
3.22.8.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the system clock frequency must exceed four times the
RX_CLK frequency.
Table 69. MII receive signal timing
No.
Parameter
Min
Max
Unit
1
2
3
4
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
RX_CLK pulse width high
5
—
—
ns
5
ns
40%
40%
60%
60%
RX_CLK period
RX_CLK period
RX_CLK pulse width low
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
123
Electrical characteristics
3
RX_CLK (input)
4
RXD[3:0] (inputs)
RX_DV
RX_ER
1
2
Figure 51. MII receive signal timing diagram
3.22.8.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the system clock frequency must exceed four times the
TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising
or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of
non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
1
Table 70. MII transmit signal timing
No.
Parameter
Min
Max
Unit
5
6
7
8
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX_CLK pulse width high
5
—
ns
—
25
ns
40%
40%
60%
60%
TX_CLK period
TX_CLK period
TX_CLK pulse width low
NOTES:
1
Output pads configured with SRC = 0b11.
7
TX_CLK (input)
5
8
TXD[3:0] (outputs)
TX_EN
TX_ER
6
Figure 52. MII transmit signal timing diagram
PXS30 Microcontroller Data Sheet, Rev. 1
124
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3.22.8.3 MII async inputs signal timing (CRS and COL)
1
Table 71. MII async inputs signal timing
No.
Parameter
CRS, COL minimum pulse width
Min
Max
Unit
9
1.5
—
TX_CLK period
NOTES:
1
Output pads configured with SRC = 0b11.
CRS, COL
9
Figure 53. MII async inputs timing diagram
3.22.8.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 5 MHz.
1
Table 72. MII serial management channel timing
No.
Parameter
Min
Max
Unit
10 MDC falling edge to MDIO output invalid (minimum propagation delay)
11 MDC falling edge to MDIO output valid (max prop delay)
12 MDIO (input) to MDC rising edge setup
13 MDIO (input) to MDC rising edge hold
14 MDC pulse width high
0
—
—
25
ns
ns
ns
10
—
0
—
ns
40%
40%
60%
60%
MDC period
MDC period
15 MDC pulse width low
NOTES:
1
Output pads configured with SRC = 0b11.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
125
Electrical characteristics
14
15
MDC (output)
MDIO (output)
10
11
MDIO (input)
12
Figure 54. MII serial management channel timing diagram
13
3.22.9 External Bus Interface (EBI) timing
Table 73. EBI timing
45 MHz (Ext. Bus Freq)1
No.
Symbol
Parameter
Unit
Notes
Min
Max
1
tC
CC D_CLKOUT period
22.2
—
ns Signals are measured
at 50% VDDE
.
2
3
4
5
tCDC CC D_CLKOUT duty cycle
45%
—
55%
—
tC
ns
ns
ns
—
—
—
—
tCRT
tCFT
CC D_CLKOUT rise time
CC D_CLKOUT fall time
—
—
tCOH CC D_CLKOUT posedge to output
1.0
—
signal invalid or high Z (hold time)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
PXS30 Microcontroller Data Sheet, Rev. 1
126
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 73. EBI timing (continued)
45 MHz (Ext. Bus Freq)1
No.
Symbol
Parameter
Unit
Notes
Min
Max
6
tCOV CC D_CLKOUT posedge to output
—
10
ns
—
signal valid (output delay)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
7
tCIS
CC Input signal valid to D_CLKOUT
7.5
—
ns
—
posedge (setup time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
8
tCIH
CC D_CLKOUT posedge to input signal
1.0
—
ns
—
invalid (hold time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
9
tAPW CC D_ALE pulse width
6.5
1.5
—
—
ns The timing is for
Asynchronous
external memory
system.
10
tAAI
CC D_ALE negated to address invalid
ns The timing is for
Asynchronous
external memory
system.
ALE is measured at
50% of VDDE.
NOTES:
1
Speed is the nominal maximum frequency. Maximum core speed allowed is 180 MHz plus frequency modulation
(FM).
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
127
Electrical characteristics
VOH_F
VDDE / 2
VOL_F
D_CLKOUT
2
3
2
4
1
Figure 55. D_CLKOUT timing
VDDE / 2
D_CLKOUT
6
5
5
Output
Bus
VDDE / 2
6
5
5
Output
Signal
VDDE / 2
6
Output
Signal
VDDE / 2
Figure 56. Synchronous output timing
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
128
Freescale Semiconductor
Electrical characteristics
D_CLKOUT
VDDE / 2
7
8
Input
Bus
VDDE / 2
7
8
Input
Signal
VDDE / 2
Figure 57. Synchronous input timing
ipg_clk
D_CLKOUT
D_ALE
D_TS
D_ADD/D_DAT
DATA
ADDR
9
10
Figure 58. ALE signal timing
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
129
Electrical characteristics
3.22.10 I2C Timing
2
Table 74. I C SCL and SDA input timing specifications
Value
Min Max
No.
Symbol
Parameter
Unit
1
2
4
6
7
8
9
—
—
—
—
—
—
—
D Start condition hold time
D Clock low time
2
8
—
—
—
—
—
—
—
IP bus cycle1
IP bus cycle1
ns
D Data hold time
0.0
4
D Clock high time
D Data setup time
IP bus cycle1
0.0
2
ns
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
IP bus cycle1
IP bus cycle1
2
NOTES:
1
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
2
Table 75. I C SCL and SDA output timing specifications
Value
No.
Symbol
Parameter
Unit
Min Max
11
21
33
41
51
61
71
81
91
—
—
—
—
—
—
—
—
—
D Start condition hold time
D Clock low time
6
—
—
IP bus cycle2
IP bus cycle1
ns
10
—
7
D SCL/SDA rise time
D Data hold time
99.6
—
IP bus cycle1
D SCL/SDA fall time
D Clock high time
—
10
2
99.5
—
ns
IP bus cycle1
IP bus cycle1
IP bus cycle1
IP bus cycle1
D Data setup time
—
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
20
10
—
—
NOTES:
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2
3
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
PXS30 Microcontroller Data Sheet, Rev. 1
130
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
2
6
5
SCL
3
1
8
4
7
9
SDA
2
Figure 59. I C input/output timing
3.22.11 LINFlex timing
The maximum bit rate is 1.875 MBit/s.
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
131
Package characteristics
4
Package characteristics
4.1
4.1.1
Package mechanical data
257 MAPBGA
Figure 60. 257 MAPBGA mechanical data (1 of 2)
PXS30 Microcontroller Data Sheet, Rev. 1
132
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package characteristics
Figure 61. 257 MAPBGA mechanical data (2 of 2)
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
133
Package characteristics
4.1.2
473 MAPBGA
Figure 62. 473 MAPBGA package mechanical data (1 of 3)
PXS30 Microcontroller Data Sheet, Rev. 1
134
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package characteristics
Figure 63. 473 MAPBGA package mechanical data (2 of 3)
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
135
Package characteristics
Figure 64. 473 MAPBGA package mechanical data (3 of 3)
PXS30 Microcontroller Data Sheet, Rev. 1
136
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Orderable parts
5
Orderable parts
M PX
S 30 20 V MS 2 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
Family
Flash Memory Size
D = Display Graphics
10 = 1 MB
15 = 1.5 MB
20 = 2 MB
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
N = Connectivity/Network
R = Performance/Real Tiime Control
S = Safety
Temperature range
Package identifier
Operating frequency
Tape and reel status
V = –40 °C to 105 °C
(ambient)
MM = 257 BGA
MS = 473 BGA
1 = 150 MHz
2 = 180 MHz
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 76 for more information.
Figure 65. PXS30 orderable part number description
Table 76. PXS30 orderable part number summary
Speed
(MHz)
Part number
MPXS3010VMM150
Flash/SRAM
Package
1 MB/256 KB
1.5 MB/384 KB
2 MB/512 KB
257 MAPBGA (14 mm x 14 mm)
473 MAPBGA (19 mm x 19 mm)
473 MAPBGA (19 mm x 19 mm)
150
180
180
MPXS3015VMS180
MPXS3020VMS180
6
Reference documents
1. Nexus (IEEE-ISTO 5001™—2008)
2. Measurement of emission of ICs—IEC 61967-2
3. Measurement of emission of ICs—IEC 61967-4
4. Measurement of immunity of ICs—IEC 62132-4
5. Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
6. JEDEC specifications are available at http://www.jedec.org
7. MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
137
Document revision history
8. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
9. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
10. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.
212–220.
7
Document revision history
Table 77 summarizes revisions to this document.
Table 77. Revision history
Description of Changes
Revision
Date
1
30 Sep 2011 Initial release.
PXS30 Microcontroller Data Sheet, Rev. 1
138
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Document revision history
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Document Number: PXS30
Rev. 1
October 3, 2011 1:35 pm
PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
139
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