PPXN4030VVU264R [FREESCALE]

PXR40 Microcontroller; PXR40微控制器


型号：	PPXN4030VVU264R
厂家：	Freescale
描述：	PXR40 Microcontroller PXR40微控制器微控制器
文件：	总100页 (文件大小：720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: PXR40

Rev. 1, 09/2011

PXR40

PXR40 Microcontroller Data

Sheet

TEPBGA–416

27mm x 27mm

• Dual issue, 32-bit CPU core complex (e200z7)

– Compliant with the Power Architecture embedded

category

single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Four enhanced queued analog-to-digital converters

(eQADC)

– 16 KB I-Cache and 16 KB D-Cache

– Includes an instruction set enhancement allowing

variable length encoding (VLE), optional encoding of

mixed 16-bit and 32-bit instructions, for code size

footprint reduction

– Support for 64 analog channels

– Includes one absolute reference ADC channel

– Includes eight decimation filters

• Four deserial serial peripheral interface (SPI) modules

• Three enhanced serial communication interface (UART)

modules

• Four controller area network (CAN) modules

• Dual-channel FlexRay controller

– Includes signal processing extension (SPE2) instruction

support for digital signal processing (DSP) and

single-precision floating point operations

• 4 MB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 256 KB on-chip general-purpose SRAM including 32 KB

of standby RAM

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003/5001-2008 standard

• Device and board test support per Joint Test Action Group

(JTAG) (IEEE 1149.1)

• Two direct memory access controller (eDMA2) blocks

– One supporting 64 channels

• On-chip voltage regulator controller regulates supply

voltage down to 1.2 V for core logic

– One supporting 32 channels

• Interrupt controller (INTC)

• Frequency modulated phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• External bus interface (EBI) for calibration and application

development (not available on all packages)

• System integration unit (SIU)

• Error correction status module (ECSM)

• Boot assist module (BAM) supports serial bootload via

CAN or SCI

• Two second-generation enhanced time processor units

(eTPU2) that share code and data RAM.

– 32 standard channels per eTPU2

– 24 KB code RAM

– 6 KB parameter (data) RAM

• Enhanced modular input output system supporting 32

unified channels (eMIOS) with each channel capable of

Table of Contents

PXR40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

5.9 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 68

5.9.1 ADC internal resource measurements. . . . . . . 69

5.10 C90 flash memory electrical characteristics . . . . . . . . 71

5.11 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.11.2 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 74

5.12 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.12.1 Generic timing diagrams . . . . . . . . . . . . . . . . . 77

5.12.2 Reset and configuration pin timing. . . . . . . . . . 78

5.12.3 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 78

5.12.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.12.5 External Bus Interface (EBI) timing . . . . . . . . . 84

5.12.6 External interrupt timing (IRQ pin) . . . . . . . . . . 88

5.12.7 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.12.8 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.12.9 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PXR40 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1 416-ball TEPBGA pin assignments. . . . . . . . . . . . . . . . .6

Signal properties and muxing. . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53

5.2.1 General notes for specifications at maximum junction

temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3 EMI (Electromagnetic Interference) characteristics . . .55

5.4 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56

5.5 PMC/POR/LVI electrical specifications . . . . . . . . . . . . .56

5.6 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59

5.6.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

5.6.2 Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . .60

5.6.3 Power sequencing and POR dependent on V_DDA60

5.7 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .61

5.7.1 I/O pad current specifications . . . . . . . . . . . . . .64

5.7.2 I/O pad V_DD33current specifications . . . . . . . . .64

5.7.3 LVDS pad specifications . . . . . . . . . . . . . . . . . .65

5.8 Oscillator and FMPLL electrical characteristics . . . . . .66

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

PXR40 features

Table 1 displays the PXR40 feature set.

Table 1. PXR40 feature set

Feature

PXR40

Core

SIMD

VLE

e200z7

Yes

Cache

32 KB

(16 KB Instruction/16 KB Data)

Non-maskable interrupt (NMI)

NMI & Critical Interrupt

MMU

64 entry

Yes

MPU

XBAR

5 × 5

Windowing software watchdog

Yes

Nexus

SRAM

256 KB

4 MB

4 × 256 bit

Flash

Flash fetch accelerator

(first 1 MB of memory is 4 × 128; last 3 MB are 4 × 256)

External bus

Yes

Calibration bus

16 bit non-muxed

32 bit muxed

DMA

96 channel

DMA Nexus

Serial

Class 3

UART_A

UART_B

UART_C

Microsecond bus uplink

CAN

Yes

CAN_A

64 message buffers

CAN_B

64 message buffers

CAN_C

CAN_D

CAN_E

64 message buffers

SPI

SPI_A

Yes

SPI_B

SPI_C

SPI_D

FlexRay

Ethernet

System timers

4 PIT chan

4 SWT

1 Watchdog

eMIOS

eTPU

32 channel

64 channel

Yes (eTPU2)

eTPU_A

eTPU_B

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

PXR40 features

Table 1. PXR40 feature set (continued)

PXR40

Feature

Code memory

24 KB

Data memory

Interrupt controller

ADC

6 KB

448

64 channel

eQADC_A

Yes

eQADC_B

Yes

Temperature sensor

Variable gain amp.

Decimation filter

Yes

Yes (8 on eQADC_B)

Sensor diagnostics

Yes

PLL

VRC

Supplies

Low Power Modes

Stop Mode

Slow Mode

Note: 3.3 V is required for certain IO segments only during debug/development (e.g., Nexus 3 trace and bus)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

PXR40 block diagram

Figure 1 shows a top-level block diagram of the PXR40 microcontrollers.

PXR40 Block Diagram

System

Data and Instruction System

Integration

Debug

SPE2

JTAG

2 x eDMA

64- and

32-ch

e200z7

Superscalar

CPU

Osc/PLL

Nexus

IEEE

ISTO

FlexRay™

Controller

Interrupt

Controller

5001™-2003

Crossbar Switch (XBAR)

Memory Protection Unit (MPU)

256 KB

SRAM

w/ECC

PBRIDGE A

PBRIDGE B

4 MB

Flash

w/ECC

Boot Assist

Module

(BAM)

(32 KB S/B)

Main Memory System

Timed I/O System

SIU

Communications

Data

24K

3 x

UART/

LIN

4 x

Dec

Fil

64-ch

QUAD

ADCi

eMIOS

32-ch

eTPU2

32-ch

eTPU2

32-ch

4 x

CAN

4 x

SPI

Code

RAM

ADC

– Analog-to-digital converter

MMU

MPU

– Memory management unit

– Memory protection unit

ADCi – ADC interface

AIPS – Peripheral I/O bridge

AMux – Analog multiplexer

PBRIDGE – Peripheral I/O bridge

S/B

– Stand-by

CAN

DECFIL– Decimation filter

EBI – External bus interface

ECSM – Error correction status module

eDMA2 – Enhanced direct memory access

eMIOS – Enhanced modular I/O system

eQADC – Enhanced queued A/D converter module

eTPU2 – Enhanced time processing unit 2

– Controller area network

SIU

SPE2

SPI

– System integration unit

– Signal processing engine 2

– Serial peripheral interface controller

– General-purpose static RAM

SRAM

UART/LIN – Universal asynchronous receiver/transmitter/

local interconnect network

– Variable length instruction encoding

VLE

Figure 1. Block diagram

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Pin assignments

The figures in this section show the primary pin function. For the full signal properties and muxing table, see Table 4.

3.1

416-ball TEPBGA pin assignments

Figure 2 shows the 416-ball TEPBGA pin assignments in one figure. The same information is shown in Figure 3 through

Figure 6.

REF–

ANA4

ANA8

ANA11 ANA15 VDDA_A0

VRL_A VRH_A

AN28

AN32

AN36 VDDA_B0

AN33 VDDA_B1

VRL_B VRH_B

ANB7

ANB11 ANB14 ANB17 ANB21 ANB23

VSS

VDD

RSTOUT ANA0

BYPCA1

BYPCB1

REF–

AN24

REF–

ANB6

ANA14 VDDA_A1 VSSA_A1

AN27

AN26

AN25

AN29

AN30

AN31

ANB8

ANB5

ANB9

ANB10 ANB15 ANB18 ANB22

VSS

TCRCLKC

VDDEH1

VSS

VDD

VSS

TEST

VDD

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

ANA10

ANA9

ANA7

VSSA_B0

AN38

BYPCA

BYPCB

ANA13 ANA17 ANA19 ANA21 ANA23

ANA12 ANA16 ANA18 ANA20 ANA22

AN34

AN35

AN37

AN39

ANB0

ANB2

ANB4

ANB3

ANB12 ANB16 ANB19

VSS

ETPUC0 ETPUC1

ETPUC2 ETPUC3

ETPUA30 ETPUA31

ANB1

ANB13 ANB20

VSS

VDDEH7

ETPUA27 ETPUA28 ETPUA29 VSS

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

ETPUA15 ETPUA16 ETPUA17 ETPUA18

ETPUA11 ETPUA12 ETPUA14 ETPUA13

ETPUA7 ETPUA8 ETPUA9 ETPUA10

ETPUA3 ETPUA4 ETPUA5 ETPUA6

TCRCLKA ETPUA0 ETPUA1 ETPUA2

VDDEH7 ETPUC4 ETPUC5 ETPUC6

ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14

ETPUC15 ETPUC16 ETPUC17 ETPUC18

ETPUC19 ETPUC20 ETPUC21ETPUC22

ETPUC23 ETPUC24ETPUC25ETPUC26

ETPUC27ETPUC28ETPUC29ETPUC30

ETPUC31ETPUB15 ETPUB14 VDDEH7

VDDEH6 ETPUB11 ETPUB12 ETPUB13

ETPUB7 ETPUB8 ETPUB9 ETPUB10

ETPUB3 ETPUB4 ETPUB5 ETPUB6

TCRCLKB ETPUB0 ETPUB1 ETPUB2

ETPUB19 ETPUB18 ETPUB17 ETPUB16

ETPUB26 ETPUB22 ETPUB21 ETPUB20

REGSEL ETPUB25 ETPUB24 ETPUB23

ETPUB29 ETPUB28 ETPUB27 REGCTL

VDD33_3 ETPUB30 VDDREG VSSSYN

PXR40 416-ball TEPBGA

(as viewed from top through the package)

VSS

VDD33_1 TXDA

RXDA

VSTBY

VSS

BOOT–

RXDB

VDDE2

WKPCFG VDD

CFG1

VDDE2 VDDE2

TXDB

PLLCFG2 VDDEH1

PLLCFG1

JCOMP RESET PLLCFG0 RDY

VDDE2 MCKO MSEO1

EVTI

MDO1

MDO5

VDDE2

VDDE2 VDDE2 VDDE2

EVTO

MDO2

MDO6

MSEO0 MDO0

MDO3

MDO7

MDO4

MDO8

MDO9 MDO10 MDO11 MDO15

MDO12 MDO13 MDO14 VDD33_2

VSSFL

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDD ETPUB31

EXTAL

PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4

VDD

EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1

VSS

VDD

VSS

VDDEH6 XTAL

AC VDDE2

AD ENGCLK

VDDE2

FR_A_

FR_B_

EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30

RXDC

SINC

PCSC3

VDD

VSS

VDDSYN

VDD

VSS

PCSA5 SOUTA

SCKA

SCKB

PCSB0 PCSB3 EMIOS2

CNTXB CNTXD

SCKC

FR_A_

FR_B_

PCSA4 PCSA0 PCSA3

SINB

EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0

PCSC2 PCSC5

VDD

FR_A_

FR_B_

EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28

VDDEH4 TXDC

PCSC4 VDDEH5

VSS

VDDE2

VDDEH3 PCSB5

SINA

PCSB2 SOUTB EMIOS1 EMIOS4

10 11

CNTXA CNTXC SOUTC

19 20 21

TX_EN TX_EN

Figure 2. PXR40 416-ball TEPBGA (full diagram)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Pin assignments

REFBYP-

CA1

VSS

VDD

RSTOUT

ANA0

ANA4

ANA8

ANA11

ANA15 VDDA_A0

VRL_A

VRH_A

AN28

VDDEH1

VSS

VDD

VSS

TEST

VDD

VSS

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

ANA10

ANA9

ANA7

ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24

AN27

AN26

AN25

ETPUA30 ETPUA31

ANA13

ANA12

ANA17

ANA16

ANA19

ANA18

ANA21

ANA20

ANA23

ANA22

ETPUA27 ETPUA28 ETPUA29

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

ETPUA15 ETPUA16 ETPUA17 ETPUA18

ETPUA11 ETPUA12 ETPUA14 ETPUA13

ETPUA7 ETPUA8 ETPUA9 ETPUA10

ETPUA3 ETPUA4 ETPUA5 ETPUA6

TCRCLKA ETPUA0 ETPUA1 ETPUA2

PXR40 416-ball TEPBGA

(as viewed from top through the package)

(1 of 4)

VSS

VDD33_1 TXDA

RXDA

VSTBY

RXDB BOOTCFG1 WKPCFG

VDD

VDDE2

VSS

Figure 3. PXR40 416-ball TEPBGA (1 of 4)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Pin assignments

REFBYP-

CB1

AN32

AN36 VDDA_B0

VRL_B

VRH_B

ANB7

ANB11

ANB14

ANB17

ANB21

ANB23

VSS

AN29

AN30

AN31

AN33 VDDA_B1 VSSA_B0 REFBYPCB ANB6

ANB8

ANB5

ANB9

ANB10

ANB12

ANB13

ANB15

ANB16

ANB20

ANB18

ANB19

VSS

ANB22

VSS

TCRCLKC

AN34

AN35

AN37

AN39

AN38

ANB1

ANB0

ANB2

ANB4

ANB3

ETPUC0 ETPUC1

VDDEH7 ETPUC2 ETPUC3

VDDEH7 ETPUC4 ETPUC5 ETPUC6

ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14

ETPUC15 ETPUC16 ETPUC17 ETPUC18

ETPUC19 ETPUC20 ETPUC21 ETPUC22

ETPUC23 ETPUC24 ETPUC25 ETPUC26

ETPUC27 ETPUC28 ETPUC29 ETPUC30

ETPUC31 ETPUB15 ETPUB14 VDDEH7

VDDEH6 ETPUB11 ETPUB12 ETPUB13

PXR40 416-ball TEPBGA

(as viewed from top through the package)

(2 of 4)

VSS

Figure 4. PXR40 416-ball TEPBGA (2 of 4)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Pin assignments

TXDB

PLLCFG1 PLLCFG2 VDDEH1

VDDE2

VSS

JCOMP RESET PLLCFG0

RDY

EVTI

VDDE2

VSS

VDDE2

EVTO

MDO2

MDO6

MDO9

MCKO

MSEO0

MDO3

MDO7

MSEO1

MDO0

MDO4

MDO8

VDDE2

MDO1

MDO5

VDDE2

VSS

PXR40 416-ball TEPBGA

(as viewed from top through the package)

(3 of 4)

MDO10 MDO11 MDO15

AA MDO12 MDO13 MDO14 VDD33_2

TDO

VDDE2

ENGCLK

VDD

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDDE2

PCSA1

PCSA2

SOUTA

PCSA3

PCSB4

SCKA

SCKB

PCSB1 VDDEH3 VDDEH4

VDD

EMIOS8

VDD

VSS

FR_A_TX FR_B_TX PCSA5

PCSB0

PCSB3 EMIOS2 EMIOS5 EMIOS9

FR_A_RX FR_B_RX PCSA4

PCSA0

SINB

EMIOS0 EMIOS3 EMIOS6 EMIOS10 AE

FR_A_

TX_EN

FR_B_

TX_EN

VSS

VDDE2

VDDEH3 PCSB5

SINA

PCSB2

SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11

Figure 5. PXR40 416-ball TEPBGA (3 of 4)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Pin assignments

VSS

ETPUB7 ETPUB8 ETPUB9 ETPUB10

ETPUB3 ETPUB4 ETPUB5 ETPUB6

TCRCLKB ETPUB0 ETPUB1 ETPUB2

ETPUB19 ETPUB18 ETPUB17 ETPUB16

ETPUB26 ETPUB22 ETPUB21 ETPUB20

REGSEL ETPUB25 ETPUB24 ETPUB23

ETPUB29 ETPUB28 ETPUB27 REGCTL

VDD33_3 ETPUB30 VDDREG VSSSYN

VSS

PXR40 416-ball TEPBGA

(as viewed from top through the package)

(4 of 4)

VDD

VSS

ETPUB31 VSSFL

EXTAL

XTAL

EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1

VDD

VSS

VDDEH6

VDD

EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD

SCKC

RXDC

SINC

PCSC3

PCSC2

VDDSYN

VDD

AE EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0

PCSC5

VSS

EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4

TXDC

PCSC4 VDDEH5

VSS

Figure 6. PXR40 416-ball TEPBGA (4 of 4)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Signal properties and muxing

Table 2 shows the signals properties for each pin on the PXR40. For each port pin that has an associated SIU_PCRn register to

control its pin properties, the supported functions column lists the functions associated with the programming of the

SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 7.

Table 2. Signal Properties Summary

GPIO/

PCR¹

Pad

I/O Type

Signal Name²

Function³

TCRCLKA

Function Summary

Primary Functions

are listed First

113 TCRCLKA_IRQ7_GPIO113

eTPU A TCR clock

5V M

IRQ7

—

External interrupt request

Secondary Functions

are alternate functions

—

I/O

GPIO Functions are

GPIO113

GPIO

listed Last

Function not implemented on this device

Figure 7. Supported functions example

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Table 2. Signal Properties and Muxing Summary

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

eTPU_A

RESET⁸

113 TCRCLKA_IRQ7_

TCRCLKA

IRQ7

eTPU A TCR clock

V_DDEH1

—/Up

GPIO113

External interrupt request

—

I/O

GPIO113

ETPUA0

ETPUA12

—

GPIO

114 ETPUA0_ETPUA12_

GPIO114

eTPU A channel

—/WKPCFG

eTPU A channel (output only)

—

I/O

GPIO114

ETPUA1

ETPUA13

—

GPIO

115 ETPUA1_ETPUA13_

GPIO115

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO115

ETPUA2

ETPUA14

—

GPIO

116 ETPUA2_ETPUA14_

GPIO116

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO116

ETPUA3

ETPUA15

—

GPIO

117 ETPUA3_ETPUA15_

GPIO117

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO117

ETPUA4

ETPUA16

—

GPIO

118 ETPUA4_ETPUA16_

GPIO118

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO118

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

119 ETPUA5_ETPUA17_

GPIO119

ETPUA5

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

ETPUA17

—

eTPU A channel (output only)

—

GPIO119

ETPUA6

ETPUA18

—

GPIO

I/O

120 ETPUA6_ETPUA18_

GPIO120

eTPU A channel

eTPU A channel (output only)

—

GPIO120

ETPUA7

ETPUA19

—

GPIO

I/O

121 ETPUA7_ETPUA19_

GPIO121

eTPU A channel

eTPU A channel (output only)

—

GPIO121

ETPUA8

ETPUA20

—

GPIO

I/O

122 ETPUA8_ETPUA20_

GPIO122

eTPU A channel

eTPU A channel (output only)

—

GPIO122

ETPUA9

ETPUA21

—

GPIO

I/O

123 ETPUA9_ETPUA21_

GPIO123

eTPU A channel

eTPU A channel (output only)

—

GPIO123

ETPUA10

ETPUA22

—

GPIO

I/O

124 ETPUA10_ETPUA22_

GPIO124

eTPU A channel

eTPU A channel (output only)

—

GPIO124

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

125 ETPUA11_ETPUA23_

GPIO125

ETPUA11

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

ETPUA23

—

eTPU A channel (output only)

—

GPIO125

ETPUA12

PCSB1

—

GPIO

I/O

126 ETPUA12_PCSB1_

GPIO126

eTPU A channel

DSPI B peripheral chip select

—

GPIO126

ETPUA13

PCSB3

—

GPIO

I/O

127 ETPUA13_PCSB3_

GPIO127

eTPU A channel

DSPI B peripheral chip select

—

GPIO127

ETPUA14

PCSB4

—

GPIO

I/O

128 ETPUA14_PCSB4_

GPIO128

eTPU A channel

DSPI B peripheral chip select

—

GPIO128

ETPUA15

PCSB5

—

GPIO

I/O

129 ETPUA15_PCSB5_

GPIO129

eTPU A channel

DSPI B peripheral chip select

—

GPIO129

ETPUA16

PCSD1

—

GPIO

I/O

130 ETPUA16_PCSD1_

GPIO130

eTPU A channel

DSPI D peripheral chip select

—

GPIO130

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

131 ETPUA17_PCSD2_

GPIO131

ETPUA17

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

PCSD2

—

DSPI D peripheral chip select

—

I/O

GPIO131

ETPUA18

PCSD3

—

GPIO

132 ETPUA18_PCSD3_

GPIO132

eTPU A channel

DSPI D peripheral chip select

—

I/O

GPIO132

ETPUA19

PCSD4

—

GPIO

133 ETPUA19_PCSD4_

GPIO133

eTPU A channel

DSPI D peripheral chip select

—

I/O

GPIO133

ETPUA20

IRQ8

GPIO

134 ETPUA20_IRQ8_

GPIO134

eTPU A channel

External interrupt request

—

I/O

GPIO134

ETPUA21

IRQ9

GPIO

135 ETPUA21_IRQ9_

GPIO135

eTPU A channel

External interrupt request

—

I/O

GPIO135

ETPUA22

IRQ10

—

GPIO

136 ETPUA22_IRQ10_

GPIO136

eTPU A channel

External interrupt request

—

I/O

GPIO136

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

137 ETPUA23_IRQ11_

GPIO137

ETPUA23

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

IRQ11

—

External interrupt request

—

I/O

GPIO137

ETPUA24

IRQ12

—

GPIO

138 ETPUA24_IRQ12_

GPIO138

eTPU A channel

External interrupt request

—

I/O

GPIO138

ETPUA25

IRQ13

—

GPIO

139 ETPUA25_IRQ13_

GPIO139

eTPU A channel

External interrupt request

—

I/O

GPIO139

ETPUA26

IRQ14

—

GPIO

140 ETPUA26_IRQ14_

GPIO140

eTPU A channel

External interrupt request

—

I/O

GPIO140

ETPUA27

IRQ15

—

GPIO

141 ETPUA27_IRQ15_

GPIO141

eTPU A channel

External interrupt request

—

I/O

GPIO141

ETPUA28

PCSC1

—

GPIO

142 ETPUA28_PCSC1_

GPIO142

eTPU A channel

DSPI C peripheral chip select

—

I/O

GPIO142

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

143 ETPUA29_PCSC2_

GPIO143

ETPUA29

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

PCSC2

—

DSPI C peripheral chip select

—

GPIO143

ETPUA30

PCSC3

—

GPIO

I/O

144 ETPUA30_PCSC3_

GPIO144

eTPU A channel

DSPI C peripheral chip select

—

GPIO144

ETPUA31

PCSC4

—

GPIO

I/O

145 ETPUA31_PCSC4_

GPIO145

eTPU A channel

DSPI C peripheral chip select

—

GPIO145

GPIO

I/O

eTPU_B

146 TCRCLKB_IRQ6_

GPIO146

TCRCLKB

IRQ6

eTPU B TCR clock

V_DDEH6

—/Up

T23

T24

T25

External interrupt request

—

I/O

GPIO146

ETPUB0

ETPUB16

—

GPIO

147 ETPUB0_ETPUB16_

GPIO147

eTPU B channel

—/WKPCFG

eTPU B channel (output only)

—

I/O

GPIO147

ETPUB1

ETPUB17

—

GPIO

148 ETPUB1_ETPUB17_

GPIO148

eTPU B channel

eTPU B channel (output only)

—

I/O

GPIO148

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

149 ETPUB2_ETPUB18_

GPIO149

ETPUB2

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

T26

R23

R24

R25

R26

P23

ETPUB18

—

eTPU B channel (output only)

—

GPIO149

ETPUB3

ETPUB19

—

GPIO

I/O

150 ETPUB3_ETPUB19_

GPIO150

eTPU B channel

eTPU B channel (output only)

—

GPIO150

ETPUB4

ETPUB20

—

GPIO

I/O

151 ETPUB4_ETPUB20_

GPIO151

eTPU B channel

eTPU B channel (output only)

—

GPIO151

ETPUB5

ETPUB21

—

GPIO

I/O

152 ETPUB5_ETPUB21_

GPIO152

eTPU B channel

eTPU B channel (output only)

—

GPIO152

ETPUB6

ETPUB22

—

GPIO

I/O

153 ETPUB6_ETPUB22_

GPIO153

eTPU B channel

eTPU B channel (output only)

—

GPIO153

ETPUB7

ETPUB23

—

GPIO

I/O

154 ETPUB7_ETPUB23_

GPIO154

eTPU B channel

eTPU B channel (output only)

—

GPIO154

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

155 ETPUB8_ETPUB24_

GPIO155

ETPUB8

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

P24

P25

P26

N24

N25

N26

ETPUB24

—

eTPU B channel (output only)

—

GPIO155

ETPUB9

ETPUB25

—

GPIO

I/O

156 ETPUB9_ETPUB25_

GPIO156

eTPU B channel

eTPU B channel (output only)

—

GPIO156

ETPUB10

ETPUB26

—

GPIO

I/O

157 ETPUB10_ETPUB26_

GPIO157

eTPU B channel

eTPU B channel (output only)

—

GPIO157

ETPUB11

ETPUB27

—

GPIO

I/O

158 ETPUB11_ETPUB27_

GPIO158

eTPU B channel

eTPU B channel (output only)

—

GPIO158

ETPUB12

ETPUB28

—

GPIO

I/O

159 ETPUB12_ETPUB28_

GPIO159

eTPU B channel

eTPU B channel (output only)

—

GPIO159

ETPUB13

ETPUB29

—

GPIO

I/O

160 ETPUB13_ETPUB29_

GPIO160

eTPU B channel

eTPU B channel (output only)

—

GPIO160

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

161 ETPUB14_ETPUB30_

GPIO161

ETPUB14

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

M25

M24

U26

U25

U24

U23

ETPUB30

—

eTPU B channel (output only)

—

GPIO161

ETPUB15

ETPUB31

—

GPIO

I/O

162 ETPUB15_ETPUB31_

GPIO162

eTPU B channel

eTPU B channel (output only)

—

GPIO162

ETPUB16

PCSA1

—

GPIO

I/O

163 ETPUB16_PCSA1_

GPIO163

eTPU B channel

DSPI A peripheral chip select

—

GPIO163

ETPUB17

PCSA2

—

GPIO

I/O

164 ETPUB17_PCSA2_

GPIO164

eTPU B channel

DSPI A peripheral chip select

—

GPIO164

ETPUB18

PCSA3

—

GPIO

I/O

165 ETPUB18_PCSA3_

GPIO165

eTPU B channel

DSPI A peripheral chip select

—

GPIO165

ETPUB19

PCSA4

—

GPIO

I/O

166 ETPUB19_PCSA4_

GPIO166

eTPU B channel

DSPI A peripheral chip select

—

GPIO166

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

167 ETPUB20_

ETPUB20

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

V26

V25

V24

W26

W25

W24

GPIO167

—

GPIO167

ETPUB21

—

GPIO

I/O

—

168 ETPUB21_

GPIO168

eTPU B channel

—

GPIO168

ETPUB22

—

GPIO

I/O

—

169 ETPUB22_

GPIO169

eTPU B channel

—

GPIO169

ETPUB23

—

GPIO

I/O

—

170 ETPUB23_

GPIO170

eTPU B channel

—

GPIO170

ETPUB24

—

GPIO

I/O

—

171 ETPUB24_

GPIO171

eTPU B channel

—

GPIO171

ETPUB25

—

GPIO

I/O

—

172 ETPUB25_

GPIO172

eTPU B channel

—

GPIO172

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

173 ETPUB26_

ETPUB26

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

V23

GPIO173

—

GPIO173

ETPUB27

—

GPIO

I/O

—

174 ETPUB27_

GPIO174

eTPU B channel

Y25

—

GPIO174

ETPUB28

—

GPIO

I/O

—

175 ETPUB28_

GPIO175

eTPU B channel

Y24

—

GPIO175

ETPUB29

—

GPIO

I/O

—

176 ETPUB29_

GPIO176

eTPU B channel

Y23

—

GPIO176

ETPUB30

—

GPIO

I/O

—

177 ETPUB30_

GPIO177

eTPU B channel

AA24

AB24

—

GPIO177

ETPUB31

—

GPIO

I/O

—

178 ETPUB31_

GPIO178

eTPU B channel

—

GPIO178

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

GPIO, IRQ, FlexRay

RESET⁸

440 TCRCLKC_

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

V_DDEH7

—/Up

B26

C25

C26

D25

D26

E24

GPIO440⁹

—

GPIO440

GPIO

—

441 ETPUC0_

GPIO441⁹

—

—/WKPCFG

—

GPIO441

GPIO

—

442 ETPUC1_

GPIO442⁹

—

GPIO442

GPIO

—

443 ETPUC2_

GPIO443⁹

—

GPIO443

GPIO

—

444 ETPUC3_

GPIO444⁹

—

GPIO444

GPIO

—

445 ETPUC4_

GPIO445⁹

—

GPIO445

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

446 ETPUC5_

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

V_DDEH7

—/WKPCFG

E25

E26

F23

F24

F25

F26

GPIO446⁹

—

GPIO446

GPIO

—

447 ETPUC6_

GPIO447⁹

—

GPIO447

GPIO

—

448 ETPUC7_

GPIO448⁹

—

GPIO448

—

GPIO

—

449 ETPUC8_

GPIO449⁹

—

GPIO449

—

GPIO

—

450 ETPUC9_IRQ0_

GPIO450⁹

IRQ0

—

External interrupt request

—

I/O

—

GPIO450

—

GPIO

451 ETPUC10__IRQ1_

GPIO451⁹

—

IRQ1

—

External interrupt request

—

I/O

GPIO451

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

452 ETPUC11_IRQ2_

—

V_DDEH7

—/WKPCFG

G23

G24

G25

G26

H23

H24

GPIO452⁹

IRQ2

—

External interrupt request

—

I/O

—

GPIO452

—

GPIO

453 ETPUC12_IRQ3_

GPIO453⁹

—

IRQ3

—

External interrupt request

—

I/O

—

GPIO453

—

GPIO

454 ETPUC13_3_IRQ4_

GPIO454⁹

—

IRQ4

—

External interrupt request

—

I/O

—

GPIO454

—

GPIO

455 ETPUC14_4_IRQ5_

GPIO455⁹

—

IRQ5

—

External interrupt request

—

I/O

—

I/O

—

GPIO455

—

GPIO

456 ETPUC15__

GPIO456⁹

—

GPIO456

—

GPIO

457 ETPUC16_FR_A_TX_

GPIO457⁹

—

FR_A_TX

—

FlexRay A transfer

—

I/O

GPIO457

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

458 ETPUC17_FR_A_RX_

GPIO458⁹

—

V_DDEH7

—/WKPCFG

H25

H26

J23

J24

J25

J26

FR_A_RX

—

FlexRay A receive

—

I/O

—

GPIO458

—

GPIO

459 ETPUC18_FR_A_TX_EN_

—

GPIO459

FR_A_TX_EN

—

FlexRay A transfer enable

—

I/O

—

GPIO459

—

GPIO

460 ETPUC19_TXDA_

GPIO460⁹

—

TXDA

—

eSCI A transmit

—

I/O

—

GPIO460

—

GPIO

461 ETPUC20_RXDA _

GPIO461⁹

—

RXDA

—

eSCI A receive

—

I/O

—

GPIO461

—

GPIO

462 ETPUC21_TXDB_

GPIO462⁹

—

TXDB

—

eSCI B transmit

—

I/O

—

GPIO462

—

GPIO

463 ETPUC22_RXDB_

GPIO463⁹

—

RXDB

—

eSCI B receive

—

I/O

GPIO463

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

464 ETPUC23_PCSD5_

GPIO464⁹

—

V_DDEH7

—/WKPCFG

K23

K24

K25

PCSD5

MAA0

MAB0

GPIO464

—

DSPI D peripheral chip select

ADC A Mux Address 0

ADC B Mux Address 0

GPIO

I/O

—

465 ETPUC24_PCSD4_

GPIO465⁹

—

PCSD4

MAA1

MAB1

GPIO465

—

DSPI D peripheral chip select

ADC A Mux Address 1

ADC B Mux Address 1

GPIO

I/O

—

466 ETPUC25_PCSD3_

GPIO466⁹

—

PCSD3

MAA2

MAB2

GPIO466

—

DSPI D peripheral chip select

ADC A Mux Address 2

ADC B Mux Address 2

GPIO

I/O

—

467 ETPUC26_PCSD2_

GPIO467⁹

—

V_DDEH7

—/WKPCFG

K26

L23

PCSD2

—

DSPI D peripheral chip select

—

I/O

—

GPIO467

—

GPIO

468 ETPUC27_PCSD1_

GPIO468⁹

—

V_DDEH7

PCSD1

—

DSPI D peripheral chip select

—

I/O

GPIO468

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

469 ETPUC28_PCSD0_

GPIO469⁹

—

I/O

—

I/O

—

I/O

—

I/O

—

V_DDEH7

—/WKPCFG

L24

L25

L26

M23

PCSD0

—

DSPI D peripheral chip select

—

GPIO469

—

GPIO

470 ETPUC29_SCKD_

GPIO470⁹

—

SCKD

—

DSPI D clock

—

GPIO470

—

GPIO

471 ETPUC30_SOUTD_

GPIO471⁹

—

SOUTD

—

DSPI D data output

—

I/O

—

GPIO471

—

GPIO

472 ETPUC31_SIND_

GPIO472⁹

—

SIND

—

DSPI D data input

—

I/O

GPIO472

GPIO

eMIOS

179 EMIOS0_ETPUA0_

GPIO179

EMIOS0

ETPUA0

—

eMIOS channel

eTPU A channel

—

I/O

V_DDEH4

—/WKPCFG

AE10

AF10

—

GPIO179

EMIOS1

ETPUA1

—

GPIO

I/O

180 EMIOS1_ETPUA1_

GPIO180

eMIOS channel

eTPU A channel

—

V_DDEH4

—

GPIO180

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

181 EMIOS2_ETPUA2_

GPIO181

EMIOS2

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

AD11

AE11

AF11

AD12

AE12

AF12

ETPUA2

—

eTPU A channel

—

GPIO181

EMIOS3

ETPUA3

—

GPIO

I/O

182 EMIOS3_ETPUA3_

GPIO182

eMIOS channel

eTPU A channel

—

GPIO182

EMIOS4

ETPUA4

—

GPIO

I/O

183 EMIOS4_ETPUA4_

GPIO183

eMIOS channel

eTPU A channel

—

GPIO183

EMIOS5

ETPUA5

—

GPIO

I/O

184 EMIOS5_ETPUA5_

GPIO184

eMIOS channel

eTPU A channel

—

GPIO184

EMIOS6

ETPUA6

—

GPIO

I/O

185 EMIOS6_ETPUA6_

GPIO185

eMIOS channel

eTPU A channel

—

GPIO185

EMIOS7

ETPUA7

—

GPIO

I/O

186 EMIOS7_ETPUA7_

GPIO186

eMIOS channel

eTPU A channel

—

GPIO186

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

187 EMIOS8_ETPUA8_

GPIO187

EMIOS8

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

AC13

AD13

AE13

AF13

AF14

AE14

ETPUA8

—

eTPU A channel

—

I/O

GPIO187

EMIOS9

ETPUA9

—

GPIO

188 EMIOS9_ETPUA9_

GPIO188

eMIOS channel

eTPU A channel

—

I/O

GPIO188

EMIOS10

SCKD

GPIO

189 EMIOS10_SCKD_

GPIO189

eMIOS channel

DSPI D clock

—

I/O

GPIO189

EMIOS11

SIND

GPIO

190 EMIOS11_SIND_

GPIO190

eMIOS channel

DSPI D data input

—

I/O

GPIO190

EMIOS12

SOUTC

—

GPIO

191 EMIOS12_SOUTC_

GPIO191

eMIOS channel

DSPI C data output

—

I/O

GPIO191

EMIOS13

SOUTD

—

GPIO

192 EMIOS13_SOUTD_

GPIO192

eMIOS channel

DSPI D data output

—

I/O

GPIO192

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

193 EMIOS14_IRQ0_

EMIOS14

eMIOS channel

V_DDEH4

—/WKPCFG

AC14

AD14

AF15

AE15

AC15

AD15

GPIO193

IRQ0

External interrupt request

FlexCAN D transmit

GPIO

CNTXD

GPIO193

EMIOS15

IRQ1

I/O

194 EMIOS15_IRQ1_

GPIO194

eMIOS channel

External interrupt request

FlexCAN D receive

GPIO

CNRXD

GPIO194

EMIOS16

ETPUB0

FR_DBG[3]

GPIO195

EMIOS17

ETPUB1

FR_DBG[2]

GPIO196

EMIOS18

ETPUB2

FR_DBG[1]

GPIO197

EMIOS19

ETPUB3

FR_DBG[0]

GPIO198

I/O

195 EMIOS16_ETPUB0_

GPIO195

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

196 EMIOS17_ETPUB1_

GPIO196

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

197 EMIOS18_ETPUB2_

GPIO197

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

198 EMIOS19_ETPUB3_

GPIO198

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

199 EMIOS20_ETPUB4_

GPIO199

EMIOS20

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

AF16

AE16

AC16

AD16

AF17

AE17

ETPUB4

—

eTPU B channel

—

GPIO199

EMIOS21

ETPUB5

—

GPIO

I/O

200 EMIOS21_ETPUB5_

GPIO200

eMIOS channel

eTPU B channel

—

GPIO200

EMIOS22

ETPUB6

—

GPIO

I/O

201 EMIOS22_ETPUB6_

GPIO201

eMIOS channel

eTPU B channel

—

GPIO201

EMIOS23

ETPUB7

—

GPIO

I/O

202 EMIOS23_ETPUB7_

GPIO202

eMIOS channel

eTPU B channel

—

GPIO202

EMIOS24

PCSB0

—

GPIO

I/O

—

203 EMIOS24_PCSB0_

GPIO203

eMIOS channel

DSPI B peripheral chip select

—

GPIO203

EMIOS25

PCSB1

—

GPIO

I/O

204 EMIOS25_PCSB1_

GPIO204

eMIOS channel

DSPI B peripheral chip select

—

GPIO204

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

432 EMIOS26_PCSB2_

GPIO432

EMIOS26

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

AD17

AC17

AF18

AE18

AD18

AC18

PCSB2

—

DSPI B peripheral chip select

—

GPIO432

EMIOS27

PCSB3

—

GPIO

I/O

433 EMIOS27_PCSB3_

GPIO433

eMIOS channel

DSPI B peripheral chip select

—

GPIO433

EMIOS28

PCSC0

—

GPIO

I/O

—

434 EMIOS28_PCSC0_

GPIO434

eMIOS channel

DSPI C peripheral chip select

—

GPIO434

EMIOS29

PCSC1

—

GPIO

I/O

435 EMIOS29_PCSC1_

GPIO435

eMIOS channel

DSPI C peripheral chip select

—

GPIO435

EMIOS30

PCSC2

—

GPIO

I/O

436 EMIOS30_PCSC2_

GPIO436

eMIOS channel

DSPI C peripheral chip select

—

GPIO436

EMIOS31

PCSC5

—

GPIO

I/O

437 EMIOS31_PCSC5_

GPIO437

eMIOS channel

DSPI C peripheral chip select

—

GPIO437

GPIO

I/O

eQADC

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

—

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

ANA0¹⁰

eQADC A analog input

AE/up-

down

V_{DDA_A1}

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

ANA1¹⁰

ANA2¹⁰

ANA3¹⁰

ANA4¹⁰

ANA5¹⁰

ANA6¹⁰

ANA7¹⁰

eQADC A analog input

AE/up-

down

AE/up-

down

AE/up-

down

AE/up-

down

AE/up-

down

AE/up-

down

AE/up-

down

—

ANA8

ANA9

ANA8

eQADC A analog input

V_{DDA_A1}

ANA8

ANA9

ANA8

ANA9

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

D10

C10

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

—

ANA20

eQADC A analog input

V_{DDA_A1}

V_{DDA_A0}

V_{DDA_B1}

V_{DDA_B0}

V_{DDA_B1}

V_{DDA_B0}

ANA20

ANA21

ANA22

ANA23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

ANA20

ANA21

ANA22

ANA23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

D11

C11

D12

C12

B12

D13

C13

B13

A13

B14

C14

D14

A14

B15

C15

D15

A15

C16

C17

D16

C18

ANA21

ANA22

ANA23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

ANA21

ANA22

ANA23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

eQADC A analog input

eQADC A and B shared analog input

eQADC B analog input

AE/up-

down

—

ANB1

ANB2

ANB1

ANB2

eQADC B analog input

AE/up-

down

V_{DDA_B0}

ANB1

ANB2

ANB1

ANB2

D17

D18

AE/up-

down

V_{DDA_B0}

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

—

ANB3

ANB4

ANB5

ANB6

ANB7

ANB3

eQADC B analog input

AE/up-

down

V_{DDA_B0}

ANB3

ANB4

ANB5

ANB6

ANB7

ANB3

ANB4

ANB5

ANB6

ANB7

D19

C19

C20

B19

A20

ANB4

ANB5

ANB6

ANB7

eQADC B analog input

AE/up-

down

AE/up-

down

AE/up-

down

AE/up-

down

—

ANB8

ANB9

ANB8

eQADC B analog input

ADC A Voltage reference high

V_{DDA_B0}

V_{RH_A}

ANB8

ANB9

ANB8

ANB9

B20

D20

B21

A21

C21

D21

A22

B22

C22

A23

B23

C23

D22

A24

B24

A25

A12

ANB9

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB17

ANB18

ANB19

ANB20

ANB21

ANB22

ANB23

VRH_A

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB17

ANB18

ANB19

ANB20

ANB21

ANB22

ANB23

VRH_A

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB17

ANB18

ANB19

ANB20

ANB21

ANB22

ANB23

VRH_A

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB17

ANB18

ANB19

ANB20

ANB21

ANB22

ANB23

VRH_A

VDDINT

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

—

VRL_A

ADC A Voltage reference low

ADC B Voltage reference high

ADC B Voltage reference low

ADC B Reference bypass capacitor

ADC A Reference bypass capacitor

Internal logic supply input

ADC A Reference bypass capacitor

Ground

VSSINT

VDDINT

VSSINT

V_{RL_A}

V_{RH_B}

VRL_A

VRH_B

VRL_A

VRH_B

A11

A19

A18

B18

B11

VRH_B

VRL_B

V_{RL_B}

VRL_B

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCA1

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

REFBYPCB1

REFBYPCB

REFBYPCA

VDDA_A

V_{DDA_B0}

V_{DDA_A1}

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

VDDE V_{DDA_A0}

VDDE V_{DDA_A1}

VDDA_A

REFBYPCA1

VSSA_A

V_{DDA_A1}REFBYPCA1 REFBYPCA1

A10

B10

A16

B16

B17

A17

VSSE V_{SSA_A1}

VDDE V_{DDA_B0}

VDDE V_{DDA_B1}

VSSE V_{SSA_B0}

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

VDDA_B

Internal logic supply input

Ground

VDDA_B

VSSA_B

REFBYPCB1

ADC B Reference bypass capacitor

V_{DDA_B0}REFBYPCB1 REFBYPCB1

FlexRay

248 FR_A_TX_

GPIO248

FR_A_TX

—

FlexRay A transfer

—

I/O

V_DDE2

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

AD4

AE3

—

GPIO248

FR_A_RX

—

GPIO

249 FR_A_RX_

GPIO249

FlexRay A receive

V_DDE2

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

—

I/O

—

GPIO249

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

250 FR_A_TX_EN_

FR_A_TX_EN

FlexRay A transfer enable

—

I/O

V_DDE2

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

AF3

AD5

AE4

AF4

GPIO250

—

GPIO250

FR_B_TX

—

GPIO

251 FR_B_TX_

GPIO251

FlexRay B transfer

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

—

I/O

—

GPIO251

FR_B_RX

—

GPIO

252 FR_B_RX_

GPIO252

FlexRay B receive

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

—

I/O

—

GPIO252

FR_B_TX_EN

—

GPIO

253 FR_B_TX_EN_

GPIO253

FlexRay B transfer enable

—/Up

(–/– for Rev.1

of the device) of the device)

—/Up

(–/– for Rev.1

—

I/O

—

GPIO253

GPIO

FlexCAN

83 CNTXA_TXDA_

GPIO83

CNTXA

TXDA

—

FlexCAN A transmit

V_DDEH4

—/Up

AF19

AE19

eSCI A transmit

—

I/O

GPIO83

CNRXA

RXDA

—

GPIO

84 CNRXA_RXDA_

GPIO84

FlexCAN A receive

eSCI A receive

—

V_DDEH4

—

I/O

GPIO84

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

85 CNTXB_PCSC3_

CNTXB

FlexCAN B transmit

V_DDEH4

—/Up

AD19

AC19

AF20

AE20

AD20

AC20

GPIO85

PCSC3

—

DSPI C peripheral chip select

—

I/O

GPIO85

CNRXB

PCSC4

—

GPIO

86 CNRXB_PCSC4_

GPIO86

FlexCAN B receive

DSPI C peripheral chip select

—

I/O

GPIO86

CNTXC

PCSD3

—

GPIO

87 CNTXC_PCSD3_

GPIO87

FlexCAN C transmit

DSPI D peripheral chip select

—

I/O

GPIO87

CNRXC

PCSD4

—

GPIO

88 CNRXC_PCSD4_

GPIO88

FlexCAN C receive

DSPI D peripheral chip select

—

I/O

GPIO88

CNTXD

—

GPIO

246 CNTXD_

GPIO246

FlexCAN D transmit

—

I/O

—

GPIO246

CNRXD

—

GPIO

247 CNRXD_

GPIO247

FlexCAN D receive

—

I/O

—

GPIO247

GPIO

eSCI

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

89 TXDA_

TXDA

eSCI A transmit

—

I/O

V_DDEH1

V_DDEH4

V_DDEH5

—/Up

GPIO89

—

GPIO89

RXDA

—

GPIO

90 RXDA _

GPIO90

eSCI A receive

—

GPIO90

TXDB

PCSD1

—

GPIO

91 TXDB_PCSD1_

GPIO91

eSCI B transmit

DSPI D peripheral chip select

—

I/O

GPIO91

RXDB

PCSD5

—

GPIO

92 RXDB_PCSD5_

GPIO92

eSCI B receive

DSPI D peripheral chip select

—

I/O

GPIO92

TXDC

ETRIG0

—

GPIO

244 TXDC_ETRIG0_

GPIO244

eSCI C transmit

AF23

AD22

eQADC trigger input

—

I/O

GPIO244

RXDC

—

GPIO

245 RXDC_

GPIO245

eSCI C receive

—

I/O

—

GPIO245

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

DSPI

RESET⁸

93 SCKA_PCSC1_

SCKA

DSPI A clock

I/O

V_DDEH3

—/Up

AD8

AF7

AD7

AE6

AC6

AC7

GPIO93

PCSC1

—

DSPI C peripheral chip select

—

I/O

GPIO93

SINA

PCSC2

—

GPIO

94 SINA_PCSC2_

GPIO94

DSPI A data input

DSPI C peripheral chip select

—

I/O

GPIO94

SOUTA

PCSC5

—

GPIO

95 SOUTA_PCSC5_

GPIO95

DSPI A data output

DSPI C peripheral chip select

—

I/O

GPIO95

PCSA0

PCSD2

—

GPIO

96 PCSA0_PCSD2_

GPIO96

DSPI A peripheral chip select

DSPI D peripheral chip select

—

I/O

GPIO96

PCSA1

—

GPIO

97 PCSA1_

GPIO97

DSPI A peripheral chip select

—

I/O

—

GPIO97

PCSA2

—

GPIO

98 PCSA2_

GPIO98

DSPI A peripheral chip select

—

I/O

—

GPIO98

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

99 PCSA3_

PCSA3

DSPI A peripheral chip select

—

I/O

V_DDEH3

—/Up

AE7

AE5

AD6

AE8

AE9

AF9

GPIO99

—

GPIO99

PCSA4

—

GPIO

100 PCSA4_

GPIO100

DSPI A peripheral chip select

—

I/O

—

GPIO100

PCSA5

ETRIG1

—

GPIO

101 PCSA5_ETRIG1_

GPIO101

DSPI A peripheral chip select

eQADC trigger input

—

I/O

—

I/O

GPIO101

SCKB

—

GPIO

102 SCKB_

GPIO102

DSPI B clock

—

GPIO102

SINB

—

GPIO

103 SINB_

GPIO103

DSPI B data input

—

I/O

—

GPIO103

SOUTB

—

GPIO

104 SOUTB_

GPIO104

DSPI B data output

—

I/O

—

GPIO104

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

105 PCSB0_PCSD2_

PCSB0

DSPI B peripheral chip select

I/O

V_DDEH3

—/Up

AD9

AC9

AF8

GPIO105

PCSD2

—

DSPI D peripheral chip select

—

I/O

GPIO105

PCSB1

PCSD0

—

GPIO

106 PCSB1_PCSD0_

GPIO106

DSPI B peripheral chip select

DSPI D peripheral chip select

I/O

—

I/O

—

GPIO106

PCSB2

SOUTC

—

GPIO

107 PCSB2_SOUTC_

GPIO107

DSPI B peripheral chip select

DSPI C data output

—

I/O

GPIO107

PCSB3

SINC

GPIO

108 PCSB3_SINC_

GPIO108

DSPI B peripheral chip select

AD10

AC8

AF6

DSPI C data input

—

I/O

GPIO108

PCSB4

SCKC

—

GPIO

109 PCSB4_SCKC_

GPIO109

DSPI B peripheral chip select

DSPI C clock

I/O

—

I/O

—

GPIO109

PCSB5

PCSC0

—

GPIO

110 PCSB5_PCSC0_

GPIO110

DSPI B peripheral chip select

DSPI C peripheral chip select

I/O

—

I/O

—

GPIO110

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

235 SCKC_SCK_C_LVDSP_

GPIO235

SCKC

DSPI C clock

I/O

MH+

LVDS

V_DDEH4

—/Up

AD21

AE22

AF21

AE21

AC22

SCK_C_LVDSP

LVDS+ downstream signal positive

output clock

—

I/O

GPIO235

SINC

GPIO

236 SINC_SCK_C_LVDSM_

GPIO236

DSPI C data input

MH+

LVDS

SCK_C_LVDSM

LVDS– downstream signal negative

output clock

—

I/O

GPIO236

SOUTC

GPIO

237 SOUTC_SOUT_C_LVDSP_

GPIO237

DSPI C data output

MH+

LVDS

SOUT_C_LVDSP

LVDS+ downstream signal positive

output data

—

I/O

GPIO237

PCSC0

GPIO

238 PCSC0_SOUT_C_LVDSM_

GPIO238

DSPI C peripheral chip select

MH+

LVDS

SOUT_C_LVDSM

LVDS– downstream signal negative

output data

—

I/O

GPIO238

PCSC1

—

GPIO

239 PCSC1_

GPIO239

DSPI C peripheral chip select

—

GPIO239

GPIO

I/O

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

240 PCSC2_GPIO240

PCSC2

DSPI C peripheral chip select

—

I/O

V_DDEH5

—/Up

AE23

AD23

AF24

AE24

—

GPIO240

PCSC3

—

GPIO

241 PCSC3_GPIO241

242 PCSC4_GPIO242

243 PCSC5_GPIO243

DSPI C peripheral chip select

—

I/O

—

GPIO241

PCSC4

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO242

PCSC5

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO243

GPIO

Reset and Clocks

—

RESET

External reset input

External reset output

V_DDEH1

RESET/Up

230 RSTOUT

RSTOUT

V_DDEH1RSTOUT/Low

RSTOUT/

High

212 BOOTCFG1_IRQ3_

GPIO212

BOOTCFG1

IRQ3

Boot configuration

V_DDEH1

BOOTCFG/

Down

Input/Down

External interrupt request

—

I/O

GPIO212

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

213 WKPCFG_NMI_

WKPCFG

Weak pull configuration input

Critical interrupt to core¹¹

—

V_DDEH1

WKPCFG/Up

PLLCFG/Up

Input/Up

GPIO213

NMI

—

GPIO213

PLLCFG0

IRQ4

GPIO

208 PLLCFG0_IRQ4_

GPIO208

FMPLL mode configuration input

External interrupt request

—

Input/Up

—

I/O

GPIO208

PLLCFG1

IRQ5

GPIO

209 PLLCFG1_IRQ5_

GPIO209

FMPLL mode configuration input

External interrupt request

DSPI D data output

GPIO

Input/Up

(for Rev2 of

the device:

—/Up)

SOUTD

GPIO209

PLLCFG2

I/O

—

PLLCFG2

FMPLL mode configuration input

PLLCFG/

Down

PLLCFG/

Down

—

XTAL

Crystal oscillator output

Crystal oscillator input

V_DD33

V_DDE2

XTAL

AC26

AB26

AD1

EXTAL

ENGCLK

EXTAL

214 ENGCLK

EBI engineering clock output

ENGCLK/

Enabled

ENGCLK/

Enabled

Note: EXTCLK (External clock input)

selected through SIU register)

JTAG and Nexus

(see footnote¹²about resets)

–

—

EVTI

Nexus event in

V_DDE2

—/Up

EVTI/Up

EVTO/HI

227 EVTO

(the BAM uses this pin to

EVTO

Nexus event out

ABS/Up

select if auto baud rate is on

or off)

Disabled¹⁴

–

219 MCKO

MCKO

Nexus message clock out

V_DDE2

O/Low

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

–

220 MDO0_GPIO220

MDO0¹⁵

Nexus message data out

—

I/O

V_DDE2

O/Low

MDO0/Low

—/Down

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

GPIO220

MDO1¹⁵

—

GPIO

–

221 MDO1_GPIO221

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO221

MDO2¹⁵

—

GPIO

–

222 MDO2_GPIO222

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO222

MDO3¹⁵

—

GPIO

–

223 MDO3_GPIO223

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO223

MDO4¹⁵

—

GPIO

–

75 MDO4_GPIO75

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO75

MDO5¹⁵

—

GPIO

–

76 MDO5_GPIO76

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO76

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

–

77 MDO6_GPIO77

MDO6¹⁵

Nexus message data out

—

I/O

V_DDE2

O/Low

—/Down

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

GPIO77

MDO7¹⁵

—

GPIO

–

78 MDO7_GPIO78

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO78

MDO8¹⁵

—

GPIO

–

79 MDO8_GPIO79

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO79

MDO9¹⁵

—

GPIO

–

80 MDO9_GPIO80

Nexus message data out

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

I/O

—

GPIO80

MDO10¹⁵

—

GPIO

–

81 MDO10_GPIO81

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO81

MDO11¹⁵

—

GPIO

–

82 MDO11_GPIO82

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO82

GPIO

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

–

231 MDO12_GPIO231

MDO12¹⁵

Nexus message data out

—

I/O

V_DDE2

O/Low

—/Down

AA1

AA2

AA3

—

GPIO231

MDO13¹⁵

—

GPIO

–

232 MDO13_GPIO232

233 MDO14_GPIO233

234 MDO15_GPIO234

Nexus message data out

—

I/O

—

GPIO232

MDO14¹⁵

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO233

MDO15¹⁵

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO234

MSEO0¹⁵

MSEO1¹⁵

RDY

GPIO

–

224 MSEO0

225 MSEO1

226 RDY

Nexus message start/end out

Nexus ready output

JTAG test clock input

JTAG test data input

JTAG test data output

JTAG test mode select input

JTAG TAP controller enable

V_DDE2

O/Low

MSEO/HI

RDY/HI

O/Low

—

TCK

TDI

TCK

TCK/Down

TDI/Up

TCK/Down

TDI/Up

AB2

AC2

AB1

AB3

TDI

228 TDO

TDO

TDO/Up

TMS/Up

TDO/Up

TMS/Up

—

TMS

JCOMP

JCOMP/Down JCOMP/Down

Table 2. Signal Properties and Muxing Summary (continued)

State

during

RESET⁷

State

after

Package

Location

(416)

Signal Name²

Function⁴

Function Summary

RESET⁸

—

TEST

Test mode select (not for customer

use)

V_DDEH1

TEST/Down

—

VDDSYN

VSSSYN

VSTBY

VDDSYN

VSSSYN

VSTBY

Clock synthesizer power input

Clock synthesizer ground input

SRAM standby power input

VDDE

VSSE

VHV

V_DDSYN

V_DDEH1

V_DDREG

VDDSYN

VSSSYN

VSTBY

VDDSYN

VSSSYN

VSTBY

AD26

AA26

REGSEL

Selects regulator mode

(Linear/Switch mode)

REGSEL

W23

—

REGCTL

Regulator controller output to

base/gate of power transistor

V_DDREG

REGCTL

Y26

—

VSSFL

Tie to V_SS

VSS

V_DDREG

VSSFL

AB25

AA25

VDDREG

Source voltage for on-chip regulators

and Low voltage detect circuits

VDDINT V_DDREG

VDDREG

The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not

have GPIO functionality, this number is the PCR number.

The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices

and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.

P/A/G stands for Primary/Alternate/GPIO. This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.

Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions

are designated in the PA field of the SIU_PCRn registers except where explicitly noted.

MH = High voltage, medium speed

F = Fast speed

FS = Fast speed with slew

AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)

VHV = Very high voltage

VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V

(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.

The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in

this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS —

Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are

off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates

the pin is enabled.

The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the

pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.

This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.

During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when

the system clock propagates through the device.

¹¹NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.

¹²Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO

and MCKO are also dependent on trace (RPM or FPM) being enabled.

¹³The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC.

SIU values have no effect on the function of these pins once enabled.

¹⁴MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).

¹⁵Do not connect pin directly to a power supply or ground.

Electrical characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications for the PXR40.

The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These

specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these

specifications will be met. Finalized specifications will be published after complete characterization and device qualifications

have been completed.

5.1

Maximum ratings

Table 3. Absolute maximum ratings

Spec

Characteristic

Symbol

Min

Max

Unit

1.2 V Core Supply Voltage

SRAM Standby Voltage

Clock Synthesizer Voltage

V_DD

V_STBY

V_DDSYN

V_DD33

–0.3

–0.1

–0.3

–0.1

–3 ¹¹

2.0 ²

3,4

6.4

5.3 ^4,5

6.4 ^3,4

5.3 ^4,5

6.4 ^3,4

0.1

I/O Supply Voltage (I/O buffers and predrivers)

Analog Supply Voltage (reference to V_SSA

)

V_DDA

I/O Supply Voltage (fast I/O pads)

V_DDE

V_DDEH

V_DDREG

I/O Supply Voltage (medium I/O pads)

Voltage Regulator Input Supply Voltage

Analog Reference High Voltage (reference to V_RL

V_SSto V_SSA⁸Differential Voltage

)

V_RH

V_SS– V_SSA

V_RH– V_RL

V_REFDifferential Voltage

6.4 ^3,4

0.3

V_RLto V_SSADifferential Voltage

V_RL– V_SSA

V_DD33– V_DDSYN

V_SSSYN– V_SS

I_MAXD

V_DD33to V_DDSYNDifferential Voltage

_SSSYNto V_SSDifferential Voltage

0.1

Maximum Digital Input Current ¹⁰(per pin, applies to all

digital pins)

3 ¹¹

Maximum Analog Input Current ¹²(per pin, applies to all

analog pins)

I_MAXA

– 3 ⁷

–40.0

–55.0

3 ^7,11

150.0

^oC

Maximum Operating Temperature Range ¹³– Die Junction

Temperature

T_J

Storage Temperature Range

T_stg

T_sdr

^oC

Maximum Solder Temperature ¹⁴

Pb-free package

—

260.0

245.0

SnPb package

Moisture Sensitivity Level ¹⁵

MSL

—

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,

and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or

cause permanent damage to the device.

2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining.

6.4 V for 10 hours cumulative time, 5.25 V +10% for time remaining.

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

5.3 V for 10 hours cumulative time, 3.60 V +10% for time remaining.

PXR40 has two analog power supply pins on the pinout: VDDA_A and VDDA_B.

PXR40 has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.

PXR40 has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.

PXR40 has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.

¹⁰Total injection current for all pins must not exceed 25 mA at maximum operating voltage.

¹¹Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated

time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or V_DDEHsupply when under

this stress condition.

¹²Total injection current for all analog input pins must not exceed 15 mA.

¹³Lifetime operation at these specification limits is not guaranteed.

¹⁴Solder profile per CDF-AEC-Q100.

¹⁵Moisture sensitivity per JEDEC test method A112.

5.2

Thermal characteristics

Table 4. Thermal characteristics, 416-pin TEPBGA package

Characteristic

Symbol

Value

Unit

Junction to Ambient ^2,3Natural Convection (Single layer board)

Junction to Ambient ^2,4Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁵

R_JA

R_JMA

R_JB

R_JC

_JT

°C/W

Junction to Case ⁶

Junction to Package Top ⁷Natural Convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization. This data is PRELIMINARY based on similar package used on other devices.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.2.1

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

* P )

Eqn. 1

JA

where:

T = ambient temperature for the package ( C)

= junction to ambient thermal resistance ( C/W)

JA

P = power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which

value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to

ambient thermal resistance:

= R

+ R

CA

Eqn. 2

JA

JC

where:

= junction to ambient thermal resistance ( C/W)

JA

JC

CA

= junction to case thermal resistance ( C/W)

= case to ambient thermal resistance ( C/W)

is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to

JC

ambient thermal resistance, R

. For instance, the user can change the size of the heat sink, the air flow around the device, the

CA

interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit

board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal

Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at

the top center of the package case using the following equation:

T = T + ( x P )

Eqn. 3

where:

T = thermocouple temperature on top of the package ( C)



= thermal characterization parameter ( C/W)

P = power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

San Jose, CA 95134

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

•

C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine

Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic

Packaging and Production, pp. 53-58, March 1998.

B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application

in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

5.3

EMI (Electromagnetic Interference) characteristics

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go

to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the

device's radiated emissions operating behaviors.

Table 5. EMC radiated emissions operating behaviors: 416 BGA

f_OSC

f_SYS

Frequency

band (MHz)

Level

(max.)

Symbol

Description

Conditions

Unit Notes

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

I²

dBV

150–500

500–1000

1, 3

CLK on

FM off

IEC and SAE level

—

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

K⁵

dBV

150–500

500–1000

1,3

CLK off

IEC and SAE level

—

FM on⁴

Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell

Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM

(GTEM) Cell Method.

I = 36 dBV

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated

Circuits—TEM/Wideband TEM (GTEM) Cell Method.

“FM on” = FM depth of ±2%

K = 30 dBV

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.4

ESD characteristics

1,2

Table 6. ESD ratings

Spec

Characteristic

Symbol

V_HBM

V_CDM

Value

Unit

ESD for Human Body Model (HBM)

ESD for Charged Device Model (CDM)

2000

750 (corners)

500 (other)

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the

device specification.

5.5

PMC/POR/LVI electrical specifications

Note: For ADC internal resource measurements, see Table 18 in Section 5.9.1 ADC internal resource measurements.

Table 7. PMC operating conditions

Name

V_DDREG

Parameter

Condition

Min

Typ

Max

Unit

Note

Supply voltage VDDREG

5V nominal

LDO5V / SMPS5V mode

4.5

5.5

V_DDREG

V_DD33

V_DD

Supply voltage VDDREG

3V nominal

LDO3V mode

3.0

3.3

1.2

3.6

Supply voltage VDDSYN / LDO3V mode

V_DD333.3V nominal

Supply voltage VDD

1.2V nominal

—

1.14

1.32

Voltage should be higher than maximum V_LVDREGto avoid LVD event

Applies to both V_DD33(flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum V_LVD33to avoid

LVD event

Voltage should be higher than maximum V_LVD12to avoid LVD event

NOTE

In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”.

Table 8. PMC electrical specifications

Name

V_BG

Parameter

Min

Typ

Max

Unit

Nominal bandgap reference voltage

Untrimmed bandgap reference voltage

Nominal VRC regulated 1.2V output VDD

0.608

V_BG– 5%

—

0.620

V_BG

1.2

0.632

V_BG+ 5%

—

V_DD12OUT

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 8. PMC electrical specifications (continued)

Name

Parameter

Min

Typ

Max

Unit

—

Untrimmed VRC 1.2V output variation before

band gap trim (unloaded)

Note: Voltage should be higher than maximum

V_LVD12to avoid LVD event

_DD12OUT– 8% V_DD12OUTV_DD12OUT+ 17%

Trimmed VRC 1.2V output variation after band

gap trim (REGCTL load max. 20mA, VDD load

max. 1A)¹

V_DD12OUT– 5% V_DD12OUTV_DD12OUT+ 10%

2c V_STEPV12

Trimming step V_DD12OUT

POR rising VDD 1.2V

POR VDD 1.2V variation

POR 1.2V hysteresis

—

0.7

—

V_PORC

—

V_PORC– 30%

V_PORC

V_PORC+ 30%

—

V_LVD12

Nominal rising LVD 1.2V

1.100

Note: ~V_DD12OUT× 0.87

—

Untrimmed LVD 1.2V variation before band gap

trim

Note: Rising VDD

V_LVD12– 6%

V_LVD12

V_LVD12+ 6%

—

Trimmed LVD 1.2V variation after band gap trim

Rising VDD

V_LVD12– 3%

V_LVD12

V_LVD12+ 3%

LVD 1.2V Hysteresis

—

4d V_LVDSTEP12

Trimming step LVD 1.2V

I_REGCTL

—

VRC DC current output on REGCTL

Voltage regulator 1.2V current consumption

VDDREG

V_DD33OUT

—

Nominal V_REG3.3V output

—

3.3

—

Untrimmed V_REG3.3V output variation before

band gap trim (unloaded)

V_DD33OUT– 6% V_DD33OUTV_DD33OUT+ 10%

Note: Rising VDDSYN

—

Trimmed V_REG3.3V output variation after band V_DD33OUT– 5% V_DD33OUTV_DD33OUT+ 10%

gap trim (max. load 80mA)

7c V_STEPV33

Trimming step VDDSYN

—

V_LVD33

Nominal rising LVD 3.3V

2.950

Note: ~V_DD33OUT× 0.872

—

Untrimmed LVD 3.3V variation before band gap

trim

Note: Rising VDDSYN

_LVD33– 5%

V_LVD33

V_LVD33+ 5%

—

Trimmed LVD 3.3V variation after bad gap trim

Note: Rising VDDSYN

V_LVD33– 3%

V_LVD33

V_LVD33+ 3%

LVD 3.3V Hysteresis

—

8d V_LVDSTEP33

Trimming step LVD 3.3V

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 8. PMC electrical specifications (continued)

Name

I_DD33

Parameter

Min

Typ

Max

Unit

V_{REG =}4.5 V, max DC output current

V_REG= 4.25 V, max DC output current, crank

condition

—

Note: Max current supplied by VDDSYN that

does not cause it to drop below V_LVD33

—

Voltage regulator 3.3V current consumption

VDDREG

Note: Except I_DD33

—

11 V_PORREG

11a —

POR rising on VDDREG

POR VDDREG variation

POR VDDREG hysteresis

2.00

V_PORREG– 30% V_PORREGV_PORREG+ 30%

11b —

—

250

—

12 V_LVDREG

Nominal rising LVD VDDREG

(LDO3V / LDO5V mode)

2.950

12a —

12b —

12c —

Untrimmed LVD VDDREG variation before band V_LVDREG– 5% V_LVDREG

gap trim

Note: Rising VDDREG

V_LVDREG+ 5%

Trimmed LVD VDDREG variation after band gap V_LVDREG– 3% V_LVDREG

trim

Note: Rising VDDREG

V_LVDREG+ 3%

LVD VDDREG Hysteresis

(LDO3V / LDO5V mode)

—

12d V_LVDSTEPREGTrimming step LVD VDDREG

(LDO3V / LDO5V mode)

—

13 V_LVDREG

Nominal rising LVD VDDREG

(SMPS5V mode)

4.360

13a —

Untrimmed LVD VDDREG variation before band V_LVDREG– 5% V_LVDREG

V_LVDREG+ 5%

gap trim

Note: Rising VDDREG

13b —

13c —

Trimmed LVD VDDREG variation after band gap V_LVDREG– 3% V_LVDREG

trim

Note: Rising VDDREG

V_LVDREG+ 3%

LVD VDDREG Hysteresis

(SMPS5V mode)

—

13d V_LVDSTEPREGTrimming step LVD VDDREG

(SMPS5V mode)

14 V_LVDA

14a —

Nominal rising LVD VDDA

—

4.60

—

Untrimmed LVD VDDA variation before band

gap trim

V_LVDA– 5%

V_LVDA

V_LVDA+ 5%

14b —

14c —

Trimmed LVD VDDA variation after band gap

trim

V_LVDA– 3%

V_LVDA

150

V_LVDA+ 3%

LVD VDDA Hysteresis

—

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 8. PMC electrical specifications (continued)

Name

Parameter

Trimming step LVD VDDA

Min

Typ

Max

Unit

14d V_LVDASTEP

—

SMPS regulator output resistance

Note: Pullup to VDDREG when high, pulldown

to VSSREG when low.

Ohm

—

SMPS regulator clock frequency (after reset)

SMPS regulator overshoot at start-up²

SMPS maximum output current

1.0

—

1.5

1.32

1.0

—

2.4

1.4

—

MHz

Voltage variation on current step²(20% to 80%

of maximum current with 4 µsec constant time)

0.1

VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 µA. When using the

recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core

voltage is up to 1A.

Parameter cannot be tested; this value is based on simulation and characterization.

5.6

Power up/down sequencing

There is no power sequencing required among power sources during power up and power down in order to operate within

specification as long as the following two rules are met:

•

When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.

When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the

internal 3.3V regulator.

The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up

each V /V first and then power up V . For power down, drop V to 0 V first, and then drop all V /V

DDE DDEH

supplies. There is no limit on the fall time for the power supplies.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,

the state of the I/O pins during power up/down varies according to Table 9 and Table 10.

Table 9. Power sequence pin states for MH and AE pads

VDD

VDD33

VDDE

MH Pad

MH+LVDS Pads¹

AE/up-down Pads

High

—

High

Low

High

Normal operation

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Outputs driven high

Pull-ups enabled,

pull-downs disabled

Low

High

Low

Output low,

pin unpowered

Outputs disabled

Output low,

pin unpowered

High

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Pull-ups enabled,

pull-downs disabled

MH+LVDS pads are output-only.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 10. Power sequence pin states for F and FS pads

VDD

VDD33

VDDE

F and FS pads

low

high

low

high

—

Outputs drive high

Outputs Disabled

Outputs drive high

high

low

high

low

high

Normal operation - except no drive current

and input buffer output is unknown.¹

high

Normal Operation

The pad pre-drive circuitry will function normally but since VDDE is unpowered

the outputs will not drive high even though the output pmos can be enabled.

5.6.1

Power-up

If V

is powered up first, then a threshold detector tristates all drivers connected to V

. There is no limit

DDE DDEH

to how long after V

powers up before V must power up. If there are multiple V

supplies, they can

DDE DDEH

be powered up in any order. For each V

supply not powered up, the drivers in that V

segment exhibit

DDE DDEH

the characteristics described in the next paragraph.

If V is powered up first, then all pads are loaded through the drain diodes to V

/V . This presents a heavy load that

DDE DDEH

pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the current

injection specification. There is no limit to how long after V powers up before V

must power up.

DDE DDEH

The rise times on the power supplies are to be no faster than 25 V/millisecond.

5.6.2

Power-down

If V is powered down first, then all drivers are tristated. There is no limit to how long after V powers down before

must power down.

DDE DDEH

If V

is powered down first, then all pads are loaded through the drain diodes to V

. This presents a heavy

DDE DDEH

load that pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the

current injection specification. There is no limit to how long after V

powers down before V must power down.

DDE DDEH DD

There are no limits on the fall times for the power supplies.

5.6.3

Power sequencing and POR dependent on V_DDA

During power up or down, V

can lag other supplies (of magnitude greater than V

/2) within 1 V to prevent any

DDA

DDEH

forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between V

is more than 1 V, the following will result:

and V

DDEH

DDA

•

Triggers POR (ADC monitors on V

segment which powers the RESET pin) if the leakage current path created,

DDEH1

when V

level.

is sufficiently low, causes sufficient voltage drop on V

node monitored crosses low-voltage detect

DDA

DDEH1

•

If V

out of reset.

is between 0–2 V, powering all the other segments (especially V

) will not be sufficient to get the part

DDEH1

DDA

Each V

will have a leakage current to V

of a magnitude of ((V

– V – 1 V(diode drop)/200 KOhms)

DDA

DDEH

DDA

DDEH

up to (V

/2 = V

+ 1 V).

DDEH

DDA

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Each V has the same behavior; however, the leakage will be small even though there is no current limiting resistor

•

since V = 1.32 V max.

5.7

DC electrical specifications

Table 11. DC electrical specifications

Spec

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage (External Regulation)

Core Supply Voltage (Internal Regulation)³

I/O Supply Voltage (fast I/O pads)

I/O Supply Voltage (medium I/O pads)

3.3 V I/O Buffer Voltage

V_DD

1.14

1.08

3.0

1.32^1,2

1.32

V_DDE

3.6^1,4

5.25^1,5

3.6^1,4

5.25^1,5

1.2

V_DDEH

V_DD33

V_DDA

3.0

Analog Supply Voltage

4.75

0.95⁶

SRAM Standby Voltage

V_{STBY_LOW}

Keep-out Range: 1.2V–2V

SRAM Standby Voltage

V_{STBY_HIGH}

Keep-out Range: 1.2V–2V

Voltage Regulator Control Input Voltage⁷

Clock Synthesizer Operating Voltage⁹

V_DDREG

V_DDSYN

V_{IH_F}

2.7⁸

3.0

5.5^1,5

3.6^1,4

Fast I/O Input High Voltage

Hysteresis enabled

_DDE+ 0.3

0.65 × V_DDE

0.55 × V_DDE

Hysteresis disabled

Fast I/O Input Low Voltage

Hysteresis enabled

V_{IL_F}

V_{IH_S}

V_{IL_S}

V_SS– 0.3

0.35 × V_DDE

0.40 × V_DDE

Hysteresis disabled

Medium I/O Input High Voltage

Hysteresis enabled

V_DDEH+ 0.3

0.65 × V_DDEH

0.55 × V_DDEH

Hysteresis disabled

Medium I/O Input Low Voltage

Hysteresis enabled

V_SS– 0.3

0.35 × V_DDEH

0.40 × V_DDEH

Hysteresis disabled

Fast I/O Input Hysteresis

V_{HYS_F}

V_{HYS_S}

V_INDC

V_{OH_F}

V_{OH_S}

V_{OL_F}

V_{OL_S}

C_L

0.1 × V_DDE

0.1 × V_DDEH

V_SSA– 0.1

0.8 × V_DDE

0.8 × V_DDEH

—

Medium I/O Input Hysteresis

Analog Input Voltage

V_DDA+ 0.1

—

Fast I/O Output High Voltage¹⁰

Medium I/O Output High Voltage¹¹

Fast I/O Output Low Voltage¹⁰

Medium I/O Output Low Voltage¹¹

—

0.2 × V_DDE

0.2 × V_DDEH

—

Load Capacitance (Fast I/O)¹²

DSC(PCR[8:9]) = 0b00

DSC(PCR[8:9]) = 0b01

DSC(PCR[8:9]) = 0b10

DSC(PCR[8:9]) = 0b11

—

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Spec

Table 11. DC electrical specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Input Capacitance (Digital Pins)

C_IN

—

Input Capacitance (Analog Pins)

C_{IN_A}

Operating Current 1.2 V Supplies @ f_sys= 264 MHz

_DD@1.32 V

I_DD

I_DDSTBY

I_DDSTBY6

—

1.0¹⁴

0.10

0.15

V_STBY¹³@1.2 V and 85^oC

V_STBY@6.0 V and 85^oC

Operating Current 3.3 V Supplies @ f_sys= 264 MHz

note¹⁵

7¹⁶

V_DD33

V_DDSYN

I_DD33

I_DDSYN

—

Operating Current 5.0 V Supplies @ f_sys= 264 MHz

V_DDA

I_DDA

I_REF

I_REG

—

50¹⁷

1.0

Analog Reference Supply Current (Transient)

V_DDREG

Operating Current V_DDE/V_DDEH¹⁸Supplies

V_DDE2

I_DD2

I_DD1

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

—

V_DDEH1

V_DDEH3

V_DDEH4

V_DDEH5

V_DDEH6

V_DDEH7

note¹⁸

Fast I/O Weak Pull Up/Down Current¹⁹

3.0 V–3.6 V

I_{ACT_F}

I_{ACT_S}

158

A

Medium I/O Weak Pull Up/Down Current²⁰

3.0 V–3.6 V

4.5 V–5.5 V

200

A

I/O Input Leakage Current²¹

I_{INACT_D}

I_IC

–2.5

–1.0

–250

2.5

1.0

A

DC Injection Current (per pin)

Analog Input Current, Channel Off²², AN[0:7], AN38,

I_{INACT_A}

250

AN39

Analog Input Current, Channel Off, all other analog

inputs AN[x]

–150

150

V_SSDifferential Voltage

V_SS– V_SSA

V_RL

V_RL– V_SSA

V_RH

–100

V_SSA

100

V_SSA+ 100

100

Analog Reference Low Voltage

V_RLDifferential Voltage

–100

Analog Reference High Voltage

V_REFDifferential Voltage

V_DDA– 100

4.75

V_DDA

5.25

V_RH– V_RL

V_SSSYN– V_SS

T_A(T_Lto T_H)

—

V_SSSYNto V_SSDifferential Voltage

Operating Temperature Range—Ambient (Packaged)

Slew rate on power supply pins

–100

100

^C

–40.0

—

125.0

V/ms

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 11. DC electrical specifications (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

Weak Pull-Up/Down Resistance²³, 200 K Option

Weak Pull-Up/Down Resistance²³, 100 K Option

Weak Pull-Up/Down Resistance²³, 5 K Option

R_PUPD200K

R_PUPD100K

R_PUPD5K

130

280

140

7.5

k

1.4

Pull-Up/Down Resistance Matching Ratios²⁴

(100K/200K)

R_PUPDMTCH

–2.5

+2.5

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

Assumed with DC load.

5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.

6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.

V_STBYbelow 0.95 V the RAM will not retain states, but will be operational. V_STBYcan be 0 V when bypass standby mode.

Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with V_DDREG= 4.5 V (min).

2.7 V minimum operating voltage allowed during vehicle crank for system with V_DDREG= 3.0 V (min). Normal operating voltage

should be either V_DDREG= 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.

Required to be supplied when 3.3 V regulator is disabled. See Section 5.5 PMC/POR/LVI electrical specifications.

= {16,32,47,77} mA and I_{OL_F}= {24,48,71,115} mA for {00,01,10,11} drive mode with V_DDE= 3.0 V. This spec is for

OH_F

characterization only.

= {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with V_DDE= 4.5 V;

OH_S

I_{OH_S}= {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with V_DDE= 3.0 V. These specs are for characterization only.

¹²Applies to D_CLKOUT, external bus pins, and Nexus pins.

current specified at 1.0 V at a junction temperature of 85 ^oC. V_STBYcurrent is 700 µA maximum at a junction temperature

STBY

of 150 ^oC.

¹⁴Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization.

900 mA based on transistor count estimate at Worst Case (wcs) process and temperature condition.

¹⁵Power requirements for the V_DD33supply depend on the frequency of operation and load of all I/O pins, and the voltages on

the I/O segments. See Section 5.7.2 I/O pad V_DD33current specifications, for information on both fast (F, FS) and medium (MH)

pads. Also refer to Table 13 for values to calculate power dissipation for specific operation.

¹⁶This value is a target that is subject to change.

¹⁷This value allows a 5 V reference to supply ADC + REF.

¹⁸Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O

segment, and the voltage of the I/O segment. See Section 5.7.1 I/O pad current specifications, for information on I/O pad

power. Also refer to Table 12 for values to calculate power dissipation for specific operation. The total power consumption of

an I/O segment is the sum of the individual power consumptions for each pin on the segment.

¹⁹Absolute value of current, measured at V_ILand V_IH.

²⁰Absolute value of current, measured at V_ILand V_IH.

²¹Weak pull up/down inactive. Measured at V_DDE= 3.6 V and V_DDEH= 5.25 V. Applies to pad types F and MH.

²²Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each

8 to 12 ^oC, in the ambient temperature range of 50 to 125 ^oC. Applies to pad types AE and AE/up-down. See Section 4 Signal

properties and muxing.

²³This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics

²⁴Pull-up and pull-down resistances are both enabled and settings are equal.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.7.1

I/O pad current specifications

The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power

consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from

Table 12 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,

and load parameters that fall outside the values given in Table 12.

The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications.

Table 12. V

I/O Pad Average DC Current

DDE DDEH

Frequency

(MHz)

Load²

(pF)

Voltage

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

I_{DRV_MH}

200

5.25

3.6

16.0

6.3

3.0

2.0

1.1

2.4

Fast

I_{DRV_FC}

6.5

3.6

9.4

3.6

10.8

33.3

12.0

6.2

3.6

Fast w/ Slew

Control

I_{DRV_FSR}

3.6

33.33

3.6

4.0

3.6

2.4

3.6

8.9

These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.

All loads are lumped.

5.7.2

I/O pad V_DD33current specifications

The power consumption of the V_DD33supply is dependent on the usage of the pins on all I/O segments. The power consumption

is the sum of all input and output pin V_DD33currents for all I/O segments. The V_DD33current draw on fast speed pads can be

calculated from Table 13 dependent on the voltage, frequency, and load on all F type pins. The V_DD33current draw on medium

pads can be calculated from Table 13 dependent on voltage and independent on the frequency and load on all MH type pins.

Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 13.

The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 13. V

Pad Average DC Current

DD33

Frequency

(MHz)

Load²

(pF)

V_DD33

(V)

V_DDE

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

Fast

I_{33_MH}

I_{33_FC}

—

200

3.6

5.5

3.6

—

0.0007

0.92

1.14

1.50

2.19

0.74

0.52

0.19

Fast w/ Slew

Control

I_{33_FSR}

33.33

These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input

pins only for the medium pads.

All loads are lumped.

5.7.3

LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI

module.

Table 14. DSPI LVDS pad specification

Min.

Value

Typ.

Value

Max.

Value

Characteristic

Symbol

Condition

Data Rate

Unit

Data Frequency

f_LVDSCLK

—

MHz

Driver Specs

Differential output voltage

V_OD

SRC=0b00 or 0b11

SRC=0b01

SRC=0b10

—

150

—

400

320

480

1.39

160

1.06

—

Common mode voltage (LVDS),

VOS

V_OS

1.2

Rise/Fall time

T_R/T_F

T_PLH

—

Propagation delay (Low to High)

Propagation delay (High to Low)

Delay (H/L), sync Mode

T_PHL

t_PDSYNC

T_DZ

Delay, Z to Normal (High/Low)

500

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 14. DSPI LVDS pad specification (continued)

Diff Skew Itphla-tplhbI or

Itplhb-tphlaI

T_SKEW

—

0.5

Termination

10 Trans. Line (differential Zo)

11 Temperature

—

100

—

105

150

ohms

–40

C

5.8

Oscillator and FMPLL electrical characteristics

Table 15. FMPLL Electrical Specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range²(Normal Mode)

Crystal Reference (PLLCFG2 = 0b0)

Crystal Reference (PLLCFG2 = 0b1)

External Reference (PLLCFG2 = 0b0)

External Reference (PLLCFG2 = 0b1)

MHz

f_{ref_crystal}

f_{ref_ext}

40³

f_{ref_ext}

Loss of Reference Frequency⁴

Self Clocked Mode Frequency⁵

PLL Lock Time⁶

f_LOR

f_SCM

t_LPLL

t_DC

100

1000

kHz

MHz

s

—

< 400

Duty Cycle of Reference ⁷

Frequency un-LOCK Range

Frequency LOCK Range

f_UL

–4.0

–2.0

–5

4.0

2.0

% f_sys

%f_clkout

f_LCK

C_Jitter

D_CLKOUT Period Jitter^{8, 9}Measured at f_SYSMax

Cycle-to-cycle Jitter

10,11

Peak-to-Peak Frequency Modulation Range Limit

C_mod

%f_sys

(f_sysMax must not be exceeded)

FM Depth Tolerance¹²

C_{mod_err}

f_VCO

–0.25

192

0.400

0.25

600

%f_sys

MHz

VCO Frequency

Modulation Rate Limits¹³

Predivider output frequency range¹⁴

f_mod

f_prediv

All values given are initial design targets and subject to change.

Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default

PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.

Upper tolerance of less than 1% is allowed on 40MHz crystal.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f_LOR. This

frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and

RFD values have no effect

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal

startup time.

For Flexray operation, duty cycle requirements are higher.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDSYNand V_SSSYNand variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval. D_CLKOUT divider set to divide-by-2.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_jitter+ C_mod

¹⁰Modulation depth selected must not result in f_pllvalue greater than the f_pllmaximum specified value.

¹¹Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 2%, 3%, and 4% peak-to-peak.

¹²Depth tolerance is the programmed modulation depth ±0.25% of F_sys. Violating the VCO min/max range may prevent the

system from exiting reset.

¹³Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

¹⁴Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.

Table 16. Oscillator electrical specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

Crystal Mode Differential Amplitude²

crystal_diff_amp

—

| V_extal– V_xtal| > 0.4 V

(Min differential voltage between EXTAL and XTAL)

Crystal Mode: Internal Differential Amplifier Noise

Rejection

V_{crystal_diff_amp_nr}

V_IHEXT

—

((V_DD33/2) + 0.4 V)

—

| V_extal– V_xtal| < 0.2 V

EXTAL Input High Voltage

—

Bypass mode, External Reference

EXTAL Input Low Voltage

V_ILEXT

(V_DD33/2) – 0.4 V

Bypass mode, External Reference

XTAL Current³

I_XTAL

C_{S_XTAL}

C_{S_EXTAL}

C_L

1.5

—

Total On-chip stray capacitance on XTAL

Total On-chip stray capacitance on EXTAL

Crystal manufacturer’s recommended capacitive load

Discrete load capacitance to be connected to EXTAL

1.5

See crystal spec

—

See crystal spec

C_{L_EXTAL}

(2 × C_L– C_{S_EXTAL}

– C_{PCB_EXTAL )}

—

Discrete load capacitance to be connected to XTAL

C_{L_XTAL}

(2 × C_L– C_{S_XTAL}

– C_{PCB_XTAL )}

All values given are initial design targets and subject to change.

This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.

In that case, V_extal– V_xtal 400 mV criterion has to be met for oscillator’s comparator to produce output clock.

I_xtalis the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

C_{PCB_EXTAL}and C_{PCB_XTAL}are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.9

eQADC electrical characteristics

Table 17. eQADC Conversion Specifications (Operating)

Spec

Characteristic

Symbol

Min

Max

Unit

ADC Clock (ADCLK) Frequency

f_ADCLK

MHz

Conversion Cycles

ADCLK cycles

Single Ended Conversion Cycles 12 bit resolution

Single Ended Conversion Cycles 10 bit resolution

Single Ended Conversion Cycles 8 bit resolution

Note: Differential conversion (min) is one clock

cycle less than the single-ended

2 + 14

2 + 12

2 + 10

128 + 14

128 + 12

128 + 10

conversion values listed here.

Stop Mode Recovery Time¹

T_SR

—

1.25

–4⁴

–8⁴

–3⁴

0⁴

—

s

Resolution²

INL: 8 MHz ADC Clock³

INL8

4⁴

LSB⁵

INL: 16 MHz ADC Clock³

INL16

DNL8

DNL16

OFFNC

OFFWC

GAINNC

GAINWC

I_INJ

8⁴

LSB

DNL: 8 MHz ADC Clock³

3⁴

LSB

DNL: 16 MHz ADC Clock³

3⁴

LSB

Offset Error without Calibration

Offset Error with Calibration

100⁴

4⁴

LSB

–4⁴

–120⁴

–4^4,6

–3

LSB

Full Scale Gain Error without Calibration

Full Scale Gain Error with Calibration

Non-Disruptive Input Injection Current ^{7, 8, 9, 10}

Incremental Error due to injection current^{11, 12}

TUE value at 8 MHz ^{13, 14}(with calibration)

TUE value at 16 MHz ^{13, 14}(with calibration)

0⁴

LSB

4^4,6

LSB

m

E_INJ

–4⁴

–4^4,6

–8

4⁴

Counts

TUE8

TUE16

4^4,6

Maximum differential voltage¹⁵

(DANx+ - DANx-) or (DANx- - DANx+)

PREGAIN set to 1X setting

DIFF_max

DIFF_max2

DIFF_max4

—

(V_RH– V_RL)/2

(V_RH– V_RL)/4

(V_RH- V_RL)/8

PREGAIN set to 2X setting

PREGAIN set to 4X setting

Differential input Common mode voltage¹⁵

(DANx- + DANx+)/2

DIFF_cmv

(V_RH– V_RL)/2

– 5%

(V_RH– V_RL)/2

+ 5%

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that

the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.

At V_RH– V_RL= 5.12 V, one count = 1.25 mV without using pregain.

INL and DNL are tested from V_RL+ 50 LSB to V_RH– 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy

(12 bit resolution selected).

New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully

included.

At V_RH– V_RL= 5.12 V, one LSB = 1.25 mV.

The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.

Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than

V_RHand $000 for values less than V_RL. Other channels are not affected by non-disruptive conditions.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do

not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= –0.3 V, then use the larger of the calculated values.

¹⁰Condition applies to two adjacent pins at injection limits.

¹¹Performance expected with production silicon.

¹²All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, I_INJ=I_INJMAX,I_INJMIN

¹³The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.

¹⁴TUE does not apply to differential conversions.

¹⁵Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the

differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode

voltage of the differential signal violates the Differential Input common mode voltage specification.

5.9.1

ADC internal resource measurements

Table 18. Power Management Control (PMC) specification

Spec

Characteristic

Symbol

Min

Typical

Max

Unit

PMC Normal Mode

Bandgap 0.62 V

ADC0 channel 145

V_ADC145

V_ADC146

V_ADC147

V_ADC180

V_ADC181

V_ADC182

V_ADC183

—

0.62

1.22

—

Bandgap 1.2 V

ADC0 channel 146

Vreg1p2 Feedback

ADC0 channel 147

V_DD/ 2.045

V_DD/ 1.774

Vreg3p3 / 5.460

Vreg3p3 / 4.758

LVD 1.2 V

ADC0 channel 180

Vreg3p3 Feedback

ADC0 channel 181

LVD 3.3 V

ADC0 channel 182

LVD 5.0 V

ADC0 channel 183

— LDO mode

— SMPS mode

V_DDREG/ 4.758

V_DDREG/7.032

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 19. Standby RAM regulator electrical specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Normal Mode

—

Standby Regulator Output

ADC1 channel 194

V_ADC194

1.2

—

Standby Source Bias

150 mV to 360 mV (30mV Increment @

V_ADC195

150

360

vref_sel)

ADC1 channel 195

Default Value 150 mV (@vref_sel = 1 1 1)

Standby Brownout Reference

ADC1 channel 195

V_ADC195

500

—

850

Table 20. ADC band gap reference / LVI electrical specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

4.75 LVD (from V_DDA

)

V_ADC196

—

4.75

—

ADC1 channel 196

ADC Bandgap

V_ADC45

1.171

1.220

1.269

ADC0 channel 45

ADC1 channel 45

Table 21. Temperature sensor electrical specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Slope

V_SADC128

—

5.8

—

mV/ C

–40 C to 100 C ±1.0 C

100 C to 150 C ±1.6 C

ADC0 channel 128

ADC1 channel 128

Accuracy

—

C

–40 C to 150 C

ADC0 channel 128

ADC1 channel 128

±10.0

Slope is the measured voltage change per °C.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.10 C90 flash memory electrical characteristics

Table 22. Flash program and erase specifications

Initial

Spec

Characteristic

Symbol

Min

Typ¹

Max³

Unit

Max²

Double Word (64 bits) Program Time⁴

Page Program Time^4,5

t_dwprogram

t_pprogram

—

500

s

160

16 KB Block Pre-program and Erase Time

64 KB Block Pre-program and Erase Time

128 KB Block Pre-program and Erase Time

256 KB Block Pre-program and Erase Time

t_16kpperase

t_64kpperase

t_128kpperase

t_256kpperase

270

800

1500

3000

1000

1800

2600

5200

5000

7500

15000

Typical program and erase times assume nominal supply values and operation at 25 ^oC.

Initial factory condition:  100 program/erase cycles, 25 ^oC, typical supply voltage, 80 MHz minimum system frequency.

The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized

but not guaranteed.

Program times are actual hardware programming times and do not include software overhead.

Page size is 128 bits (4 words).

Table 23. Flash EEPROM module life

Spec

Characteristic

Symbol

Min

Typical¹

Unit

Number of program/erase cycles per block for 16 KB and 64

KB blocks over the operating temperature range (T_J)

P/E

100,000

—

cycles

Number of program/erase cycles per block for 128 KB and 256

KB blocks over the operating temperature range (T_J)

P/E

1,000

100,000

cycles

years

Minimum Data Retention at 85 °C ambient temperature²

Blocks with 0–1,000 P/E cycles

Retention

—

Blocks with 1,001–10,000 P/E cycles

Blocks with 10,001–100,000 P/E cycles

Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional

information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance

for Nonvolatile Memory.

Ambient temperature averaged over duration of application, not to exceed product operating temperature range.

Table 24 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the

device reference manual for definitions of these bit fields.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 24. PFCPR1 settings vs. frequency of operation

Maximum Frequency²

(MHz)

Clock

Spec

APC =

RWSC

WWSC DPFEN³IPFEN³

PFLIM⁴

BFEN⁵

Mode

Core

f_sys

Platform

f_platf

Enhanced 264 MHz⁶

132 MHz⁶

100 MHz

132 MHz

0b011

0b01

0b11

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Enhanced/ 200 MHz

Full

0b010

0b100

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Legacy

132 MHz

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Default setting after reset: 0b111

0b00

0b0

Illegal combinations exist. Use entries from the same row in this table.

This is the nominal maximum frequency of operation: platform runs at f_sys/2 in Enhanced Mode .

For maximum flash performance, set to 0b1.

For maximum flash performance, set to 0b10.

For maximum flash performance, set to 0b1.

This is the nominal maximum frequency of operation in Enhanced Mode. Max speed is the maximum speed

allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(f_sys) + 2% FM

and 132 Mhz platform clock (f_platf)+ 2% FM.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.11 AC specifications

5.11.1 Clocking

Figure 8 shows the operating frequency domains of various blocks on PXR40.

PLLCFG[0:1]

CORE

f_sys

SYSDIV

 X

 2

PLATFORM /

BLOCKS /

FLASH

f_platf

EXTAL

PLL

IPG DIV SEL

f_periph

SIU_SYSDIV[SYSCLKDIV[0:1]]

X = 2, 4, 8, or 16

f_etpu

eTPU /

NDEDI

ETPU DIV SEL

SIU_SYSDIV[BYPASS]

X = 1

f_{ebi_cal}

EBI

CAL BUS

SIU_SYSDIV[IPCLKDIV[0:1]]

DIV

SIU_ECCR[EBDF[0:1]]

Note: t_cycsys= 1 / f_sys

t_cyc= 1 / f_platf

D_CLKOUT

2 = divide-by-2

 X = divide-by-X, depending on SIU_SYSDIV[BYPASS]

(D_CLKOUT is not available

on all packages and cannot

be programmed for faster

than fsys/2.)

and SIU_SYSDIV[SYSCLKDIV].

Figure 8. PXR40 block operating frequency domain diagram

Table 25 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see

Table 26 and Table 27 for descriptions of bit settings).

1, 2

Table 25. PXR40 operating frequencies

etpu

platf

(platform and all blocks (eTPU, eTPU RAM,

SIU_ECCR

4,5

ebi_cal

sys

Mode

Unit

[EBDF[0:1]]³

(core)

except eTPU)

and NDEDI)

Enhanced

Full

264

132

MHz

200

100

200

Legacy

132

The values in the table are specified at:

V_DD= 1.02 V to 1.32 V

V_DDE= 3.0 V to 3.6 V

V_DDEH= 4.5 V to 5.5 V

V_DD33and V_DDSYN= 3.0 V to 3.6 V

T_A= T_Lto T_H.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Up to the maximum frequency rating of the device (refer to Table 39). The f_sysspeed is the nominal maximum frequency.

270 Mhz parts allow for 264 Mhz system clock + 2% FM.

See the PXR40 Reference Manual for full description as not all bit combinations are valid.

EBI/Calibration bus is not available in all packages.

The EBI/Calibration Bus operating frequency, f_{ebi_cal}, depends on clock divider settings of block’s max allowed

frequency of operation. Normally f_{ebi_cal}= f_platf/2, but can be limited to < f_platf/2 in Full Mode.

Table 26. IPCLKDIV settings

SIU_SYSDIV

Mode

Description

[IPCLKDIV[0:1]]

Enhanced

CPU frequency is doubled (Max 264Mhz). Platform,

peripheral, and eTPU clocks are 1/2 of CPU frequency

Full

CPU and eTPU frequency is doubled (Max 200Mhz).

Platform and peripheral clocks are 1/2 of CPU frequency.

—

Reserved

Legacy

CPU, eTPU, platform, and peripheral’s clocks all run at

same speed (Max 132Mhz).

Table 27. SYSCLKDIV settings

SIU_SYSDIV

Description

[SYSCLKDIV[0:1]]

Divide by 2.

Divide by 4.

Divide by 8.

Divide by 16.

5.11.2 Pad AC specifications

Table 28. Pad AC specifications (v

= 5.0 V, V

= 3.3 V)

DDE

ddeh

Out Delay^2,4

H/H L (ns)

Rise/Fall^3,4

(ns)

Load Drive

(pF)

Spec

Pad

SRC/DSC



Medium⁵

152/165

205/220

28/34

70/74

96/96

12/15

28/31

5.3/5.9

22/22

200

52/59

200

12/12

32/32

200

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

= 3.3 V) (continued)

Table 28. Pad AC specifications (v

= 5.0 V, V

DDE

ddeh

Out Delay^2,4

H/H L (ns)

Rise/Fall^3,4

(ns)

Load Drive

(pF)

Spec

Pad

SRC/DSC



Fast⁶

2.5

1.2

Fast with Slew Rate

40/40

50/50

13/13

19/19

8/8

16/16

21/21

5/5

200

8/8

200

2.4/2.4

5/5

12/12

5/5

200

1.1/1/1

2.6

8/8

2.6

Pull Up/Down (3.6 V max)

Pull Up/Down (5.25 V max)

—

7500

6000

5000/5000

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

V_DD= 1.02 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 4.75 V to 5.25 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock.

Table 29. Derated pad AC specifications (V

= 3.3 V)

DDEH

Out Delay^2,3

H/H L (ns)

Rise/Fall^4,3

Load Drive

(pF)

Spec

Pad

SRC/DSC



(ns)

Medium⁵

200/210

270/285

37/45

86/86

120/120

15.5/19

38/43

200

69/82

200

18/17

7.6/8.5

30/34

46/49

200

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

V_DDEn/ 2

V_DDEHn/ 2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

Pad

Output

V_OL

Figure 9. Pad output delay

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.12 AC timing

5.12.1 Generic timing diagrams

The generic timing diagrams in Figure 10 and Figure 11 apply to all I/O pins with pad types F and MH. See 4, Signal properties

and muxing, for the pad type for each pin.

D_CLKOUT

V_DDE/ 2

I/O Outputs

V_DDEn/ 2

V_DDEHn/ 2

A – Maximum Output Delay Time

Figure 10. Generic output delay/hold timing

B – Minimum Output Hold Time

D_CLKOUT

V_DDE/ 2

I/O Inputs

V_DDEn/ 2

V_DDEHn/ 2

A – Minimum Input Setup Time

B – Minimum Input Hold Time

Figure 11. Generic input setup/hold timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.12.2 Reset and configuration pin timing

Table 30. Reset and configuration pin timing

Spec

Characteristic

Symbol

Min

Max

Unit

RESET Pulse Width

t_RPW

t_GPW

t_RCSU

t_RCH

—

t_cyc

RESET Glitch Detect Pulse Width

t_cyc

PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid

PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid

t_cyc

Reset timing specified at: V_DDEH= 3.0 V to 5.25 V, V_DD= 1.08 V to 1.32 V, T_A= T_Lto T_H.

See Notes on t_cycon Figure 8 and Table 25 in Section 5.11.1 Clocking.

RESET

RSTOUT

PLLCFG

BOOTCFG

WKPCFG

Figure 12. Reset and configuration pin timing

5.12.3 IEEE 1149.1 interface timing

Table 31. JTAG pin AC electrical characteristics

Spec

Characteristic

Symbol

Min

Max

Unit

TCK Cycle Time

t_JCYC

t_JDC

t_TCKRISE

_TMSS,t_TDIS

t_{TMSH, TDIH}

t_TDOV

100

—

TCK Clock Pulse Width (Measured at V_DDE/ 2)

TCK Rise and Fall Times (40%–70%)

TMS, TDI Data Setup Time

—

TMS, TDI Data Hold Time

—

TCK Low to TDO Data Valid

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 31. JTAG pin AC electrical characteristics (continued)

Spec

Characteristic

TCK Low to TDO Data Invalid

Symbol

Min

Max

Unit

t_TDOI

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

—

TCK Low to TDO High Impedance

JCOMP Assertion Time

100

—

JCOMP Setup Time to TCK Low

TCK Falling Edge to Output Valid

TCK Falling Edge to Output Valid out of High Impedance

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

TCK Rising Edge to Boundary Scan Input Invalid

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

—

JTAG timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 32 for functional

specifications.

TCK

Figure 13. JTAG test clock input timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

TCK

TMS, TDI

TDO

Figure 14. JTAG Test Access Port (TAP) timing

TCK

JCOMP

Figure 15. JTAG JCOMP timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

TCK

Output

Signals

Output

Signals

Input

Signals

Figure 16. JTAG boundary scan timing

5.12.4 Nexus timing

Table 32. Nexus debug port timing

Spec

Characteristic

Symbol

Min

Max

Unit

MCKO Cycle Time

t_MCYC

t_MDC

2²

t_CYC

MCKO Duty Cycle

0.2

—

MCKO Low to MDO Data Valid⁴

MCKO Low to MSEO Data Valid⁴

MCKO Low to EVTO Data Valid⁴

EVTI Pulse Width

t_MDOV

t_MSEOV

t_EVTOV

t_EVTIPW

t_EVTOPW

t_TCYC

–0.1

4.0

t_MCYC

t_TCYC

t_MCYC

EVTO Pulse Width

—

TCK Cycle Time

4⁵

—

t_CYC

TCK Duty Cycle

t_TDC

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Spec

Table 32. Nexus debug port timing (continued)

Characteristic

Symbol

t_{NTDIS, NTMSS}

T_{NTDIH, NTMSH}

t_NTDOV

—

Min

Max

Unit

10 TDI, TMS Data Setup Time

11 TDI, TMS Data Hold Time

12 TCK Low to TDO Data Valid

13 RDY Valid to MCKO⁶

—

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified

at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30 pF with

DSC = 0b10.

The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending

on the system frequency, not to exceed maximum Nexus AUX port frequency.

See Notes on t_cycon Figure 13 and Table 25 in Section Section 5.11.1 Clocking.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Lower frequency is required to be fully compliant to standard.

The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MCKO

MDO

Output Data Valid

MSEO

EVTO

EVTI

Figure 17. Nexus timings

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

TCK

TMS, TDI

TDO

Figure 18. Nexus TCK, TDI, TMS, TDO timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.12.5 External Bus Interface (EBI) timing

Table 33. Bus operation timing

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Notes

Min

Max

D_CLKOUT Period

t_C

15.2

45%

—

ns Signals are measured at 50% V_DDE.

D_CLKOUT Duty Cycle

D_CLKOUT Rise Time

D_CLKOUT Fall Time

t_CDC

t_CRT

t_CFT

t_COH

55%

t_C

—

D_CLKOUT Posedge to Output

Signal Invalid or High Z (Hold Time)

1.0/1.5

—

ns Hold time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 1.0 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 1.5 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

D_CLKOUT Posedge to Output

Signal Valid (Output Delay)

t_COV

—

7.0/7.5

ns Output valid time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 7.0 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 7.5 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

Table 33. Bus operation timing (continued)

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Notes

Min

Max

Input Signal Valid to D_CLKOUT

Posedge (Setup Time)

t_CIS

5.0/4.5

—

ns Input setup time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0; 5.0ns

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

EBTS = 1; 4.5ns

D_TS

D_CLKOUT Posedge to Input

Signal Invalid (Hold Time)

t_CIH

1.0

—

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

D_ALE Pulse Width

t_APW

t_AAI

6.5

—

ns The timing is for Asynchronous

external memory system.

10 D_ALE Negated to Address Invalid

2.0/1.0 ⁵

ns The timing is for Asynchronous

external memory system.

ALE is measured at 50% of VDDE.

EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

270 MHz parts allow for 264 MHz system clock + 2% FM.

Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.

The maximum external bus frequency is 66 MHz.

Refer to Fast pad timing in Table 28 and Table 29.

ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 C. 2.0 ns spec applies to

temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.

V_{OH_F}

V_DDE/ 2

V_{OL_F}

D_CLKOUT

Figure 19. D_CLKOUT timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

V_DDE/ 2

D_CLKOUT

Output

Bus

V_DDE/ 2

Output

Signal

V_DDE/ 2

Output

Signal

V_DDE/ 2

Figure 20. Synchronous output timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

D_CLKOUT

V_DDE/ 2

Input

Bus

V_DDE/ 2

Input

Signal

V_DDE/ 2

Figure 21. Synchronous input timing

ipg_clk

D_CLKOUT

D_ALE

D_TS

D_ADD/D_DAT

DATA

ADDR

Figure 22. ALE signal timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

5.12.6 External interrupt timing (IRQ pin)

Table 34. External interrupt timing

Spec

Characteristic

IRQ Pulse Width Low

Symbol

Min

Max

Unit

t_IPWL

t_IPWH

t_ICYC

—

t_cyc

IRQ Pulse Width High

t_cyc

IRQ Edge to Edge Time³

t_cyc

IRQ timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_L

to T_H.

See Notes on t_cycon Figure 8 and Table 25 in Section 5.11.1 Clocking.

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

Figure 23. External interrupt timing

5.12.7 eTPU timing

Table 35. eTPU timing

Spec

Characteristic

Symbol

Min

Max

Unit

eTPU Input Channel Pulse Width

eTPU Output Channel Pulse Width

t_ICPW

—

t_cyc

t_OCPW

1³

t_cyc

eTPU timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 200 pF with SRC = 0b00.

See Notes on t_cycon Figure 8 and Table 25 in Section 5.11.1 Clocking.

This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

eTPU Input

and TCRCLK

eTPU

Output

Figure 24. eTPU timing

5.12.8 eMIOS timing

Table 36. eMIOS timing

Spec

Characteristic

Symbol

Min

Max

Unit

eMIOS Input Pulse Width

eMIOS Output Pulse Width

t_MIPW

—

t_cyc

t_MOPW

1³

t_cyc

eMIOS timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 50 pF with SRC = 0b00.

See Notes on t_cycon Figure 8 and Table 25 in Section 5.11.1 Clocking.

This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

eMIOS Input

eMIOS

Output

Figure 25. eMIOS timing

5.12.9 DSPI timing

1 2

Table 37. DSPI timing

Peripheral Bus Freq: 132 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

DSPI Cycle Time^{3, 4}

Master (MTFE = 0)

Slave (MTFE = 0)

Master (MTFE = 1)

Slave (MTFE = 1)

t_SCK

t_SYS* 2

t_SYS*32768*7

PCS to SCK Delay⁵

t_CSC

t_ASC

—

After SCK Delay⁶

Master mode

Slave mode

t_SYS* 2

t_SYS*3 –

constraints ⁷

SCK Duty Cycle

t_SDC

t_A

0.33 * t_SCK

—

0.66 * t_SCK

Slave Access Time

(SS active to SOUT valid)

Slave SOUT Disable Time

t_DIS

—

(SS inactive to SOUT High-Z or invalid)

PCSx to PCSS time

PCSS to PCSx time

t_PCSC

t_PASC

t_SYS* 2

t_SYS* 7

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

1 2

Table 37. DSPI timing (continued)

Peripheral Bus Freq: 132 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

Data Setup Time for Inputs

Master (MTFE = 0)

t_SUI

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

Data Hold Time for Inputs

Master (MTFE = 0)

t_HI

t_SUO

t_HO

–3

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

Data Valid (after SCK edge)

Master (MTFE = 0)

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Data Hold Time for Outputs

Master (MTFE = 0)

–5

2.5

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

–5

DSPI timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, and T_A= T_Lto T_H

Speed is the nominal maximum frequency of platform clock (f_platf). Max speed is the maximum speed allowed including

frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (f_sys) + 2% FM.

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].

The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].

For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS

This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.

DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high

speed operation.

1, 2

Table 38. DSPI LVDS timing

Characteristic

Symbol

Min

Max

Unit

LVDS Clock to Data/Chip Select Outputs

t_LVDSDATA

–0.25 ×

t_SCYC

+0.25 ×

t_SCYC

These are typical values that are estimated from simulation.

See DSPI LVDS Pad related data in Table 14.

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

Last Data

SIN

First Data

Data

First Data

Last Data

SOUT

Figure 26. DSPI classic SPI timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Figure 27. DSPI classic SPI timing — Master, CPHA = 1

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Data

First Data

Last Data

SOUT

SIN

First Data

Data

Last Data

Figure 28. DSPI classic SPI timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Figure 29. DSPI classic SPI timing — Slave, CPHA = 1

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Figure 30. DSPI modified transfer format timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Figure 31. DSPI modified transfer format timing — Master, CPHA = 1

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Electrical characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Figure 32. DSPI modified transfer format timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

First Data

Data

SOUT

SIN

First Data

Last Data

Figure 33. DSPI modified transfer format timing — Slave, CPHA = 1

PCSS

PCSx

Figure 34. DSPI PCS strobe (PCSS) timing

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Ordering information

6.1

Orderable parts

Figure 35 and Table 39 describe and list the orderable part numbers for the PXR40.

M PX

40 30 V VU 264 R

Qualification status

Brand

Family

Class

Flash memory size

Temperature range

Package identifier

Operating frequency

Tape and reel indicator

Qualification status

Family

Flash Memory Size

D = Display Graphics

N = Connectivity/Network

R = Performance/Real Time Control

S = Safety

30 = 3 MB

40 = 4 MB

P = Pre-qualification (engineering samples)

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

Temperature range

Package identifier

VU = 416 PBGA

Operating frequency

Tape and reel status

V = –40 °C to 105 °C

(ambient)

1 = 150 MHz

2 = 180 MHz

R = Tape and reel

(blank) = Trays

Note: Not all options are available on all devices. See Table 39 for more information.

Figure 35. PXR40 orderable part number description

Table 39. PXR40 orderable part number summary

Speed

(MHz)

Part number

Flash/SRAM

Package

MPXR4030VVU264

MPXR4040VVU264

3 MB / 192 KB

4 MB / 256 KB

416 PBGA (27 mm x 27 mm)

264

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Package information

7.1

416-pin package

The package drawings of the 416-pin TEPBGA package are shown in Figure 36 and Figure 37.

Figure 36. 416 TEPBGA package (1 of 2)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Package information

Figure 37. 416 TEPBGA package (2 of 2)

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Product documentation

This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these

types are available at: http://www.freescale.com.

The following documents are required for a complete description of the device and are necessary to design properly with the

parts:

•

PXR40 Microprocessor Reference Manual (document number PXR40RM).

Revision history

Table 40 describes the changes made to this document between revisions.

Table 40. Revision history

Revision

Date

Description of Changes

September 2011 Initial release: Technical Data

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

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Document Number: PXR40

Rev. 1

09/2011

PPXN4030VVU264R [FREESCALE]

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