MK53DN512CLQ10 [FREESCALE]
K53 Sub-Family; K53次家庭
| 型号： | MK53DN512CLQ10 |
| 厂家： | 
Freescale |
| 描述： | K53 Sub-Family |
| 文件： | 总85页 (文件大小：1961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K53P144M100SF2V2
Rev. 1, 6/2012
Freescale Semiconductor
Data Sheet: Advance Information
K53P144M100SF2V2
K53 Sub-Family
Supports the following:
MK53DN512CLQ10,
MK53DN512CMD10,
MK53DX256CLQ10,
MK53DX256CMD10
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per chip
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 85°C
•
•
•
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Human-machine interface
•
•
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes, depending on the package size
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 256 KB program flash memory on
FlexMemory devices
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Serial programming interface (EzPort)
– FlexBus external bus interface
– Two 12-bit DACs
– Two operational amplifiers
– Two transimpedance amplifiers
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Clocks
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
Timers
•
System peripherals
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2012 Freescale Semiconductor, Inc.
Preliminary
General Business Information
Communication interfaces
•
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– I2S module
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
2
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Table of Contents
1 Ordering parts...........................................................................5
5.4.2
Thermal attributes...............................................22
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3 Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................7
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................8
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
6.1.1
6.1.2
Debug trace timing specifications.......................23
JTAG electricals..................................................24
6.2 System modules................................................................27
6.3 Clock modules...................................................................27
6.3.1
6.3.2
6.3.3
MCG specifications.............................................27
Oscillator electrical specifications.......................29
32 kHz Oscillator Electrical Characteristics........32
6.4 Memories and memory interfaces.....................................32
6.4.1
6.4.2
6.4.3
Flash electrical specifications.............................32
EzPort Switching Specifications.........................37
Flexbus Switching Specifications........................38
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............9
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................11
4.1 Thermal handling ratings...................................................11
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................12
6.5 Security and integrity modules..........................................41
6.6 Analog...............................................................................41
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
ADC electrical specifications..............................41
CMP and 6-bit DAC electrical specifications......49
12-bit DAC electrical characteristics...................52
Op-amp electrical specifications.........................55
Transimpedance amplifier electrical
specifications — full range..................................56
Transimpedance amplifier electrical
6.6.6
6.6.7
specifications — limited range............................57
Voltage reference electrical specifications..........58
6.7 Timers................................................................................59
6.8 Communication interfaces.................................................59
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Voltage and current operating requirements......13
LVD and POR operating requirements...............14
Voltage and current operating behaviors............14
Power mode transition operating behaviors.......15
Power consumption operating behaviors............16
EMC radiated emissions operating behaviors....19
Designing with radiated emissions in mind.........20
Capacitance attributes........................................20
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Ethernet switching specifications........................59
USB electrical specifications...............................61
USB DCD electrical specifications......................61
USB VREG electrical specifications...................62
DSPI switching specifications (limited voltage
range).................................................................62
DSPI switching specifications (full voltage
6.8.6
5.3 Switching specifications.....................................................20
range).................................................................64
I2C switching specifications................................66
UART switching specifications............................66
SDHC specifications...........................................66
5.3.1
5.3.2
Device clock specifications.................................20
General switching specifications.........................21
6.8.7
6.8.8
6.8.9
5.4 Thermal specifications.......................................................22
5.4.1 Thermal operating requirements.........................22
6.8.10 I2S/SAI Switching Specifications........................67
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
3
Preliminary
General Business Information
6.9 Human-machine interfaces (HMI)......................................73
7.1 Obtaining package dimensions.........................................76
8 Pinout........................................................................................76
8.1 K53 Signal Multiplexing and Pin Assignments..................76
8.2 K53 Pinouts.......................................................................82
6.9.1
6.9.2
TSI electrical specifications................................73
LCD electrical characteristics.............................74
7 Dimensions...............................................................................75
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
4
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK53 and MK53.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K53
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
5
Preliminary
General Business Information
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• ML = 104 MAPBGA (8 mm x 8 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK53DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
6
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
7
Preliminary
General Business Information
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
8
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
9
Preliminary
General Business Information
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
10
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
11
Preliminary
General Business Information
General
Symbol
IDD
VDIO
Description
Min.
—
Max.
185
Unit
mA
V
Digital supply current
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
Analog1, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all port pins)
Analog supply voltage
VAIO
–0.3
VDD + 0.3
25
V
ID
–25
mA
V
VDDA
VDD – 0.3
–0.3
VDD + 0.3
3.63
VUSB_DP
VUSB_DM
VREGIN
VBAT
USB_DP input voltage
V
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
12
Freescale Semiconductor, Inc.
Preliminary
General Business Information
General
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
3
mA
Analog2, EXTAL, and XTAL pin DC injection current —
single pin
IICAIO
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
13
Preliminary
General Business Information
General
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
VHYSL
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
14
Freescale Semiconductor, Inc.
Preliminary
General Business Information
General
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
VDD – 0.5
VDD – 0.5
—
—
V
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
100
mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range except TRI0_DM, TRI0_DP, TRI1_DM,
TRI1_DP
1
IIN
Input leakage current (per pin) at 25°C except
TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP
—
—
0.025
5
μA
nA
1
1
IILKG_A
Input leakage current (per pin) for TRI0_DM, TRI0_DP,
TRI1_DM, TRI1_DP
IOZ
RPU
RPD
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
20
20
1
μA
kΩ
kΩ
50
50
2
3
Internal pulldown resistors
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
15
Preliminary
General Business Information
General
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
—
—
—
—
—
—
112
74
μs
μs
μs
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
73
5.9
5.8
4.2
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
32
34
TBD
TBD
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
46
TBD
mA
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
—
48
TBD
TBD
mA
mA
TBD
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
—
20
9
—
—
—
mA
mA
mA
2
5
6
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.12
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
16
Freescale Semiconductor, Inc.
Preliminary
General Business Information
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.71
—
mA
7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
0.77
—
mA
8
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
mA
mA
mA
—
—
—
0.74
2.45
6.61
TBD
TBD
TBD
• @ 70°C
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
83
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
425
1280
• @ 105°C
IDD_LLS Low leakage stop mode current at 3.0 V
9
9
—
—
—
4.58
30.6
137
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
3.0
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
18.6
84.9
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
2.2
9.3
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
41.4
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
2.1
7.6
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
33.5
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
• @ 105°C
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
17
Preliminary
General Business Information
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
10
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.57
0.90
2.4
0.67
1.2
μA
μA
μA
• @ 105°C
• @ 3.0V
3.5
• @ –40 to 25°C
• @ 70°C
—
—
—
0.67
1.0
0.94
1.4
μA
μA
μA
• @ 105°C
2.7
3.9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
18
Freescale Semiconductor, Inc.
Preliminary
General Business Information
General
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 144LQFP
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
23
27
28
14
K
dBμV
dBμV
dBμV
dBμV
—
1 , 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
19
Preliminary
General Business Information
General
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
100
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fENET
System and core clock when ethernet in operation
MHz
• 10 Mbps
• 100 Mbps
5
—
—
50
50
25
25
50
—
—
—
—
fBUS
FB_CLK
fFLASH
Bus clock
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
LPTMR clock
fLPTMR
VLPR mode1
fSYS
System and core clock
—
4
MHz
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
20
Freescale Semiconductor, Inc.
Preliminary
General Business Information
General
Notes
Table 9. Device clock specifications (continued)
Symbol
fBUS
Description
Bus clock
Min.
—
—
—
—
—
—
—
—
—
Max.
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
4
1
fERCLK
External reference clock
LPTMR clock
16
25
16
8
fLPTMR_pin
fLPTMR_ERCLK LPTMR external reference clock
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, IEEE 1588 timer, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
—
—
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
36
24
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
21
Preliminary
General Business Information
General
Table 10. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
Port rise and fall time (low drive strength)
• Slew disabled
5
• 1.71 ≤ VDD ≤ 2.7V
—
—
12
6
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
—
—
36
24
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75pF load
5. 15pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
85
Unit
°C
Die junction temperature
Ambient temperature
TA
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144
MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
45
48
°C/W
1
ambient (natural
convection)
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
22
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Board type
Symbol
Description
144 LQFP
144
MAPBGA
Unit
Notes
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
36
29
38
25
16
°C/W
1
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
36
30
24
°C/W
°C/W
°C/W
1
1
2
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
9
2
9
2
°C/W
°C/W
3
4
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2.
3.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
23
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
3
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
2
ns
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
24
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 13. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• Boundary Scan
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
0
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
—
—
8
25
J8
25
J9
—
J10
J11
J12
1.4
—
—
—
22.1
22.1
TCLK low to TDO high-Z
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
25
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
J13
Description
Min.
100
8
Max.
—
Unit
ns
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
ns
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
26
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
TCLK
TRST
J14
J13
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
27
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
3
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
TBD
fintf_ft
fintf_t
floc_low
floc_high
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
—
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
4, 5
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
28
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Jcyc_fll
FLL period jitter
ps
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
8
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
%
%
s
150 × 10-6
+ 1075(1/
tpll_lock
9
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
29
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
30
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
5
Peak-to-peak amplitude of oscillation (oscillator
—
0.6
—
V
Vpp
mode) — low-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
31
Preliminary
General Business Information
Peripheral operating requirements and behaviors
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32 kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
Parasitical capacitance of EXTAL32 and XTAL32
Peak-to-peak amplitude of oscillation
100
5
MΩ
pF
V
Cpara
—
7
1
—
0.6
—
Vpp
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32kHz oscillator frequency specifications
Table 19. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
fec_extal32
vec_extal32
Oscillator crystal
Crystal start-up time
—
—
1
2
Externally provided input clock frequency
Externally provided input clock amplitude
—
—
kHz
mV
VBAT
700
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
32
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk256k Erase Block high-voltage time for 256 KB
—
13
113
904
ms
ms
1
1
—
104
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 256 KB program/data flash
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
—
—
1.7
ms
trd1sec2k Read 1s Section execution time (flash sector)
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 256 KB program/data flash
30
tpgm4
145
2
2
tersblk256k
tersscr
—
—
122
14
985
114
ms
ms
Erase Flash Sector execution time
Program Section execution time
• 512 B flash
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
2.4
4.7
9.3
—
—
—
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
65
250
—
—
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
2000
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
• control code 0x02
• control code 0x04
• control code 0x08
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
33
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
Program Partition for EEPROM execution time
Min.
Typ.
Max.
Unit
Notes
tpgmpart64k
tpgmpart256k
• 64 KB FlexNVM
• 256 KB FlexNVM
—
—
138
145
—
—
ms
ms
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
tsetram256k
—
—
—
—
70
0.8
1.3
4.5
—
μs
ms
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 256 KB EEPROM backup
1.2
1.9
5.5
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
630
810
2050
2250
2675
3500
μs
μs
μs
μs
1200
1900
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
34
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
2.5
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
2
3
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
10 K
100
50 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
Write endurance
5
50
—
—
years
years
20
100
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree32k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
• EEPROM backup to FlexRAM ratio =
32,768
80 M
400 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
35
Preliminary
General Business Information
Peripheral operating requirements and behaviors
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash
memory module to obtain an effective endurance increase for the EEPROM data. The
built-in EEPROM record management system raises the number of program/erase cycles
that can be attained prior to device wear-out by cycling the EEPROM data through a
larger EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycd
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000
cycles)
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
36
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
16
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
37
Preliminary
General Business Information
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP4
EP2
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
1
1
2
2
0.5
8.5
0.5
ns
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
38
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
Max.
3.6
Unit
Notes
Operating voltage
V
Frequency of operation
—
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
Clock period
1/FB_CLK
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
0
13.5
—
ns
1
1
2
2
ns
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
39
Preliminary
General Business Information
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 11. FlexBus read timing diagram
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
40
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
41
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 29 and
Table 30.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Typ.1
—
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
Delta to VDD (VDD-VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
Delta to VSS (VSS-VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
Reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
CADIN
Input voltage
VREFL
—
—
8
VREFH
10
V
Input capacitance
• 16 bit modes
pF
• 8/10/12 bit modes
—
4
5
RADIN
RAS
Input resistance
—
2
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
—
5
fADCK
fADCK
Crate
ADC conversion ≤ 13 bit modes
clock frequency
4
4
5
1.0
2.0
—
—
—
18.0
12.0
MHz
MHz
Ksps
ADC conversion 16 bit modes
clock frequency
ADC conversion ≤ 13 bit modes
rate
No ADC hardware averaging
20.000
818.330
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
42
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion 16 bit modes
rate
5
No ADC hardware averaging
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 13. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
43
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
2.4
Symbol Description
Min.
1.2
3.0
2.4
4.4
Max.
3.9
Unit
Notes
ADC
asynchronous
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
4.0
7.3
clock source
fADACK
5.2
6.1
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
LSB4
LSB4
TUE
DNL
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
—
4
6.8
2.1
5
5
1.4
Differential non-
linearity
• 12 bit modes
—
0.7
-1.1 to +1.9
-0.3 to 0.5
• <12 bit modes
• 12 bit modes
—
—
0.2
1.0
LSB4
INL
EFS
Integral non-
linearity
-2.7 to +1.9
-0.7 to +0.5
5
• <12 bit modes
• 12 bit modes
• <12 bit modes
—
—
—
0.5
-4
LSB4
LSB4
Full-scale error
-5.4
-1.8
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16 bit differential mode
6
of bits
• Avg=32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg=4
16 bit single-ended mode
• Avg=32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg=4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
7
—
—
–94
-85
—
—
dB
dB
16 bit single-ended mode
• Avg=32
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
82
78
95
90
—
—
dB
dB
16 bit single-ended mode
• Avg=32
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
44
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IIn
leakage
current
EIL
Input leakage
error
IIn × RAS
mV
=
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
25°C
—
—
1.715
719
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
45
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
V
2, 3
T
T
T
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
V
Input Common
Mode range
IN+ to IN-4
RPGAD
Differential input Gain = 1, 2, 4, 8
—
—
—
—
128
64
—
—
—
—
kΩ
impedance
Gain = 16, 32
Gain = 64
32
RAS
TS
Analog source
resistance
100
Ω
5
6
ADC sampling
time
1.25
—
—
µs
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
46
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 29. 16-bit ADC with PGA operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion ≤ 13 bit modes
18.484
—
450
Ksps
7
rate
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
37.037
—
250
Ksps
8
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics with Chop enabled
(ADC_PGA[PGACHPb] =0)
Table 30. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
—
420
644
μA
2
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
—
1.54
0.57
—
—
μA
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
47
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Typ.1
1
Symbol
Description
Conditions
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
Min.
0.95
1.9
Max.
1.05
2.1
Unit
Notes
Gain4
G
R
AS < 100Ω
2
3.8
4
4.2
7.6
8
8.4
15.2
30.0
58.8
16
31.6
63.3
16.6
33.2
67.8
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ratio
Gain=1
-84
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
Common mode
rejection ratio
• Gain=1
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
VOFS
TGSW
dG/dT
Input offset
voltage
—
—
0.2
—
—
mV
µs
Output offset =
VOFS*(Gain+1)
Gain switching
settling time
10
5
Gain drift over full
temperature range
• Gain=1
• Gain=64
—
—
—
—
6
31
10
42
ppm/°C
ppm/°C
%/V
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
0.07
0.21
0.31
VDDA from 1.71
to 3.6V
0.14
%/V
EIL
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
V
6
signal swing
where VX = VREFPGA × 0.583
SNR
Signal-to-noise
ratio
• Gain=1
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
48
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Typ.1
100
95
Symbol
Description
Conditions
• Gain=1
Min.
85
Max.
—
Unit
dB
Notes
THD
Total harmonic
distortion
16-bit
differential
mode,
• Gain=64
49
—
dB
Average=32,
fin=100Hz
SFDR
ENOB
Spurious free
dynamic range
• Gain=1
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
• Gain=64
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
11.6
8.0
13.4
13.6
9.6
—
—
—
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100Hz
7.2
6.3
9.6
12.8
11.0
7.9
14.5
14.3
13.8
13.1
12.5
11.5
10.6
7.3
6.8
6.8
7.5
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
Gain = 2PGAG
4.
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
VDD
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
49
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
VAIO
Description
Min.
Typ.
Max.
Unit
Analog input offset voltage
—
—
20
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
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Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
51
Preliminary
General Business Information
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
TA
Desciption
Min.
1.71
1.13
−40
—
Max.
3.6
3.6
105
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Temperature
V
1
2
°C
pF
mA
CL
Output load capacitance
Output load current
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
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Freescale Semiconductor, Inc.
Preliminary
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Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
TBD
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
TBD
μA
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
—
—
—
100
15
0.7
—
200
μs
μs
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
30
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
100
VDACR
8
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA > = 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
0.05
0.12
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
53
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Figure 18. Typical INL error vs. digital code
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
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Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Figure 19. Offset at half scale vs. temperature
6.6.4 Op-amp electrical specifications
Table 34. Op-amp electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Operating voltage
ISUPPLY
ISUPPLY
VOS
Supply current (IOUT=0mA, CL=0), low-power mode
Supply current (IOUT=0mA, CL=0), high-speed mode
Input offset voltage
TBD
TBD
3
TBD
TBD
10
μA
—
μA
—
mV
μV/C
pA
αVOS
Input offset voltage temperature coefficient
—
10
—
IOS
Typical input offset current across the following temp
range (0–50°C)
—
500
—
IOS
Typical input offset current across the following temp
range (-40–105°C)
—
4
—
nA
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
55
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 34. Op-amp electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IBIAS
Typical input bias current across the following temp
range (0–50°C)
—
500
—
pA
IBIAS
Typical input bias current across the following temp
range (-40–105°C)
—
4
—
nA
VCML
VCMH
RIN
Input common mode voltage low
Input common mode voltage high
Input resistance
0
—
—
—
—
V
V
VDD
—
500
—
MΩ
pF
171
50
—
CIN
Input capacitance
—
—
|XIN|
CMRR
PSRR
SR
AC input impedance (fIN=100kHz)
Input common mode rejection ratio
Power supply rejection ratio
—
—
MΩ
dB
60
60
0.1
1.5
0.15
1
—
—
—
dB
Slew rate (ΔVIN=500mV), low-power mode
Slew rate (ΔVIN=500mV), high-speed mode
Unity gain bandwidth, low-power mode
Unity gain bandwidth, high-speed mode
DC open-loop voltage gain
—
—
V/μs
V/μs
MHz
MHz
dB
SR
4
—
GBW
GBW
AV
—
—
—
—
80
—
90
100
1500
—
—
CL(max) Load capacitance driving capability
—
pF
ROUT
VOUT
IOUT
GM
Output resistance @ 100 kHz, high speed mode
—
—
Ω
Output voltage range
Output load current
Gain margin
0.12
—
VDD - 0.12
V
0.5
20
56
5.7
—
—
—
—
mA
dB
—
PM
Phase margin
45
—
deg
μs
Settling time2 (Buffer mode, low-power mode)
(To<0.1%, Vin=1.65V)
Tsettle
Settling time2 (Buffer mode, high-speed mode)
(To<0.1%, Vin=1.65V)
Tsettle
—
3.0
—
μs
Vn
Vn
Voltage noise density (noise floor) 1kHz
Voltage noise density (noise floor) 10kHz
—
—
350
90
—
—
nV/√Hz
nV/√Hz
1. The input capacitance is dependant on the package type used.
2. Settling time is measured from the time the Op-amp is enabled until the output settles to within 0.1% of final value. This
time includes Op-amp startup time, output slew, and settle time.
6.6.5 Transimpedance amplifier electrical specifications — full range
Table 35. TRIAMP full range operating requirements
Symbol
VDDA
Description
Min.
Max.
Unit
Notes
Supply voltage
1.71
-0.1
—
3.6
V
V
pf
VIN
CL
Input voltage range
Output load capacitance
VDDA-1.4
100
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
56
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 36. TRIAMP full range operating behaviors
Symbol Description
ISUPPLY Supply current (IOUT=0mA, CL=0) — Low-power
mode
Min.
Typ.
Max.
Unit
Notes
—
60
80
μA
μA
mV
ISUPPLY
Supply current (IOUT=0mA, CL=0) — High-speed —
mode
280
450
VOS
αVOS
IOS
Input offset voltage
—
—
—
—
500
—
—
TBD
4.8
0.3
0.3
—
TBD
—
Input offset voltage temperature coefficient
Input offset current
μV/C
nA
5
IBIAS
RIN
Input bias current
5
nA
Input resistance
—
MΩ
pF
CIN
Input capacitance
17
—
ROUT
Output AC impedance
—
1500
Ω
@ 100kHz,
High speed
mode
|XIN|
CMRR
PSRR
SR
AC input impedance (fIN=100kHz)
—
60
60
0.1
1
159
—
—
kΩ
Input common mode rejection ratio
Power supply rejection ratio
—
dB
—
—
dB
Slew rate (ΔVIN=100mV) — Low-power mode
Slew rate (ΔVIN=100mV) — High speed mode
—
—
V/μs
V/μs
MHz
MHz
dB
SR
—
—
GBW
GBW
AV
Unity gain bandwidth — Low-power mode 50pF 0.15
—
—
Unity gain bandwidth — High speed mode 50pF
DC open-loop voltage gain
Output voltage range
1
—
—
80
0.15
—
—
50
—
—
—
—
VOUT
IOUT
GM
—
VDD-0.15
—
V
Output load current
0.5
20
60
280
100
mA
Gain margin
—
dB
PM
Phase margin
—
deg
nV/√Hz
nV/√Hz
Vn
Voltage noise density (noise floor) 1kHz
Voltage noise density (noise floor) 10kHz
—
Vn
—
6.6.6 Transimpedance amplifier electrical specifications — limited
range
Table 37. TRIAMP limited range operating requirements
Symbol
VDDA
Description
Min.
Max.
Unit
Notes
Supply voltage
Input voltage range
Temperature
2.4
0.1
0
3.3
V
V
C
VIN
TA
VDDA-1.4
50
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
57
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 37. TRIAMP limited range operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
Notes
CL
Output load capacitance
—
100
pf
Table 38. TRIAMP limited range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
VOS
αVOS
IOS
IBIAS
ROUT
Input offset voltage
—
—
—
—
—
3
5
mV
Input offset voltage temperature coefficient
Input offset current
4.8
—
μV/C
pA
300
300
600
600
Input bias current
pA
Output AC impedance
—
1500
Ω
@ 100kHz,
High speed
mode
|XIN|
CMRR
PSRR
SR
AC input impedance (fIN=100kHz)
—
159
70
70
—
—
—
—
—
—
—
—
—
—
—
kΩ
Input common mode rejection ratio
Power supply rejection ratio
—
dB
—
dB
Slew rate (ΔVIN=500mV) — Low-power mode
Slew rate (ΔVIN=500mV) — High speed mode
0.1
1.5
V/μs
V/μs
MHz
MHz
dB
SR
3.5
—
GBW
GBW
AV
Unity gain bandwidth — Low-power mode 50pF 0.15
Unity gain bandwidth — High speed mode 50pF
DC open-loop voltage gain
Gain margin
1
—
80
—
60
—
GM
20
69
dB
PM
Phase margin
deg
6.6.7 Voltage reference electrical specifications
Table 39. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Min.
1.71
−40
Max.
3.6
Unit
V
Notes
Supply voltage
Temperature
105
°C
nF
CL
Output load capacitance
100
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
58
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 40. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 41. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 42. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
59
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 43. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
MHz
RXCLK frequency
RXCLK pulse width high
MII1
35%
65%
RXCLK
period
RXCLK
period
ns
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
TXCLK
period
ns
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
MII6
MII5
MII7
TXCLK (input)
MII8
Valid data
TXD[n:0]
TXEN
Valid data
Valid data
TXER
Figure 20. MII transmit signal timing diagram
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
60
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
MII2
MII3
MII1
MII4
RXCLK (input)
RXD[n:0]
RXDV
Valid data
Valid data
Valid data
RXER
Figure 21. MII receive signal timing diagram
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 44. RMII signal switching specifications
Num
—
Description
Min.
—
Max.
50
Unit
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RMII7
RMII8
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
4
2
—
—
—
15
ns
ns
ns
ns
4
RMII_CLK to TXD[1:0], TXEN valid
—
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
61
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.8.3 USB DCD electrical specifications
Table 45. USB DCD electrical specifications
Symbol
VDP_SRC
VLGC
Description
Min.
0.5
Typ.
—
Max.
0.7
Unit
V
USB_DP source voltage (up to 250 μA)
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
—
2.0
V
IDP_SRC
IDM_SINK
7
10
13
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.33
6.8.4 USB VREG electrical specifications
Table 46. USB VREG electrical specifications
Typ.1
—
Symbol Description
Min.
Max.
Unit
Notes
VREGIN Input supply voltage
2.7
—
5.5
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load current
equal zero
—
1.1
1.54
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
62
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
0
8
ns
ns
ns
ns
—
—
—
14
0
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 22. DSPI classic SPI timing — master mode
Table 48. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
63
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 48. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK input high/low time
Min.
Max.
Unit
ns
(tSCK/2) − 2
(tSCK/2) + 2
DSPI_SCK to DSPI_SOUT valid
—
0
20
—
—
—
14
14
ns
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 49. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
64
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 49. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-1.2
19.1
0
8.5
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 24. DSPI classic SPI timing — master mode
Table 50. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6.25
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
24
—
—
—
19
19
ns
ns
3.2
7
ns
ns
—
—
ns
ns
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
65
Preliminary
General Business Information
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
DS12
DS16
DS11
(CPOL=0)
First data
Last data
DSPI_SOUT
Data
Data
DS13
DS14
First data
Last data
DSPI_SIN
Figure 25. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.7
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 51. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25
20
400
—
—
3
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
ns
Clock rise time
—
—
ns
Clock fall time
3
ns
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
66
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 51. SDHC switching specifications
(continued)
Num
Symbol
Description
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Min.
Max.
Unit
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 26. SDHC timing
6.8.10 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.10.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
67
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 52. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 27. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
68
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
2
—
—
ns
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
15
—
—
—
25
ns
ns
ns
ns
ns
4.5
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 28. I2S/SAI timing — slave modes
6.8.10.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 54. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
69
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 54. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
Characteristic
Min.
Max.
55%
Unit
BCLK period
S4
S5
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
—
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
15
—
—
ns
ns
ns
0
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 29. I2S/SAI timing — master modes
Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
S15
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
2
—
ns
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
20.6
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
70
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
0
—
—
—
25
ns
ns
ns
ns
5.8
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 30. I2S/SAI timing — slave modes
6.8.10.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 56. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
71
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 56. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
Min.
Max.
Unit
S7
S8
S9
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 31. I2S/SAI timing — master modes
Table 57. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
3
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
63
—
—
—
72
ns
ns
ns
ns
ns
30
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
72
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Peripheral operating requirements and behaviors
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 32. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 58. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE Target electrode capacitance range
Min.
1.71
1
Typ.
—
20
8
Max.
3.6
500
15
Unit
V
Notes
pF
1
fREFmax Reference oscillator frequency
fELEmax Electrode oscillator frequency
—
MHz
MHz
pF
2, 3
2, 4
—
1
1.8
—
CREF
VDELTA
IREF
Internal reference capacitor
Oscillator delta voltage
—
1
—
500
—
mV
μA
2, 5
2, 6
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
—
—
2
3
36
50
• 32 μA setting (REFCHRG = 15)
IELE
Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
μA
2, 7
—
—
2
3
50
36
• 32 μA setting (EXTCHRG = 15)
Pres5
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
1.46
—
38400
38400
38400
—
fF/count
fF/count
fF/count
fF/count
bits
8
9
Pres20 Electrode capacitance measurement precision
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
—
10
11
0.008
—
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
μs
12
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
73
Preliminary
General Business Information
Peripheral operating requirements and behaviors
Table 58. TSI electrical specifications (continued)
Symbol Description
Min.
—
Typ.
55
Max.
—
Unit
μA
Notes
ITSI_RUN Current added in run mode
ITSI_LP
Low power mode current adder
—
1.3
2.5
μA
13
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
I
ext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
ext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
I
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
6.9.2 LCD electrical characteristics
Table 59. LCD electricals
Symbol Description
fFrame LCD frame frequency
CLCD LCD charge pump capacitance — nominal value
CBYLCD LCD bypass capacitance — nominal value
CGlass LCD glass capacitance
Min.
28
—
Typ.
30
Max.
58
Unit
Hz
nF
Notes
100
100
2000
—
1
1
2
—
—
nF
—
8000
pF
Table continues on the next page...
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
74
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Dimensions
Table 59. LCD electricals (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VIREG
VIREG
• HREFSEL=0, RVTRIM=1111
3
—
—
—
1.11
1.01
0.91
—
—
—
V
V
V
• HREFSEL=0, RVTRIM=1000
• HREFSEL=0, RVTRIM=0000
—
—
—
1.84
1.69
1.54
—
—
—
V
V
V
• HREFSEL=1, RVTRIM=1111
• HREFSEL=1, RVTRIM=1000
• HREFSEL=1, RVTRIM=0000
ΔRTRIM
VIREG TRIM resolution
VIREG ripple
—
—
3.0
% VIREG
—
—
—
—
—
30
50
mV
mV
• HREFSEL = 0
• HREFSEL = 1
IVIREG
IRBIAS
VIREG current adder — RVEN = 1
RBIAS current adder
—
—
—
1
10
1
—
—
—
µA
µA
µA
4
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
RRBIAS
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
—
—
0.28
2.98
—
—
MΩ
MΩ
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL2
VLL3
VLL2 voltage
• HREFSEL = 0
• HREFSEL = 1
2.0 − 5%
3.3 − 5%
2.0
3.3
—
—
V
V
VLL3 voltage
• HREFSEL = 0
• HREFSEL = 1
3.0 − 5%
5 − 5%
3.0
5
—
—
V
V
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
75
Preliminary
General Business Information
Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
98ASA00222D
144-pin MAPBGA
8 Pinout
8.1 K53 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
For FlexBus applications, use only the CLKOUT signal on the
PTA6 pin to ensure proper timing.
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
1
2
D3
D2
PTE0
ADC1_SE4a
ADC1_SE5a
ADC1_SE4a
ADC1_SE5a
PTE0
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
FB_AD27
FB_AD26
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
PTE1/
PTE1/
LLWU_P0
LLWU_P0
3
4
D1
E4
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE7a
ADC1_SE6a
ADC1_SE7a
PTE2/
LLWU_P1
SPI1_SCK
SPI1_SIN
UART1_CTS_
b
SDHC0_DCLK FB_AD25
PTE3
PTE3
UART1_RTS_
b
SDHC0_CMD
FB_AD24
SPI1_SOUT
5
6
7
E5
F6
E3
VDD
VSS
VDD
VDD
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
SPI1_PCS2
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
FB_CS3_b/
FB_BE7_0_b
FB_TA_b
8
E2
PTE5
DISABLED
PTE5
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
76
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
DISABLED
DISABLED
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
9
E1
PTE6
PTE6
SPI1_PCS3
UART3_CTS_
b
I2S0_MCLK
FB_ALE/
FB_CS1_b/
FB_TS_b
USB_SOF_
OUT
10
F4
PTE7
PTE7
UART3_RTS_
b
I2S0_RXD0
FB_CS0_b
11
12
F3
F2
PTE8
PTE9
DISABLED
DISABLED
PTE8
PTE9
I2S0_RXD1
I2S0_TXD1
UART5_TX
UART5_RX
I2S0_RX_FS
FB_AD4
FB_AD3
I2S0_RX_
BCLK
13
14
15
F1
G4
G3
PTE10
PTE11
PTE12
DISABLED
DISABLED
DISABLED
PTE10
PTE11
PTE12
UART5_CTS_
b
I2S0_TXD0
FB_AD2
FB_AD1
FB_AD0
UART5_RTS_
b
I2S0_TX_FS
I2S0_TX_
BCLK
16
17
18
19
20
21
22
23
E6
F7
H3
H1
H2
G1
G2
J1
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DP1/
OP0_DP0
ADC0_DP1/
OP0_DP0
24
25
J2
ADC0_DM1/
OP0_DM0
ADC0_DM1/
OP0_DM0
ADC0_DM1/
OP0_DM0
K1
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
26
27
K2
L1
ADC1_DM1/
OP1_DM0
ADC1_DM1/
OP1_DM0
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
28
29
30
L2
M1
M2
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
31
32
33
34
H5
G5
G6
H6
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
77
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
35
K3
ADC1_SE16/
OP1_OUT/
CMP2_IN2/
ADC0_SE22/
OP0_DP2/
OP1_DP2
ADC1_SE16/
OP1_OUT/
CMP2_IN2/
ADC0_SE22/
OP0_DP2/
OP1_DP2
ADC1_SE16/
OP1_OUT/
CMP2_IN2/
ADC0_SE22/
OP0_DP2/
OP1_DP2
36
J3
ADC0_SE16/
OP0_OUT/
CMP1_IN2/
ADC0_SE21/
OP0_DP1/
OP1_DP1
ADC0_SE16/
OP0_OUT/
CMP1_IN2/
ADC0_SE21/
OP0_DP1/
OP1_DP1
ADC0_SE16/
OP0_OUT/
CMP1_IN2/
ADC0_SE21/
OP0_DP1/
OP1_DP1
37
38
M3
L3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
TRI0_OUT/
OP1_DM2
TRI0_OUT/
OP1_DM2
TRI0_OUT/
OP1_DM2
39
40
41
42
43
L4
M4
L5
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
M5
K5
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
44
45
K4
J4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
OP0_DP4/
OP1_DP4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
OP0_DP4/
OP1_DP4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
OP0_DP4/
OP1_DP4
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
46
47
48
49
50
M7
M6
L6
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
H4
J5
PTE28
PTA0
DISABLED
PTE28
FB_AD20
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
51
52
J6
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
K6
JTAG_TDO/
TRACE_SWO/
EZP_DO
UART0_TX
JTAG_TDO/
TRACE_SWO
EZP_DO
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
78
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
53
54
55
K7
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_
b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
L7
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
M8
PTA5
DISABLED
PTA5
USB_CLKIN
RMII0_RXER/
MII0_RXER
CMP2_OUT
CLKOUT
I2S0_TX_
BCLK
JTAG_TRST_
b
56
57
58
E7
G7
J7
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
DISABLED
PTA6
FTM0_CH3
TRACE_
CLKOUT
59
60
J8
PTA7
PTA8
ADC0_SE10
ADC0_SE11
ADC0_SE10
ADC0_SE11
PTA7
PTA8
FTM0_CH4
FTM1_CH0
FB_AD18
FB_AD17
TRACE_D3
TRACE_D2
K8
FTM1_QD_
PHA
61
62
63
64
L8
M9
L9
PTA9
DISABLED
DISABLED
DISABLED
CMP2_IN0
PTA9
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
MII0_RXD3
MII0_RXD2
MII0_RXCLK
FB_AD16
FB_AD15
FB_OE_b
FTM1_QD_
PHB
TRACE_D1
TRACE_D0
PTA10
PTA11
PTA12
PTA10
PTA11
PTA12
FTM2_QD_
PHA
FTM2_QD_
PHB
K9
CMP2_IN0
CMP2_IN1
RMII0_RXD1/
MII0_RXD1
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
b
I2S0_TXD0
FTM1_QD_
PHA
65
66
J9
PTA13/
LLWU_P4
CMP2_IN1
DISABLED
PTA13/
LLWU_P4
FTM1_CH1
RMII0_RXD0/
MII0_RXD0
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_
b
I2S0_TX_FS
FTM1_QD_
PHB
L10
PTA14
PTA14
SPI0_PCS0
UART0_TX
UART0_RX
RMII0_CRS_
DV/
MII0_RXDV
FB_AD31
I2S0_RX_
BCLK
I2S0_TXD1
I2S0_RXD1
67
68
L11
K10
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
RMII0_TXEN/
MII0_TXEN
FB_AD30
FB_AD29
I2S0_RXD0
SPI0_SOUT
UART0_CTS_
b/
RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS
UART0_COL_
b
69
K11
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_
b
RMII0_TXD1/
MII0_TXD1
FB_AD28
I2S0_MCLK
70
71
72
73
E8
G8
VDD
VDD
VDD
VSS
VSS
VSS
M12
M11
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
LPTMR0_
ALT1
74
75
76
77
L12
K12
J12
J11
RESET_b
PTA24
RESET_b
DISABLED
DISABLED
DISABLED
RESET_b
PTA24
PTA25
PTA26
MII0_TXD2
MII0_TXCLK
MII0_TXD3
FB_AD14
FB_AD13
FB_AD12
PTA25
PTA26
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
79
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
78
79
80
81
J10
H12
H11
H10
PTA27
DISABLED
DISABLED
DISABLED
PTA27
MII0_CRS
MII0_TXER
MII0_COL
FB_AD11
FB_AD10
FB_AD19
PTA28
PTA29
PTA28
PTA29
PTB0/
LLWU_P5
LCD_P0/
LCD_P0/
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
LCD_P0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
82
H9
PTB1
LCD_P1/
LCD_P1/
PTB1
RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
LCD_P1
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
83
84
G12
G11
PTB2
PTB3
LCD_P2/
ADC0_SE12/
TSI0_CH7
LCD_P2/
ADC0_SE12/
TSI0_CH7
PTB2
PTB3
I2C0_SCL
I2C0_SDA
UART0_RTS_
b
ENET0_1588_
TMR0
FTM0_FLT3
FTM0_FLT0
LCD_P2
LCD_P3
LCD_P3/
ADC0_SE13/
TSI0_CH8
LCD_P3/
ADC0_SE13/
TSI0_CH8
UART0_CTS_
b/
UART0_COL_
b
ENET0_1588_
TMR1
85
86
87
88
89
90
91
92
G10
G9
PTB4
PTB5
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
LCD_P4/
ADC1_SE10
LCD_P4/
ADC1_SE10
PTB4
PTB5
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
ENET0_1588_
TMR2
FTM1_FLT0
FTM2_FLT0
LCD_P4
LCD_P5
LCD_P6
LCD_P7
LCD_P8
LCD_P9
LCD_P10
LCD_P11
LCD_P5/
ADC1_SE11
LCD_P5/
ADC1_SE11
ENET0_1588_
TMR3
F12
F11
F10
F9
LCD_P6/
ADC1_SE12
LCD_P6/
ADC1_SE12
LCD_P7/
ADC1_SE13
LCD_P7/
ADC1_SE13
LCD_P8
LCD_P9
LCD_P8
LCD_P9
UART3_RTS_
b
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
UART3_CTS_
b
E12
E11
LCD_P10/
ADC1_SE14
LCD_P10/
ADC1_SE14
UART3_RX
FTM0_FLT1
FTM0_FLT2
LCD_P11/
LCD_P11/
UART3_TX
ADC1_SE15
ADC1_SE15
93
94
95
H7
F5
VSS
VSS
VDD
VSS
VDD
VDD
E10
PTB16
LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16
PTB17
PTB18
PTB19
SPI1_SOUT
SPI1_SIN
UART0_RX
UART0_TX
FTM2_CH0
FTM2_CH1
EWM_IN
LCD_P12
LCD_P13
LCD_P14
LCD_P15
96
97
98
E9
PTB17
PTB18
PTB19
LCD_P13/
TSI0_CH10
LCD_P13/
TSI0_CH10
EWM_OUT_b
D12
D11
LCD_P14/
TSI0_CH11
LCD_P14/
TSI0_CH11
I2S0_TX_
BCLK
FTM2_QD_
PHA
LCD_P15/
TSI0_CH12
LCD_P15/
TSI0_CH12
I2S0_TX_FS
FTM2_QD_
PHB
99
D10
D9
PTB20
PTB21
PTB22
LCD_P16
LCD_P17
LCD_P18
LCD_P16
LCD_P17
LCD_P18
PTB20
PTB21
PTB22
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
CMP0_OUT
CMP1_OUT
CMP2_OUT
LCD_P16
LCD_P17
LCD_P18
100
101
C12
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
80
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
102
103
C11
B12
PTB23
LCD_P19
LCD_P19
PTB23
SPI2_SIN
SPI0_PCS5
LCD_P19
LCD_P20
PTC0
LCD_P20/
ADC0_SE14/
TSI0_CH13
LCD_P20/
ADC0_SE14/
TSI0_CH13
PTC0
SPI0_PCS4
PDB0_EXTRG
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
104
105
B11
A12
PTC1/
LLWU_P6
LCD_P21/
ADC0_SE15/
TSI0_CH14
LCD_P21/
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3
SPI0_PCS2
UART1_RTS_
b
FTM0_CH0
FTM0_CH1
LCD_P21
LCD_P22
PTC2
LCD_P22/
LCD_P22/
PTC2
UART1_CTS_
b
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
106
A11
PTC3/
LLWU_P7
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
LCD_P23
107
108
109
110
111
112
113
H8
C10
C9
VSS
VSS
VSS
VLL3
VLL3
VLL3
VLL2
VLL2
VLL2
B9
VLL1
VLL1
VLL1
B10
A10
A9
VCAP2
VCAP1
VCAP2
VCAP1
LCD_P24
VCAP2
VCAP1
LCD_P24
PTC4/
LLWU_P8
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
CMP1_OUT
CMP0_OUT
I2S0_MCLK
LCD_P24
LCD_P25
LCD_P26
LCD_P27
LCD_P28
114
115
116
117
D8
C8
B8
A8
PTC5/
LLWU_P9
LCD_P25
LCD_P25
PTC5/
LLWU_P9
LPTMR0_
ALT2
PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
PDB0_EXTRG I2S0_RX_
BCLK
PTC7
PTC8
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
PTC8
USB_SOF_
OUT
I2S0_RX_FS
LCD_P28/
LCD_P28/
I2S0_MCLK
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
118
D7
PTC9
LCD_P29/
ADC1_SE5b/
CMP0_IN3
LCD_P29/
ADC1_SE5b/
CMP0_IN3
PTC9
I2S0_RX_
BCLK
FTM2_FLT0
LCD_P29
119
120
121
122
C7
B7
A7
D6
PTC10
LCD_P30/
ADC1_SE6b
LCD_P30/
ADC1_SE6b
PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
I2S0_RXD1
LCD_P30
LCD_P31
LCD_P32
LCD_P33
PTC11/
LLWU_P11
LCD_P31/
ADC1_SE7b
LCD_P31/
ADC1_SE7b
PTC11/
LLWU_P11
PTC12
PTC13
LCD_P32
LCD_P33
LCD_P32
LCD_P33
PTC12
PTC13
UART4_RTS_
b
UART4_CTS_
b
123
124
125
C6
B6
A6
PTC14
PTC15
PTC16
LCD_P34
LCD_P35
LCD_P36
LCD_P34
LCD_P35
LCD_P36
PTC14
PTC15
PTC16
UART4_RX
UART4_TX
UART3_RX
LCD_P34
LCD_P35
LCD_P36
ENET0_1588_
TMR0
126
D5
PTC17
LCD_P37
LCD_P37
PTC17
UART3_TX
ENET0_1588_
TMR1
LCD_P37
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
81
Preliminary
General Business Information
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
127
128
129
130
131
C5
B5
A5
D4
C4
PTC18
LCD_P38
LCD_P39
LCD_P40
LCD_P38
LCD_P39
LCD_P40
PTC18
UART3_RTS_
b
ENET0_1588_
TMR2
LCD_P38
LCD_P39
LCD_P40
LCD_P41
LCD_P42
PTC19
PTC19
UART3_CTS_
b
ENET0_1588_
TMR3
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART2_RTS_
b
PTD1
LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1
UART2_CTS_
b
PTD2/
LCD_P42
LCD_P42
PTD2/
UART2_RX
LLWU_P13
LLWU_P13
132
133
B4
A4
PTD3
LCD_P43
LCD_P44
LCD_P43
LCD_P44
PTD3
SPI0_SIN
UART2_TX
LCD_P43
LCD_P44
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_
b
FTM0_CH4
FTM0_CH5
EWM_IN
134
A3
PTD5
LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5
SPI0_PCS2
SPI0_PCS3
UART0_CTS_
b/
UART0_COL_
b
EWM_OUT_b
LCD_P45
135
A2
PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
UART0_RX
FTM0_CH6
FTM0_CH7
FTM0_FLT0
LCD_P46
136
137
138
139
M10
F8
VSS
VSS
VSS
VDD
VDD
VDD
A1
PTD7
PTD10
LCD_P47
DISABLED
LCD_P47
PTD7
CMT_IRO
UART0_TX
FTM0_FLT1
LCD_P47
B3
PTD10
UART5_RTS_
b
FB_AD9
140
B2
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_CTS_
b
SDHC0_
CLKIN
FB_AD8
141
142
143
144
B1
C3
C2
C1
PTD12
PTD13
PTD14
PTD15
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
FB_AD7
FB_AD6
FB_AD5
FB_RW_b
SPI2_PCS1
8.2 K53 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
82
Freescale Semiconductor, Inc.
Preliminary
General Business Information
Pinout
PTE0
1
108
107
106
105
104
103
102
101
100
99
VLL3
PTE1/LLWU_P0
2
VSS
PTE2/LLWU_P1
3
PTC3/LLWU_P7
PTC2
PTE3
4
VDD
5
PTC1/LLWU_P6
PTC0
VSS
6
PTE4/LLWU_P2
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE5
8
PTE6
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9
97
PTE10
96
PTE11
95
PTE12
94
VDD
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
91
USB0_DP
90
USB0_DM
PTB8
89
VOUT33
PTB7
88
VREGIN
PTB6
87
ADC0_DP1/OP0_DP0
PTB5
86
ADC0_DM1/OP0_DM0
PTB4
85
ADC1_DP1/OP1_DP0/OP1_DM1
PTB3
84
ADC1_DM1/OP1_DM0
PTB2
83
PGA0_DP/ADC0_DP0/ADC1_DP3
PTB1
82
PGA0_DM/ADC0_DM0/ADC1_DM3
PTB0/LLWU_P5
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
81
PGA1_DP/ADC1_DP0/ADC0_DP3
80
PGA1_DM/ADC1_DM0/ADC0_DM3
79
VDDA
78
VREFH
77
VREFL
VSSA
76
75
ADC1_SE16/OP1_OUT/CMP2_IN2/ADC0_SE22/OP0_DP2/OP1_DP2
ADC0_SE16/OP0_OUT/CMP1_IN2/ADC0_SE21/OP0_DP1/OP1_DP1
74
73
Figure 33. K53 144 LQFP Pinout Diagram
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
83
Preliminary
General Business Information
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTD6/
LLWU_P15
PTD4/
LLWU_P14
PTD0/
LLWU_P12
A
B
C
D
E
F
PTC8
VCAP1
PTC2
A
B
C
D
E
F
PTD7
PTD5
PTC16
PTC12
PTC11/
LLWU_P11
PTC1/
LLWU_P6
PTD12
PTD15
PTD11
PTD14
PTD10
PTD13
PTE0
PTD3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC7
VLL1
VLL2
VCAP2
VLL3
PTC0
PTB22
PTB18
PTB10
PTB6
PTD2/
LLWU_P13
PTC6/
LLWU_P10
PTC10
PTC9
VDD
PTB23
PTB19
PTB11
PTB7
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTC5/
LLWU_P9
PTD1
PTE3
PTE7
PTE11
PTB21
PTB17
PTB9
PTB5
PTB1
PTB20
PTB16
PTB8
PTE4/
LLWU_P2
PTE6
PTE10
PTE5
PTE9
VDD
VDD
VSS
PTE8
PTE12
VSS
VDD
VSS
VSS
G
H
J
G
H
J
VOUT33
USB0_DP
VREGIN
USB0_DM
VREFH
VDDA
VREFL
VSSA
PTA1
PTA2
VBAT
VSS
PTB4
PTB3
PTB2
PTB0/
LLWU_P5
PTE28
VSS
VSS
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
DAC1_OUT/
ADC0_SE16/
OP0_OUT/
CMP1_IN2/
CMP0_IN4/
ADC0_DP1/ ADC0_DM1/
CMP2_IN3/
PTA13/
LLWU_P4
PTA0
PTA6
PTA3
PTA7
PTA8
PTA9
PTA27
PTA16
PTA14
OP0_DP0
OP0_DM0 ADC0_SE21/ ADC1_SE23/
OP0_DP1/
OP0_DP5/
OP1_DP1
OP1_DP5
ADC1_SE16/
OP1_OUT/
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/ CMP2_IN5/
ADC1_DP1/
OP1_DP0/
OP1_DM1
TRI1_OUT/
ADC1_DM1/ CMP2_IN2/
OP1_DM0
K
L
K
L
PTA12
PTA11
ADC0_SE22/
OP0_DP4/
ADC1_SE22
OP0_DP2/
OP1_DP4
OP1_DP2
PGA0_DP/
PGA0_DM/
ADC0_DP0/ ADC0_DM0/
TRI0_OUT/
OP1_DM2
PTA4/
LLWU_P3
TRI0_DM
TRI1_DM
ADC1_DP3
ADC1_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PGA1_DP/
ADC1_DP0/ ADC1_DM0/
ADC0_DP3
PGA1_DM/
M
M
TRI0_DP
TRI1_DP
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
ADC0_DM3
1
2
3
4
5
6
7
8
9
10
11
12
Figure 34. K53 144 MAPBGA Pinout Diagram
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
84
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Document Number: K53P144M100SF2V2
Rev. 1, 6/2012
Preliminary
General Business Information
相关型号：
MK53N512CLQ100
Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
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