MCF5484 [FREESCALE]
Microprocessor Electrical Characteristics; 微处理器的电气特性
| 型号： | MCF5484 |
| 厂家： | 
Freescale |
| 描述： | Microprocessor Electrical Characteristics |
| 文件： | 总28页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCF5485EC
Rev. 2.1, 12/2004
Freescale Semiconductor
Data Sheet
MCF548x Integrated
Microprocessor Electrical
Characteristics
Applies to the MCF5480, MCF5481, MCF5482, MCF5483,
MCF5484, and MCF5485
Table of Contents
This chapter contains electrical specification tables and
reference timing diagrams for the MCF548x
microprocessor. This section contains detailed
information on power considerations, DC/AC electrical
characteristics, and AC timing specifications of the
MCF548x.
1
2
3
4
Maximum Ratings................................................1
Thermal Characteristics ......................................2
DC Electrical Specifications ................................3
Supply Voltage Sequencing and Separation
Cautions ..............................................................5
Output Driver Capability and Loading .................6
PLL Timing Specifications...................................7
Reset Timing Specifications................................8
FlexBus................................................................9
SDRAM Bus ......................................................11
5
6
7
8
9
NOTE
The parameters specified
in this MPU document
supersede any values
found in the module
specifications.
10 PCI Bus .............................................................17
11 Fast Ethernet AC Timing Specifications............18
12 General Timing Specifications...........................21
13 I2C Input/Output Timing Specifications .............21
14 JTAG and Boundary Scan Timing .....................23
15 DSPI Electrical Specifications ...........................26
16 Timer Module AC Timing Specifications............26
1 Maximum Ratings
Table 1 lists maximum and minimum ratings for supply
and operating voltages and storage temperature.
Operating outside of these ranges may cause erratic
behavior or damage to the processor.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Thermal Characteristics
Table 1. Absolute Maximum Ratings
Symbol
Rating
Value
Units
External (I/O pads) supply voltage (3.3-V power pins)
Internal logic supply voltage
EVDD
IVDD
–0.3 to +4.0
–0.5 to +2.0
V
V
V
Memory (I/O pads) supply voltage (2.5-V power pins)
SD VDD
–0.3 to +4.0 SDR Memory
–0.3 to +2.8 DDR Memory
PLL supply voltage
PLL VDD
Vin
–0.5 to +2.0
–0.5 to +3.6
–55 to +150
V
V
Internal logic supply voltage, input voltage level
Storage temperature range
Tstg
oC
2 Thermal Characteristics
2.1 Operating Temperatures
Table 2 lists junction and ambient operating temperatures.
Table 2. Operating Temperatures
Characteristic
Symbol
Value
Units
Maximum operating junction temperature
Maximum operating ambient temperature
Minimum operating ambient temperature
N1 OTES:
Tj
105
<851
– 40
oC
oC
oC
TAmax
TAmin
This published maximum operating ambient temperature should be used only as a system design guideline. All
device operating parameters are guaranteed only when the junction temperature lies within the specified range.
2.2 Thermal Resistance
Table 3 lists thermal resistance values.
Table 3. Thermal Resistance
Characteristic
Symbol
Value
Unit
324 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)
convection
θJMA
22–241,2
°C/W
388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)
convection
θJMA
20–221,2
°C/W
Junction to ambient (@200 ft/min)
Junction to board
Four layer board (2s2p)
Natural convection
θJMA
θJB
θJC
Ψjt
231,2
153
°C/W
°C/W
°C/W
°C/W
Junction to case
104
Junction to top of package
21,5
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
2
Freescale Semiconductor
DC Electrical Specifications
N1 OTES:
JA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.
θ
Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
2
3
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
4
5
3 DC Electrical Specifications
Table 4 lists DC electrical operating temperatures. This table is based on an operating voltage of
EV = 3.3 V ± 0.3 V and IV of 1.5 ± 0.07 V .
DD
DC
DC
DD
Table 4. DC Electrical Specifications
DC
Characteristic
Symbol
Min
Max
Units
External (I/O pads) operation voltage range
Memory (I/O pads) operation voltage range (DDR Memory)
Internal logic operation voltage range 1
PLL Analog operation voltage range 1
USB oscillator operation voltage range
USB digital logic operation voltage range
USB PHY operation voltage range
EVDD
SD VDD
IVDD
3.0
2.30
1.43
1.43
3.0
3.6
2.70
1.58
1.58
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
pF
PLL VDD
USB_OSVDD
USBVDD
USB_PHYVDD
USB_OSCAVDD
USB_PLLVDD
VIH
3.0
3.6
3.0
3.6
USB oscillator analog operation voltage range
USB PLL operation voltage range
1.43
1.43
2.0
1.58
1.58
3.6
Input high voltage SSTL 3.3V (SDR DRAM)
Input low voltage SSTL 3.3V (SDR DRAM)
Input high voltage SSTL 2.5V (DDR DRAM)
Input low voltage SSTL 2.5V (DDR DRAM)
Output high voltage IOH = 8 mA, 16 mA,24 mA
Output low voltage IOL = 8 mA, 16 mA,24 mA5
Capacitance 2, Vin = 0 V, f = 1 MHz
VIL
–0.5
2.0
0.8
VIH
2.8
VIL
–0.5
2.4
0.8
VOH
—
VOL
—
0.5
CIN
—
TBD
N1 OTES:
IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure 1 for an
example circuit. Note: There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input.
Capacitance CIN is periodically sampled rather than 100% tested.
2
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
3
DC Electrical Specifications
3.1 PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins.
DD
The filter shown in Figure 1 should be connected between the board V and the PLL V pins. The
DD
DD
resistor and capacitors should be placed as close to the dedicated PLL V pin as possible.
DD
10 W
Board VDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 1. System PLL V Power Filter
DD
3.2 USB Power Filtering
To minimize noise, a external filters are required for each of the USB power pins. The filter shown in
Figure 2 should be connected between the board EV or IV and each of the USB V pins. The
DD
DD
DD
resistor and capacitors should be placed as close to the dedicated USB V pin as possible. A separate
DD
filter circuit should be included for each USB V pin, a total of five circuits.
DD
R
Board EVDD/IVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 2. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also
recommended in parallel with those shown.
Table 5 lists the resistor values and supply voltages to be used in the circuit for each of the USB V pins.
DD
Table 5. USB Filter Circuit Values
USB VDD Pin
Nominal Voltage
Resistor Value (R)
USB_OSCVDD
USBVDD
3.3V
3.3V
3.3V
1.5V
1.5V
0Ω
0Ω
USB_PHYVDD
USB_OSCAVDD
USB_PLLVDD
0Ω
0Ω
10Ω
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
4
Supply Voltage Sequencing and Separation Cautions
4 Supply Voltage Sequencing and Separation
Cautions
Figure 3 shows situations in sequencing the I/O V (EV ), SDRAM V (SD V ), PLL V (PLL
DD
DD
DD
DD
DD
V
), and Core V (IV ).
DD
DD DD
EVDD, SD VDD (3.3V)
SD VDD (2.5V)
3.3V
Supplies Stable
2.5V
IVDD, PLL VDD
1.5V
1
2
0
Time
NOTES:
1. IVDD should not exceed EVDD, SD VDD or PLL VDD by more than
0.4V at any time, including power-up.
2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (EVDD, SD VDD
,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
4. Use 1 microsecond or slower rise time for all supplies.
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD V and EV is non-critical during power-up and power-down sequences.
DD
DD
Both SD V (2.5V or 3.3V) and EV are specified relative to IV .
DD
DD
DD
4.1 Power Up Sequence
If EV /SD V are powered up with the IV at 0V, then the sense circuits in the I/O pads will cause
DD
DD
DD
all pad output drivers connected to the EV /SD V to be in a high impedance state. There is no limit
DD
DD
on how long after EV /SD V powers up before IV must power up. IV should not lead the EV ,
DD
DD
DD
DD
DD
SD V or PLL V by more than 0.4V during power ramp up, or there will be high current in the internal
DD
DD
ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid
turning on the internal ESD protection clamp diodes.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
5
Output Driver Capability and Loading
The recommended power up sequence is as follows:
1. Use 1 microsecond or slower rise time for all supplies.
2. IV /PLL V and EV /SD V should track up to 0.9V, then separate for the completion of
DD
DD
DD
DD
ramps with EV /SD V going to the higher external voltages. One way to accomplish this is to
DD
DD
use a low drop-out voltage regulator.
4.2 Power Down Sequence
If IV PLL V are powered down first, then sense circuits in the I/O pads will cause all output drivers
DD
DD
to be in a high impedance state. There is no limit on how long after IV and PLL V power down before
DD
DD
EV or SD V must power down. IV should not lag EV , SD V , or PLL V going low by
DD
DD
DD
DD
DD
DD
more than 0.4V during power down or there will be undesired high current in the ESD protection diodes.
There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PLL V to 0V
DD
DD
2. Drop EV /SD V supplies
DD
DD
5 Output Driver Capability and Loading
Table 6 lists values for drive capability and output loading.
Table 6. I/O Driver Capability
Drive
Output
Signal
Capability Load (CL)
SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0],
SDWE, SDBA[1:0]
24 mA
15 pF
SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0],
SDCLK[1:0], SDCKE)
24 mA
15 pF
SDRAMC chip selects (SDCS[3:0])
24 mA
16 mA
8 mA
8 mA
8 mA
8 mA
8 mA
24 mA
15 pF
20 pF
15 pF
50 pF
30 pF
30 pF
30 pF
50 pF
FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE)
FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER
Timer (TOUT[3:0])
FlexCAN (CANTX)
DACK[1:0]
PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,
DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
6
Freescale Semiconductor
PLL Timing Specifications
Output
Table 6. I/O Driver Capability (continued)
Signal
Drive
Capability Load (CL)
PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL,
PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP,
PCIPAR, PCITRDY, PCIIRDY
16 mA
50 pF
I2C (SCL, SDA)
8 mA
8 mA
8 mA
50 pF
25 pF
50 pF
BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO,
RSTO
6 PLL Timing Specifications
The specifications in Table 7 are for the CLKIN pin.
Table 7. Clock Timing Specification
Num Characteristic
Min
Max
Units
C1 Cycle time
15.15
—
33.3
2
ns
ns
ns
%
C2 Rise time (20% of Vdd to 80% of vdd)
C3 Fall time (80% of Vdd to 20% of Vdd)
C4 Duty cycle (at 50% of Vdd)
—
2
40
60
C1
CLKIN
C4
C4
C2
C3
Figure 4. Input Clock Timing Diagram
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
7
Reset Timing Specifications
Figure 5 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
CLKIN
Internal Clock
Core Clock
2x
2x
2x
4x
50.0
100.0
25.0
50.0
100.0
100.0
200.0
200.0
25.0
25 40 50 60 70
CLKIN (MHz)
30 40 50 60 70 80 90 100
Internal Clock (MHz)
60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Core Clock (MHz)
Table 8. MCF548X Divide Ratio Encodings
Internal XLB, SDRAM
Bus, and PSTCLK Frequency
Range (MHz)
Clock
Ratio
CLKIN—PCI and FlexBus
Frequency Range (MHz)
Core Frequency Range
(MHz)
AD[12:8]1
00011
00101
1:2
1:2
1:4
41.6–50.0
25.0–41.5
25
83.33–100
50.0–83.02
100
166.66–200
100.0–166.66
200
01111
N1 OTES:
All other values of AD[12:8] are reserved.
Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specify down to 75 MHz.
Check with memory component specifications to verify.
2
Figure 5. CLKIN, Internal Bus, and Core Clock Ratios
7 Reset Timing Specifications
Table 9 lists specifications for the reset timing parameters shown in Figure 6
Table 9. Reset Timing Specification
66 MHz CLKIN
Num
Characteristic
Units
Min
Max
R1 1 Valid to CLKIN (setup)
8
—
—
—
nS
nS
nS
R2
R3
CLKIN to invalid (hold)
RSTI to invalid (hold)
1.0
1.0
N1 OTES:
RSTI and FlexBus data lines are synchronized internally. Setup and hold
times must be met only if recognition on a particular clock is required.
Figure 6 shows reset timing for the values in Table 9.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
8
FlexBus
CLKIN
RSTI
R1
R2
Mode Select
FlexBus
R1
R3
NOTE:
Mode selects are registered on the rising clock edge before
the cycle in which RSTI is recognized as being negated.
Figure 6. Reset Timing
8 FlexBus
A multi-function external bus interface called FlexBus is provided on the MCF5482 with basic
functionality to interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be
directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories,
gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six
general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and
can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing
is compatible with common ROM / flash memories.
8.1 FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
Table 10. FlexBus AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Frequency of Operation
FB1 Clock Period (CLKIN)
25
15.15
—
66
33.33
7.0
Mhz
ns
2
3
FB2 Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
ns
3, 4
FB3 Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
1
—
ns
FB4 Data Input Setup
FB5 Data Input Hold
3.5
0
—
—
ns
ns
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
9
FlexBus
Table 10. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
FB6 Transfer Acknowledge (TA) Input Setup
FB7 Transfer Acknowledge (TA) Input Hold
FB8 Address Output Valid (PCIAD[31:0])
FB9 Address Output Hold (PCIAD[31:0])
4
0
—
—
ns
ns
ns
ns
5
5
—
0
7.0
—
N1 OTES:
The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section 9.2, “DDR SDRAM AC
Timing Characteristics” for SDCS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the MCF548X
specification manual for more information.
These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.
2
3
4
5
CLKIN
FB1
FB3
AD[X:0]
A[X:0]
FB2
FB5
AD[31:Y]
A[31:Y]
DATA
R/W
FB4
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
FB7
OE
TA
FB6
Figure 7. FlexBus Read Timing
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
10
SDRAM Bus
CLKIN
FB1
FB3
FB3
AD[X:0]
A[X:0]
FB2
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
FB7
OE
TA
FB6
Figure 8. FlexBus Write Timing
9 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.
9.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read
cycles. The MCF548x SDRAM controller is a DDR controller that has an SDR mode. Because it is
designed to support DDR, a DQS pulse must still be supplied to the MCF548x for each data beat of an
SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SDR_DQS signal and its usage.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
11
SDRAM Bus
Symbol
Table 11. SDR Timing Specifications
Characteristic
Frequency of Operation
Clock Period (tCK
Clock Skew (tSK
Pulse Width High (tCKH
Pulse Width Low (tCKL
Min
Max
Unit
Notes
1
50
133
12
Mhz
ns
2
SD1
SD2
SD3
SD4
SD5
)
7.52
)
TBD
0.55
0.55
3
4
)
0.45
0.45
SDCLK
SDCLK
ns
)
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (tCMV
)
)
0.5 × SDCLK +
1.0ns
SD6
SD7
SD8
SD9
SD10
Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (tCMH
2.0
ns
ns
ns
5
6
7
8
SDRDQS Output Valid (tDQSOV
SDDQS[3:0] input setup relative to SDCLK (tDQSIS
SDDQS[3:0] input hold relative to SDCLK (tDQSIH
Data Input Setup relative to SDCLK (reference only) (tDIS
)
Self timed
)
0.25 × SDCLK 0.40 × SDCLK
)
Does not apply. 0.5 SDCLK fixed width.
)
0.25 × SDCLK
ns
SD11
SD12
Data Input Hold relative to SDCLK (reference only) (tDIH
)
1.0
ns
ns
Data and Data Mask Output Valid (tDV
)
0.75 × SDCLK
+0.500ns
SD13
Data and Data Mask Output Hold (tDH
)
1.5
ns
N1 OTES:
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Specification for
more information on setting the SDRAM clock rate.
2
3
4
5
SDCLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
6
7
8
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the MCF548X, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input
setup spec is just provided as guidance.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
12
Freescale Semiconductor
SDRAM Bus
SD1
SD3
SD2
SDCLK0
SDCLK1
SD2
SD4
SD6
SDCSn,SDWE,
RAS, CAS
CMD
SD5
SDADDR,
SDBA[1:0]
ROW
COL
SD12
SDDM
SD13
WD2
SDDATA
WD1
WD3
WD4
Figure 9. SDR Write Timing
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
13
SDRAM Bus
SD1
SD2
SDCLK0
SD2
SDCLK1
SD6
SDCSn,SDWE,
RAS, CAS
CMD
3/4 MCLK
Reference
SD5
SDADDR,
SDBA[1:0]
ROW
COL
tDQS
SDDM
SD7
SDRQS (Measured at Output Pin)
SDDQS (Measured at Input Pin)
Board Delay
Board Delay
SD9
SD8
Delayed
SDCLK
SD10
SDDATA
form
Memories
WD1
WD2
WD3
WD4
NOTE: Data driven from memories relative
to delayed memory clock.
SD11
Figure 10. SDR Read Timing
9.2 DDR SDRAM AC Timing Characteristics
When using the DDR SDRAM controller, the following timing numbers must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Table 12shows the DDR clock crossover specifications.
Table 12. DDR Clock Crossover Specifications
Symbol
Characteristic
Clock output mid-point voltage
Min
Max
Unit
VMP
VOUT
VID
1.05
–0.3
0.7
1.45
V
V
V
V
Clock output voltage level
SD_VDD + 0.3
SD_VDD + 0.6
1.45
Clock output differential voltage (peak to peak swing)
Clock crossing point voltage1
VIX
1.05
N1 OTES:
The clock crossover voltage is only guaranteed when using the highest drive strength option for the
SDCLK[1:0] and SDCLK[1:0] signals.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
14
Freescale Semiconductor
SDRAM Bus
SDCLK
SDCLK
VIX
VMP
VIX
VID
Figure 11. DDR Clock Timing Diagram
Table 13. DDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit
MHz
Notes
2
Frequency of Operation
501
7.52
0.45
0.45
—
133
12
3
4
5
6
DD1 Clock Period (tCK
DD2 Pulse Width High (tCKH
DD3 Pulse Width Low (tCKL
DD4 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output
Valid (tCMV
DD5 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold
(tCMH
DD6 Write Command to first DQS Latching Transition (tDQSS
DD7 Data and Data Mask Output Setup (DQ−>DQS) Relative to
DQS (DDR Write Mode) (tQS
DD8 Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS
(DDR Write Mode) (tQH
)
ns
)
0.55
0.55
SDCLK
SDCLK
ns
)
0.5 × SDCLK
+ 1.0 ns
)
2.0
—
ns
)
)
—
1.25
—
SDCLK
ns
7
8
1.0
)
9
1.0
—
ns
)
10
11
DD9 Input Data Skew Relative to DQS (Input Setup) (tIS)
DD10 Input Data Hold Relative to DQS (tIH)
1
ns
ns
0.25 × SDCLK
—
+ 0.5ns
DD11 DQS falling edge to SDCLK rising (output setup time) (tDSS
)
0.5
0.5
0.9
—
—
ns
DD12 DQS falling edge from SDCLK rising (output hold time) (tDSH
DD13 DQS input read preamble width (tRPRE
DD14 DQS input read postamble width (tRPST
DD15 DQS output write preamble width (tWPRE
DD16 DQS output write postamble width (tWPST
)
ns
)
1.1
0.6
—
SDCLK
SDCLK
SDCLK
SDCLK
)
0.4
)
0.25
0.4
)
0.6
N1 OTES:
Note that DDR memories typically have a minimum speed specification of 83 MHz. Some vendors go to 75 MHz. Check
with memory component specifications to verify.
2
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see Section 2.2.6, “Reset Configuration Pins.”
SDCLK is one memory clock in (ns).
Pulse width high plus pulse width low cannot exceed max clock period.
Pulse width high plus pulse width low cannot exceed max clock period.
3
4
5
6
Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
7
This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to
SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative
SDDQS0.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
15
SDRAM Bus
8
The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining
data beats will be valid for each subsequent SDDQS edge.
9
This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
10
11
Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
DD1
DD2
SDCLK0
SDCLK1
SDCLK0
SDCLK1
DD3
DD5
SDCSn,SDWE,
RAS, CAS
CMD
ROW
DD4
DD6
SDADDR,
SDBA[1:0]
COL
DD7
SDDM
SDDQS
SDDATA
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 12. DDR Write Timing
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
16
PCI Bus
DD1
DD2
SDCLK0
SDCLK1
SDCLK0
SDCLK1
DD3
DD5
CL=2
SDCSn,SDWE,
RAS, CAS
CMD
ROW
DD4
CL=2.5
SDADDR,
SDBA[1:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SDDQS
SDDATA
SDDQS
SDDATA
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
WD1 WD2 WD3 WD4
Figure 13. DDR Read Timing
10 PCI Bus
The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the
PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis.
Table 14. PCI Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Frequency of Operation
Clock Period (tCK
25
15.15
3.0
7.0
—
66
33.33
—
MHz
ns
2
P1
P2
P3
P4
P5
)
Address, Data, and Command (33< PCI ≤ 66 Mhz)—Input Setup (tIS)
Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS)
ns
—
ns
3
Address, Data, and Command (33-66 Mhz) - Output Valid (tDV
)
6.0
ns
Address, Data, and Command (0 -33 Mhz) - Output Valid (tDV
)
—
11.0
ns
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
17
Fast Ethernet AC Timing Specifications
Table 14. PCI Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
4
P6
P7
P8
P9
PCI signals (0 - 66 Mhz) - Output Hold (tDH
)
0
—
—
6
ns
ns
ns
ns
ns
ns
ns
5
6
PCI signals (0 - 66 Mhz) - Input Hold (tIH)
0
PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Output valid (tDV
)
—
—
—
12
10
PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV
)
12
5
P10 PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Input Setup (tIS)
P11 PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS)
P12 PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS)
—
—
NOTES:
1
Please see Section 2.2.6, “Reset Configuration Pins,” for more information on setting the PCI clock rate. Also
specific guidelines may need to be followed when operating the system PLL below certain frequencies.
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
2
3
4
5
6
PCI 2.2 spec requires zero input hold.
These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
P1
CLKIN
P4
P6
Output
Valid/Hold
Output Valid
P2
Input
Setup/Hold
Input Valid
P7
Figure 14. PCI Timing
11 Fast Ethernet AC Timing Specifications
11.1 MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of
transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may
be altered to match that specific transceiver.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
18
Freescale Semiconductor
Fast Ethernet AC Timing Specifications
Table 15. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
M4
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
RXCLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
RXCLK period
RXCLK period
RXCLK pulse width low
M3
M1
RXCLK (Input)
M4
RXD[3:0] (Inputs)
RXDV,
RXER
M2
Figure 15. MII Receive Signal Timing Diagram
11.2 MII Transmit Signal Timing
Table 16. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
M8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
TXCLK pulse width high
0
—
ns
—
25
ns
35%
35%
65%
65%
TXCLK period
TXCLK period
TXCLK pulse width low
M7
TXCLK (Input)
M5
M8
TXD[3:0] (Outputs)
TXEN,
TXER
M6
Figure 16. MII Transmit Signal Timing Diagram
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
19
Fast Ethernet AC Timing Specifications
11.3 MII Async Inputs Signal Timing (CRS, COL)
Table 17. MII Transmit Signal Timing
Num
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
M9
1.5
—
TX_CLK period
CRS, COL
M9
Figure 17. MII Async Inputs Timing Diagram
11.4 MII Serial Management Channel Timing (MDIO,MDC)
Table 18. MII Serial Management Channel Signal Timing
Num
Characteristic
Min
Max
Unit
M10
MDC falling edge to MDIO output invalid
(min prop delay)
0
—
ns
M11
MDC falling edge to MDIO output valid
(max prop delay)
—
25
ns
M12
M13
M14
M15
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
MDC pulse width high
10
0
—
—
ns
ns
40%
40%
60%
60%
MDC period
MDC period
MDC pulse width low
M14
M15
MDC (Output)
MDIO (Output)
MDIO (Input)
M10
M12
M11
M13
Figure 18. MII Serial Management Channel TIming Diagram
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
20
Freescale Semiconductor
General Timing Specifications
12 General Timing Specifications
Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts.
Table 19. General AC Timing Specifications
Name
G1
Characteristic
CLKIN high to signal output valid
Min
Max
Unit
—
0
2
PSTCLK
ns
G2
G3
CLKIN high to signal invalid (output hold)
Signal input pulse width
—
—
2
PSTCLK
13 I2C Input/Output Timing Specifications
2
Table 20 lists specifications for the I C input timing parameters shown in Figure 19.
2
Table 20. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
I5
I6
I7
I8
I9
2
8
—
—
1
Bus clocks
Bus clocks
mS
Clock low period
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
1
ns
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
mS
—
—
—
—
Bus clocks
ns
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
Bus clocks
Bus clocks
2
2
Table 21 lists specifications for the I C output timing parameters shown in Figure 19.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
21
I2C Input/Output Timing Specifications
2
Table 21. I C Output Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I11
I2 1
I3 2
I4 1
I5 3
I6 1
I7 1
I8 1
6
—
—
—
—
3
Bus clocks
Bus clocks
µS
Clock low period
10
—
7
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
Bus clocks
ns
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
10
2
—
—
—
Bus clocks
Bus clocks
Bus clocks
Data setup time
Start condition setup time (for repeated start
condition only)
20
I9 1
Stop condition setup time
10
—
Bus clocks
N1 OTES:
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 21. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the SCL low period. The actual position is affected by the prescale and division values
programmed into the IFDR; however, the numbers given in Table 21 are minimum values.
Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.
2
3
Specified at a nominal 50-pF load.
Figure 19 shows timing for the values in Table 20 and Table 21.
I2
I6
I5
SCL
SDA
I1
I3
I7
I4
I8
I9
2
Figure 19. I C Input/Output Timings
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
22
Freescale Semiconductor
JTAG and Boundary Scan Timing
14 JTAG and Boundary Scan Timing
Table 22. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fJCYC
tJCYC
DC
2
10
—
MHz
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK Cycle Period
TCLK Clock Pulse Width
tJCW
15.15
0.0
—
TCLK Rise and Fall Times
tJCRF
3.0
—
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
tBSDST
tBSDHT
tBSDV
5.0
24.0
0.0
—
15.0
15.0
—
tBSDZ
0.0
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
5.0
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
10.0
0.0
—
15.0
15.0
—
J12 TCLK Low to TDO High Z
0.0
J13 TRST Assert Time
100.0
10.0
J14 TRST Setup Time (Negation) to TCLK High
—
N1 OTES:
MTMOD is expected to be a static signal. Hence, it is not associated with any timing
J2
J3
J3
VIH
TCLK (Input)
VIL
J4
J4
Figure 20. Test Clock Input Timing
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
23
JTAG and Boundary Scan Timing
VIH
TCLK
Data Inputs
VIL
5
6
Input Data Valid
7
8
Data Outputs
Data Outputs
Data Outputs
Output Data Valid
7
Output Data Valid
Figure 21. Boundary Scan (JTAG) Timing
VIH
TCLK
TDI, TMS, BKPT
TDO
VIL
9
10
Input Data Valid
11
12
Output Data Valid
TDO
11
TDO
Output Data Valid
Figure 22. Test Access Port Timing
TCLK
TRST
14
13
Figure 23. TRST Timing Debug AC Timing Specifications
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
24
Freescale Semiconductor
JTAG and Boundary Scan Timing
Table 23 lists specifications for the debug AC timing parameters shown in Figure 25.
Table 23. Debug AC Timing Specification
66 MHz
Num
Characteristic
Units
Min
Max
D1
D2
PSTDDATA to PSTCLK setup
PSTCLK to PSTDDATA hold
DSI-to-DSCLK setup
4.5
4.5
1
ns
ns
D3
PSTCLKs
PSTCLKs
PSTCLKs
D4 1
DSCLK-to-DSO hold
4
D5
DSCLK cycle time
5
N1 OTES:
DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 24 shows real-time trace timing for the values in Table 23.
PSTCLK
D1
D2
PSTDDATA[7:0]
Figure 24. Real-Time Trace AC Timing
Figure 25 shows BDM serial port AC timing for the values in Table 23.
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Figure 25. BDM Serial Port AC Timing
Current
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
25
DSPI Electrical Specifications
15 DSPI Electrical Specifications
Table 24 lists DSPI timings.
Table 24. DSPI Modules AC Timing Specifications
Name
DS1
Characteristic
Min
Max
Unit
DSPI_CS[3:0] to DSPI_CLK
1 × tck
—
510 × tck
ns
ns
ns
ns
ns
DS2
DS3
DS4
DS5
DSPI_CLK high to DSPI_DOUT valid.
DSPI_CLK high to DSPI_DOUT invalid. (Output hold)
DSPI_DIN to DSPI_CLK (Input setup)
DSPI_DIN to DSPI_CLK (Input hold)
12
—
—
—
2
10
10
The values in Table 24 correspond to Figure 26.
DSPI_CS[3:0]
DS1
DSPI_CLK
DSPI_DOUT
DSPI_DIN
DS2
DS3
DS4
DS5
Figure 26. DSPI Timing
16 Timer Module AC Timing Specifications
Table 25 lists timer module AC timings.
Table 25. Timer Module AC Timing Specifications
0–66 MHz
Name
Characteristic
Unit
Min
Max
T1
T2
TIN0 / TIN1 / TIN2 / TIN3 cycle time
TIN0 / TIN1 / TIN2 / TIN3 pulse width
3
1
—
—
PSTCLK
PSTCLK
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
26
Freescale Semiconductor
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MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
Freescale Semiconductor
27
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MCF5485EC
Rev. 2.1
12/2004
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