MC68HC11K3VFN3 [FREESCALE]
8-Bit Microcontroller; 8位微控制器
| 型号： | MC68HC11K3VFN3 |
| 厂家： | 
Freescale |
| 描述： | 8-Bit Microcontroller |
| 文件： | 总80页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Order this document
by MC68HC11KTS/D
M68HC11 K Series
Technical Summary
8-Bit Microcontroller
The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the
MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1,
MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul-
tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static
design allows operation at frequencies from 4 MHz to dc.
This document contains information concerning standard, custom-ROM, and extended-voltage devic-
es. Standard devices include those with disabled ROM (MC68HC11K1), disabled EEPROM
(MC68HC11K3), disabled ROM and EEPROM (MC68HC11K0), or EPROM replacing ROM
(MC68HC711K4). Custom-ROM devices have a ROM array that is programmed at the factory to cus-
tomer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage
range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the device ordering
information tables for details concerning these differences.
1 Features
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 768 Bytes RAM (All Saved During Standby)
• 24 Kbytes ROM or EPROM
• 640 Bytes Electrically Erasable Programmable Read Only Memory (EEPROM)
• Optional Security Feature Protects Memory Contents
• On-Chip Memory Mapping Logic Allows Expansion to Over 1 Mbyte of Address Space
• PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)
• Nonmultiplexed Address and Data Buses
• Four Programmable Chip Selects with Clock Stretching (Expanded Modes)
• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Four 8-Bit or Two 16-Bit Pulse Width Modulation (PWM) Timer Channels
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Clock Monitor
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Seven Bidirectional Input/Output (I/O) Ports (54 Pins)
• One Fixed Input-Only Port (8 Pins)
• Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip
Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
For More Information On This Product,
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© MOTOROLA INC., 1997
Freescale Semiconductor, Inc.
Table 1 Standard Device Ordering Information
Package
Temperature
–40°to + 85°C
–40°to + 85°C
CONFIG
$DF
Description
BUFFALO ROM
No ROM
Frequency
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
MC Order Number
MC68HC11K4BCFN4
MC68HC11K1CFN2
MC68HC11K1CFN3
MC68HC11K1CFN4
MC68HC11K1VFN2
MC68HC11K1VFN3
MC68HC11K1VFN4
MC68HC11K1MFN2
MC68HC11K1MFN3
MC68HC11K1MFN4
MC68HC11K0CFN2
MC68HC11K0CFN3
MC68HC11K0CFN4
MC68HC11K0VFN2
MC68HC11K0VFN3
MC68HC11K0VFN4
MC68HC11K0MFN2
MC68HC11K0MFN3
MC68HC11K0MFN4
MC68HC711K4CFN2
MC68HC711K4CFN3
MC68HC711K4CFN4
MC68HC711K4VFN2
MC68HC711K4VFN3
MC68HC711K4VFN4
MC68HC711K4MFN2
MC68HC711K4MFN3
MC68HC711K4MFN4
MC68HC11K4BCFU4
MC68HC11K1CFU2
MC68HC11K1CFU3
MC68HC11K1CFU4
MC68HC11K1VFU2
MC68HC11K1VFU3
MC68HC11K1VFU4
MC68HC11K0CFU2
MC68HC11K0CFU3
MC68HC11K0CFU4
MC68HC11K0VFU2
MC68HC11K0VFU3
MC68HC11K0VFU4
84-Pin PLCC
$DD
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
$DD
$DD
$DC
$DC
$DC
$DF
$DF
$DF
No ROM
No ROM
No ROM, No EEPROM
No ROM, No EEPROM
No ROM, No EEPROM
OTPROM
OTPROM
OTPROM
80-Pin QFP
(14 mm X 14
mm)
–40°to + 85°C
–40°to + 85°C
$DF
$DD
BUFFALO ROM
No ROM
–40°to + 105°C
–40°to + 85°C
–40°to + 105°C
$DD
$DC
$DC
No ROM
No ROM, No EEPROM
No ROM, No EEPROM
MOTOROLA
2
M68HC11 K Series
MC68HC11KTS/D
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Table 1 Standard Device Ordering Information (Continued)
Package
Temperature
CONFIG
Description
Frequency
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
MC Order Number
MC68HC711K4CFS2
MC68HC711K4CFS3
MC68HC711K4CFS4
MC68HC711K4VFS2
MC68HC711K4VFS3
MC68HC711K4VFS4
MC68HC711K4MFS2
MC68HC711K4MFS3
MC68HC711K4MFS4
84-Pin CLCC
(Windowed)
–40°to + 85°C
$DF
EPROM
–40°to + 105°C
–40°to + 125°C
$DF
$DF
EPROM
EPROM
Table 2 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering Information
Package
Temperature
Description
Frequency
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
1 MHz
3 MHz
MC Order Number
MC68L11K4FN1
MC68L11K4FN3
MC68L11K1FN1
MC68L11K1FN3
MC68L11K0FN1
MC68L11K0FN3
MC68L11K3FN1
MC68L11K3FN3
MC68L11K4FU1
MC68L11K4FU3
MC68L11K1FU1
MC68L11K1FU3
MC68L11K0FU1
MC68L11K0FU3
MC68L11K3FU1
MC68L11K3FU3
84-Pin PLCC
–20°to + 70°C
Custom ROM
No ROM
No ROM, No EEPROM
Custom ROM, No EEPROM
Custom ROM
80-Pin QFP
–20°to + 70°C
No ROM
No ROM, No EEPROM
Custom ROM, No EEPROM
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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3
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Table 3 Custom ROM Device Ordering Information
Package
Temperature
Description
Frequency
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
MC Order Number
MC68HC11K4CFN2
MC68HC11K4CFN3
MC68HC11K4CFN4
MC68HC11K4VFN2
MC68HC11K4VFN3
MC68HC11K4VFN4
MC68HC11K4MFN2
MC68HC11K4MFN3
MC68HC11K4MFN4
MC68HC11K3CFN2
MC68HC11K3CFN3
MC68HC11K3CFN4
MC68HC11K3VFN2
MC68HC11K3VFN3
MC68HC11K3VFN4
MC68HC11K3MFN2
MC68HC11K3MFN3
MC68HC11K3MFN4
MC68HC11K4CFU2
MC68HC11K4CFU3
MC68HC11K4CFU4
MC68HC11K4VFU2
MC68HC11K4VFU3
MC68HC11K4VFU4
MC68HC11K3CFU2
MC68HC11K3CFU3
MC68HC11K3CFU4
MC68HC11K3VFU2
MC68HC11K3VFU3
MC68HC11K3VFU4
84-Pin PLCC
–40°to + 85°C
Custom ROM
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 85°C
–40°to + 105°C
Custom ROM
Custom ROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
Custom ROM
80-Pin QFP
Custom ROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
MOTOROLA
4
M68HC11 K Series
MC68HC11KTS/D
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74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PD2/MISO
PD1/TxD
PD0/RxD
MODA/LIR
MODB/V
PH0/PW1
PH1/PW2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
PH2/PW3
PH3/PW4
PH4/CSIO
STBY
RESET
XTAL
EXTAL
XOUT
E
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
1
TEST16
2
XIRQ/V
PPE
1
V
TEST15
MC68HC11K SERIES
DD
V
V
DD
SS
V
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
PC0/DATA0
IRQ
SS
1
TEST14
PG7/R/W
PG6
PG5/XA18
PG4/XA17
PG3/XA16
PG2/XA15
PG1/XA14
1. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry.
2. V
PPE
applies only to devices with EPROM.
Figure 1 Pin Assignments for 84-Pin PLCC/CLCC
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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PD3/MOSI
PD4/SCK
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PF0/ADDR0
PF1/ADDR1
PF2/ADDR2
PF3/ADDR3
PF4/ADDR4
PF5/ADDR5
PF6/ADDR6
PF7/ADDR7
PD5/SS
PA7/PAI/OC1
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
AV
SS
V
PA1/IC2
10
11
12
13
14
15
16
17
18
19
20
RH
MC68HC11K SERIES
V
PA0/IC3
RL
V
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
PE4/AN4
PE5/AN5
PE6/AN6
PE7/AN7
DD
V
SS
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
AV
DD
Figure 2 Pin Assignments for 80-Pin 14 mm X 14 mm TQFP
MOTOROLA
6
M68HC11 K Series
MC68HC11KTS/D
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XTAL
EXTAL
IRQ
XIRQ/V
RESET
INTERRUPT
LOGIC
PPE
E
*XOUT
MODA/
LIR
V
A/D
CONVERTER
RH
OSCILLATOR
V
RL
CLOCK
LOGIC
MODE
CONTROL
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
MODB/
V
STBY
PULSE
ACCUMULATOR
COP
PA7
PAI/OC1
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OC2/OC1
OC3/OC1
OC4/OC1
OC5/IC4/OC1
IC1
IC2
IC3
TIMER
SYSTEM
AV
DD
AV
SS
PERIODIC
INTERRUPT
V
DD
CHIP
SELECTS
V
SS
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
CSPROG
CSGP2
CSGP1
CSIO
PH7
PH6
PH5
PH4
24
KBYTES
ROM/
EPROM
(K3, K4)
640
PW4
PW3
PW2
PH3
PH2
PH1
PH0
BYTES
EEPROM
(K1, K4)
ADDR8
PWM
PW1
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
0
0
SS
PD5
PD4
PD3
PD2
KBYTES KBYTES
ROM/
EPROM
(K0, K1)
SCK
SPI
EEPROM
(K0, K3)
768
BYTES
RAM
MOSI
CPU
MISO
PD1
PD0
TxD
SCI
RxD
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
R/W
MEMORY
EXPANSION
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
XA18
XA17
XA16
XA15
XA14
XA13
*XOUT pin omitted on 80-pin QFP.
Figure 3 M68HC11 K-Series Block Diagram
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
7
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TABLE OF CONTENTS
Section
Page
1
2
Features
Operating Modes
1
11
2.1
2.2
2.3
2.4
2.5
Single-Chip Operating Mode .....................................................................................................11
Expanded Operating Mode .......................................................................................................11
Bootstrap Mode .........................................................................................................................11
Special Test Mode .....................................................................................................................11
Mode Selection ..........................................................................................................................11
3
On-Chip Memory
14
3.1
3.2
3.3
3.4
3.5
3.6
Memory Map and Register Block ..............................................................................................14
RAM ..........................................................................................................................................17
ROM/EPROM ............................................................................................................................18
EEPROM ...................................................................................................................................22
Configuration Control Register (CONFIG) .................................................................................24
Security Feature ........................................................................................................................25
4
Memory Expansion and Chip Selects
27
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Memory Expansion ....................................................................................................................27
Overlap Guidelines ....................................................................................................................30
Chip Selects ..............................................................................................................................30
Program Chip Select (CSPROG) ...................................................................................31
I/O Chip Select (CSIO) ...................................................................................................31
General-Purpose Chip Selects (CSGP1, CSGP2) .........................................................32
Chip Select Priorities ......................................................................................................32
Chip Select Control Registers ........................................................................................32
Examples of Memory Expansion Using Chip Selects .....................................................35
5
6
7
8
9
10
Resets and Interrupts
Parallel Input/Output
38
42
49
56
60
64
Serial Communications Interface
Serial Peripheral Interface
Analog-to-Digital Converter
Main Timer
10.1 Real-Time Interrupt ...................................................................................................................70
11
12
Pulse Accumulator
Pulse-Width Modulation Timer
12.1 PWM Boundary Cases ..............................................................................................................78
71
74
MOTOROLA
8
M68HC11 K Series
MC68HC11KTS/D
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REGISTER INDEX
C
CFORC
CONFIG
COPRST
CSCSTR
CSCTL
Timer Compare Force
$000B
$003F
$003A
$005A
$005B
66
25
40
33
32
System Configuration Register
Arm/Reset COP Timer Circuitry
Chip Select Clock Stretch
Chip Select Control
D
DDRA
DDRB
DDRF
DDRG
DDRH
Data Direction Register for Port A
Data Direction Register for Port B
Data Direction Register for Port F
Data Direction Register for Port G
Data Direction Register for Port H
$0001
$0002
$0003
$007F
$007D
42
43
46
47
46
E
EPROG
EPROM Programming Control
$002B
19
G
GPCS1A
GPCS1C
GPCS2A
GPCS2C
General-Purpose Chip Select 1 Address
General-Purpose Chip Select 1 Control
General-Purpose Chip Select 2 Address
General-Purpose Chip Select 2 Control
$005C
$005D
$005E
$005F
33
34
34
34
H
HPRIO
Highest Priority I-Bit Interrupt and Miscellaneous
$003C
11, 40
I
RAM and Register Mapping
EEPROM Mapping
INIT
INIT2
$003D
$0037
18
24
M
Memory Mapping Size
Memory Mapping Window Base
MMSIZ
MMWBR
$0056
$0057
28
29
O
Output Compare 1 Data
Output Compare 1 Mask
System Configuration Options 2
System Configuration Options
OC1D
OC1M
OPT2
$000D
$000C
$0038
$0039
66
66
12, 44, 59
39
OPTION
P
Pulse Accumulator Counter
Pulse Accumulator Control
Port G Assignment
Port A Data
Port B Data
Port C Data
Port E Data
Port F Data
Port G Data
Port H Data
Port Pull-Up Assignment
EEPROM Programming Control
Pulse-Width Modulation Clock Select
PACNT
PACTL
PGAR
$0027
$0026
$002D
$0000
$0004
$0006
$000A
$0005
$007E
$007C
$002C
$003B
$0060
73
73
28, 47
42
PORTA
PORTB
PORTC
PORTE
PORTF
PORTG
PORTH
PPAR
43
43
46
46
47
46
48
22
PPROG
PWCLK
62, 76
M68HC11 K Series
MC68HC11KTS/D
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PWCNT[4:1]
PWDTY[4:1]
PWEN
PWPER[4:1]
PWPOL
Pulse-Width Modulation Timer Counter 1 to 4
$0064–$0067
$006C–$006F
$0063
$0068–$006B
$0061
77
78
77
Pulse-Width Modulation Timer Duty Cycle 1 to 4
Pulse-Width Modulation Timer Enable
Pulse-Width Modulation Timer Period 1 to 4
Pulse-Width Modulation Timer Polarity
Pulse-Width Modulation Timer Prescaler
78
62, 76
63, 77
PWSCAL
$0062
S
SCI Baud Rate Control High/Low
SCI Control 1
SCI Control 2
SCI Status Register 1
SCBDH/L
SCCR1
SCCR2
SCSR1
SCSR2
SPCR
SPCR
SPDR
SPSR
$0070, $0071
$0072
$0073
$0074
$0075
$0028
$0028
$002A
$0029
52
45, 52
53
54
55
45
57
58
58
SCI Status Register 2
Serial Peripheral Control
Serial Peripheral Control Register
SPI Data
Serial Peripheral Status Register
T
TCNT
Timer Count
Timer Control 2
Timer Interrupt Flag 2
$000E, $000F
$0021
$0025
$001E–$001F
$0022
$0024
66
67
69, 72
67
68
68, 72
67
TCTL2
TFLG2
TI4/O5
TMSK1
TMSK2
Timer Input Capture 4/Output Compare 5
Timer Interrupt Mask 1
Timer Interrupt Mask 2
TOC1–TOC4 Timer Output Compare
$0016–$001D
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
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2 Operating Modes
The M68HC11 K-series MCUs have four modes of operation that directly affect the address space.
These modes are described as follows.
2.1 Single-Chip Operating Mode
In single-chip operating mode, the M68HC11 K-series MCUs are stand-alone microcontrollers with no
external address or data bus. Addressing range is 64 Kbytes and is limited to on-chip resources. Refer
to the memory map diagram.
2.2 Expanded Operating Mode
In expanded operating mode, the MCU has a 64 Kbyte address range and, using the expansion bus,
can access external resources within the 64 Kbyte space. This space includes the same on-chip mem-
ory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral
and memory devices. Addressing beyond 64 Kbytes is available only in expanded mode using the on-
chip, register-based memory mapping logic. The additional address lines for memory expansion
(XA[18:13]) are implemented as alternate functions of port G. The expansion bus (external address and
data buses) is made up of ports B, C, and F, and the R/W signal. In expanded operating mode, high
order address bits are output on the port B pins, low order address bits on the port F pins, and the data
bus on port C. Refer to the memory map diagram.
2.3 Bootstrap Mode
Bootstrap mode allows special-purpose programs to be loaded into internal RAM. The MCU contains
448 bytes of bootstrap ROM which is enabled and present in the memory map only when the device is
in bootstrap mode. The bootstrap ROM contains a program which initializes the SCI and allows the user
to download up to 768 bytes of code into on-chip RAM. After a four-character delay, or after receiving
the character for address $037F, control passes to the loaded program at $0080. Refer to the memory
map diagram. Refer also to Application Note M68HC11 Bootstrap Mode (AN1060/D).
2.4 Special Test Mode
Special test mode is used primarily for factory testing. In this operating mode, ROM/EPROM is removed
from the address space and interrupt vectors are accessed externally at $BFC0–$BFFF.
2.5 Mode Selection
Operating modes are selected by a combination of logic levels applied to two input pins (MODA and
MODB) during reset. The logic level present (at the rising edge of reset) on these inputs is reflected in
bits in the HPRIO register. After reset, the operating mode may be changed according to the table con-
tained in the description of the HPRIO register.
The functions of two features that are enabled by bits in OPT2 register are dependent upon the operat-
ing mode. LIR driven is enabled with the LIRDV bit. Internal read visibility/not E is enabled with the
IRVNE bit. Refer to the OPT2 register description that follows HPRIO.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT* SMOD* MDA*
PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
RESET:
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Single Chip
Expanded
Bootstrap
Special Test
*The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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RBOOT — Read Bootstrap ROM/EPROM
Valid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes.
0 = Bootstrap ROM disabled and not in map
1 = Bootstrap ROM enabled and in map at $BE00–$BFFF
SMOD and MDA —Special Mode Select and Mode Select A
These two bits can be read at any time. They can be written anytime in special modes. MDA can only
be written once in normal modes. SMOD cannot be set once it has been cleared.
Inputs
Latched at Reset
MODB
MODA
Mode
SMOD
MDA
1
1
0
0
0
1
0
1
Single Chip
Expanded
Bootstrap
Special Test
0
0
1
1
0
1
0
1
PSEL[4:0] —Priority Select Bits [4:0]
Refer to 5 Resets and Interrupts.
OPT2 — System Configuration Options 2
$0038
Bit 7
LIRDV
0
6
CWOM
0
5
—
0
4
IRVNE*
—
3
LSBF
0
2
SPR2
0
1
Bit 0
XDV0
0
XDV1
0
RESET:
*Can be written only once in normal modes. Can be written anytime in special modes.
LIRDV —LIR Driven
In single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is normally configured
for wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed ap-
plication, this signal can be made to drive high for a short time to prevent false triggering.
0 = LIR not driven high out of reset
1 = LIR driven high for one quarter cycle to reduce transition time
CWOM —Port C Wired-OR Mode
Refer to 6 Parallel Input/Output.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
IRVNE can be written only once in normal modes (SMOD = 0). In special modes IRVNE can be written
any time. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
In expanded modes this bit determines whether IRV is on or off.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Mode
IRVNE Out
of Reset
E Clock Out
of Reset
IRV Out of
Reset
IRVNE
Affects Only
IRVNE Can
Be Written
Single Chip
Expanded
Boot
0
0
0
1
On
On
On
On
Off
Off
Off
On
E
Once
Once
IRV
E
Anytime
Anytime
Special Test
IRV
MOTOROLA
12
M68HC11 K Series
MC68HC11KTS/D
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LSBF —LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 —SPI Clock Rate Select
Refer to 8 Serial Peripheral Interface.
XDV[1:0] —XOUT Clock Divide Select
Controls the frequency of the clock driven out of the XOUT pin
XDV
[1:0]
XOUT = EXTAL
Divided By
Frequency at
EXTAL = 8 MHz
Frequency at
EXTAL = 12 MHz
Frequency at
EXTAL = 16 MHz
0 0
0 1
1 0
1 1
1
4
6
8
8 MHz
2 MHz
12 MHz
3 MHz
16 MHz
4 MHz
1.3 MHz
1 MHz
2 MHz
2.7 MHz
2 MHz
1.5 MHz
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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3 On-Chip Memory
In general, K-series MCUs have 768 bytes RAM, 640 bytes EEPROM, and 24 Kbytes ROM/EPROM.
Some devices in the series have portions of their memory resources disabled. Some have ROM and
some have EPROM replacing ROM. The following paragraphs describe the memory systems of devices
in the series.
3.1 Memory Map and Register Block
The INIT, INIT2, and CONFIG registers control the presence and location of the registers, RAM, EE-
PROM, and ROM/EPROM in the 64 Kbyte CPU address space. The 128-byte register block originates
at $0000 after reset and can be placed at any 4 Kbyte boundary ($x000) after reset by writing an ap-
propriate value to the INIT register. Refer to Figure 4.
128-BYTE REGISTER BLOCK
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT REGISTER)
$0000
$1000
x000
x07F
x080
EXT
EXT
768 BYTES RAM
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT REGISTER)
EXT
EXT
x37F
xD00
xD7F
RESERVED (SPECIAL TEST MODE ONLY)
640 BYTES EEPROM
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT2 REGISTER)
xD80
xFFF
A000
BOOT ROM
(ONLY PRESENT IN
BE00
$A000
BOOTSTRAP MODE)
SPECIAL MODE
INTERRUPT
VECTORS
BFC0
BFFF
24 KBYTES ROM/EPROM
(CAN BE REMAPPED TO $2000–$7FFF OR
$A000–$FFFF BY THE CONFIG REGISTER)
FFC0 NORMAL MODE
INTERRUPT
FFFF
$FFFF
VECTORS
FFFF
SINGLE
CHIP
SPECIAL
TEST
EXPANDED BOOTSTRAP
NOTE: ROM/EPROM can be enabled in special test mode by setting ROMON bit in the config register after reset.
Figure 4 Memory Map
MOTOROLA
14
M68HC11 K Series
MC6HC11KTS/D
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INIT = $00
INIT = $10
INIT = $04
REG @ $0000
RAM @ $0080
REG @ $0000
RAM @ $1000
REG @ $4000
RAM @ $0000
$0000
$0000
$0000
REGISTER
BLOCK
REGISTER
BLOCK
RAM
A
$007F
$0080
$007F
$007F
$0080
$1000
RAM
A
RAM
B
RAM
B
$107F
$1080
$02FF
$0300
$02FF
$4000
REGISTER
BLOCK
RAM
B
RAM
A
$037F
$12FF
$407F
Figure 5 RAM and Register Mapping
Table 4 M68HC11 K Series Register and Control Bit Assignments
(Can be remapped to any 4-Kbyte boundary)
Bit 7
PA7
6
PA6
DDA6
DDB6
DDF6
PB6
PF6
PC6
DDC6
0
5
PA5
DDA5
DDB5
DDF5
PB5
PF5
PC5
DDC5
PD5
DDD5
PE5
FOC3
OC1M5
OC1D5
13
4
PA4
DDA4
DDB4
DDF4
PB4
PF4
PC4
DDC4
PD4
DDD4
PE4
FOC4
OC1M4
OC1D4
12
3
PA3
DDA3
DDB3
DDF3
PB3
PF3
PC3
DDC3
PD3
DDD3
PE3
FOC5
OC1M3
OC1D3
11
2
PA2
DDA2
DDB2
DDF2
PB2
PF2
PC2
DDC2
PD2
DDD2
PE2
0
1
PA1
DDA1
DDB1
DDF1
PB1
PF1
PC1
DDC1
PD1
DDD1
PE1
0
Bit 0
PA0
DDA0
DDB0
DDF0
PB0
PF0
PC0
DDC0
PD0
DDD0
PE0
0
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
PORTA
DDRA
DDA7
DDB7
DDF7
PB7
DDRB
DDRF
PORTB
PF7
PORTF
PC7
PORTC
DDC7
0
DDRC
PORTD
0
0
DDRD
PE7
PE6
FOC2
OC1M6
OC1D6
14
PORTE
FOC1
OC1M7
OC1D7
Bit 15
Bit 7
CFORC
OC1M
0
0
0
0
0
0
OC1D
10
9
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
TCNT (High)
TCNT (Low)
TIC1 (High)
TIC1 (Low)
TIC2 (High)
TIC2 (Low)
TIC3 (High)
6
5
4
3
2
1
Bit 15
Bit 7
14
13
12
11
10
9
6
5
4
3
2
1
Bit 15
Bit 7
14
13
12
11
10
9
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
M68HC11 K Series
MC6HC11KTS/D
MOTOROLA
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Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued)
(Can be remapped to any 4-Kbyte boundary)
Bit 7
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
OM2
EDG4B
OC1I
OC1F
TOI
6
5
4
4
3
2
1
Bit 0
Bit 0
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
$0040
to
6
14
5
3
2
1
TIC3 (Low)
TOC1(High)
TOC1 (Low)
TOC2 (High)
TOC2 (Low)
TOC3 (High)
TOC3 (Low)
TOC4 (High)
TOC4 (Low)
TI4/O5 (High)
TI4/O5 (Low)
TCTL1
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
5
12
11
10
9
Bit 8
6
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
9
Bit 0
14
13
12
11
10
Bit 8
6
5
4
3
2
10
1
Bit 0
14
13
12
11
9
Bit 8
6
5
4
3
OM4
EDG2B
I4/O5I
I4/O5F
0
2
1
Bit 0
OL2
EDG4A
OC2I
OC2F
RTII
RTIF
PAEN
6
OM3
EDG1B
OC3I
OC3F
PAOVI
PAOVF
PAMOD
5
OL3
EDG1A
OC4I
OC4F
PAII
PAIF
PEDGE
4
OL4
EDG2A
IC1I
IC1F
0
OM5
EDG3B
IC2I
IC2F
PR1
0
OL5
EDG3A
IC3I
TCTL2
TMSK1
IC3F
PR0
TFLG1
TMSK2
TOF
0
0
0
0
TFLG2
0
I4/O5
2
RTR1
1
RTR0
Bit 0
PACTL
Bit 7
SPIE
SPIF
Bit 7
MBE
0
3
PACNT
SPE
WCOL
6
DWOM
0
MSTR
MODF
4
CPOL
0
CPHA
0
SPR1
0
SPR0
Bit 0
SPCR
SPSR
5
3
2
1
Bit 0
SPDR
0
ELAT
0
EXCOL
0
EXROW
HPPUE
PGAR3
T1
T0
EPGM
BPPUE
PGAR0
EPROG*
PPAR
0
GPPUE
PGAR2
FPPUE
PGAR1
0
0
PGAR5
PGAR4
PGAR
Reserved
Reserved
ADCTL
CCF
Bit 7
0
SCAN
MULT
CD
CC
CB
CA
Bit 0
6
5
4
3
2
1
ADR1
Bit 7
6
5
4
3
2
1
Bit 0
ADR2
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
ADR3
Bit 7
Bit 0
ADR4
BULKP
LVPEN
BPRT4
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
BPROT
Reserved
INIT2
EE3
LIRDV
ADPU
Bit 7
EE2
CWOM
CSEL
6
EE1
0
EE0
IRVNE
DLY
0
0
0
0
LSBF
CME
3
SPR2
FCME
2
XDV1
CR1
XDV0
CR0
OPT2
IRQE
5
OPTION
COPRST
PPROG
HPRIO
4
1
Bit 0
ODD
EVEN
SMOD
RAM2
0
LVPI
MDA
RAM1
OCCR
CLKX
BYTE
PSEL4
RAM0
CBYP
PAREN
ROW
PSEL3
REG3
DISR
NOSEC
ERASE
PSEL2
REG2
FCM
EELAT
PSEL1
REG1
FCOP
EEPGM
PSEL0
REG0
0
RBOOT
RAM3
TILOP
ROMAD
INIT
TEST1
1
NOCOP ROMON
EEON
CONFIG
Reserved
$0055
$0056
$0057
Reserved
MMSIZ
MXGS2
W2A15
MXGS1
W2A14
W2SZ1
W2A13
W2SZ0
0
0
0
W1SZ1
W1A13
W1SZ0
0
W1A15
W1A14
MMWBR
MOTOROLA
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M68HC11 K Series
MC6HC11KTS/D
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Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued)
(Can be remapped to any 4-Kbyte boundary)
Bit 7
0
6
5
4
3
2
1
Bit 0
0
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
$006C
$006D
$006E
$006F
$0070
$0071
$0072
$0073
$0074
$0075
$0076
$0077
$0078
to
X1A18
X1A17
X1A16
X1A15
X1A14
X1A13
MM1CR
MM2CR
CSCSTR
CSCTL
0
X2A18
X2A17
X2A16
X2A15
X2A14
X2A13
0
IOSA
IOEN
G1A18
G1DG2
G2A18
0
IOSB
GP1SA
GP1SB
GP2SA
GP2SB
PCSA
PCSB
PCSZB
G1A11
G1SZD
G2A11
G2SZD
PCKB1
PPOL1
Bit 0
IOPL
IOCSA
IOSZ
GCSPR
PCSEN
PCSZA
G1A17
G1A16
G1A15
G1A14
G1A13
G1A12
GPCS1A
GPCS1C
GPCS2A
GPCS2C
PWCLK
PWPOL
PWSCAL
PWEN
G1DPC
G1POL
G1AV
G1SZA
G1SZB
G1SZC
G2A17
G2A16
G2A15
G2A14
G2A13
G2A12
G2DPC
G2POL
G2AV
G2SZA
G2SZB
G2SZC
CON34
PCLK4
Bit 7
TPWSL
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
BTST
SBR7
LOOPS
TIE
CON12
PCKA2
PCKA1
0
PCKB3
PCKB2
PCLK3
PCLK2
PCLK1
PPOL4
PPOL3
PPOL2
6
5
4
3
2
1
DISCP
0
0
PWEN4
PWEN3
PWEN2
PWEN1
Bit 0
6
5
4
3
2
1
PWCNT1
PWCNT2
PWCNT3
PWCNT4
PWPER1
PWPER2
PWPER3
PWPER4
PWDTY1
PWDTY2
PWDTY3
PWDTY4
SCBDH
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
6
5
4
3
2
1
Bit 0
5
4
3
2
1
1
Bit 0
6
5
4
4
3
3
2
2
Bit 0
6
5
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
0
4
3
2
1
Bit 0
BSPL
SBR6
WOMS
TCIE
TC
SBR12
SBR4
M
SBR11
SBR3
WAKE
TE
SBR10
SBR2
ILT
RE
NF
0
SBR9
SBR1
PE
RWU
FE
0
SBR8
SBR0
PT
SBR5
0
SCBDL
SCCR1
RIE
RDRF
0
ILIE
IDLE
0
SBK
SCCR2
TDRE
0
OR
0
PF
SCSR1
0
RAF
SCSR2
R8
T8
0
0
0
0
0
0
SCDRH
SCDRL
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Reserved
$007B
$007C
$007D
$007E
$007F
Reserved
PORTH
DDRH
PH7
DDH7
PG7
PH6
DDH6
PG6
PH5
DDH5
PG5
PH4
DDH4
PG4
PH3
DDH3
PG3
PH2
DDH2
PG2
PH1
DDH1
PG1
PH0
DDH0
PG0
PORTG
DDRG
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
*MC68HC711K4 only.
3.2 RAM
All members of the M68HC11 K series have 768 bytes of static RAM. The RAM can be mapped to any
4-Kbyte boundary. Upon reset, the RAM is mapped at $0080–$037F. The registers are also mapped to
this 4-Kbyte boundary. In previous versions of the M68HC11 devices the register block being mapped
to the same boundary would cause the portion of RAM overlapped by the register block to be lost. How-
ever, a new RAM remapping feature has been added which automatically allows all of the RAM to be
accessible even if the register block overlaps the RAM. Because the registers are located in the same
M68HC11 K Series
MC6HC11KTS/D
MOTOROLA
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4-Kbyte boundary after reset, 128 bytes of the RAM are located at $0300 to $037F. Remapping is ac-
complished by writing appropriate values to the INIT register. Refer to the register and RAM mapping
examples following the memory map diagram.
When power is removed from the MCU, RAM contents may be preserved using the MODB/V
pin.
STBY
A power source (2.0 Vdc –V ) applied to this pin protects all 768 bytes of RAM.
DD
INIT — RAM and Register Mapping
$003D
Bit 7
RAM3
0
6
RAM2
0
5
RAM1
0
4
RAM0
0
3
REG3
0
2
REG2
0
1
REG1
0
Bit 0
REG0
0
RESET:
Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode.
RAM[3:0] —Internal RAM Map Position
These bits determine the upper four bits of the RAM address. At reset RAM is mapped to $0000. Nor-
mally the RAM would be mapped at $0000–$02FF (768 bytes). However, the register block overlaps
the first 128 bytes of RAM, causing them to be remapped to $0300–$037F. Refer to Figure 4 and Fig-
ure 5.
REG[3:0] —128-Byte Register Block Map Position
These bits determine the upper four bits of the register block starting address. At reset registers are
mapped to $0000 and overlap the first 128 bytes of RAM, causing them to be remapped to $0300–
$037F. Refer to Figure 4 and Figure 5.
3.3 ROM/EPROM
Standard devices have 24 kbytes of EPROM (OTPROM in a non-windowed package). Custom ROM
devices have a 24-Kbyte ROM array that is mask programmed at the factory to customer specifications.
The MC68HC11K0, MC68HC11K1, MC68L11K0, and MC68L11K1 have no ROM/EPROM. Refer to
the ordering information tables.
The ROMAD and ROMON control bits in the CONFIG register control the position and presence of
ROM/EPROM in the memory map. The ROM/EPROM can be mapped at $2000–$7FFF or $A000–
$FFFF. If it is mapped to $A000–$FFFF, vector space is included. In single-chip mode the ROM/
EPROM is forced to $A000–$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value
in the CONFIG register. This ensures that there will be ROM/EPROM at the vector space. In special
test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map.
Refer to Figure 4.
Programming EPROM requires an external 12.25 volt nominal power supply (V
) that must be ap-
PPE
plied to the XIRQ/V
pin. Three methods are used to program and verify EPROM/OTPROM.
PPE
Normal EPROM/OTPROM programming can be accomplished in any operating mode. Normal pro-
gramming is accomplished using the EPROM/OTPROM programming register (EPROG). The EPROG
register enables the EPROM programming voltage, controls the latching of data to be programmed, and
selects single- or multiple-byte programming.
To program the EPROM, complete the following steps using the EPROG register:
1. Set the ELAT bit in EPROG register. EELAT bit in PPROG must be cleared as it negates the
function of the ELAT bit.
2. Write data to the desired address.
3. Turn on programming voltage to the EPROM array by setting the EPGM bit in EPROG register.
4. Delay for 2 ms or more, as appropriate.
5. Clear the EPGM bit in EPROG to turn off the programming voltage.
MOTOROLA
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M68HC11 K Series
MC6HC11KTS/D
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6. Clear the EPROG register to reconfigure the EPROM address and data buses for normal op-
eration.
In EPROM emulation mode (PROG mode), the EPROM/OTPROM is programmed as a stand-alone
EPROM by adapting the MCU footprint to the 27C256-type EPROM and using an appropriate EPROM
programmer. To put the MCU in PROG mode, pull the following pins low: MODA/LIR, MODB/V
,
STBY
RESET, PA[2:0]. Refer to Figure 6.
In the third method, the EPROM is programmed by software while in the special test or bootstrap
modes. User-developed software can be uploaded through the SCI, or a ROM resident EPROM pro-
gramming utility can be used. To use the resident utility, bootload a three-byte program consisting of a
single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming util-
ity. The utility program sets the X and Y index registers to default values, then receives programming
data from an external host and programs it into EPROM. The value in IX determines programming delay
time. The value in IY is a pointer to the first address in EPROM to be programmed (default = $A000).
When the utility program is ready to receive programming data, it sends the host the $FF character.
Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting
with the first location in the EPROM array. After the last byte to be programmed is sent and the corre-
sponding verification data is returned, the programming operation is terminated by resetting the MCU.
Although the external 12.25 V programming voltage must be applied to the XIRQ/V
pin during
PPE
EPROM programming, it should be equal to V before verifying the data that was just programmed. It
DD
should equal V during normal operation also. The XIRQ/V
pin has a high voltage detect circuit
DD
PPE
that inhibits assertion of the ELAT bit when programming voltage is at low levels.
CAUTION
If the MCU is used in any operating mode while high voltage (12.25 V nominal) is
present on the XIRQ/V
pin, the IRQ/CE pin must be pulled high to avoid acci-
PPE
dental programming or corruption of EPROM contents. After programming an
EPROM location, IRQ pin must also be pulled high before the address and data
are changed to program the next location.
EPROG — EPROM Programming Control
$002B
Bit 7
MBE
0
6
—
0
5
ELAT
0
4
EXCOL
0
3
EXROW
0
2
—
0
1
—
0
Bit 0
EPGM
0
RESET:
MBE —Multiple-Byte Programming Enable
0 = EPROM array configured for normal programming
1 = Program two bytes with the same data
When multiple-byte programming is enabled, address bit 5 is considered a don't care so that bytes with
address bit 5 = 0 and address bit 5 = 1 both get programmed. MBE can be read in any mode and always
reads zero in normal modes. MBE can only be written in special modes.
Bit 6 —Not implemented
Always reads zero
ELAT —EPROM Latch Control
ELAT can be read any time. ELAT can be written any time except when EPGM = 1, then the write to
ELAT will be disabled. When ELAT = 1, writes to EPROM cause address and data to be latched and
the EPROM cannot be read.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
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EXCOL —Select Extra Columns
0 = User array selected
1 = User array is disabled and extra columns are accessed at bits [7:0]. Addresses use bits [11:5]
and bits [4:0] are don't care. EXCOL can only be read in special modes and always returns zero
in normal modes. EXCOL can be written in special modes only.
EXROW —Select Extra Rows
0 = User array selected
1 = User array is disabled and two extra rows are available. Addresses use bits [5:0] and bits [11:6]
are don't care. EXROW can only be read in special modes and always returns zero in normal
modes. EXROW can be written in special modes only.
Bits [2:1] —Not implemented
Always read zero
EPGM —EPROM Programming Voltage Enable
EPGM can be read any time and can only be written when ELAT = 1.
0 = Programming voltage to EPROM array disconnected
1 = Programming voltage to EPROM array connected
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EPROM MODE PIN CONNECTIONS
MCU PIN FUNCTIONS
EPROM
PIN FUNCTIONS
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
PF0/ADDR0
PF1/ADDR1
PF2/ADDR2
PF3/ADDR3
PF4/ADDR4
PF5/ADDR5
PF6/ADDR6
PF7/ADDR7
PB0/ADDR8
PB1/ADDR9
PB2/ADDR10 ADDR10
PB3/ADDR11 ADDR11
PB4/ADDR12 ADDR12
PB5/ADDR13 ADDR13
PB6/ADDR14 ADDR14
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
O0
O1
O2
O3
O4
O5
O6
O7
PC0/DATA0
PC1/DATA1
PC2/DATA2
PC3/DATA3
PC4/DATA4
PC5/DATA5
PC6/DATA6
PC7/DATA7
O0
O1
O2
O3
O4
O5
O6
O7
INTERNAL
24 KBYTE
EPROM
OE
CE
V
PB7/ADDR15
IRQ
OE
CE
XIRQ/V
V
V
PP
CC
SS
PPE
PP
CC
V
V
V
V
DD
V
SS
SS
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
PE4/AN4
PE5/AN5
PE6/AN6
PE7/AN7
NOTE 2
UNUSED
INPUTS
GND
GND
GND
PA0/IC3
PA1/IC2
PA2/IC1
NOTE 4
MC68HC711K4
PH0/PW1
PH1/PW2
PH2/PW3
PH3/PW4
PH4/CSIO
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
GND
GND
GND
GND
GND
GND
GND
GND
GND PA3/IC4/OC5/OC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PG0/XA13
PG1/XA14
PG2/XA15
PG3/XA16
PG4/XA17
PG5/XA18
PG6
NOTE 1
V
GND
GND
GND
RL
V
RH
EXTAL
NOTE 1
XTAL
XOUT
E
UNUSED
OUTPUTS
NOTE 3
NOTE 4
PG7/R/W
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
TESTxx (3)
MODA/LIR
MODB/V
RESET
GND
GND
GND
STBY
PD5/SS
NOTES:
1. Unused Inputs – grounding is recommended.
2. Unused Inputs – these pins may be left unterminated.
3. Unused Outputs – these pins should be left unconnected.
4. Grounding these six pins configures the MC68HC711K4 for EPROM emulation mode.
Figure 6 Pin Assignments of the MC68HC711K4 MCU in PROG Mode
M68HC11 K Series
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3.4 EEPROM
The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the
memory map by the EEON bit in the CONFIG register. EEPROM can be placed at any 4-Kbyte bound-
ary ($xD80) by writing appropriate values to the INIT2 register. Note that EEPROM can be mapped so
that it contains the vector space. Refer to Figure 4. The MC68HC11K0, MC68HC11K3, MC68L11K0,
and MC68L11K3 have no EEPROM. Refer to the ordering information tables.
Programming and erasing the EEPROM is controlled by the PPROG register, and dependent upon the
block protect (BPROT) register value. An on-chip charge pump develops the high voltage required for
programming and erasing. When the frequency of the E clock is less than 1 MHz, select the internal
clock source to drive the EEPROM charge pump by writing one to the CSEL bit in the OPTION register.
The CONFIG register consists of a single EEPROM byte. Although the byte is not included in the 640-
byte EEPROM array, programming the CONFIG register requires the same procedure as any byte in
the array. The erased state of bits in the CONFIG register is logic one. Refer to the CONFIG register
description that follows this section.
The erased state of an EEPROM byte is $FF (all ones).
To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, then complete
the following steps using the PPROG register:
1. Set the ERASE, EELAT, and appropriate BYTE and ROW bits in PPROG register.
2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to
any location in the row. Bulk erase is done by writing to any location in the array.
3. Set the ERASE, EELAT, EEPGM, and appropriate BYTE and ROW bits in PPROG register.
4. Delay for 10 ms or more, as appropriate.
5. Clear the EEPGM bit in PPROG to turn off the programming voltage.
6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-
eration.
To program the EEPROM, ensure the proper bits of the BPROT register are cleared and use the
PPROG register to complete the following steps:
1. Set the EELAT bit in PPROG register.
2. Write data to the desired address.
3. Set EEPGM bit in PPROG.
4. Delay for 10 ms or more, as appropriate.
5. Clear the EEPGM bit in PPROG to turn off the programming voltage.
6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-
eration.
CAUTION
Since it is possible to perform other operations while the EEPROM programming/
erase operation is in progress, it is common to start the operation and then return
to the main program until the 10 ms is completed. When the EELAT bit is set at the
beginning of a program/erase operation, the EEPROM is electronically removed
from the memory map; thus, it is not accessible during the program/erase cycle.
Care must be taken to ensure that EEPROM resources will not be needed by any
routines in the code during the 10 ms program/erase time.
PPROG —EEPROM Programming Control
$003B
Bit 7
ODD
0
6
EVEN
0
5
LVPI
0
4
BYTE
0
3
ROW
0
2
ERASE
0
1
EELAT
0
Bit 0
EEPGM
0
RESET:
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ODD —Program Odd Rows in Half of EEPROM (TEST)
EVEN —Program Even Rows in Half of EEPROM (TEST)
LVPI —Low Voltage Programming Inhibit
LVPI can be read at any time and writes to LVPI have no meaning nor effect. LVPI is set if LVPEN bit
in BPROT register equals one and the LVPI circuit detects that V has fallen below a safe operating
DD
voltage. Once set, LVPI is cleared when V
returns to a safe operating voltage or if LVPEN bit in
DD
BPROT register is cleared. If LVPEN equals zero, then LVPI is always zero and has no meaning nor
effect.
0 = EEPROM programming enabled
1 = EEPROM programming disabled
BYTE —Byte/Other EEPROM Erase Mode
0 = Row or bulk erase mode used
1 = Erase only one byte of EEPROM
ROW —Row/All EEPROM Erase Mode (only valid when BYTE = 0)
0 = All 640 bytes of EEPROM erased
1 = Erase only one 16-byte row of EEPROM
BYTE
ROW
Action
Bulk Erase (All 640 Bytes)
Row Erase (16 Bytes)
Byte Erase
0
0
1
1
0
1
0
1
Byte Erase
ERASE —Erase/Normal Control for EEPROM
0 = Normal read or program mode
1 = Erase mode
EELAT —EEPROM Latch Control
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or erasing
EEPGM —EEPROM Program Command
0 = Program or erase voltage switched off to EEPROM array
1 = Program or erase voltage switched on to EEPROM array
BPROT — Block Protect
$0035
Bit 7
BULKP
1
6
LVPEN
1
5
BPRT4
1
4
PTCON
1
3
BPRT3
1
2
BPRT2
1
1
BPRT1
1
Bit 0
BPRT0
1
RESET:
NOTE
Block protect register bits can be written to zero (protection disabled) only once
within 64 cycles of a reset in normal modes, or at any time in special modes. Block
protect register bits can be written to one (protection enabled) at any time.
BULKP —Bulk Erase of EEPROM Protect
0 = EEPROM can be bulk erased normally
1 = EEPROM cannot be bulk or row erased
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LVPEN —Low Voltage Programming Protect Enable
If LVPEN = 1, programming of the EEPROM is enabled unless the LVPI circuit detects that V has
DD
fallen below a safe operating voltage, thus setting the low voltage programming inhibit bit in PPROG
register (LVPI = 1).
0 = Low voltage programming protect for EEPROM disabled
1 = Low voltage programming protect for EEPROM enabled
BPRT4 —Block Protect Bit for Upper 128 Bytes of EEPROM
Refer to description for BPRT[3:0].
PTCON —Protect for CONFIG
0 = CONFIG register can be programmed or erased normally
1 = CONFIG register cannot be programmed or erased
BPRT[3:0] —Block Protect Bits for EEPROM
0 = Protection disabled
1 = Protection enabled
Bit Name
BPRT4
BPRT3
BPRT2
BPRT1
BPRT0
Block Protected
$xF80–$xFFF
$xE60–$xF7F
$xDE0–$xE5F
$xDA0–$xDDF
$xD80–$xD9F
Block Size
128 Bytes
288 Bytes
128 Bytes
64 Bytes
32 Bytes
INIT2 —EEPROM Mapping
$0037
Bit 7
EE3
0
6
5
EE1
0
4
EE0
0
3
0
0
2
0
0
1
0
0
Bit 0
EE2
0
0
0
RESET:
INIT2 can be written only once in normal modes, any time in special modes.
EE[3:0] —EEPROM Map Position
EEPROM is at $xD80–$xFFF, where x is the hexadecimal digit represented by EE[3:0].
Bits [3:0] —Not implemented
Always read zero
3.5 Configuration Control Register (CONFIG)
The CONFIG register is used to define several system functions. Although the CONFIG register is an
address within the register block, it is actually an EEPROM byte with the address of $x03F. CONFIG is
made up of EEPROM cells and static latches. The operation of the MCU is controlled directly by these
latches and not the actual EEPROM byte. When programming the CONFIG register, the EEPROM byte
is being accessed. When the CONFIG register is being read, the static latches are being accessed.
The CONFIG register can be read at any time. The value read is the one latched from the EEPROM
cells during the last reset sequence. A new value programmed into this register cannot be read until a
subsequent reset occurs. Unused bits always read as ones.
In normal modes (SMOD = 0), CONFIG bits can only be written using the EEPROM programming se-
quence, and are neither readable nor active until latched via the next reset. In special modes (SMOD =
1), CONFIG bits can be written at any time.
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CONFIG —System Configuration Register
$003F
Bit 7
ROMAD
—
6
1
1
5
CLKX
—
4
PAREN
—
3
NOSEC
—
2
1
Bit 0
EEON
—
NOCOP ROMON
RESET:
—
—
ROMAD —ROM/EPROM Mapping Control
In single-chip mode ROMAD is forced to one out of reset.
0 = ROM/EPROM located at $2000–$7FFF
1 = ROM/EPROM located at $A000–$FFFF
Bit 6 —Not implemented
Always reads one
CLKX —XOUT Clock Enable
0 = XOUT pin disabled
1 = Buffered XTAL signal (four times E frequency) driven out on the XOUT pin
PAREN —Pull-Up Assignment Register Enable
0 = Pull-ups always disabled regardless of state of bits in PPAR
1 = Pull-ups either enabled or disabled through PPAR
NOSEC —Security Disable
NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If se-
curity mask option is omitted NOSEC always reads one. Refer to 3.6 Security Feature.
0 = Security enabled
1 = Security disabled
NOCOP —COP System Disable
Resets to programmed value
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
ROMON —ROM/EPROM Enable
In single-chip mode, ROMON is forced to one out of reset. In special test mode, ROMON is forced to
zero out of reset.
0 = ROM/EPROM removed from memory map
1 = ROM/EPROM present in memory map
EEON —EEPROM Enable
0 = EEPROM disabled from memory map
1 = EEPROM present in memory map with location depending on value specified in EE[3:0] in INIT2
3.6 Security Feature
The security feature protects memory contents from unauthorized access. Although many devices in
the M68HC11 family support the security feature, an enhancement has been added to the MC68S11K4
that protects the contents of EPROM/OTPROM.
The security feature affects how the MCU behaves in certain modes. When the optional security feature
has been specified prior to manufacture and enabled via the NOSEC bit in CONFIG, the MCU is re-
stricted to operation in single-chip modes only. When the NOSEC bit equals zero, the MCU ignores the
state of the MODA pin during reset. This allows the MCU to be operated in single-chip and bootstrap
modes only. These modes of operation do not allow external visibility of the internal address and data
buses. Although the security feature can easily be disabled when in bootstrap mode, the bootloader
firmware residing in bootstrap ROM checks to see if the NOSEC bit is clear. If NOSEC is clear (security
enabled), the bootloader program performs the following:
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• Output $FF on SCI transmitter.
• Erase EEPROM array.
• Verify that EEPROM has been erased. If it has not, repeat erase procedure.
• Write $FF to every location in RAM.
• Check EPROM for data. If data is present, stay in loop. Otherwise proceed.
• Erase the CONFIG register.
• Continue executing bootloader routine.
Notice that the bootloader routine checks the EPROM to see if it contains any data. The presence of
data causes the routine to stay in a loop. At this time, devices with the security enhancement are only
available as one-time-programmable (OTP) MCUs in non-windowed packages. Once they have been
programmed and secured, they will not function in bootstrap mode.
For more information refer to M68HC11 Reference Manual (M68HC11RM/AD).
MOTOROLA
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4 Memory Expansion and Chip Selects
Two additional on-chip blocks are provided with the M68HC11 K-series MCUs. The first block imple-
ments additional address lines that become active only when required by the CPU. The second block
provides chip-select signals that simplify the interface to external peripheral devices. Both of these
blocks are fully programmable by values written to associated control registers.
4.1 Memory Expansion
New to the M68HC11 family of microcontrollers is the ability of the M68HC11 K-series MCUs to extend
the address range of the M68HC11 CPU beyond the physical 64 Kbyte limit of the 16 CPU address
lines. The following is a brief description of how the extended addressing is achieved. For a more de-
tailed discussion refer to application note Using the MC68HC11K4 Memory Mapping Logic (AN452/D).
Memory expansion is achieved by manipulating the CPU address lines such that, even though the CPU
cannot distinguish more than 64 Kbytes of physical memory, up to 1 Mbyte can be accessed through a
paged memory scheme. Additional address lines XA[18:13] are provided as alternate functions of port
G pins. Bits in the port G assignment register (PGAR) define which port G pins are to be used for mem-
ory expansion address lines and which are to be used for general-purpose I/O.
In order to access expanded memory, the user must first allocate a range of the 64 Kbyte address space
to be used for the window(s) through which external expanded memory is viewed by the CPU. The size
and placement of the window(s) depend upon values written to the MMSIZ and MMWBR registers, re-
spectively. Which bank or page of the expanded memory that is present in the window(s) at a given time
is dependent upon values written to the MM1CR and MM2CR registers.
Up to two windows can be designated and each can be programmed to 0 (disabled), 8, 16, or 32 Kbytes.
The base address for each window must be an integer multiple of the window size. When the window
size is 32 Kbytes, the base address can be at $0000, $4000, or $8000.
If the windows are defined in such a way that they overlap, bank window 1 has priority and the part of
window 2 that is not overlapped by bank window 1 remains active. If a window is defined such that it
overlaps any internal registers, RAM, or EEPROM, the portion of the registers, RAM, or EEPROM that
is overlapped is repeated in all banks associated with that window. However, if ROM/EPROM is en-
abled and overlapped by a window, the ROM/EPROM is present only in banks with XA[18:16] = 0:0:0.
Expanded memory is addressed by using a combination of the CPU's normal address lines ADDR[15:0]
and the expansion address lines XA[18:13]. Window size and the number of banks associated with the
window determine exactly which address lines are used. The additional address lines (XA[18:13]) de-
termine which bank is present in a window at a given time. The lower three expansion address lines
(XA[15:13]) are used only when needed by the CPU and replace the CPU's equivalent address lines
(ADDR[15:13]). The following tables show which address lines are used for various configurations of
expanded memory.
Five registers control operation of the memory expansion function. MM1CR and MM2CR registers in-
dicate which bank of a window is active. Each contains the value to be output when the CPU selects
addresses within the memory expansion window. PGAR selects which pins are used for I/O or memory
expansion address lines, defining which extended address lines are used. The MMWBR register de-
fines the starting address of each of the two windows within the CPU 64-Kbyte address range. The MM-
SIZ register sets the size of the windows in use and selects whether the on-board general-purpose chip
selects are active for CPU addresses or for expansion addresses.
M68HC11 K Series
MC68HC11KTS/D
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Table 5 CPU Address and Address Expansion Signals
Window Size
Number of Banks
8 Kbytes
16 Kbytes
32 Kbytes
32 Kbytes
(Window Based at
$4000)
2
4
ADDR[12:0]
XA13
ADDR[13:0]
XA14
ADDR[14:0]
XA15
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
ADDR[12:0]
XA[14:13]
ADDR[12:0]
XA[15:13]
ADDR[12:0]
XA[16:13]
ADDR[12:0]
XA[17:13]
ADDR[12:0]
XA[18:13]
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
ADDR[14:0]
XA[16:15]
ADDR[14:0]
XA[17:15]
ADDR[14:0]
XA[18:15]
—
8
16
32
64
—
—
—
—
—
—
—
PGAR — Port G Assignment
$002D
Bit 7
—
6
—
0
5
PGAR5
0
4
3
PGAR3
0
2
PGAR2
0
1
Bit 0
PGAR0
0
PGAR4
0
PGAR1
0
RESET:
0
Bits [7:6] — Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is address line, XA[18:13]
NOTE
A special case exists for expansion address lines XA[15:13] that overlap the CPU
address lines ADDR[15:13]. If these lines are selected as expansion address lines
in PGAR, but are not used in either window, the corresponding CPU address line
is output on the appropriate port G pin.
MMSIZ — Memory Mapping Size
$0056
Bit 7
MXGS2
0
6
MXGS1
0
5
W2SZ1
0
4
W2SZ0
0
3
—
0
2
—
0
1
W1SZ1
0
Bit 0
W1SZ0
0
RESET:
MXGS[2:1] — Memory Expansion Select for General-Purpose Chip Select 2 or 1
0 = General-purpose chip select 2 or 1 based on 64 Kbyte CPU address
1 = General-purpose chip select 2 or 1 based on expansion address
W2SZ[1:0] — Window 2 Size
These bits select the size of memory expansion window 2. Refer to the table following W1SZ[1:0].
Bits [3:2] — Not implemented
Always read zero
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W1SZ[1:0] —Window 1 Size
These bits select the size of memory expansion window 1.
WxSZ[1:0]
Window Size
0
0
1
1
0
1
0
1
Window disabled
8 K —Window can have up to 64 8-Kbyte banks
16 K —Window can have up to 32 16-Kbyte banks
32 K —Window can have up to 16 32-Kbyte banks
MMWBR — Memory Mapping Window Base
$0057
Bit 7
W2A15
0
6
W2A14
0
5
W2A13
0
4
—
0
3
W1A15
0
2
W1A14
0
1
W1A13
0
Bit 0
$0057
—
0
RESET:
W2A[15:13] —Window 2 Base Address
Selects the three most significant bit (MSB) of the base address for memory mapping window 2. Refer
to the table following W1A[15:13].
Bit 4 —Not implemented
Always reads zero
W1A[15:13] —Window Base 1 Address
Selects the three MSB of the base address for memory mapping window 1. Refer to the following table
for additional information.
MSB Bits
Window Base Address
WxA[15:13]
8 K
16 K
32 K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
$0000
$2000
$4000
$6000
$8000
$A000
$C000
$E000
$0000
$0000
$4000
$4000
$8000
$8000
$C000
$C000
$0000
$0000
$4000
$4000
$8000
$8000
$8000
$8000
Bit 0 —Not implemented
Always reads zero
NOTE
A special case exists when the bank size is 32 Kbytes and the window base ad-
dress is $4000. The XA14 signal connected to the ADDR14 pin of the memory de-
vice automatically drives an inverted CPU ADDR14 signal onto the XA14 pin when
the window is active. The effect occurs while the CPU address is in the $4000–
$BFFF range, the XA pins and external physical memory range is $0000–$7FFF.
MM1CR–MM2CR —Memory Mapping Window 1 and 2 Control
$0058–$0059
Bit 7
—
6
5
4
3
2
1
Bit 0
$0058
$0059
X1A18 X1A17 X1A16 X1A15 X1A14 X1A13
X2A18 X2A17 X2A16 X2A15 X2A14 X2A13
—
—
0
MM1CR
MM2CR
—
RESET:
0
0
0
0
0
0
0
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Bit 7 — Not implemented
Always reads zero
MM1CR — Memory Mapping Window 1 Control Register
When a 64 Kbyte CPU address falls within window 1, the value in MM1CR is driven out from the corre-
sponding expansion address lines to enable the specified bank in the window.
MM2CR — Memory Mapping Window 2 Control Register
When a 64 Kbyte CPU address falls within window 2, the value in MM2CR is driven out from the corre-
sponding expansion address lines to enable the specified bank in the window.
Bit 0 — Not implemented
Always reads zero
4.2 Overlap Guidelines
• On-chip registers, RAM, and EEPROM are higher priority than expansion windows. If a window
overlaps RAM, registers, or EEPROM, they appear in all banks at their CPU address.
• If a window overlaps on-chip ROM/EPROM, the ROM/EPROM appears only in banks with
XA[18:16] = 0:0:0.
• Window 1 is higher priority than window 2, therefore any overlapped portion of window 2 is inac-
cessible.
4.3 Chip Selects
M68HC11 K-series MCUs have four software configured chip selects that are enabled in expanded
modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select (CSPROG)
is used with an external memory that contains the reset vectors and program. The two general-purpose
chip selects, CSGP1 and CSGP2, are used to enable external devices. These external devices can be
in the 64 Kbyte memory space or in the expanded memory space. Chip select signals are a shared func-
tion of port H. When an MCU pin is not used for chip select functions it can be used for general-purpose
I/O. The following table contains a summary of the attributes of each chip select that can be controlled
by user software.
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CSIO
Enable
Valid
IOEN in CSCTL —1 = On, off at reset (0)
IOCSA in CSCTL —1 = Address valid, 0 = E valid
IOPL in CSCTL —1 = Active high, 0 = Active low
IOSZ in CSCTL —1 = 4K ($1000–$1FFF), 0 = 8K ($0000–$1FFF)
Fixed (see Size)
Polarity
Size
Start Address
Stretch
IO1SA:IO1SB in CSCSTR —0, 1, 2, or 3 E clocks
CSPROG
Enable
Valid
PSCEN in CSCTL —1 = On, ON at reset
Fixed (Address valid)
Polarity
Size
Fixed (Active low)
PCSZA:PCSZB in CSCTL — 0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Start Address
Stretch
Fixed (see Size)
PCSA:PCSB in CSCSTR —0, 1, 2, or 3 E clocks
Priority
GCSPR in CSCTL —
1 = CSGPx above CSPROG
0 = CSPROG above CSGPx
CSGP1,
CSGP2
Enable
Valid
Set size to 0K to disable
GxPOL in GPCS1C (GPCS2C) —1 = Address valid, 0 = E valid
GxAV in GPCS1C (GPCS2C) —1 = Active high, 0 = Active low
Polarity
Size
Refer to GPCS1C (GPCS2C) —2K to 512K in nine steps, 0K = dis-
able, can also follow memory expansion window 1 or window 2
Start Address
Stretch
Refer to GPCS1A (GPCS2A)
Refer to CSCSTR —0, 1, 2, or 3 E clocks
Other
G1DG2 in GPCS1C allows CSGP1 and CSGP2 to be connected to
an internal OR gate and driven out the CSGP2 pin.
G1DPC in GPCS1C allows CSGP1 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
G2DPC in GPCS2C allows CSGP2 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses
or 512K expansion addresses.
MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses
or 512K expansion addresses.
4.3.1 Program Chip Select (CSPROG)
The program chip select (CSPROG) is active in the range of memory where the main program exists.
CSPROG is enabled out of reset in all modes. After reset in normal mode, the PCS stretch select bit is
set to provide one cycle of stretch so that slow memory devices can be used.
4.3.2 I/O Chip Select (CSIO)
The I/O chip select (CSIO) is programmable for a four Kbyte size located at addresses $1000 to $1FFF
or eight Kbyte size located at addresses $0000 to $1FFF. Polarity of the active state is programmable
for active high or active low. Clock stretching can be set from zero to three cycles.
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4.3.3 General-Purpose Chip Selects (CSGP1, CSGP2)
The general-purpose chip selects are the most flexible and programmable and have the most control
bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable.
Clock stretching can be set from zero to three cycles. Each chip select can be programmed to become
active whenever the CPU address enters a memory expansion window regardless of the actual bank
selected. This is known as following a window.
Each general purpose chip select can be configured to drive the program chip select. CSGP1 can be
configured to drive CSGP2 or the program chip select. Using one chip select to drive another allows the
same device to cover the address space defined by both chip selects. The two chip selects are con-
nected to an internal OR gate. The output of the OR gate is then driven onto the pin corresponding to
the driven chip select. For example, this is useful when the same external device is used with both bank
windows but the windows are opened independently. In cases where one chip select drives another,
determine the priority from the following table.
Condition
GPCS1 drives GPCS2
GPCS1 drives PCS
Priority
GPCS1
GPCS1
GPCS2
GPCS1
GPCS2 drives PCS
GPCS1 and GPCS2 drive PCS
4.3.4 Chip Select Priorities
To minimize chip select conflicts (with one another or with internal memory and registers), the priority
is determined by the GCSPR bit in the CSCTL register. Refer to the following table.
GCSPR = 0
On-Chip Registers
On-Chip RAM
GCSPR = 1
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
Program Chip Select
GP Chip Select 1
GP Chip Select 2
GP Chip Select 1
GP Chip Select 2
Program Chip Select
4.3.5 Chip Select Control Registers
There are six chip select control registers. Chip select functions are enabled by control bits in CSCTL
register. Chip selects are configured by bits in CSCSTR, IOEN, IOPL, IOCSA, and IOSZ registers.
CSCTL — Chip Select Control
$005B
Bit 7
IOEN
0
6
IOPL
0
5
IOCSA
0
4
IOSZ
0
3
GCSPR
0
2
PCSEN
1
1
PCSZA
0
Bit 0
PCSZB
0
RESET:
IOEN —I/O Chip Select Enable
0 = CSIO disabled
1 = CSIO enabled
IOPL —I/O Chip Select Polarity Select
0 = CSIO active low
1 = CSIO active high
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IOCSA —I/O Chip Select Address Valid
0 = Valid during E-clock high time
1 = Valid during address valid time
IOSZ —I/O Chip Select Size Select
0 = $1000–$1FFF (4 Kbyte)
1 = $0000–$1FFF (8 Kbyte)
GCSPR —General-Purpose Chip Select Priority
0 = Program chip select has priority over general-purpose chip selects
1 = General-purpose chip selects have priority over program chip select
PCSEN —Program Chip Select Enable
0 = CSPROG disabled
1 = CSPROG enabled
PCSZA, PCSZB —Program Chip Select Size (A or B)
PCSZA
PCSZB
Size (Bytes)
64 K
Address Range
$0000–$FFFF
$8000–$FFFF
$C000–$FFFF
$E000–$FFFF
0
0
1
1
0
1
0
1
32 K
16 K
8 K
CSCSTR —Chip Select Clock Stretch
$005A
Bit 7
IOSA
0
6
IOSB
0
5
4
3
2
1
Bit 0
GP1SA GP1SB GP2SA GP2SB PCSA PCSB
RESET:
0
0
0
0
0
0
0
0
0
0
1
0
Normal Modes
Special Modes
0
0
IOSA, IOSB —CSIO Stretch Select
GP1SA, GP1SB —CSGP1 Stretch Select
GP2SA, GP2SB —CSGP2 Stretch Select
PCSA, PCSB —CSPROG Stretch Select
Bit [A:B]
Clock Stretch
None
0 0
0 1
1 0
1 1
1 Cycle
2 Cycles
3 Cycles
GPCS1A —General-Purpose Chip Select 1 Address
$005C
Bit 7
G1A18
0
6
G1A17
0
5
G1A16
0
4
G1A15
0
3
G1A14
0
2
G1A13
0
1
Bit 0
G1A12
0
G1A11
0
RESET:
G1A[18:11] —General-Purpose Chip Select 1 Address
Selects the starting address of general-purpose chip select 1 range. Refer to the G1SZA–G1SZD table.
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GPCS1C —General-Purpose Chip Select 1 Control
$005D
Bit 7
G1DG2
0
6
G1DPC
0
5
G1POL
0
4
G1AV
0
3
G1SZA
0
2
G1SZB
0
1
G1SZC
0
Bit 0
G1SZD
0
RESET:
G1DG2 —General-Purpose Chip Select 1 Drives General-Purpose Chip Select 2
0 = CSGP1 does not affect CSGP2
1 = CSGP1 and CSGP2 are connected to an OR gate and driven out CSGP2
G1DPC —General-Purpose Chip Select 1 Drives Program Chip Select
0 = CSGP1 does not affect CSPROG
1 = CSGP1 and CSPROG are connected to an OR gate and driven out CSPROG
G1POL —General-Purpose Chip Select 1 Polarity Select
0 = CSGP1 active low
1 = CSGP1 active high
G1AV —General-Purpose Chip Select 1 Address Valid Select
0 = CSGP1 active during E high time
1 = CSGP1 active during address valid time
G1SZA–G1SZD —General-Purpose Chip Select 1 Size
G1SZx
Valid Bits
(MXGS1 = 0)
None
Valid Bits
(MXGS1 = 1)
None
A
0
0
0
0
0
0
0
0
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
C
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
Size (Bytes)
Disabled
2 K
ADDR[15:11]
ADDR[15:12]
ADDR[15:13]
ADDR[15:14]
ADDR15
None
G1A[18:11]
G1A[18:12]
G1A[18:13]
G1A[18:14]
G1A[18:15]
G1A[18:16]
G1A[18:17]
G1A18
4 K
8 K
16 K
32 K
64 K
128 K
None
256 K
None
512 K
None
None
Follow Window 1
Follow Window 2
Default to 512 K
None
None
None
None
1100–1111
None
None
GPCS2A —General-Purpose Chip Select 2 Address
$005E
Bit 7
G2A18
0
6
G2A17
0
5
G2A16
0
4
G2A15
0
3
G2A14
0
2
1
G2A12
0
Bit 0
G2A11
0
G2A13
0
RESET:
G2A[18:11] —General-Purpose Chip Select 2 Address
Selects the Starting Address of General-Purpose Chip Select 2 Range. Refer to G2SZA–G2SZD table.
GPCS2C —General-Purpose Chip Select 2 Control
$005F
Bit 7
—
6
G2DPC
0
5
G2POL
0
4
G2AV
0
3
G2SZA
0
2
G2SZB
0
1
G2SZC
0
Bit 0
G2SZD
0
RESET:
0
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Bit 7 — Not implemented
Always reads zero
G2DPC — General-Purpose Chip Select 2 Drives Program Chip Select
0 = CSGP2 does not affect CSPROG
1 = CSGP2 and CSPROG are connected to an OR gate and driven out CSPROG
G2POL — General-Purpose Chip Select 2 Polarity Select
0 = CSGP2 active low
1 = CSGP2 active high
G2AV — General-Purpose Chip Select 2 Address Valid Select
0 = Active during E high time
1 = Active during address valid time
G2SZA–G2SZD — General-Purpose Chip Select 2 Size
G2SZx
Valid Bits
(MXGS2 = 0)
None
Valid Bits
(MXGS2 = 1)
None
A
0
0
0
0
0
0
0
0
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
C
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
Size (Bytes)
Disabled
2 K
ADDR[15:11]
ADDR[15:12]
ADDR[15:13]
ADDR[15:14]
ADDR15
None
G2A[18:11]
G2A[18:12]
G2A[18:13]
G2A[18:14]
G2A[18:15]
G2A[18:16]
G2A[18:17]
G2A18
4 K
8 K
16 K
32 K
64 K
128 K
None
256 K
None
512 K
None
None
Follow Window 1
Follow Window 2
Default to 512 K
None
None
None
None
1100–1111
None
None
4.3.6 Examples of Memory Expansion Using Chip Selects
On the following two pages are examples of memory expansion schemes that use chip select signals
to simplify the interface to the external memory devices. Although schematics are not provided, careful
study of the memory map diagram for each example will reveal the simplicity with which an expanded
system can be created. Both examples require a minimum of external circuitry as well as very little pro-
gram code.
This example is a system consisting of the MCU and a single 27C512-type memory device. This system
uses one chip select and has one window containing eight banks of eight Kbytes each. In this example,
a total of 64 Kbytes is added to the address range of the MCU. Three of the expansion address lines
(XA[15:13]) are used. Register values particular to this example are given below the diagram.
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$0000
$1000
WINDOW 1
$00000
BANK 0
$04000
BANK 2
$06000
$08000
$0A000
BANK 5
$0C000
BANK 6
$0E000
BANK 7
$02000
BANK 1
$4000
$6000
BANK 3
BANK 4
CHIP SELECT 1
XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]=
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF
$0DFFF
$0FFFF
$A000
$FFFF
PGAR = $07 XA[15:13]
MMWBR = $04 WINDOW 1 @ $4000,
WINDOW 2 DISABLED
MMSIZ = $41 WINDOW 1 = 8 KBYTES,
WINDOW 2 DISABLED
CSCTL = $00 NO I/O OR PROGRAM CHIP SELECTS
GPCS1A = $00 GEN. PURPOSE CHIP SELECT 1 FROM $00000
GPSC1C = $06 64 KBYTE RANGE (8 X 8K)
GPCS2A = $00 N/A
INTERNAL
EPROM
GPCS2C = $00 GEN. PURPOSE CHIP SELECT 2 DISABLED
Figure 7 Memory Expansion Example 1
This example is a system consisting of the MCU, a single 27C512-type memory device as in the previ-
ous example, and two 6226-type memory devices as well. This system uses two chip selects and has
two windows. For purposes of explanation, the setup of the first window is identical to the previous ex-
ample. In addition, a second window consisting of 16 banks of 16 Kbytes each uses the second chip
select signal. Window 1 contains 64 Kbytes of expanded memory pages, window 2 contains a total of
256 Kbytes of expanded memory. A total of five expansion address lines are used. Register values par-
ticular to this example are given below the diagram.
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WINDOW 1
$00000
BANK 0
$04000
BANK 2
$06000
$08000
$0A000
BANK 5
$0C000
BANK 6
$0E000
BANK 7
$02000
BANK 1
$0000
$1000
EE/REG/RAM
BANK 3
BANK 4
$4000
$6000
$8000
XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]=
CHIP SELECT 1
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF
$0DFFF
$0FFFF
WINDOW 2
CHIP SELECT 2
$00000
BANK 0
$08000
BANK 2
$0C000
$10000
$3C000
$04000
BANK 1
$A000
$C000
INTERNAL
EPROM
BANK 3
BANK 4
BANK 15
• • • • • • •
XA[17:14]= XA[17:14]= XA[17:14]= XA[17:14]= XA[17:14]=
XA[17:14]=
1:1:1:1
$FFFF
0:0:0:0
0:0:0:1
0:0:1:0
0:0:1:1
0:1:0:0
$03FFF
$07FFF
$0BFFF
$0FFFF
$13FFF
$3FFFF
PGAR = $1F XA[17:13]
MMWBR = $84 WINDOW 1 @ $4000,
WINDOW 2 @ $8000
CSCTL = $00 NO I/O OR PROGRAM CHIP SELECTS
GPCS1A = $00 GEN. PURPOSE CHIP SELECT 1 FROM $00000
GPSC1C = $06 64 KBYTE RANGE (8 X 8K)
MMSIZ = $E1 WINDOW 1 = 8 KBYTES,
WINDOW 2 = 16 KBYTES
GPCS2A = $00 GEN. PURPOSE CHIP SELECT 2 FROM $00000
GPCS2C = $08 256 KBYTE RANGE (16 X 16K)
Figure 8 Memory Expansion Example 2
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5 Resets and Interrupts
All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
• RESET, or Power-On Reset
• Clock Monitor Fail
• COP Failure
The 18 interrupt vectors service 22 interrupt sources (three nonmaskable, 19 maskable). The three non-
maskable interrupt sources are as follows:
• XIRQ Pin (X-Bit Interrupt)
• Illegal Opcode Trap
• Software Interrupt
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Nineteen interrupt sources in the M68HC11 K series devices are subject to masking by the global inter-
rupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external
interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in
M68HC11 devices have separate interrupt vectors; therefore, there is usually no need for software to
poll control registers to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any
special instructions.
Refer to the following table for a list of interrupt and reset vector assignments.
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Vector Address
Interrupt Source
CCR Mask Local Mask
Priority
Bit
—
I
(1 = High)
FFC0, C1 —FFD4, D5
FFD6, D7
Reserved
—
—
SCI Serial System
• SCI Receive Data Register Full
• SCI Receiver Overrun
• SCI Transmit Data Register Empty
• SCI Transmit Complete
• SCI Idle Line Detect
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
RIE
RIE
19
20
21
22
23
18
17
16
15
14
13
12
11
10
9
TIE
TCIE
ILIE
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
I
SPIE
PAII
I
I
PAOVI
TOI
I
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
I
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
I
I
I
I
I
I
IC2I
8
I
IC1I
7
I
RTII
6
IRQ
I
None
None
None
None
NOCOP
CME
None
5
XIRQ Pin
X
4
Software Interrupt
None
None
None
None
None
*
Illegal Opcode Trap
*
COP Failure
3
Clock Monitor Fail
2
RESET
1
*Same level as an instruction
OPTION —System Configuration Options
$0039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
1
CR1*
0
Bit 0
CR0*
0
FCME*
0
RESET:
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU —A/D Converter Power up
Refer to 9 Analog-to-Digital Converter.
CSEL —Clock Select
Refer to 9 Analog-to-Digital Converter.
IRQE —IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY —Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
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CME —Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME —Force Clock Monitor Enable
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
CR[1:0] —COP Timer Rate Select
Refer to NOCOP bit in CONFIG register.
Table 6 COP Timer Rate Select (Timeout Period Length)
CR[1:0]
Rate
Selected
XTAL = 8.0 MHz
Timeout
XTAL = 12.0 MHz
Timeout
XTAL = 16.0 MHz
Timeout
–0 ms, +16.4 ms
–0 ms, +10.9 ms
–0 ms, +8.2 ms
15
0 0
0 1
1 0
1 1
16.384 ms
65.536 ms
262.14 ms
1.049 sec
2.0 MHz
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
8.192 ms
32.768 ms
131.07 ms
524.29 ms
4.0 MHz
2
17
2
19
2
21
2
E =
COPRST —Arm/Reset COP Timer Circuitry
$003A
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
7
0
0
0
RESET:
Write $55 (%01010101) to COPRST to arm COP watchdog clearing mechanism. Write $AA
(%10101010) to COPRST to reset COP watchdog. Refer to NOCOP bit in CONFIG register.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
MDA*
—
4
PSEL4
0
3
PSEL3
0
2
PSEL2
1
1
PSEL1
1
Bit 0
PSEL0
0
RBOOT* SMOD*
RESET:
—
—
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT —Read Bootstrap ROM
Refer to 2 Operating Modes.
SMOD —Special Mode Select
Refer to 2 Operating Modes.
MDA —Mode Select A
Refer to 2 Operating Modes.
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
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PSEL[4:0] —Priority Select Bit 4 through Bit 0
Can be written only while the I-bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
PSELx
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
2
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Interrupt Source Promoted
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
IRQ
Real-Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
Timer Output Compare 1
Timer Output Compare 2
Timer Output Compare 3
Timer Output Compare 4
Timer Output Compare 5/Input Capture 4
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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6 Parallel Input/Output
M68HC11 K-series MCUs have up to 62 input/output lines, depending on the operating mode. To en-
hance the I/O functions, the data bus of this microcontroller is nonmultiplexed. The following table is a
summary of the configuration and features of each port.
Port
Input Pins
Output Pins
Bidirectional Pins
Shared Functions
Timer
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
—
—
—
—
8
—
—
—
—
—
—
—
—
8
8
High Order Address
Data Bus
8
6
SCI and SPI
—
8
A/D Converter
Low Order Address
Memory Expansion
PWM, Chip Select
—
—
—
8
8
NOTE
Port pin function is mode dependent. Do not confuse pin function with the electrical
state of the pin at reset. Port pins are either driven to a specified logic level or are
configured as high impedance inputs. I/O pins configured as high-impedance in-
puts have port data that is indeterminate. The contents of the corresponding latch-
es are dependent upon the electrical state of the pins during reset. In port
descriptions, an "I" indicates this condition. Port pins that are driven to a known log-
ic level during reset are shown with a value of either one or zero. Some control bits
are unaffected by reset. Reset states for these bits are indicated with a "U".
PORTA —Port A Data
$0000
Bit 7
PA7
6
PA6
I
5
PA5
I
4
PA4
I
3
PA3
I
2
PA2
I
1
PA1
I
Bit 0
PA0
I
RESET:
I
Alt. Pin
Func.:
PAI
OC2
OC1
OC3
OC1
OC4
OC1
IC4/OC5
OC1
IC1
—
IC2
—
IC3
—
And/or:
OC1
NOTE
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Oth-
erwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being
cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled,
writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5
has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O or output com-
pare. Note that even when PA7 is configured as an output, the pin still drives the
pulse accumulator input.
DDRA —Data Direction Register for Port A
$0001
Bit 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
RESET:
DDA[7:0] —Data Direction for Port A
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
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PORTB —Port B Data
$0004
Bit 7
PB7
6
5
4
3
2
1
Bit 0
PB0
PB6
PB5
PB4
PB3
PB2
PB1
S. Chip or
Boot:
PB7
I
PB6
I
PB5
I
PB4
I
PB3
I
PB2
I
PB1
I
PB0
I
RESET:
Expan. or
Test:
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9
ADDR8
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order ad-
dress outputs and PORTB is not in the memory map.
DDRB —Data Direction Register for Port B
$0002
Bit 7
DDB7
0
6
DDB6
0
5
DDB5
0
4
DDB4
0
3
DDB3
0
2
DDB2
0
1
DDB1
0
Bit 0
DDB0
0
RESET:
DDB[7:0] —Data Direction for Port B
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTC —Port C Data
$0006
Bit 7
6
5
4
3
2
1
Bit 0
PC0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
S. Chip or
Boot:
PC7
0
PC6
0
PC5
0
PC4
0
PC3
0
PC2
0
PC1
0
PC0
0
RESET:
Expan. or
Test:
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset state is mode dependent. In single-chip or bootstrap modes, port C pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port C pins are data bus inputs
and outputs and PORTC is not in the memory map. Refer to CWOM bit in OPT2 register description
that follows.
DDRC —Data Direction Register for Port C
$0007
Bit 7
DDC7
0
6
DDC6
0
5
DDC5
0
4
DDC4
0
3
DDC3
0
2
DDC2
0
1
DDC1
0
Bit 0
DDC0
0
RESET:
DDC[7:0] —Data Direction for Port C. Refer to CWOM bit in OPT2 register description that follows.
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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OPT2 —System Configuration Options 2
$0038
Bit 7
LIRDV
0
6
CWOM
0
5
—
0
4
IRVNE
—
3
LSBF
0
2
SPR2
0
1
XDV1
0
Bit 0
XDV0
0
RESET:
LIRDV—LIR Driven
Refer to 2 Operating Modes.
CWOM —Port C Wired-OR Mode
0 = Port C operates normally.
1 = Port C outputs are open-drain.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to 2 Operating Modes.
LSBF —SPI LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 —SPI Clock (SCK) Rate Select
Refer to 8 Serial Peripheral Interface.
XDV[1:0] —XOUT Clock Divide Select
Refer to 2 Operating Modes.
PORTD —Port D Data
$0008
Bit 7
—
6
—
0
5
PD5
I
4
PD4
I
3
PD3
I
2
PD2
I
1
PD1
I
Bit 0
PD0
I
RESET:
0
Alt. Pin
Func.:
—
—
SS
SCK
MOSI
MISO
TxD
RxD
DDRD —Data Direction Register for Port D
$0009
Bit 7
—
6
—
0
5
DDD5
0
4
DDD4
0
3
DDD3
0
2
DDD2
0
1
DDD1
0
Bit 0
DDD0
0
RESET:
0
Bits [7:6] — Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
NOTE
When the SPI system is in slave mode, DDD5 has no meaning nor effect. When
the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an
error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI
system is enabled and expects any of bits [4:2] to be an input that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2] are expected
to be outputs that bit will be an output only if the associated DDR bit is set.
MOTOROLA
44
M68HC11 K Series
MC68HC11KTS/D
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SPCR —Serial Peripheral Control
$0028
Bit 7
SPIE
0
6
SPE
0
5
4
3
2
1
SPR1
0
Bit 0
SPR0
0
DWOM MSTR
CPOL
CPHA
RESET:
1
0
0
0
0
0
0
0
Boot Mode
0
0
0
0
Other Modes
SPIE —SPI Interrupt Enable
Refer to 8 Serial Peripheral Interface.
SPE —SPI System Enable
Refer to 8 Serial Peripheral Interface.
DWOM —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1)
0 = PD[5:2] are normal CMOS outputs
1 = PD[5:2] are open-drain outputs
MSTR —Master/Slave Mode Select
Refer to 8 Serial Peripheral Interface.
CPOL —Clock Polarity
Refer to 8 Serial Peripheral Interface.
CPHA —Clock Phase
Refer to 8 Serial Peripheral Interface.
SPR[1:0] —SPI Clock Rate Selects
Refer to 8 Serial Peripheral Interface.
SCCR1 —SCI Control 1
$0072
Bit 7
6
5
—
0
4
M
0
3
2
ILT
0
1
PE
0
Bit 0
PT
0
LOOPS WOMS
WAKE
RESET:
0
0
1
0
0
0
Boot Mode
0
0
0
0
0
Other Modes
LOOPS —SCI LOOP Mode Enable
Refer to 7 Serial Communications Interface.
WOMS —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also DWOM bit in SPCR.)
0 = TxD and RxD operate normally
1 = TxD and RxD are open drains if operating as an output
Bit 5 —Not implemented
Always reads zero
M —Mode (Select Character Format)
Refer to 7 Serial Communications Interface.
WAKE —Wakeup by Address Mark/Idle
Refer to 7 Serial Communications Interface.
ILT —Idle Line Type
Refer to 7 Serial Communications Interface.
PE —Parity Enable
Refer to 7 Serial Communications Interface.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
45
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PT —Parity Type
Refer to 7 Serial Communications Interface.
PORTE —Port E Data
$000A
Bit 7
PE7
I
6
PE6
I
5
PE5
I
4
PE4
I
3
PE3
I
2
PE2
I
1
PE1
I
Bit 0
PE0
I
RESET:
Alt. Pin
Func.:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
DDRF —Data Direction Register for Port F
$0003
Bit 7
DDF7
0
6
DDF6
0
5
DDF5
0
4
DDF4
0
3
DDF3
0
2
DDF2
0
1
DDF1
0
Bit 0
DDF0
0
RESET:
DDF[7:0] —Data Direction for Port F
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTF —Port F Data
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PF0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
S. Chip or
Boot:
PF7
I
PF6
I
PF5
I
PF4
I
PF3
I
PF2
I
PF1
I
PF0
I
RESET:
Expan. or
Test:
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
Reset state is mode dependent. In single-chip or bootstrap modes, port F is high-impedance input with
selectable internal pull-up resistors. In expanded or test modes, port F pins are low order address out-
puts and PORTF is not in the memory map.
PORTH —Port H Data
$007C
Bit 7
PH7
6
PH6
I
5
PH5
I
4
PH4
I
3
PH3
I
2
PH2
I
1
PH1
I
Bit 0
PH0
I
RESET:
I
Alt. Pin
Func.:
CSPROG CSGP2
CSGP1
CSIO
PW4
PW3
PW2
PW1
Port H pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes, reset also causes PH7 to be configured as CSPROG.
DDRH —Data Direction Register for Port H
$007D
Bit 7
DDH7
0
6
DDH6
0
5
DDH5
0
4
DDH4
0
3
DDH3
0
2
DDH2
0
1
DDH1
0
Bit 0
DDH0
0
RESET:
DDH[7:0] —Data Direction for Port H
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
MOTOROLA
46
M68HC11 K Series
MC68HC11KTS/D
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NOTE
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to 4.3 Memory
Expansion and Chip Selects and 12 Pulse-Width Modulation Timer for further
information.
PORTG —Port G Data
$007E
Bit 7
PG7
I
6
PG6
I
5
PG5
I
4
PG4
I
3
PG3
I
2
PG2
I
1
PG1
I
Bit 0
PG0
I
RESET:
Alt. Pin
Func.:
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
DDRG —Data Direction Register for Port G
$007F
Bit 7
DDG7
0
6
DDG6
0
5
DDG5
0
4
DDG4
0
3
DDG3
0
2
DDG2
0
1
DDG1
0
Bit 0
DDG0
0
RESET:
DDG[7:0] —Data Direction for Port G
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
PGAR — Port G Assignment
$002D
Bit 7
—
6
—
0
5
PGAR5
0
4
PGAR4
0
3
PGAR3
0
2
PGAR2
0
1
PGAR1
0
Bit 0
PGAR0
0
$002D
RESET:
0
Bits [7:6] —Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
NOTE
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to 4.1 Memory Ex-
pansion for further information.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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PPAR —Port Pull-Up Assignment
$002C
Bit 7
—
6
—
0
5
—
0
4
—
0
3
HPPUE
1
2
GPPUE
1
1
FPPUE
1
Bit 0
BPPUE
1
RESET:
0
Bits [7:4] —Not implemented
Always read zero
xPPUE —Port x Pin Pull-Up Enable
Valid only when PAREN = 1. Refer to PAREN bit in the CONFIG register description.
0 = Port x pin on-chip pull-up devices disabled
1 = Port x pin on-chip pull-up devices enabled
NOTE
FPPUE and BPPUE have no effect in expanded mode because port F and port B
are address outputs.
MOTOROLA
48
M68HC11 K Series
MC68HC11KTS/D
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7 Serial Communications Interface
The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one
of two independent serial I/O subsystems in M68HC11 K-series MCUs. Rearranging registers and con-
trol bits used in previous M68HC11 family devices has enhanced the existing SCI system and added
new features, which include the following:
• A 13-bit modulus prescaler that allows greater baud rate control
• A new idle mode detect, independent of preceding serial data
• A receiver active flag
• Hardware parity for both transmitter and receiver
The enhanced baud rate generator is shown in the following diagram. Refer to Table 7 for standard val-
ues.
EXTAL
13-BIT COUNTER
INTERNAL
PHASE 2 CLOCK
RESET
=
RECEIVER
BAUD RATE
CLOCK
SYNCH
13-BIT COMPARE
÷ 2
SCBDH/L SCI BAUD CONTROL
TRANSMITTER
BAUD RATE
CLOCK
÷ 16
Figure 9 SCI Baud Generator Circuit Diagram
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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TRANSMITTER
BAUD RATE
CLOCK
(WRITE ONLY)
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER
PIN BUFFER
AND CONTROL
PD1
TxD
H (8)
7
6
5
4
3
2
1
0
L
8
FORCE PIN
DIRECTION (OUT)
TRANSMITTER
CONTROL LOGIC
8
SCCR1 SCI CONTROL 1
SCSR INTERRUPT STATUS
8
TDRE
TIE
TC
TCIE
SCCR2 SCI CONTROL 2
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10 SCI Transmitter Block Diagram
MOTOROLA
50
M68HC11 K Series
MC68HC11KTS/D
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RECEIVER
BAUD RATE
CLOCK
DDD0
÷16
10 (11) - BIT
Rx SHIFT REGISTER
PIN BUFFER
AND CONTROL
DATA
RECOVERY
PD0/
RxD
(8)
7
6
5
4
3
2
1
0
MSB
ALL ONES
DISABLE
DRIVER
RE
PARITY
DETECT
SCSR2 SCI STATUS 2
M
WAKE-UP
LOGIC
RWU
R8 T8
–
–
–
–
–
–
0
$x076
$x077
SCDRH Tx/Rx DATA HIGH
7
6
5
4
3
2
1
SCCR1 SCI CONTROL 1
SCSR1 SCI STATUS 1
SCDRL Tx/Rx DATA LOW
(READ-ONLY)
RDRF
RIE
IDLE
ILIE
OR
RIE
SCCR2 SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 11 SCI Receiver Block Diagram
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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SCBDH/L —SCI Baud Rate Control High/Low
$0070, $0071
Bit 7
BTST
0
6
BSPL
0
5
—
0
4
3
2
1
SBR9
0
Bit 0
$0070
SBR12 SBR11 SBR10
SBR8
0
High
Low
RESET:
0
0
0
$0071
SBR7
0
SBR6
0
SBR5
0
SBR4
0
SBR3
0
SBR2
1
SBR1
0
SBR0
0
RESET:
BTST —Baud Register Test (TEST)
Factory test only
BSPL —Baud Rate Counter Split (TEST)
Factory test only
Bit 5 —Not implemented
Always reads zero
SBR[12:0] —SCI Baud Rate Selects
Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values for
example rates.
SCI baud rate = EXTAL ÷[16 (2 BR)]
Where BR is the contents of SCBDH/L (BR = 1, 2, 3 ... 8191).
BR = 0 disables the baud rate generator.
Table 7 SCI Baud Rate Control Values
Target
Baud
Rate
110
Crystal Frequency (EXTAL)
12 MHz
8 MHz
16 MHz
Dec Value
Dec Value
2272
1666
833
Hex Value
$08E0
$0682
$0341
$01A0
$00D0
$0068
$0034
$001A
$000D
—
Dec Value
3409
2500
1250
625
Hex Value
$0D51
$09C4
$04E2
$0271
$0138
$009C
$004E
$0027
$0014
—
Hex Value
$11C1
$0D05
$0682
$0341
$01A0
$00D0
$0068
$0034
$001A
$000D
4545
3333
1666
833
416
208
104
52
150
300
600
416
1200
2400
4800
9600
19.2 K
38.4 K
208
312
104
156
52
78
26
39
13
20
26
—
—
13
SCCR1 —SCI Control 1
$0072
Bit 7
6
5
4
M
0
3
WAKE
0
2
ILT
0
1
PE
0
Bit 0
LOOPS WOMS
—
0
PT
0
RESET:
0
1
Bootstrap
Mode
0
0
0
0
0
0
0
0
Other Modes
MOTOROLA
52
M68HC11 K Series
MC68HC11KTS/D
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LOOPS —SCI LOOP Mode Enable
0 = SCI transmit and receive operate normally
1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is
fed back into the receiver input
WOMS —Wired-OR Mode Option for PD[1:0] (See also DWOM bit in SPCR.)
0 = TxD and RxD operate normally
1 = TxD and RxD are open drains if operating as an output
Bit 5 —Not implemented
Always reads zero
M —Mode (Select Character Format)
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE —Wakeup by Address Mark/Idle
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
ILT —Idle Line Type
0 = Short (SCI counts consecutive ones after start bit)
1 = Long (SCI counts ones only after stop bit)
PE —Parity Enable
0 = Parity disabled
1 = Parity enabled
PT —Parity Type
0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes par-
ity bit to be one)
1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity
bit to be one)
SCCR2 —SCI Control 2
$0073
Bit 7
TIE
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
RESET:
0
TIE —Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE —Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE —Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE —Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE —Transmitter Enable
0 = Transmitter disabled
1 = Transmitter enabled
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
53
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RE —Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
RWU —Receiver Wakeup Control
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK —Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
SCSR1 —SCI Status Register 1
$0074
Bit 7
TDRE
1
6
TC
1
5
RDRF
0
4
IDLE
0
3
OR
0
2
NF
0
1
FE
0
Bit 0
PF
0
RESET:
TDRE —Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC —Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR1 and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF —Receive Data Register Full Flag
RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR1 and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE —Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR —Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
the OR flag by reading SCSR1 and then reading SCDR.
0 = No overrun
1 = Overrun detected
NF —Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR1 and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE —Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1
and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
MOTOROLA
54
M68HC11 K Series
MC68HC11KTS/D
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PF —Parity Error Flag
PF is set if received data has incorrect parity. Clear PF by reading SCSR1 and then reading SCDR.
0 = Parity correct
1 = Incorrect parity detected
SCSR2 —SCI Status Register 2
$0075
Bit 7
—
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
Bit 0
RAF
0
RESET:
0
Bits [7:1] —Not implemented
Always read zero
RAF —Receiver Active Flag (Read Only)
0 = A character is not being received
1 = A character is being received
SCDRH, SCDRL —SCI Data Register High/Low
$0076, $0077
Bit 7
R8
6
5
4
3
2
1
Bit 0
$0076
$0077
T8
—
—
—
—
—
—
SCDRH
(High)
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
SCDRL
(Low)
R8 —Receiver Bit 8
Ninth serial data bit received when SCI is configured for nine-data-bit operation.
T8 —Transmitter Bit 8
Ninth serial data bit transmitted when SCI is configured for nine-data-bit operation.
Bits [5:0] —Not implemented
Always read zero
R/T[7:0] —Receiver/Transmitter Data Bits [7:0]
SCI data is double buffered in both directions.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
55
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8 Serial Peripheral Interface
The SPI allows the MCU to communicate synchronously with peripheral devices and other micropro-
cessors. Data rates can be as high as 2 Mbits per second when configured as a master and 4 Mbits per
second when configured as a slave (assuming 4 MHz bus speed).
Two control bits in OPT2 allow the transfer of data either MSB or LSB first and select an additional divide
by four stage to be inserted before the SPI baud rate clock divider.
MISO/
PD2
S
INTERNAL
MCU CLOCK
M
MSB
LSB
MOSI/
PD3
M
S
8-BIT SHIFT REGISTER
READ DATA BUFFER
DIVIDER
÷2 ÷4 ÷16 ÷32 ÷8 ÷16 ÷64 ÷128
PIN
CONTROL
LOGIC
CLOCK
SPI CLOCK (MASTER)
SELECT
S
CLOCK
LOGIC
SCK/
PD4
M
SS/
PD5
OPTIONS REGISTER 2
SPI CONTROL
MSTR
SPE
SPIE
SPSR SPI STATUS REGISTER
SPCR SPI CONTROL REGISTER
8
8
8
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 12 SPI Block Diagram
MOTOROLA
56
M68HC11 K Series
MC68HC11KTS/D
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SPCR —Serial Peripheral Control Register
$0028
Bit 7
SPIE
0
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
RESET:
SPIE —Serial Peripheral Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE —Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1.)
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR —Master Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA —Clock Polarity, Clock Phase
Refer to the following figure, SPI Transfer Format.
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 13 SPI Transfer Format
NOTE
This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is
transferred in reverse order (LSB first).
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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SPR[2:0] —SPI Clock Rate Selects (SPR2 is located in OPT2 register)
Table 8 SPI Clock Rate Selects
SPR[2:0]
Divide
Frequency at
Frequency at
Frequency at
E Clock By
E = 2 MHz (Baud)
E = 3 MHz (Baud)
E = 4 MHz (Baud)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
4
1.0 MHz
500 kHz
3.0 MHz
750 kHz
4.0 MHz
1.0 MHz
250 kHz
125 kHz
500 kHz
250 kHz
62.5 kHz
31.25 kHz
16
32
8
125 kHz
187.5 kHz
93.75 kHz
375 kHz
62.5 kHz
250 kHz
16
64
128
125 kHz
187.5 kHz
46.875 kHz
23.438 kHz
31.25 kHz
15.625 kHz
SPSR —Serial Peripheral Status Register
$0029
Bit 7
SPIF
0
6
WCOL
0
5
—
0
4
MODF
0
3
—
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
SPIF —SPI Transfer Complete Flag
This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this
flag by reading SPSR, then access SPDR.
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
WCOL —Write Collision Error Flag
This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear
this flag by reading SPSR, then access SPDR.
0 = No write collision error
1 = SPDR written while SPI transfer in progress
Bit 5 —Not implemented
Always reads zero
MODF —Mode Fault (Mode fault terminates SPI operation)
Set when SS is pulled low while MSTR = 1. Cleared by SPSR read followed by SPCR write.
0 = No mode fault error
1 = SS pulled low in master mode
Bits [3:0] —Not implemented
Always read zero
SPDR —SPI Data
$002A
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
SPI is double buffered in, single buffered out.
MOTOROLA
58
M68HC11 K Series
MC68HC11KTS/D
For More Information On This Product,
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OPT2 —System Configuration Options 2
$0038
Bit 7
LIRDV
0
6
CWOM
0
5
—
0
4
IRVNE
—
3
LSBF
0
2
SPR2
0
1
XDV1
0
Bit 0
XDV0
0
RESET:
LIRDV—LIR Driven
Refer to 2 Operating Modes.
CWOM —Port C Wired-OR Mode
Refer to 6 Parallel Input/Output.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to 2 Operating Modes.
LSBF —SPI LSB First Enable
0 = SPI data transferred MSB first
1 = SPI data transferred LSB first
SPR2 —SPI Clock (SCK) Rate Select
Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register.
XDV[1:0] —XOUT Clock Divide Select
Refer to 2 Operating Modes.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
59
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9 Analog-to-Digital Converter
The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to
convert analog signals to digital values. The A/D converter system contained in M68HC11 K-series
MCUs is an 8-channel,8-bit, multiplexed-input, successive-approximation converter. It does not require
external sample and hold circuits.
The clock source for the A/D converter’s charge pump, like the clock source for the EEPROM charge
pump, is selected with the CSEL bit in the OPTION register. When the E clock is slower than 1 MHz,
the CSEL bit must be set to ensure that the successive approximation sequence for the A/D converter
will be completed before any charge loss occurs. In the case of the EEPROM, it is the efficiency of the
charge pump that is affected.
PE0/
AN0
V
V
RH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1/
AN1
RL
PE2/
AN2
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
PE3/
AN3
RESULT
ANALOG
MUX
PE4/
AN4
PE5/
AN5
INTERNAL
DATA BUS
PE6/
AN6
PE7/
AN7
ADCTL A/D CONTROL
RESULT REGISTER INTERFACE
ADDR 1 A/D RESULT 1
ADDR 2 A/D RESULT 2
ADDR 3 A/D RESULT 3
ADDR 4 A/D RESULT 4
Figure 14 A/D Converter Block Diagram
The A/D converter can operate in single or multiple conversion modes. Multiple conversions are per-
formed in sequences of four. Sequences can be performed on a single channel or an a group of chan-
nels.
Dedicated lines V and V provide the reference supply voltage inputs.
RH
RL
MOTOROLA
60
M68HC11 K Series
MC68HC11KTS/D
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A multiplexer allows the single A/D converter to select one of 16 analog input signals.
The A/D converter control logic implements automatic conversion sequences on a selected channel
four times or on four channels once each. A write to the ADCTL register initiates conversions and, if
made while a conversion is in progress, a write to ADCTL also halts that conversion operation, sets
CCF, and proceeds to the next instruction.
When the SCAN bit is zero, four requested conversions are performed, once each, to fill the four result
registers. When SCAN is one, conversions continue in a round-robin fashion with the result registers
being updated as new data becomes available. When the MULT bit is zero, the A/D converter system
is configured to perform conversions on each channel in the group of four channels specified by the CD
and CC channel select bits.
E CLOCK
MSB
4
CYCLES
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
WRITE
TO
12 E CYCLES
2
2
2
2
2
2
2
2
CYC CYC CYC CYC CYC CYC CYC CYC
ADCTL
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE END
REPEAT
SEQUENCE
IF
SCAN = 1
SET
CCF
FLAG
CONVERT FIRST
CHANNEL
AND UPDATE ADDR1
CONVERT SECOND
CHANNEL
AND UPDATE ADDR2
CONVERT THIRD
CHANNEL
AND UPDATE ADDR3
CONVERT FOURTH
CHANNEL
AND UPDATE ADDR4
0
32
64
96
128
E
CYCLES
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
INPUT
DIFFUSION AND
PROTECTION
POLY COUPLER
DEVICE
ANALOG
INPUT
PIN
≤ 4 kΩ
*
20 pF
< 2 pF
~
+
–
20 V
0.7 V
~
~
400 nA
JUNCTION
LEAKAGE
DAC
CAPACITANCE
V
RL
*
This analog switch is closed only during the 12-cycle sample time.
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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ADCTL —A/D Control/Status
$0030
Bit 7
CCF
0
6
—
0
5
SCAN
0
4
MULT
0
3
CD
0
2
CC
0
1
CB
0
Bit 0
CA
0
RESET:
CCF — Conversions Complete Flag
0 = Write to ADCTL is complete
1 = A/D conversion cycle is complete
Bit 6 — Not implemented
Always reads zero
SCAN —Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT —Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD:CA —Channel Select D through A
Table 9 A/D Converter Channel Assignments
Channel Select Control Bits
Channel Signal
Result in ADRx if
MULT = 1
CD
CC
CB
CA
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
AN0
AN1
AN2
AN3
ADR1
ADR2
ADR3
ADR4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
AN4
AN5
AN6
AN7
ADR1
ADR2
ADR3
ADR4
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
—
—
—
—
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
V
*
*
ADR1
ADR2
ADR3
ADR4
RH
V
RL
(V )/2*
RH
Reserved*
*Used for factory testing
ADR[4:1] —A/D Results
$0031 – $0034
$0031
$0032
$0033
$0034
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
ADR1
ADR2
ADR3
ADR4
5
5
5
MOTOROLA
62
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MC68HC11KTS/D
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OPTION —System Configuration Options
$0039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
FCME*
0
1
CR1*
0
Bit 0
CR0*
0
RESET:
ADPU —A/D Converter Power-Up
0 = A/D converter powered down
1 = A/D converter powered up
CSEL — Clock Select
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock source
IRQE —IRQ Select Edge Sensitive Only
Refer to 5 Resets and Interrupts
DLY —Enable Oscillator Startup Delay on Exit from Stop
Refer to 5 Resets and Interrupts
CME —Clock Monitor Enable
Refer to 5 Resets and Interrupts
FCME —Force Clock Monitor Enable
Refer to 5 Resets and Interrupts
CR[1:0] —COP Timer Rate Select
Refer to 10 Main Timer
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
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10 Main Timer
The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-
bit range of the counter.
The timer has three channels for input capture, four channels for output compare, and one channel that
can be configured as a fourth input capture or a fifth output compare. In addition, the timing system in-
cludes pulse accumulator and real-time interrupt (RTI) functions, as well as a clock monitor function,
which can be used to detect clock failures that are not detected by the COP.
Refer to 11 Pulse Accumulator and 10.1 Real-Time Interrupt for further information about these func-
tions. Refer to the following table for a summary of the crystal-related frequencies and periods.
Table 10 Timer Summary
Control Bits
Common System Frequencies
Definition
XTAL
E
8.0 MHz
2.0 MHz
12.0 MHz
3.0 MHz
16.0 MHz
4.0 MHz
PR[1:0]
Main Timer Count Rates (Period Length)
0 0
1 count —
overflow —
500 ns
32.768 ms
333 ns
21.845 ms
250 ns
16.384 ms
1/E
16
2
/E
0 1
1 count —
overflow —
2.0 µs
131.07 ms
1.333 µs
87.381 ms
1.0 µs
65.536 ms
4/E
18
2
/E
1 0
1 count —
overflow —
4.0 µs
262.14 ms
2.667 µs
174.76 ms
2.0 µs
131.07 ms
8/E
19
2
/E
1 1
1 count —
overflow —
8.0 µs
524.29 ms
5.333 µs
349.52 ms
4.0 µs
262.14 ms
16/E
20
2
/E
RTR[1:0]
Periodic (RTI) Interrupt Rates (Period Length)
13
14
15
16
0 0
0 1
1 0
1 1
4.096 ms
2.731 ms
5.461 ms
10.923 ms
21.845 ms
2.048 ms
2
2
2
2
/E
/E
/E
/E
8.192 ms
16.384 ms
32.768 ms
4.096 ms
8.192 ms
16.384 ms
CR[1:0]
COP Watchdog Timeout Rates (Period Length)
15
17
19
21
0 0
0 1
1 0
1 1
16.384 ms
65.536 ms
262.14 ms
1.049 s
10.923 ms
43.691 ms
174.76 ms
699.05 ms
8.192 ms
32.768 ms
131.07 ms
524.28 ms
2
2
2
2
/E
/E
/E
/E
Timeout Tolerance
(–0 ms/+...)
15
16.4 ms
10.9 ms
8.192 ms
2
/E
MOTOROLA
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MC68HC11KTS/D
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PRESCALER–DIVIDE BY
1, 4, 8, OR 16
TCNT (HI)
TCNT (LO)
TOI
TO
9
MCU
ECLK
16-BIT FREE-RUNNING
COUNTER
PULSE
TOF
ACCUMULATOR
PR1
PR0
TAPS FOR RTI, COP
WATCHDOG AND
PULSE ACCUMULATOR
INTERRUPT REQUESTS
(FURTHER QUALIFIED
BY I-BIT IN CCR)
16-BIT TIMER BUS
TMSK1
OC1I
PIN
FUNCTIONS
8
TFLG1
OC1F
PA7/
OC1/
PAI
CFORC
=
16-BIT COMPARATOR
BIT-7
TOC1 (HI)
TOC1 (LO)
FOC1
FOC2
FOC3
FOC4
FOC5
OC2I
OC3I
OC4I
I4/O5I
7
PA6/
OC2/
OC1
=
16-BIT COMPARATOR
TOC2 (HI)
OC2F
OC3F
OC4F
BIT-6
TOC2 (LO)
6
PA5/
OC3/
OC1
=
16-BIT COMPARATOR
TOC3 (HI)
BIT-5
TOC3 (LO)
5
=
16-BIT COMPARATOR
TOC4 (HI)
PA4/
OC4/
OC1
TOC4 (LO)
BIT-4
4
=
OC5
I4/O5F
16-BIT COMPARATOR
PA3
OC5/
IC4/
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
BIT-3
OC1
IC4
FORCE
OUTPUT
COMPARE
I4/O5
IC1I
IC2I
IC3I
PA2/
IC1
3
2
1
BIT-2
BIT-1
BIT-0
16-BIT LATCH CLK
IC1F
IC2F
IC3F
TIC1 (HI)
TIC1 (LO)
PA1/
IC2
16-BIT LATCH CLK
TIC2 (HI)
TIC2 (LO)
PA0/
IC3
16-BIT LATCH CLK
TIC3 (HI)
TIC3 (LO)
PORT A
PIN
CONTROL
STATUS
FLAGS
INTERRUPT
ENABLES
Figure 17 Timer Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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CFORC —Timer Compare Force
$000B
Bit 7
FOC1
0
6
FOC2
0
5
FOC3
0
4
FOC4
0
3
FOC5
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
FOC[5:1] —Force Output Compare
Write ones to force compare(s)
0 = Not affected
1 = Output x action occurs
Bits [2:0] —Not implemented
Always read zero
OC1M —Output Compare 1 Mask
$000C
Bit 7
OC1M7
0
6
OC1M6
0
5
OC1M5
0
4
OC1M4
0
3
OC1M3
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
Set bit(s) to enable OC1 to control corresponding pin(s) of port A
Bits [2:0] —Not implemented
Always read zero
OC1D —Output Compare 1 Data
$000D
Bit 7
OC1D7
0
6
OC1D6
0
5
OC1D5
0
4
OC1D4
0
3
OC1D3
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] —Not implemented
Always read zero
TCNT —Timer Count
$000E, $000F
$000E Bit 15
$000F Bit 7
14
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High TCNT
6
Low
TCNT resets to $0000. In normal modes, TCNT is read only.
TIC1–TIC3 —Timer Input Capture
$0010–$0015
$0010
$0011
$0012
$0013
$0014
$0015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
High
Low
High
Low
High
Low
TIC1
TIC2
TIC3
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
TICx not affected by reset
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MC68HC11KTS/D
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TOC1–TOC4 —Timer Output Compare
$0016–$001D
$0016
$0017
$0018
$0019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
High TOC1
Low
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
High TOC2
Low
$001A Bit 15
$001B Bit 7
$001C Bit 15
$001D Bit 7
14
6
13
5
12
4
11
3
10
2
High TOC3
Low
14
6
13
5
12
4
11
3
10
2
High TOC4
Low
All TOCx register pairs reset to ones ($FFFF).
TI4/O5 —Timer Input Capture 4/Output Compare 5
$001E–$001F
$001E
$001F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit
I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. The
TI4/O5 register pair resets to ones ($FFFF).
TCTL1 —Timer Control 1
$0020
Bit 7
6
5
OM3
0
4
OL3
0
3
OM4
0
2
OL4
0
1
OM5
0
Bit 0
OL5
0
OM2
0
OL2
0
RESET:
OM[5:2] —Output Mode
OL[5:2] —Output Level
OMx
OLx
Action Taken on Successful Compare
Timer disconnected from output pin logic
Toggle OCx output line
0
0
1
1
0
1
0
1
Clear OCx output line to zero
Set OCx output line to one
TCTL2 —Timer Control 2
$0021
Bit 7
EDG4B
0
6
5
EDG1B
0
4
EDG1A
0
3
EDG2B
0
2
EDG2A
0
1
EDG3B
0
Bit 0
EDG4A
0
EDG3A
0
RESET:
Table 11 Timer Control Configuration
EDGxB
EDGxA
Configuration
0
0
1
1
0
1
0
1
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
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MC68HC11KTS/D
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TMSK1 —Timer Interrupt Mask 1
$0022
Bit 7
OC1I
0
6
OC2I
0
5
OC3I
0
4
OC4I
0
3
I4/O5I
0
2
IC1I
0
1
IC2I
0
Bit 0
IC3I
0
RESET:
OC1I–OC4I —Output Compare x Interrupt Enable
If the OCxF flag bit is set while the OCxI enable bit is set, a hardware interrupt sequence is requested.
I4/O5I —Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt bit. When I4/O5 in PACTL is zero,
I4/O5I is the output compare 5 interrupt control bit.
IC1I–IC3I —Input Capture x Interrupt Enable
If the ICxF flag bit is set while the ICxI enable bit is set, a hardware interrupt sequence is requested.
TFLG1 —Timer Interrupt Flag 1
$0023
Bit 7
OC1F
0
6
OC2F
0
5
OC3F
0
4
OC4F
0
3
I4/O5F
0
2
IC1F
0
1
IC2F
0
Bit 0
IC3F
0
RESET:
Clear flags by writing a one to the corresponding bit position(s).
OC1F–OC5F —Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F —Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL
IC1F–IC3F —Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
NOTE
Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1
enable the corresponding interrupt sources.
TMSK2 —Timer Interrupt Mask 2
$0024
Bit 7
TOI
0
6
RTII
0
5
PAOVI
0
4
PAII
0
3
—
0
2
—
0
1
PR1
0
Bit 0
PR0
0
RESET:
TOI —Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Timer overflow interrupt enabled
RTII —Real-Time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one.
PAOVI —Pulse Accumulator Overflow Interrupt Enable
Refer to 11 Pulse Accumulator.
PAII —Pulse Accumulator Interrupt Enable
Refer to 11 Pulse Accumulator.
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NOTE
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones
in TMSK2 enable the corresponding interrupt sources.
Bits [3:2] —Not implemented
Always read zero
PR[1:0] —Timer Prescaler Select
In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles
after reset. Refer to Table 10 for specific timing values.
PR[1:0]
0 0
Prescaler
1
4
0 1
1 0
8
1 1
16
TFLG2 —Timer Interrupt Flag 2
$0025
Bit 7
TOF
0
6
RTIF
0
5
PAOVF
0
4
3
—
0
2
—
0
1
—
0
Bit 0
—
PAIF
RESET:
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF —Timer Overflow Flag
Set when TCNT changes from $FFFF to $0000
RTIF —Real-Time (Periodic) Interrupt Flag
0 = No RTI interrupt
1 = RTI interrupt request pending
PAOVF —Pulse Accumulator Overflow Flag
Refer to 11 Pulse Accumulator.
PAIF —Pulse Accumulator Input Edge Flag
Refer to 11 Pulse Accumulator.
Bits [3:0] —Not implemented
Always read zero
PACTL —Pulse Accumulator Control
$0026
Bit 7
—
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
—
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
RESET:
0
Bit 7 —Not implemented
Always read zero
PAEN —Pulse Accumulator System Enable
Refer to 11 Pulse Accumulator.
PAMOD —Pulse Accumulator Mode
Refer to 11 Pulse Accumulator.
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PEDGE —Pulse Accumulator Edge Control
Refer to 11 Pulse Accumulator.
Bit 3 —Not implemented
Always reads zero
I4/O5 —Input Capture 4/Output Compare 5
Configure TI4/O5 for input capture or output compare
0 = OC5 enabled
1 = IC4 enabled
RTR[1:0] —Real-Time Interrupt (RTI) Rate
Refer to 10.1 Real-Time Interrupt.
10.1 Real-Time Interrupt
These rates are a function of the MCU oscillator frequency and the value of the software-accessible
control bits, RTR1 and RTR0. These bits determine the rate at which interrupts are requested by the
13
RTI system. The RTI system is driven by an E divided by 2 rate clock compensated so that it is inde-
pendent of the timer prescaler. The RTR1 and RTR0 control bits select an additional division factor. RTI
is set to its fastest rate by default out of reset and can be changed at any time.
Table 12 Real-Time Interrupt Rates (Period Length)
Period Length
Selected
13 ÷
Period Length
E = 3.0 MHz
2.731 ms
RTR[1:0]
E = 2.0 MHz
E = 4.0 MHz
0 0
4.096 ms
2.048 ms
2
2
2
2
E
Ε
Ε
Ε
14 ÷
15 ÷
16 ÷
0 1
1 0
1 1
8.192 ms
16.384 ms
32.768 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.383 ms
Table 13 Real-Time Interrupt Rates (Frequency)
Frequency
RTR[1:0]
Rate Selected
E = 2.0 MHz
E = 3.0 MHz
E = 4.0 MHz
13
0 0
244.141 Hz
366.211 Hz
488.281 Hz
E ÷2
14
0 1
1 0
1 1
122.070 Hz
61.035 Hz
30.518 Hz
183.105 Hz
91.553 Hz
45.776 Hz
244.141 Hz
122.070 Hz
61.035 Hz
E ÷2
15
E ÷2
16
E ÷2
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MC68HC11KTS/D
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11 Pulse Accumulator
M68HC11 K-series MCUs have an 8-bit counter that can be configured as a simple event counter or for
gated time accumulation. The counter can be read or written at any time.
The port A bit 7 I/O pin can be configured to act as a clock in event counting mode, or as a gate signal
to enable a free-running clock (E divided by 64) to the 8-bit counter in gated time accumulation mode.
Common XTAL Frequencies
8.0 MHz
12.0 MHz
3.0 MHz
333 ns
16.0 MHz
4.0 MHz
250 ns
CPU Clock
Cycle Time
(E)
2.0 MHz
(1/E)
500 ns
Pulse Accumulator (Gated Mode)
32.0 µs
6
1 Count —
21.33 µs
16.0 µs
(2 /E)
14
Overflow —
8.192 ms
5.461 ms
4.096 ms
(2 /E)
PAOVI
1
PAOVF
INTERRUPT
REQUESTS
PAII
2
PAIF
E ÷ 64 CLOCK
(FROM MAIN TIMER)
TMSK2 INT ENABLES
TFLG2 INTERRUPT STATUS
PAI EDGE
PAEN
DISABLE
FLAG SETTING
OVERFLOW
PACNT 8-BIT COUNTER
ENABLE
PIN
2:1
MUX
CLOCK
PAEN
PA7/
PAI/
OC1
INPUT BUFFER
AND
EDGE DETECTOR
DATA BUS
OUTPUT
BUFFER
FROM
MAIN TIMER
OC1
FROM
DDRA7
PACTL CONTROL
INTERNAL
DATA BUS
Figure 18 Pulse Accumulator System Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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TMSK2 —Timer Interrupt Mask 2
$0024
Bit 7
TOI
0
6
RTII
0
5
PAOVI
0
4
PAII
0
3
—
0
2
—
0
1
PR1
0
Bit 0
PR0
0
RESET:
TOI —Timer Overflow Interrupt Enable
Refer to 10 Main Timer.
RTII —Real-Time Interrupt Enable
Refer to 10 Main Timer.
PAOVI —Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Pulse accumulator overflow interrupt enabled
PAII —Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator input interrupt disabled
1 = Pulse accumulator input interrupt enabled if PAIF bit in TFLG2 register is set
Bits [3:2] —Not implemented
Always read zero
PR[1:0] —Timer Prescaler Select
Refer to 10 Main Timer.
NOTE
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones
in TMSK2 enable the corresponding interrupt sources.
TFLG2 —Timer Interrupt Flag 2
$0025
Bit 7
TOF
0
6
RTIF
0
5
PAOVF
0
4
PAIF
0
3
—
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
Clear flags by writing a one to the corresponding bit position(s).
TOF —Timer Overflow Enable
Refer to 10 Main Timer.
RTIF —Real-Time Interrupt Flag
Refer to 10 Main Timer.
PAOVF —Pulse Accumulator Overflow Flag
Set when PACNT changes from $FF to $00
PAIF —Pulse Accumulator Input Edge Flag
Set each time a selected active edge is detected on the PAI input line
Bits [3:0] —Not implemented
Always read zero
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PACTL —Pulse Accumulator Control
$0026
Bit 7
—
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
—
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
RESET:
0
Bit 7 —Not implemented
Always reads zero
PAEN —Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD —Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE —Pulse Accumulator Edge Control
0 = In event mode, falling edges increment counter. In gated accumulation mode, high level enables
accumulator and falling edge sets PAIF.
1 = In event mode, rising edges increment counter. In gated accumulation mode, low level enables
accumulator and rising edge sets PAIF.
I4/O5 —Input Capture 4/Output Compare 5
Refer to 10 Main Timer.
RTR[1:0] —Real-Time Interrupt Rate
Refer to 10 Main Timer.
PACNT —Pulse Accumulator Counter
$0027
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Can be read and written.
M68HC11 K Series
MC68HC11KTS/D
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12 Pulse-Width Modulation Timer
M68HC11 K-series MCUs contains a PWM timer that is composed of a four-channel 8-bit modulator.
Each of the modulators can create independent continuous waveforms with software-selectable duty
rates from 0% to 100%.
The PWM provides up to four pulse-width modulated waveforms on port H pins. Each channel has its
own counter. Pairs of counters can be concatenated to create 16-bit PWM outputs based on 16-bit
counts. Three clock sources (A, B, and S) and a flexible clock select scheme give the PWM system a
wide range of frequencies.
Four control registers configure the PWM outputs —PWCLK, PWPOL, PWSCAL, and PWEN. The PW-
CLK register selects the prescale value for the PWM clock sources and enables the 16-bit PWM func-
tions. The PWPOL register determines each channel's polarity and selects the clock source for each
channel. The PWSCAL register derives a user-scaled clock based on the A clock source, and the
PWEN register enables the PWM channels.
Each channel has a separate 8-bit counter, period register, and duty cycle register. The period and duty
cycle registers are double buffered so that if they are changed while the channel is enabled, the change
does not take effect until the counter rolls over or the channel is disabled. A new period or duty cycle
can be forced into effect immediately by writing to the period or duty cycle register and then writing to
the counter.
With channels configured for 8-bit mode and E = 4 MHz, PWM signals of 40 kHz (1% duty cycle reso-
lution) to less than 10 Hz (approximately 0.4% duty cycle resolution) can be produced. By configuring
the channels for 16-bit mode with E = 4 MHz, PWM periods greater than one minute are possible.
In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM frequen-
cy of about 60 Hz). In the same system, a PWM frequency of 1 kHz corresponds to a duty cycle reso-
lution of 0.025%.
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MC68HC11TS/D
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MCU
E CLOCK
CLOCK S
=
÷ 1
÷ 2
8-BIT COMPARE
÷ 2
PWSCAL
8
÷ 4
RESET
÷ 8
÷ 16
÷ 32
÷ 64
÷ 128
SELECT
8-BIT COUNTER
CLOCK A
PCKA1 PCKA2
CLOCK B
PCKB1
PCKB2
PCKB3
SELECT
PWEN3
PWEN4
CON34
PWEN1
PWEN2
CON12
CLOCK
SELECT
CLOCK
SELECT
PCLK3
PCLK4
PCLK1
PCLK2
CNT3
CNT4
CNT1
CNT2
PWCNT1
PWCNT2
RESET
CARRY
CON12
PPOL1
RESET
S
Q
Q
PH0/
PW1
MUX
MUX
BIT 0
BIT 1
R
8
8
16-BIT
PWM
CONTROL
=
=
=
=
8-BIT COMPARE
PWPER1
8-BIT COMPARE
PWPER2
S
R
Q
Q
PH1/
PW2
8-BIT COMPARE
PWDTY1
8-BIT COMPARE
PWDTY2
PPOL2
PPOL3
PORT H
PIN
CONTROL
PWCNT3
RESET
PWCNT4
RESET
CARRY
CON34
S
R
Q
PH2/
PW3
MUX
BIT 2
BIT 3
Q
8
8
16-BIT
PWM
CONTROL
=
=
=
=
8-BIT COMPARE
PWPER3
8-BIT COMPARE
PWPER4
S
R
Q
Q
PH3/
PW4
MUX
8-BIT COMPARE
PWDTY3
8-BIT COMPARE
PWDTY4
PPOL4
PWM
OUTPUT
PWDTY
PWPER
Figure 19 Pulse-Width Modulation Block Diagram
M68HC11 K Series
MC68HC11TS/D
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PWCLK —Pulse-Width Modulation Clock Select
$0060
Bit 7
CON34
0
6
CON12
0
5
PCKA2
0
4
PCKA1
0
3
—
0
2
PCKB3
0
1
PCKB2
0
Bit 0
PCKB1
0
RESET:
CON34 —Concatenate Channels 3 and 4
Channel 3 is high-order byte, and channel 4 is the low-order byte. The resulting output is available on
port H, pin 3. Clock source is determined by PCLK4.
0 = Channels 3 and 4 are separate 8-bit PWMs.
1 = Channels 3 and 4 are concatenated to create one 16-bit PWM channel.
CON12 —Concatenate Channels One and Two
Channel 1 is high-order byte, and channel 2 is the low-order byte. The resulting output is available on
port H, pin 1. Clock source is determined by PCLK2.
0 = Channels 1 and 2 are separate 8-bit PWMs.
1 = Channels 1 and 2 are concatenated to create one 16-bit PWM channel.
PCKA[2:1] —Prescaler for Clock A (See also PWSCAL register)
Determines the rate of clock A
PCKA[2:1]
Value of Clock A
0 0
0 1
1 0
1 1
E
E/2
E/4
E/8
Bit 3 —Not implemented
Always reads zero
PCKB[3:1] —Prescaler for Clock B
Determines the rate for clock B
PCKB[3:1]
0 0 0
Value of Clock B
E
0 0 1
E/2
0 1 0
E/4
0 1 1
E/8
1 0 0
E/16
E/32
E/64
E/128
1 0 1
1 1 0
1 1 1
PWPOL —Pulse-Width Modulation Timer Polarity
$0061
Bit 7
PCLK4
0
6
PCLK3
0
5
PCLK2
0
4
PCLK1
0
3
PPOL4
0
2
PPOL3
0
1
PPOL2
0
Bit 0
PPOL1
0
RESET:
PCLK4 —Pulse-Width Channel 4 Clock Select
0 = Clock B is source
1 = Clock S is source
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PCLK3 —Pulse-Width Channel 3 Clock Select
0 = Clock B is source
1 = Clock S is source
PCLK2 —Pulse-Width Channel 2 Clock Select
0 = Clock A is source
1 = Clock S is source
PCLK1 —Pulse-Width Channel 1 Clock Select
0 = Clock A is source
1 = Clock S is source
PPOL[4:1] —Pulse-Width Channel x Polarity
0 = PWM channel x output is low at the beginning of the clock cycle and goes high when duty count
is reached
1 = PWM channel x output is high at the beginning of the clock cycle and goes low when duty count
is reached
PWSCAL —Pulse-Width Modulation Timer Prescaler
$0062
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
7
0
0
0
RESET:
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by 2.
If PWSCAL = $00, divide clock A by 256, then divide the result by 2.
PWEN —Pulse-Width Modulation Timer Enable
$0063
Bit 7
TPWSL
0
6
DISCP
0
5
—
0
4
—
0
3
PWEN4
0
2
PWEN3
0
1
PWEN2
0
Bit 0
PWEN1
0
RESET:
TPWSL —PWM Scaled Clock Test Bit (TEST)
Factory test only
DISCP —Disable Compare Scaled E Clock (TEST)
Factory test only
Bits [5:4] —Not implemented
Always read zero
PWEN[4:1] —Pulse-Width Channel 4–1
0 = Channel disabled
1 = Channel enabled
PWCNT1–PWCNT4 —Pulse-Width Modulation Timer Counter 1 to 4
$0064–$0067
$0064
$0065
$0066
$0067
RESET:
Bit 7
Bit 7
Bit 7
Bit 7
0
6
6
6
6
0
5
5
5
5
0
4
4
4
4
0
3
3
3
3
0
2
2
2
2
0
1
1
1
1
0
Bit 0
PWCNT1
PWCNT2
PWCNT3
PWCNT4
Bit 0
Bit 0
Bit 0
0
PWCNT1–PWCNT4
Begins count using whichever clock was selected
M68HC11 K Series
MC68HC11TS/D
MOTOROLA
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PWPER1–PWPER4 —Pulse-Width Modulation Timer Period 1 to 4
$0068–$006B
$0068
$0069
Bit 7
Bit 7
Bit 7
Bit 7
1
6
6
6
6
1
5
5
5
5
1
4
4
4
4
1
3
3
3
3
1
2
2
2
2
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
1
PWPER1
PWPER2
PWPER3
PWPER4
$006A
$006B
RESET:
PWPER1–PWPER4
Determines period of associated PWM channel
PWDTY1–4 —Pulse-Width Modulation Timer Duty Cycle 1 to 4
$006C–$006F
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
6
6
6
6
6
1
5
5
5
5
5
1
4
4
4
4
4
1
3
3
3
3
3
1
2
2
2
2
2
1
1
1
1
1
1
1
Bit 0
$006C
$006D
$006E
$006F
RESET:
Bit 0
Bit 0
Bit 0
Bit 0
1
PWDTY1
PWDTY2
PWDTY3
PWDTY4
PWDTY1–4
Determines duty cycle of associated PWM channel
12.1 PWM Boundary Cases
Certain values written to PWM control registers, counters, etc. can cause outputs that are not what the
user might expect. These are referred to as boundary cases. Boundary cases occur when the user
specifies a value that is either a maximum or a minimum. This value combined with other conditions
causes unexpected behavior of the PWM system.
The following conditions always cause the corresponding output to be high:
PWDTYx = $00, PWPERx > $00, and PPOLx = 0
PWDTYx ≥PWPERx, and PPOLx = 1
PWPERx = $00 and PPOLx = 1
The following conditions always cause the corresponding output to be low:
PWDTYx = $00, PWPERx > $00, and PPOLx = 1
PWDTYx ≥PWPERx, and PPOLx = 0
PWPERx = $00 and PPOLx = 0
MOTOROLA
78
M68HC11 K Series
MC68HC11TS/D
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
79
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